mirror of
git://nv-tegra.nvidia.com/tegra/optee-src/atf.git
synced 2025-12-22 09:21:26 +03:00
Updating prebuilts and/or headers
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arm-trusted-firmware/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S c86abd9bf2685dab74d5844d44b08b1c1a76fd8d - arm-trusted-firmware/lib/cpus/aarch64/a64fx.S 4ef2e504a667d7529f6e9f0629c04db77435a28a - arm-trusted-firmware/lib/utils/mem_region.c cf339f00e977a47612e93384a6a0b8e73d731c21 - arm-trusted-firmware/lib/locks/bakery/bakery_lock_coherent.c 977e6d078bc957f8bdaaf5007e9192de38d79bee - arm-trusted-firmware/lib/locks/bakery/bakery_lock_normal.c edf2b7a02784eccffa70a8f06817929dd1a8f993 - arm-trusted-firmware/lib/locks/exclusive/aarch32/spinlock.S 70011c90369b5b9a9d55faec233e60b90b31801e - arm-trusted-firmware/lib/locks/exclusive/aarch64/spinlock.S 7643d09d9577c6232b14eccb6e1fc3a1c8acc0d9 - arm-trusted-firmware/lib/pmf/pmf_smc.c bc4f07448420d9d32b327b6516b618223272961e - arm-trusted-firmware/lib/pmf/pmf_main.c 520eaa82ebafcd44f850b2d49c5e9d500fbf4c2d - arm-trusted-firmware/lib/optee/optee_utils.c 5b4b8798bdd0c34e076d2e3cf365ea5451837b57 - arm-trusted-firmware/lib/zlib/inflate.h 1c1467906f8d4ff84cc17a4dc057cf4913dbbeeb - arm-trusted-firmware/lib/zlib/zutil.c 7e5be478693b1a35e1e4cd1ce317b4500829c6c9 - arm-trusted-firmware/lib/zlib/inflate.c 083ae032c7ce5cde8a3324c4887e88d3bb667e32 - arm-trusted-firmware/lib/zlib/crc32.h 8770ab43c9050b824c646f6e6cee8b3c0628cbda - arm-trusted-firmware/lib/zlib/inffixed.h 4fc803c43a562b2b92a97e22300754ddfe44c603 - arm-trusted-firmware/lib/zlib/inffast.h 81a3e31c1cf436b7b37d0fd2173f5d2cb41842a2 - arm-trusted-firmware/lib/zlib/inftrees.c 370f01d26f5b8fa7030cd5fb054c5f8117d3efc6 - arm-trusted-firmware/lib/zlib/inftrees.h 6c1114794db137af50f9b060aaade1a1a35ed784 - arm-trusted-firmware/lib/zlib/adler32.c 37d67e3a5edffcda681cd70c6ba56f76ede5352b - arm-trusted-firmware/lib/zlib/inffast.c 8bb206723f10a7635c07f3e77abad21e4e47f520 - arm-trusted-firmware/lib/zlib/tf_gunzip.c f5d71470e37d9b6a4e22ff3cf83db854217f3672 - arm-trusted-firmware/lib/zlib/crc32.c 5e3458a3e458b1bea750c6007fc259e233d37887 - arm-trusted-firmware/lib/zlib/zutil.h 915a3be354066f5d3af420ceec193b411076c68b - arm-trusted-firmware/lib/zlib/zlib.h e3329c0bcd4fb66dbba89f8181a971f61cab6ea0 - arm-trusted-firmware/lib/zlib/zconf.h 886c1e8212ddafb0663811837c76ce60a9afb42a - arm-trusted-firmware/lib/bl_aux_params/bl_aux_params.c 8f6358e8adff333d53864e9d728b50b3cfccdd57 - arm-trusted-firmware/lib/aarch64/cache_helpers.S 96718b39d24ee4ca5fd1eb4f87d53c45c9e4f079 - arm-trusted-firmware/lib/aarch64/armclang_printf.S da63c15641cb6cf532770db54efc30b3f8122a7c - arm-trusted-firmware/lib/aarch64/misc_helpers.S 88bbfcb3f9b827bdab7f16cdfe892b2aa1470576 - arm-trusted-firmware/bl2/bl2_image_load_v2.c 4e6964af8a924859ce477b03706fa91fac4ab723 - arm-trusted-firmware/bl2/bl2.ld.S d8756b1a7295709e6757c7dbfc53741267823e2a - arm-trusted-firmware/bl2/bl2_main.c 991c05cee7a30247e2edcade94405aef95480121 - arm-trusted-firmware/bl2/bl2_private.h 6f387fa12de655645d96da6fce67619f1377bda9 - arm-trusted-firmware/bl2/bl2_el3.ld.S 2534665e628b7612c3896fed4e659f3351601296 - arm-trusted-firmware/bl2/aarch32/bl2_arch_setup.c aac463ba1d35408d94f960ade6d2db95d68455ab - arm-trusted-firmware/bl2/aarch32/bl2_el3_entrypoint.S 1f72bb253974087b2a555dc3a89651f7ad462387 - arm-trusted-firmware/bl2/aarch32/bl2_entrypoint.S 44692bdbcbccddc6c4fc022d5028cacb8842376a - arm-trusted-firmware/bl2/aarch32/bl2_el3_exceptions.S f64693060b1ef904b4abfc04b8480a0f458494c5 - arm-trusted-firmware/bl2/aarch32/bl2_run_next_image.S 776c1699268eee43ba9230cb7e785e298e56a233 - arm-trusted-firmware/bl2/aarch64/bl2_arch_setup.c a34048b4cc67bca14b7594e2c1a53b4c0376d779 - arm-trusted-firmware/bl2/aarch64/bl2_el3_entrypoint.S c426fa02b617581d2495667828e9430110cf713a - arm-trusted-firmware/bl2/aarch64/bl2_entrypoint.S 62ef4221f56feaf0907dbe17cad47a9bab86bf03 - arm-trusted-firmware/bl2/aarch64/bl2_el3_exceptions.S 777576955f2ae3959035c33791a33835fe6578f4 - arm-trusted-firmware/bl2/aarch64/bl2_rme_entrypoint.S 247751d71fb2863f439cc217ac18c219dbf15453 - arm-trusted-firmware/bl2/aarch64/bl2_run_next_image.S 20113f49289a58e42b03525ea9427f94e093f58f - arm-trusted-firmware/bl1/bl1_private.h d006178768f88929b34ddd8b6f7caf6ffb1577b4 - arm-trusted-firmware/bl1/bl1_main.c 653f6de57d95cb1d74a23acc6389ab9292ef0451 - arm-trusted-firmware/bl1/bl1_fwu.c 77c0d42875cfa4640d3c5e481334bbb62f6a7a3e - arm-trusted-firmware/bl1/bl1.ld.S 85b2afc44851dc57e79c264641730d0e2eca3016 - arm-trusted-firmware/bl1/tbbr/tbbr_img_desc.c caf76eacd5e8708391bbf7db7315acad4b89c7fd - arm-trusted-firmware/bl1/aarch32/bl1_entrypoint.S 095ac3b2483b968f263618a4bd6cdd8d6f66d321 - arm-trusted-firmware/bl1/aarch32/bl1_context_mgmt.c 8d6e2008e280f848fb14017ba5ba559a10724421 - arm-trusted-firmware/bl1/aarch32/bl1_arch_setup.c bea69e37646041aff3c96bf107e1db48f382a1b4 - arm-trusted-firmware/bl1/aarch32/bl1_exceptions.S 5c5e2355ca375fa98ae30f56bcf2f57ea7056c71 - arm-trusted-firmware/bl1/aarch64/bl1_entrypoint.S 587ecb158bf5940ddc7f95250a8802df39806ef0 - arm-trusted-firmware/bl1/aarch64/bl1_context_mgmt.c 284a0afe619de982f2bd1d4b1c625831ef7b3b5e - arm-trusted-firmware/bl1/aarch64/bl1_arch_setup.c d6181e93a353f492a54a5222fe53d793cc6d46d7 - arm-trusted-firmware/bl1/aarch64/bl1_exceptions.S 2c87153926f8a458cffc9a435e15571ba721c2fa - arm-trusted-firmware/licenses/LICENSE.MIT 201f68ff32e77e6400dc5624a726bb46fafe1ac3 - arm-trusted-firmware/.husky/commit-msg.gerrit fd32ceb86780ba4682d238401c5bdc6c51f6652f - arm-trusted-firmware/.husky/prepare-commit-msg.cz edf09f8f672ed108a22d57c3be9c64c542957347 - arm-trusted-firmware/.husky/commit-msg.commitlint d04e79c7e2d1ff0546074efcfda2290f20c1c923 - arm-trusted-firmware/.husky/commit-msg 11dae66f5031e4fc368d8b20d11916dbcc90b1c0 - arm-trusted-firmware/.husky/prepare-commit-msg Change-Id: Ibacfa2e40f438fdc2107c4979df3e5152074355a
This commit is contained in:
svcmobrel-release
25
arm-trusted-firmware/docs/Makefile
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25
arm-trusted-firmware/docs/Makefile
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||||
#
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||||
# Copyright (c) 2019-2020, ARM Limited. All rights reserved.
|
||||
#
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||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
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||||
# Minimal makefile for Sphinx documentation
|
||||
#
|
||||
|
||||
# You can set these variables from the command line.
|
||||
SPHINXOPTS = -W
|
||||
SPHINXBUILD = sphinx-build
|
||||
SPHINXPROJ = TrustedFirmware-A
|
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SOURCEDIR = .
|
||||
BUILDDIR = build
|
||||
|
||||
# Put it first so that "make" without argument is like "make help".
|
||||
help:
|
||||
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
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|
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.PHONY: help Makefile
|
||||
|
||||
# Catch-all target: route all unknown targets to Sphinx using the new
|
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# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
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%: Makefile
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||||
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
|
||||
15
arm-trusted-firmware/docs/_static/css/custom.css
vendored
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arm-trusted-firmware/docs/_static/css/custom.css
vendored
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||||
/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
|
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
|
||||
|
||||
/*
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||||
* Set the white-space property of tables to normal.
|
||||
* With this setting sequences of whitespace inside
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* a table will collapse into a single whitespace,
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||||
* and text will wrap when necessary.
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*/
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.wy-table-responsive table td {
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white-space: normal;
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}
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arm-trusted-firmware/docs/about/acknowledgements.rst
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arm-trusted-firmware/docs/about/acknowledgements.rst
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||||
Contributor Acknowledgements
|
||||
============================
|
||||
|
||||
.. note::
|
||||
This file is only relevant for legacy contributions, to acknowledge the
|
||||
specific contributors referred to in "Arm Limited and Contributors" copyright
|
||||
notices. As contributors are now encouraged to put their name or company name
|
||||
directly into the copyright notices, this file is not relevant for new
|
||||
contributions. See the :ref:`License` document for the correct template to
|
||||
use for new contributions.
|
||||
|
||||
- Linaro Limited
|
||||
- Marvell International Ltd.
|
||||
- NVIDIA Corporation
|
||||
- NXP Semiconductors
|
||||
- Socionext Inc.
|
||||
- STMicroelectronics
|
||||
- Xilinx, Inc.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019, Arm Limited. All rights reserved.*
|
||||
56
arm-trusted-firmware/docs/about/contact.rst
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arm-trusted-firmware/docs/about/contact.rst
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|
||||
Support & Contact
|
||||
-----------------
|
||||
|
||||
We welcome any feedback on |TF-A| and there are several methods for providing
|
||||
it or for obtaining support.
|
||||
|
||||
.. warning::
|
||||
If you think you have found a security vulnerability, please report this using
|
||||
the process defined in the :ref:`Security Handling` document.
|
||||
|
||||
Mailing Lists
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
Public mailing lists for TF-A and the wider Trusted Firmware project are
|
||||
hosted on TrustedFirmware.org. The mailing lists can be used for general
|
||||
enquiries, enhancement requests and issue reports, or to follow and participate
|
||||
in technical or organizational discussions around the project. These discussions
|
||||
include design proposals, advance notice of changes and upcoming events.
|
||||
|
||||
The relevant lists for the TF-A project are:
|
||||
|
||||
- `TF-A development`_
|
||||
- `TF-A-Tests development`_
|
||||
|
||||
You can see a `summary of all the lists`_ on the TrustedFirmware.org website.
|
||||
|
||||
Open Tech Forum Call
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Every other week, we organize a call with all interested TF-A contributors.
|
||||
Anyone is welcome to join. This is an opportunity to discuss any technical
|
||||
topic within the community. More details can be found `here`_.
|
||||
|
||||
.. _here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/
|
||||
|
||||
Issue Tracker
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
Bug reports may be filed on the `issue tracker`_ on the TrustedFirmware.org
|
||||
website. Using this tracker gives everyone visibility of the known issues in
|
||||
TF-A.
|
||||
|
||||
Arm Licensees
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
Arm licensees have an additional support conduit - they may contact Arm directly
|
||||
via their partner managers.
|
||||
|
||||
.. _`issue tracker`: https://developer.trustedfirmware.org
|
||||
.. _`TF-A development`: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/
|
||||
.. _`TF-A-Tests development`: https://lists.trustedfirmware.org/mailman3/lists/tf-a-tests.lists.trustedfirmware.org/
|
||||
.. _`summary of all the lists`: https://lists.trustedfirmware.org/mailman3/lists/
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
|
||||
128
arm-trusted-firmware/docs/about/features.rst
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arm-trusted-firmware/docs/about/features.rst
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|
||||
Feature Overview
|
||||
================
|
||||
|
||||
This page provides an overview of the current |TF-A| feature set. For a full
|
||||
description of these features and their implementation details, please see
|
||||
the documents that are part of the *Components* and *System Design* chapters.
|
||||
|
||||
The :ref:`Change Log & Release Notes` provides details of changes made since the
|
||||
last release.
|
||||
|
||||
Current features
|
||||
----------------
|
||||
|
||||
- Initialization of the secure world, for example exception vectors, control
|
||||
registers and interrupts for the platform.
|
||||
|
||||
- Library support for CPU specific reset and power down sequences. This
|
||||
includes support for errata workarounds and the latest Arm DynamIQ CPUs.
|
||||
|
||||
- Drivers to enable standard initialization of Arm System IP, for example
|
||||
Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
|
||||
Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
|
||||
Controller (TZC).
|
||||
|
||||
- A generic |SCMI| driver to interface with conforming power controllers, for
|
||||
example the Arm System Control Processor (SCP).
|
||||
|
||||
- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
|
||||
Convention`_ using an EL3 runtime services framework.
|
||||
|
||||
- |PSCI| library support for CPU, cluster and system power management
|
||||
use-cases.
|
||||
This library is pre-integrated with the AArch64 EL3 Runtime Software, and
|
||||
is also suitable for integration with other AArch32 EL3 Runtime Software,
|
||||
for example an AArch32 Secure OS.
|
||||
|
||||
- A minimal AArch32 Secure Payload (*SP_MIN*) to demonstrate |PSCI| library
|
||||
integration with AArch32 EL3 Runtime Software.
|
||||
|
||||
- Secure Monitor library code such as world switching, EL1 context management
|
||||
and interrupt routing.
|
||||
When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
|
||||
AArch64 EL3 Runtime Software must be integrated with a Secure Payload
|
||||
Dispatcher (SPD) component to customize the interaction with the SP.
|
||||
|
||||
- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
|
||||
interaction with PSCI.
|
||||
|
||||
- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_,
|
||||
`Trusty Secure OS`_ and `ProvenCore Secure OS`_.
|
||||
|
||||
- A Trusted Board Boot implementation, conforming to all mandatory TBBR
|
||||
requirements. This includes image authentication, Firmware Update (or
|
||||
recovery mode), and packaging of the various firmware images into a
|
||||
Firmware Image Package (FIP).
|
||||
|
||||
- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
|
||||
its hardware Root of Trust and crypto acceleration services.
|
||||
|
||||
- Reliability, Availability, and Serviceability (RAS) functionality, including
|
||||
|
||||
- A Secure Partition Manager (SPM) to manage Secure Partitions in
|
||||
Secure-EL0, which can be used to implement simple management and
|
||||
security services.
|
||||
|
||||
- An |SDEI| dispatcher to route interrupt-based |SDEI| events.
|
||||
|
||||
- An Exception Handling Framework (EHF) that allows dispatching of EL3
|
||||
interrupts to their registered handlers, to facilitate firmware-first
|
||||
error handling.
|
||||
|
||||
- A dynamic configuration framework that enables each of the firmware images
|
||||
to be configured at runtime if required by the platform. It also enables
|
||||
loading of a hardware configuration (for example, a kernel device tree)
|
||||
as part of the FIP, to be passed through the firmware stages.
|
||||
This feature is now incorporated inside the firmware configuration framework
|
||||
(fconf).
|
||||
|
||||
- Support for alternative boot flows, for example to support platforms where
|
||||
the EL3 Runtime Software is loaded using other firmware or a separate
|
||||
secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
|
||||
at EL3.
|
||||
|
||||
- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
|
||||
|
||||
- Support for combining several libraries into a "romlib" image that may be
|
||||
shared across images to reduce memory footprint. The romlib image is stored
|
||||
in ROM but is accessed through a jump-table that may be stored
|
||||
in read-write memory, allowing for the library code to be patched.
|
||||
|
||||
- Support for the Secure Partition Manager Dispatcher (SPMD) component as a
|
||||
new standard service.
|
||||
|
||||
- Support for ARMv8.3 pointer authentication in the normal and secure worlds.
|
||||
The use of pointer authentication in the normal world is enabled whenever
|
||||
architectural support is available, without the need for additional build
|
||||
flags.
|
||||
|
||||
- Position-Independent Executable (PIE) support. Currently for BL2, BL31, and
|
||||
TSP, with further support to be added in a future release.
|
||||
|
||||
Still to come
|
||||
-------------
|
||||
|
||||
- Support for additional platforms.
|
||||
|
||||
- Refinements to Position Independent Executable (PIE) support.
|
||||
|
||||
- Continued support for the FF-A v1.0 (formally known as SPCI) specification, to enable the
|
||||
use of secure partition management in the secure world.
|
||||
|
||||
- Documentation enhancements.
|
||||
|
||||
- Ongoing support for new architectural features, CPUs and System IP.
|
||||
|
||||
- Ongoing support for new Arm system architecture specifications.
|
||||
|
||||
- Ongoing security hardening, optimization and quality improvements.
|
||||
|
||||
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
|
||||
.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
|
||||
.. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
|
||||
.. _Trusty Secure OS: https://source.android.com/security/trusty
|
||||
.. _ProvenCore Secure OS: https://provenrun.com/products/provencore/
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
|
||||
12
arm-trusted-firmware/docs/about/index.rst
Normal file
12
arm-trusted-firmware/docs/about/index.rst
Normal file
@@ -0,0 +1,12 @@
|
||||
About
|
||||
=====
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Contents
|
||||
|
||||
features
|
||||
release-information
|
||||
maintainers
|
||||
contact
|
||||
acknowledgements
|
||||
960
arm-trusted-firmware/docs/about/maintainers.rst
Normal file
960
arm-trusted-firmware/docs/about/maintainers.rst
Normal file
@@ -0,0 +1,960 @@
|
||||
Project Maintenance
|
||||
===================
|
||||
|
||||
Trusted Firmware-A (TF-A) is an open governance community project. All
|
||||
contributions are ultimately merged by the maintainers listed below. Technical
|
||||
ownership of most parts of the codebase falls on the code owners listed
|
||||
below. An acknowledgement from these code owners is required before the
|
||||
maintainers merge a contribution.
|
||||
|
||||
More details may be found in the `Project Maintenance Process`_ document.
|
||||
|
||||
.. |M| replace:: **Mail**
|
||||
.. |G| replace:: **GitHub ID**
|
||||
.. |F| replace:: **Files**
|
||||
|
||||
.. _maintainers:
|
||||
|
||||
Maintainers
|
||||
-----------
|
||||
|
||||
:|M|: Dan Handley <dan.handley@arm.com>
|
||||
:|G|: `danh-arm`_
|
||||
:|M|: Soby Mathew <soby.mathew@arm.com>
|
||||
:|G|: `soby-mathew`_
|
||||
:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
|
||||
:|G|: `sandrine-bailleux-arm`_
|
||||
:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
|
||||
:|G|: `AlexeiFedorov`_
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|M|: Mark Dykes <mark.dykes@arm.com>
|
||||
:|G|: `mardyk01`_
|
||||
:|M|: Olivier Deprez <olivier.deprez@arm.com>
|
||||
:|G|: `odeprez`_
|
||||
:|M|: Bipin Ravi <bipin.ravi@arm.com>
|
||||
:|G|: `bipinravi-arm`_
|
||||
:|M|: Joanna Farley <joanna.farley@arm.com>
|
||||
:|G|: `joannafarley-arm`_
|
||||
:|M|: Julius Werner <jwerner@chromium.org>
|
||||
:|G|: `jwerner-chromium`_
|
||||
:|M|: Varun Wadekar <vwadekar@nvidia.com>
|
||||
:|G|: `vwadekar`_
|
||||
:|M|: Andre Przywara <andre.przywara@arm.com>
|
||||
:|G|: `Andre-ARM`_
|
||||
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
|
||||
:|G|: `laurenw-arm`_
|
||||
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
|
||||
:|G|: `madhukar-Arm`_
|
||||
:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
|
||||
:|G|: `raghuncstate`_
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
|
||||
LTS Maintainers
|
||||
---------------
|
||||
|
||||
:|M|: Bipin Ravi <bipin.ravi@arm.com>
|
||||
:|G|: `bipinravi-arm`_
|
||||
:|M|: Joanna Farley <joanna.farley@arm.com>
|
||||
:|G|: `joannafarley-arm`_
|
||||
:|M|: Okash Khawaja <okash@google.com>
|
||||
:|G|: `bytefire`_
|
||||
:|M|: Varun Wadekar <vwadekar@nvidia.com>
|
||||
:|G|: `vwadekar`_
|
||||
|
||||
.. _code owners:
|
||||
|
||||
Code owners
|
||||
-----------
|
||||
|
||||
Common Code
|
||||
~~~~~~~~~~~
|
||||
|
||||
Armv7-A architecture port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Etienne Carriere <etienne.carriere@linaro.org>
|
||||
:|G|: `etienne-lms`_
|
||||
|
||||
Build Definitions for CMake Build System
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Chris Kay <chris.kay@arm.com>
|
||||
:|G|: `CJKay`_
|
||||
:|F|: /
|
||||
|
||||
Software Delegated Exception Interface (SDEI)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
|
||||
:|G|: `jayanthchidanand-arm`_
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|F|: services/std_svc/sdei/
|
||||
|
||||
Trusted Boot
|
||||
^^^^^^^^^^^^
|
||||
:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
|
||||
:|G|: `sandrine-bailleux-arm`_
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
|
||||
:|G|: `laurenw-arm`_
|
||||
:|F|: drivers/auth/
|
||||
|
||||
Secure Partition Manager Core (EL3 FF-A SPMC)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Marc Bonnici <marc.bonnici@arm.com>
|
||||
:|G|: `marcbonnici`_
|
||||
:|F|: services/std_svc/spm/el3_spmc/\*
|
||||
|
||||
Secure Partition Manager Dispatcher (SPMD)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Olivier Deprez <olivier.deprez@arm.com>
|
||||
:|G|: `odeprez`_
|
||||
:|M|: Joao Alves <Joao.Alves@arm.com>
|
||||
:|G|: `J-Alves`_
|
||||
:|F|: services/std_svc/spmd/\*
|
||||
|
||||
Exception Handling Framework (EHF)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
|
||||
:|G|: `jayanthchidanand-arm`_
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|F|: bl31/ehf.c
|
||||
|
||||
Realm Management Monitor Dispatcher (RMMD)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
|
||||
:|G|: `javieralso-arm`_
|
||||
:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
|
||||
:|G|: `AlexeiFedorov`_
|
||||
:|F|: services/std_svc/rmmd/\*
|
||||
:|F|: include/services/rmmd_svc.h
|
||||
:|F|: include/services/rmm_core_manifest.h
|
||||
|
||||
Realm Management Extension (RME)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
|
||||
:|G|: `javieralso-arm`_
|
||||
:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
|
||||
:|G|: `AlexeiFedorov`_
|
||||
|
||||
Drivers, Libraries and Framework Code
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Console API framework
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Julius Werner <jwerner@chromium.org>
|
||||
:|G|: `jwerner-chromium`_
|
||||
:|F|: drivers/console/
|
||||
:|F|: include/drivers/console.h
|
||||
:|F|: plat/common/aarch64/crash_console_helpers.S
|
||||
|
||||
coreboot support libraries
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Julius Werner <jwerner@chromium.org>
|
||||
:|G|: `jwerner-chromium`_
|
||||
:|F|: drivers/coreboot/
|
||||
:|F|: include/drivers/coreboot/
|
||||
:|F|: include/lib/coreboot.h
|
||||
:|F|: lib/coreboot/
|
||||
|
||||
eMMC/UFS drivers
|
||||
^^^^^^^^^^^^^^^^
|
||||
:|M|: Haojian Zhuang <haojian.zhuang@linaro.org>
|
||||
:|G|: `hzhuang1`_
|
||||
:|F|: drivers/partition/
|
||||
:|F|: drivers/synopsys/emmc/
|
||||
:|F|: drivers/synopsys/ufs/
|
||||
:|F|: drivers/ufs/
|
||||
:|F|: include/drivers/dw_ufs.h
|
||||
:|F|: include/drivers/ufs.h
|
||||
:|F|: include/drivers/synopsys/dw_mmc.h
|
||||
|
||||
Arm® Ethos™-N NPU driver
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Joshua Slater <joshua.slater@arm.com>
|
||||
:|G|: `jslater8`_
|
||||
:|M|: Mikael Olsson <mikael.olsson@arm.com>
|
||||
:|G|: `mikaelolsson-arm`_
|
||||
:|F|: drivers/arm/ethosn/
|
||||
:|F|: include/drivers/arm/ethosn.h
|
||||
:|F|: plat/arm/common/fconf/fconf_ethosn_getter.c
|
||||
:|F|: include/plat/arm/common/fconf_ethosn_getter.h
|
||||
:|F|: fdts/juno-ethosn.dtsi
|
||||
|
||||
JTAG DCC console driver
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:M: Michal Simek <michal.simek@amd.com>
|
||||
:G: `michalsimek`_
|
||||
:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
|
||||
:G: `venkatesh`_
|
||||
:F: drivers/arm/dcc/
|
||||
:F: include/drivers/arm/dcc.h
|
||||
|
||||
Power State Coordination Interface (PSCI)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
|
||||
:|G|: `madhukar-Arm`_
|
||||
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
|
||||
:|G|: `laurenw-arm`_
|
||||
:|F|: lib/psci/
|
||||
|
||||
DebugFS
|
||||
^^^^^^^
|
||||
:|M|: Olivier Deprez <olivier.deprez@arm.com>
|
||||
:|G|: `odeprez`_
|
||||
:|F|: lib/debugfs/
|
||||
|
||||
Firmware Configuration Framework (FCONF)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
|
||||
:|G|: `madhukar-Arm`_
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
|
||||
:|G|: `laurenw-arm`_
|
||||
:|F|: lib/fconf/
|
||||
|
||||
Performance Measurement Framework (PMF)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Joao Alves <Joao.Alves@arm.com>
|
||||
:|G|: `J-Alves`_
|
||||
:|F|: lib/pmf/
|
||||
|
||||
Errata Management
|
||||
^^^^^^^^^^^^^^^^^
|
||||
:|M|: Bipin Ravi <bipin.ravi@arm.com>
|
||||
:|G|: `bipinravi-arm`_
|
||||
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
|
||||
:|G|: `laurenw-arm`_
|
||||
|
||||
Arm CPU libraries
|
||||
^^^^^^^^^^^^^^^^^
|
||||
:|M|: Bipin Ravi <bipin.ravi@arm.com>
|
||||
:|G|: `bipinravi-arm`_
|
||||
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
|
||||
:|G|: `laurenw-arm`_
|
||||
:|F|: lib/cpus/
|
||||
|
||||
Reliability Availability Serviceabilty (RAS) framework
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|M|: Olivier Deprez <olivier.deprez@arm.com>
|
||||
:|G|: `odeprez`_
|
||||
:|F|: lib/extensions/ras/
|
||||
|
||||
Activity Monitors Unit (AMU) extensions
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
|
||||
:|G|: `AlexeiFedorov`_
|
||||
:|M|: Chris Kay <chris.kay@arm.com>
|
||||
:|G|: `CJKay`_
|
||||
:|F|: lib/extensions/amu/
|
||||
|
||||
Memory Partitioning And Monitoring (MPAM) extensions
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|F|: lib/extensions/mpam/
|
||||
|
||||
Pointer Authentication (PAuth) and Branch Target Identification (BTI) extensions
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
|
||||
:|G|: `AlexeiFedorov`_
|
||||
:|F|: lib/extensions/pauth/
|
||||
|
||||
Statistical Profiling Extension (SPE)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|F|: lib/extensions/spe/
|
||||
|
||||
Standard C library
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Chris Kay <chris.kay@arm.com>
|
||||
:|G|: `CJKay`_
|
||||
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
|
||||
:|G|: `madhukar-Arm`_
|
||||
:|F|: lib/libc/
|
||||
|
||||
Library At ROM (ROMlib)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
|
||||
:|G|: `madhukar-Arm`_
|
||||
:|F|: lib/romlib/
|
||||
|
||||
Translation tables (``xlat_tables``) library
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|M|: Joao Alves <Joao.Alves@arm.com>
|
||||
:|G|: `J-Alves`_
|
||||
:|F|: lib/xlat\_tables_\*/
|
||||
|
||||
IO abstraction layer
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|M|: Olivier Deprez <olivier.deprez@arm.com>
|
||||
:|G|: `odeprez`_
|
||||
:|F|: drivers/io/
|
||||
|
||||
GIC driver
|
||||
^^^^^^^^^^
|
||||
:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
|
||||
:|G|: `AlexeiFedorov`_
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
|
||||
:|G|: `madhukar-Arm`_
|
||||
:|M|: Olivier Deprez <olivier.deprez@arm.com>
|
||||
:|G|: `odeprez`_
|
||||
:|F|: drivers/arm/gic/
|
||||
|
||||
Message Handling Unit (MHU) driver
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: David Vincze <david.vincze@arm.com>
|
||||
:|G|: `davidvincze`_
|
||||
:|F|: include/drivers/arm/mhu.h
|
||||
:|F|: drivers/arm/mhu
|
||||
|
||||
Runtime Security Subsystem (RSS) comms driver
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: David Vincze <david.vincze@arm.com>
|
||||
:|G|: `davidvincze`_
|
||||
:|F|: include/drivers/arm/rss_comms.h
|
||||
:|F|: drivers/arm/rss
|
||||
|
||||
Libfdt wrappers
|
||||
^^^^^^^^^^^^^^^
|
||||
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
|
||||
:|G|: `madhukar-Arm`_
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|F|: common/fdt_wrappers.c
|
||||
|
||||
Firmware Encryption Framework
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Sumit Garg <sumit.garg@linaro.org>
|
||||
:|G|: `b49020`_
|
||||
:|F|: drivers/io/io_encrypted.c
|
||||
:|F|: include/drivers/io/io_encrypted.h
|
||||
:|F|: include/tools_share/firmware_encrypted.h
|
||||
|
||||
Measured Boot
|
||||
^^^^^^^^^^^^^
|
||||
:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
|
||||
:|G|: `sandrine-bailleux-arm`_
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|F|: drivers/measured_boot
|
||||
:|F|: include/drivers/measured_boot
|
||||
:|F|: docs/components/measured_boot
|
||||
:|F|: plat/arm/board/fvp/fvp\*_measured_boot.c
|
||||
|
||||
DRTM
|
||||
^^^^
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|F|: services/std_svc/drtm
|
||||
|
||||
PSA Firmware Update
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
|
||||
:|G|: `sandrine-bailleux-arm`_
|
||||
:|F|: drivers/fwu
|
||||
:|F|: include/drivers/fwu
|
||||
|
||||
Platform Security Architecture (PSA) APIs
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
|
||||
:|G|: `sandrine-bailleux-arm`_
|
||||
:|F|: include/lib/psa
|
||||
:|F|: lib/psa
|
||||
|
||||
System Control and Management Interface (SCMI) Server
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Etienne Carriere <etienne.carriere@st.com>
|
||||
:|G|: `etienne-lms`_
|
||||
:|M|: Peng Fan <peng.fan@nxp.com>
|
||||
:|G|: `MrVan`_
|
||||
:|F|: drivers/scmi-msg
|
||||
:|F|: include/drivers/scmi\*
|
||||
|
||||
Max Power Mitigation Mechanism (MPMM)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Chris Kay <chris.kay@arm.com>
|
||||
:|G|: `CJKay`_
|
||||
:|F|: include/lib/mpmm/
|
||||
:|F|: lib/mpmm/
|
||||
|
||||
Granule Protection Tables Library (GPT-RME)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Soby Mathew <soby.mathew@arm.com>
|
||||
:|G|: `soby-mathew`_
|
||||
:|M|: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
|
||||
:|G|: `javieralso-arm`_
|
||||
:|F|: lib/gpt_rme
|
||||
:|F|: include/lib/gpt_rme
|
||||
|
||||
Platform Ports
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
Allwinner ARMv8 platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Andre Przywara <andre.przywara@arm.com>
|
||||
:|G|: `Andre-ARM`_
|
||||
:|M|: Samuel Holland <samuel@sholland.org>
|
||||
:|G|: `smaeul`_
|
||||
:|F|: docs/plat/allwinner.rst
|
||||
:|F|: plat/allwinner/
|
||||
:|F|: drivers/allwinner/
|
||||
|
||||
Amlogic Meson S905 (GXBB) platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Andre Przywara <andre.przywara@arm.com>
|
||||
:|G|: `Andre-ARM`_
|
||||
:|F|: docs/plat/meson-gxbb.rst
|
||||
:|F|: drivers/amlogic/
|
||||
:|F|: plat/amlogic/gxbb/
|
||||
|
||||
Amlogic Meson S905x (GXL) platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Remi Pommarel <repk@triplefau.lt>
|
||||
:|G|: `remi-triplefault`_
|
||||
:|F|: docs/plat/meson-gxl.rst
|
||||
:|F|: plat/amlogic/gxl/
|
||||
|
||||
Amlogic Meson S905X2 (G12A) platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Carlo Caione <ccaione@baylibre.com>
|
||||
:|G|: `carlocaione`_
|
||||
:|F|: docs/plat/meson-g12a.rst
|
||||
:|F|: plat/amlogic/g12a/
|
||||
|
||||
Amlogic Meson A113D (AXG) platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Carlo Caione <ccaione@baylibre.com>
|
||||
:|G|: `carlocaione`_
|
||||
:|F|: docs/plat/meson-axg.rst
|
||||
:|F|: plat/amlogic/axg/
|
||||
|
||||
Arm FPGA platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Andre Przywara <andre.przywara@arm.com>
|
||||
:|G|: `Andre-ARM`_
|
||||
:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
|
||||
:|G|: `javieralso-arm`_
|
||||
:|F|: plat/arm/board/arm_fpga
|
||||
|
||||
Arm FVP Platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
|
||||
:|G|: `madhukar-Arm`_
|
||||
:|F|: plat/arm/board/fvp
|
||||
|
||||
Arm Juno Platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|M|: Chris Kay <chris.kay@arm.com>
|
||||
:|G|: `CJKay`_
|
||||
:|F|: plat/arm/board/juno
|
||||
|
||||
Arm Morello and N1SDP Platform ports
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manoj Kumar <manoj.kumar3@arm.com>
|
||||
:|G|: `manojkumar-arm`_
|
||||
:|M|: Chandni Cherukuri <chandni.cherukuri@arm.com>
|
||||
:|G|: `chandnich`_
|
||||
:|F|: plat/arm/board/morello
|
||||
:|F|: plat/arm/board/n1sdp
|
||||
|
||||
Arm Rich IoT Platform ports
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
|
||||
:|G|: `abdellatif-elkhlifi`_
|
||||
:|M|: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
:|G|: `vishnu-banavath`_
|
||||
:|F|: plat/arm/board/corstone700
|
||||
:|F|: plat/arm/board/a5ds
|
||||
:|F|: plat/arm/board/corstone1000
|
||||
|
||||
Arm Reference Design platform ports
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Thomas Abraham <thomas.abraham@arm.com>
|
||||
:|G|: `thomas-arm`_
|
||||
:|M|: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
|
||||
:|G|: `vijayenthiran-arm`_
|
||||
:|F|: plat/arm/css/sgi/
|
||||
:|F|: plat/arm/board/rde1edge/
|
||||
:|F|: plat/arm/board/rdn1edge/
|
||||
:|F|: plat/arm/board/rdn2/
|
||||
:|F|: plat/arm/board/rdv1/
|
||||
:|F|: plat/arm/board/rdv1mc/
|
||||
:|F|: plat/arm/board/sgi575/
|
||||
|
||||
Arm Total Compute platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Anders Dellien <anders.dellien@arm.com>
|
||||
:|G|: `andersdellien-arm`_
|
||||
:|F|: plat/arm/board/tc
|
||||
|
||||
HiSilicon HiKey and HiKey960 platform ports
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Haojian Zhuang <haojian.zhuang@linaro.org>
|
||||
:|G|: `hzhuang1`_
|
||||
:|F|: docs/plat/hikey.rst
|
||||
:|F|: docs/plat/hikey960.rst
|
||||
:|F|: plat/hisilicon/hikey/
|
||||
:|F|: plat/hisilicon/hikey960/
|
||||
|
||||
HiSilicon Poplar platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Shawn Guo <shawn.guo@linaro.org>
|
||||
:|G|: `shawnguo2`_
|
||||
:|F|: docs/plat/poplar.rst
|
||||
:|F|: plat/hisilicon/poplar/
|
||||
|
||||
Intel SocFPGA platform ports
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
||||
:|G|: `sieumunt`_
|
||||
:|M|: Benjamin Jit Loon Lim <jit.loon.lim@intel.com>
|
||||
:|G|: `BenjaminLimJL`_
|
||||
:|F|: plat/intel/soc/
|
||||
:|F|: drivers/intel/soc/
|
||||
|
||||
MediaTek platform ports
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Rex-BC Chen <rex-bc.chen@mediatek.com>
|
||||
:|G|: `mtk-rex-bc-chen`_
|
||||
:|M|: Leon Chen <leon.chen@mediatek.com>
|
||||
:|G|: `leon-chen-mtk`_
|
||||
:|F|: docs/plat/mt\*.rst
|
||||
:|F|: plat/mediatek/
|
||||
|
||||
Marvell platform ports and SoC drivers
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Konstantin Porotchkin <kostap@marvell.com>
|
||||
:|G|: `kostapr`_
|
||||
:|F|: docs/plat/marvell/
|
||||
:|F|: plat/marvell/
|
||||
:|F|: drivers/marvell/
|
||||
:|F|: tools/marvell/
|
||||
|
||||
NVidia platform ports
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Varun Wadekar <vwadekar@nvidia.com>
|
||||
:|G|: `vwadekar`_
|
||||
:|F|: docs/plat/nvidia-tegra.rst
|
||||
:|F|: include/lib/cpus/aarch64/denver.h
|
||||
:|F|: lib/cpus/aarch64/denver.S
|
||||
:|F|: plat/nvidia/
|
||||
|
||||
NXP i.MX 7 WaRP7 platform port and SoC drivers
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
|
||||
:|G|: `bryanodonoghue`_
|
||||
:|M|: Jun Nie <jun.nie@linaro.org>
|
||||
:|G|: `niej`_
|
||||
:|F|: docs/plat/warp7.rst
|
||||
:|F|: plat/imx/common/
|
||||
:|F|: plat/imx/imx7/
|
||||
:|F|: drivers/imx/timer/
|
||||
:|F|: drivers/imx/uart/
|
||||
:|F|: drivers/imx/usdhc/
|
||||
|
||||
NXP i.MX 8 platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Peng Fan <peng.fan@nxp.com>
|
||||
:|G|: `MrVan`_
|
||||
:|F|: docs/plat/imx8.rst
|
||||
:|F|: plat/imx/
|
||||
|
||||
NXP i.MX8M platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jacky Bai <ping.bai@nxp.com>
|
||||
:|G|: `JackyBai`_
|
||||
:|F|: docs/plat/imx8m.rst
|
||||
:|F|: plat/imx/imx8m/
|
||||
|
||||
NXP QorIQ Layerscape common code for platform ports
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
|
||||
:|G|: `pangupta`_
|
||||
:|M|: Jiafei Pan <jiafei.pan@nxp.com>
|
||||
:|G|: `JiafeiPan`_
|
||||
:|F|: docs/plat/nxp/
|
||||
:|F|: plat/nxp/
|
||||
:|F|: drivers/nxp/
|
||||
:|F|: tools/nxp/
|
||||
|
||||
NXP SoC Part LX2160A and its platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
|
||||
:|G|: `pangupta`_
|
||||
:|F|: plat/nxp/soc-lx2160a
|
||||
:|F|: plat/nxp/soc-lx2160a/lx2162aqds
|
||||
:|F|: plat/nxp/soc-lx2160a/lx2160aqds
|
||||
:|F|: plat/nxp/soc-lx2160a/lx2160ardb
|
||||
|
||||
NXP SoC Part LS1028A and its platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jiafei Pan <jiafei.pan@nxp.com>
|
||||
:|G|: `JiafeiPan`_
|
||||
:|F|: plat/nxp/soc-ls1028a
|
||||
:|F|: plat/nxp/soc-ls1028a/ls1028ardb
|
||||
|
||||
NXP SoC Part LS1043A and its platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jiafei Pan <jiafei.pan@nxp.com>
|
||||
:|G|: `JiafeiPan`_
|
||||
:|F|: plat/nxp/soc-ls1043a
|
||||
:|F|: plat/nxp/soc-ls1043a/ls1043ardb
|
||||
|
||||
NXP SoC Part LS1046A and its platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jiafei Pan <jiafei.pan@nxp.com>
|
||||
:|G|: `JiafeiPan`_
|
||||
:|F|: plat/nxp/soc-ls1046a
|
||||
:|F|: plat/nxp/soc-ls1046a/ls1046ardb
|
||||
:|F|: plat/nxp/soc-ls1046a/ls1046afrwy
|
||||
:|F|: plat/nxp/soc-ls1046a/ls1046aqds
|
||||
|
||||
NXP SoC Part LS1088A and its platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jiafei Pan <jiafei.pan@nxp.com>
|
||||
:|G|: `JiafeiPan`_
|
||||
:|F|: plat/nxp/soc-ls1088a
|
||||
:|F|: plat/nxp/soc-ls1088a/ls1088ardb
|
||||
:|F|: plat/nxp/soc-ls1088a/ls1088aqds
|
||||
|
||||
QEMU platform port
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jens Wiklander <jens.wiklander@linaro.org>
|
||||
:|G|: `jenswi-linaro`_
|
||||
:|F|: docs/plat/qemu.rst
|
||||
:|F|: plat/qemu/
|
||||
|
||||
QTI platform port
|
||||
^^^^^^^^^^^^^^^^^
|
||||
:|M|: Saurabh Gorecha <sgorecha@codeaurora.org>
|
||||
:|G|: `sgorecha`_
|
||||
:|M|: Lachit Patel <lpatel@codeaurora.org>
|
||||
:|G|: `lachitp`_
|
||||
:|M|: Sreevyshanavi Kare <skare@codeaurora.org>
|
||||
:|G|: `sreekare`_
|
||||
:|M|: Muhammad Arsath K F <quic_mkf@quicinc.com>
|
||||
:|G|: `quic_mkf`_
|
||||
:|M|: QTI TF Maintainers <qti.trustedfirmware.maintainers@codeaurora.org>
|
||||
:|F|: docs/plat/qti.rst
|
||||
:|F|: plat/qti/
|
||||
|
||||
QTI MSM8916 platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Stephan Gerhold <stephan@gerhold.net>
|
||||
:|G|: `stephan-gh`_
|
||||
:|M|: Nikita Travkin <nikita@trvn.ru>
|
||||
:|G|: `TravMurav`_
|
||||
:|F|: docs/plat/qti-msm8916.rst
|
||||
:|F|: plat/qti/msm8916/
|
||||
|
||||
Raspberry Pi 3 platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
|
||||
:|G|: `grandpaul`_
|
||||
:|F|: docs/plat/rpi3.rst
|
||||
:|F|: plat/rpi/rpi3/
|
||||
:|F|: plat/rpi/common/
|
||||
:|F|: drivers/rpi3/
|
||||
:|F|: include/drivers/rpi3/
|
||||
|
||||
Raspberry Pi 4 platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Andre Przywara <andre.przywara@arm.com>
|
||||
:|G|: `Andre-ARM`_
|
||||
:|F|: docs/plat/rpi4.rst
|
||||
:|F|: plat/rpi/rpi4/
|
||||
:|F|: plat/rpi/common/
|
||||
:|F|: drivers/rpi3/
|
||||
:|F|: include/drivers/rpi3/
|
||||
|
||||
Renesas rcar-gen3 platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
|
||||
:|G|: `ldts`_
|
||||
:|M|: Marek Vasut <marek.vasut@gmail.com>
|
||||
:|G|: `marex`_
|
||||
:|F|: docs/plat/rcar-gen3.rst
|
||||
:|F|: plat/renesas/common
|
||||
:|F|: plat/renesas/rcar
|
||||
:|F|: drivers/renesas/common
|
||||
:|F|: drivers/renesas/rcar
|
||||
:|F|: tools/renesas/rcar_layout_create
|
||||
|
||||
Renesas RZ/G2 platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Biju Das <biju.das.jz@bp.renesas.com>
|
||||
:|G|: `bijucdas`_
|
||||
:|M|: Marek Vasut <marek.vasut@gmail.com>
|
||||
:|G|: `marex`_
|
||||
:|M|: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
:|G|: `prabhakarlad`_
|
||||
:|F|: docs/plat/rz-g2.rst
|
||||
:|F|: plat/renesas/common
|
||||
:|F|: plat/renesas/rzg
|
||||
:|F|: drivers/renesas/common
|
||||
:|F|: drivers/renesas/rzg
|
||||
:|F|: tools/renesas/rzg_layout_create
|
||||
|
||||
RockChip platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Tony Xie <tony.xie@rock-chips.com>
|
||||
:|G|: `TonyXie06`_
|
||||
:|G|: `rockchip-linux`_
|
||||
:|M|: Heiko Stuebner <heiko@sntech.de>
|
||||
:|G|: `mmind`_
|
||||
:|M|: Julius Werner <jwerner@chromium.org>
|
||||
:|G|: `jwerner-chromium`_
|
||||
:|F|: plat/rockchip/
|
||||
|
||||
STM32MP1 platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Yann Gautier <yann.gautier@st.com>
|
||||
:|G|: `Yann-lms`_
|
||||
:|F|: docs/plat/stm32mp1.rst
|
||||
:|F|: drivers/st/
|
||||
:|F|: fdts/stm32\*
|
||||
:|F|: include/drivers/st/
|
||||
:|F|: include/dt-bindings/\*/stm32\*
|
||||
:|F|: plat/st/
|
||||
:|F|: tools/stm32image/
|
||||
|
||||
Synquacer platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Sumit Garg <sumit.garg@linaro.org>
|
||||
:|G|: `b49020`_
|
||||
:|F|: docs/plat/synquacer.rst
|
||||
:|F|: plat/socionext/synquacer/
|
||||
|
||||
Texas Instruments platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Nishanth Menon <nm@ti.com>
|
||||
:|G|: `nmenon`_
|
||||
:|F|: docs/plat/ti-k3.rst
|
||||
:|F|: plat/ti/
|
||||
|
||||
UniPhier platform port
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Orphan
|
||||
:|F|: docs/plat/socionext-uniphier.rst
|
||||
:|F|: plat/socionext/uniphier/
|
||||
|
||||
Xilinx platform port
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Michal Simek <michal.simek@amd.com>
|
||||
:|G|: `michalsimek`_
|
||||
:|M|: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
|
||||
:|G|: `venkatesh`_
|
||||
:|F|: docs/plat/xilinx\*
|
||||
:|F|: plat/xilinx/
|
||||
|
||||
|
||||
Secure Payloads and Dispatchers
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
OP-TEE dispatcher
|
||||
^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jens Wiklander <jens.wiklander@linaro.org>
|
||||
:|G|: `jenswi-linaro`_
|
||||
:|F|: docs/components/spd/optee-dispatcher.rst
|
||||
:|F|: services/spd/opteed/
|
||||
|
||||
TLK
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Varun Wadekar <vwadekar@nvidia.com>
|
||||
:|G|: `vwadekar`_
|
||||
:|F|: docs/components/spd/tlk-dispatcher.rst
|
||||
:|F|: include/bl32/payloads/tlk.h
|
||||
:|F|: services/spd/tlkd/
|
||||
|
||||
Trusty secure payloads
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Arve Hjønnevåg <arve@android.com>
|
||||
:|G|: `arve-android`_
|
||||
:|M|: Marco Nelissen <marcone@google.com>
|
||||
:|G|: `marcone`_
|
||||
:|M|: Varun Wadekar <vwadekar@nvidia.com>
|
||||
:|G|: `vwadekar`_
|
||||
:|F|: docs/components/spd/trusty-dispatcher.rst
|
||||
:|F|: services/spd/trusty/
|
||||
|
||||
|
||||
Test Secure Payload (TSP)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|F|: bl32/tsp/
|
||||
:|F|: services/spd/tspd/
|
||||
|
||||
ProvenCore Secure Payload Dispatcher
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
:|M|: Jérémie Corbier <jeremie.corbier@provenrun.com>
|
||||
:|G|: `jcorbier`_
|
||||
:|F|: docs/components/spd/pnc-dispatcher.rst
|
||||
:|F|: services/spd/pncd/
|
||||
|
||||
Tools
|
||||
~~~~~
|
||||
|
||||
Fiptool
|
||||
^^^^^^^
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|M|: Joao Alves <Joao.Alves@arm.com>
|
||||
:|G|: `J-Alves`_
|
||||
:|F|: tools/fiptool/
|
||||
|
||||
Cert_create tool
|
||||
^^^^^^^^^^^^^^^^
|
||||
:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
|
||||
:|G|: `sandrine-bailleux-arm`_
|
||||
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
|
||||
:|G|: `ManishVB-Arm`_
|
||||
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
|
||||
:|G|: `laurenw-arm`_
|
||||
:|F|: tools/cert_create/
|
||||
|
||||
Encrypt_fw tool
|
||||
^^^^^^^^^^^^^^^
|
||||
:|M|: Sumit Garg <sumit.garg@linaro.org>
|
||||
:|G|: `b49020`_
|
||||
:|F|: tools/encrypt_fw/
|
||||
|
||||
Sptool
|
||||
^^^^^^
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|M|: Joao Alves <Joao.Alves@arm.com>
|
||||
:|G|: `J-Alves`_
|
||||
:|F|: tools/sptool/
|
||||
|
||||
Build system
|
||||
^^^^^^^^^^^^
|
||||
:|M|: Chris Kay <chris.kay@arm.com>
|
||||
:|G|: `CJKay`_
|
||||
:|M|: Manish Pandey <manish.pandey2@arm.com>
|
||||
:|G|: `manish-pandey-arm`_
|
||||
:|F|: Makefile
|
||||
:|F|: make_helpers/
|
||||
|
||||
Threat Model
|
||||
~~~~~~~~~~~~~
|
||||
:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
|
||||
:|G|: `sandrine-bailleux-arm`_
|
||||
:|M|: Joanna Farley <joanna.farley@arm.com>
|
||||
:|G|: `joannafarley-arm`_
|
||||
:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
|
||||
:|G|: `raghuncstate`_
|
||||
:|M|: Varun Wadekar <vwadekar@nvidia.com>
|
||||
:|G|: `vwadekar`_
|
||||
:|F|: docs/threat_model/
|
||||
|
||||
Conventional Changelog Extensions
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
:|M|: Chris Kay <chris.kay@arm.com>
|
||||
:|G|: `CJKay`_
|
||||
:|F|: tools/conventional-changelog-tf-a
|
||||
|
||||
.. _AlexeiFedorov: https://github.com/AlexeiFedorov
|
||||
.. _andersdellien-arm: https://github.com/andersdellien-arm
|
||||
.. _Andre-ARM: https://github.com/Andre-ARM
|
||||
.. _Anson-Huang: https://github.com/Anson-Huang
|
||||
.. _bijucdas: https://github.com/bijucdas
|
||||
.. _bryanodonoghue: https://github.com/bryanodonoghue
|
||||
.. _b49020: https://github.com/b49020
|
||||
.. _carlocaione: https://github.com/carlocaione
|
||||
.. _danh-arm: https://github.com/danh-arm
|
||||
.. _davidvincze: https://github.com/davidvincze
|
||||
.. _etienne-lms: https://github.com/etienne-lms
|
||||
.. _glneo: https://github.com/glneo
|
||||
.. _grandpaul: https://github.com/grandpaul
|
||||
.. _hzhuang1: https://github.com/hzhuang1
|
||||
.. _JackyBai: https://github.com/JackyBai
|
||||
.. _jcorbier: https://github.com/jcorbier
|
||||
.. _jenswi-linaro: https://github.com/jenswi-linaro
|
||||
.. _jslater8: https://github.com/jslater8
|
||||
.. _jwerner-chromium: https://github.com/jwerner-chromium
|
||||
.. _kostapr: https://github.com/kostapr
|
||||
.. _lachitp: https://github.com/lachitp
|
||||
.. _ldts: https://github.com/ldts
|
||||
.. _marex: https://github.com/marex
|
||||
.. _masahir0y: https://github.com/masahir0y
|
||||
.. _michalsimek: https://github.com/michalsimek
|
||||
.. _mikaelolsson-arm: https://github.com/mikaelolsson-arm
|
||||
.. _mmind: https://github.com/mmind
|
||||
.. _MrVan: https://github.com/MrVan
|
||||
.. _mtk-rex-bc-chen: https://github.com/mtk-rex-bc-chen
|
||||
.. _leon-chen-mtk: https://github.com/leon-chen-mtk
|
||||
.. _niej: https://github.com/niej
|
||||
.. _npoushin: https://github.com/npoushin
|
||||
.. _prabhakarlad: https://github.com/prabhakarlad
|
||||
.. _quic_mkf: https://github.com/quicmkf
|
||||
.. _remi-triplefault: https://github.com/repk
|
||||
.. _rockchip-linux: https://github.com/rockchip-linux
|
||||
.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
|
||||
.. _sgorecha: https://github.com/sgorecha
|
||||
.. _shawnguo2: https://github.com/shawnguo2
|
||||
.. _smaeul: https://github.com/smaeul
|
||||
.. _soby-mathew: https://github.com/soby-mathew
|
||||
.. _sreekare: https://github.com/sreekare
|
||||
.. _stephan-gh: https://github.com/stephan-gh
|
||||
.. _sieumunt: https://github.com/sieumunt
|
||||
.. _BenjaminLimJL: https://github.com/BenjaminLimJL
|
||||
.. _thomas-arm: https://github.com/thomas-arm
|
||||
.. _TonyXie06: https://github.com/TonyXie06
|
||||
.. _TravMurav: https://github.com/TravMurav
|
||||
.. _vwadekar: https://github.com/vwadekar
|
||||
.. _venkatesh: https://github.com/vabbarap
|
||||
.. _Yann-lms: https://github.com/Yann-lms
|
||||
.. _manish-pandey-arm: https://github.com/manish-pandey-arm
|
||||
.. _mardyk01: https://github.com/mardyk01
|
||||
.. _odeprez: https://github.com/odeprez
|
||||
.. _bipinravi-arm: https://github.com/bipinravi-arm
|
||||
.. _joannafarley-arm: https://github.com/joannafarley-arm
|
||||
.. _ManishVB-Arm: https://github.com/ManishVB-Arm
|
||||
.. _max-shvetsov: https://github.com/max-shvetsov
|
||||
.. _javieralso-arm: https://github.com/javieralso-arm
|
||||
.. _laurenw-arm: https://github.com/laurenw-arm
|
||||
.. _J-Alves: https://github.com/J-Alves
|
||||
.. _madhukar-Arm: https://github.com/madhukar-Arm
|
||||
.. _raghuncstate: https://github.com/raghuncstate
|
||||
.. _CJKay: https://github.com/cjkay
|
||||
.. _nmenon: https://github.com/nmenon
|
||||
.. _manojkumar-arm: https://github.com/manojkumar-arm
|
||||
.. _chandnich: https://github.com/chandnich
|
||||
.. _abdellatif-elkhlifi: https://github.com/abdellatif-elkhlifi
|
||||
.. _vishnu-banavath: https://github.com/vishnu-banavath
|
||||
.. _vijayenthiran-arm: https://github.com/vijayenthiran-arm
|
||||
.. _arugan02: https://github.com/arugan02
|
||||
.. _uarif1: https://github.com/uarif1
|
||||
.. _pangupta: https://github.com/pangupta
|
||||
.. _JiafeiPan: https://github.com/JiafeiPan
|
||||
.. _arve-android: https://github.com/arve-android
|
||||
.. _marcone: https://github.com/marcone
|
||||
.. _marcbonnici: https://github.com/marcbonnici
|
||||
.. _jayanthchidanand-arm: https://github.com/jayanthchidanand-arm
|
||||
.. _bytefire: https://github.com/bytefire
|
||||
|
||||
.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
|
||||
78
arm-trusted-firmware/docs/about/release-information.rst
Normal file
78
arm-trusted-firmware/docs/about/release-information.rst
Normal file
@@ -0,0 +1,78 @@
|
||||
Release Processes
|
||||
=================
|
||||
|
||||
Project Release Cadence
|
||||
-----------------------
|
||||
|
||||
The project currently aims to do a release once every 6 months which will be
|
||||
tagged on the master branch. There will be a code freeze (stop merging
|
||||
non-essential changes) up to 4 weeks prior to the target release date. The release
|
||||
candidates will start appearing after this and only bug fixes or updates
|
||||
required for the release will be merged. The maintainers are free to use their
|
||||
judgement on what changes are essential for the release. A release branch may be
|
||||
created after code freeze if there are significant changes that need merging onto
|
||||
the integration branch during the merge window.
|
||||
|
||||
The release testing will be performed on release candidates and depending on
|
||||
issues found, additional release candidates may be created to fix the issues.
|
||||
|
||||
::
|
||||
|
||||
|<----------6 months---------->|
|
||||
|<---4 weeks--->| |<---4 weeks--->|
|
||||
+-----------------------------------------------------------> time
|
||||
| | | |
|
||||
code freeze ver w.x code freeze ver y.z
|
||||
|
||||
|
||||
Upcoming Releases
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
These are the estimated dates for the upcoming release. These may change
|
||||
depending on project requirement and partner feedback.
|
||||
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| Release Version | Target Date | Expected Code Freeze |
|
||||
+=================+===========================+==============================+
|
||||
| v2.0 | 1st week of Oct '18 | 1st week of Sep '18 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| v2.1 | 5th week of Mar '19 | 1st week of Mar '19 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| v2.2 | 4th week of Oct '19 | 1st week of Oct '19 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| v2.3 | 4th week of Apr '20 | 1st week of Apr '20 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| v2.4 | 2nd week of Nov '20 | 4th week of Oct '20 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| v2.5 | 3rd week of May '21 | 5th week of Apr '21 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| v2.6 | 4th week of Nov '21 | 2nd week of Nov '21 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| v2.7 | 5th week of May '22 | 3rd week of May '22 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| v2.8 | 5th week of Nov '22 | 3rd week of Nov '22 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
| v2.9 | 1st week of May '23 | 3rd week of Apr '23 |
|
||||
+-----------------+---------------------------+------------------------------+
|
||||
|
||||
Removal of Deprecated Interfaces
|
||||
--------------------------------
|
||||
|
||||
As mentioned in the :ref:`Platform Ports Policy`, this is a live document
|
||||
cataloging all the deprecated interfaces in TF-A project and the Release version
|
||||
after which it will be removed.
|
||||
|
||||
+--------------------------------+-------------+---------+---------------------------------------------------------+
|
||||
| Interface | Deprecation | Removed | Comments |
|
||||
| | Date | after | |
|
||||
| | | Release | |
|
||||
+================================+=============+=========+=========================================================+
|
||||
| plat_convert_pk() function | Nov'22 | Next | Platform conversion to manage specific PK hash |
|
||||
| | | release | |
|
||||
| | | after | |
|
||||
| | | 2.8 | |
|
||||
+--------------------------------+-------------+---------+---------------------------------------------------------+
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.*
|
||||
6850
arm-trusted-firmware/docs/change-log.md
Normal file
6850
arm-trusted-firmware/docs/change-log.md
Normal file
File diff suppressed because it is too large
Load Diff
34
arm-trusted-firmware/docs/components/activity-monitors.rst
Normal file
34
arm-trusted-firmware/docs/components/activity-monitors.rst
Normal file
@@ -0,0 +1,34 @@
|
||||
Activity Monitors
|
||||
=================
|
||||
|
||||
FEAT_AMUv1 of the Armv8-A architecture introduces the Activity Monitors
|
||||
extension. This extension describes the architecture for the Activity Monitor
|
||||
Unit (|AMU|), an optional non-invasive component for monitoring core events
|
||||
through a set of 64-bit counters.
|
||||
|
||||
When the ``ENABLE_AMU=1`` build option is provided, Trusted Firmware-A sets up
|
||||
the |AMU| prior to its exit from EL3, and will save and restore architected
|
||||
|AMU| counters as necessary upon suspend and resume.
|
||||
|
||||
.. _Activity Monitor Auxiliary Counters:
|
||||
|
||||
Auxiliary counters
|
||||
------------------
|
||||
|
||||
FEAT_AMUv1 describes a set of implementation-defined auxiliary counters (also
|
||||
known as group 1 counters), controlled by the ``ENABLE_AMU_AUXILIARY_COUNTERS``
|
||||
build option.
|
||||
|
||||
As a security precaution, Trusted Firmware-A does not enable these by default.
|
||||
Instead, platforms may configure their auxiliary counters through one of two
|
||||
possible mechanisms:
|
||||
|
||||
- |FCONF|, controlled by the ``ENABLE_AMU_FCONF`` build option.
|
||||
- A platform implementation of the ``plat_amu_topology`` function (the default).
|
||||
|
||||
See :ref:`Activity Monitor Unit (AMU) Bindings` for documentation on the |FCONF|
|
||||
device tree bindings.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2021, Arm Limited. All rights reserved.*
|
||||
435
arm-trusted-firmware/docs/components/arm-sip-service.rst
Normal file
435
arm-trusted-firmware/docs/components/arm-sip-service.rst
Normal file
@@ -0,0 +1,435 @@
|
||||
Arm SiP Services
|
||||
================
|
||||
|
||||
This document enumerates and describes the Arm SiP (Silicon Provider) services.
|
||||
|
||||
SiP services are non-standard, platform-specific services offered by the silicon
|
||||
implementer or platform provider. They are accessed via ``SMC`` ("SMC calls")
|
||||
instruction executed from Exception Levels below EL3. SMC calls for SiP
|
||||
services:
|
||||
|
||||
- Follow `SMC Calling Convention`_;
|
||||
- Use SMC function IDs that fall in the SiP range, which are ``0xc2000000`` -
|
||||
``0xc200ffff`` for 64-bit calls, and ``0x82000000`` - ``0x8200ffff`` for 32-bit
|
||||
calls.
|
||||
|
||||
The Arm SiP implementation offers the following services:
|
||||
|
||||
- Performance Measurement Framework (PMF)
|
||||
- Execution State Switching service
|
||||
- DebugFS interface
|
||||
|
||||
Source definitions for Arm SiP service are located in the ``arm_sip_svc.h`` header
|
||||
file.
|
||||
|
||||
Performance Measurement Framework (PMF)
|
||||
---------------------------------------
|
||||
|
||||
The :ref:`Performance Measurement Framework <firmware_design_pmf>`
|
||||
allows callers to retrieve timestamps captured at various paths in TF-A
|
||||
execution.
|
||||
|
||||
Execution State Switching service
|
||||
---------------------------------
|
||||
|
||||
Execution State Switching service provides a mechanism for a non-secure lower
|
||||
Exception Level (either EL2, or NS EL1 if EL2 isn't implemented) to request to
|
||||
switch its execution state (a.k.a. Register Width), either from AArch64 to
|
||||
AArch32, or from AArch32 to AArch64, for the calling CPU. This service is only
|
||||
available when Trusted Firmware-A (TF-A) is built for AArch64 (i.e. when build
|
||||
option ``ARCH`` is set to ``aarch64``).
|
||||
|
||||
``ARM_SIP_SVC_EXE_STATE_SWITCH``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t Function ID
|
||||
uint32_t PC hi
|
||||
uint32_t PC lo
|
||||
uint32_t Cookie hi
|
||||
uint32_t Cookie lo
|
||||
|
||||
Return:
|
||||
uint32_t
|
||||
|
||||
The function ID parameter must be ``0x82000020``. It uniquely identifies the
|
||||
Execution State Switching service being requested.
|
||||
|
||||
The parameters *PC hi* and *PC lo* defines upper and lower words, respectively,
|
||||
of the entry point (physical address) at which execution should start, after
|
||||
Execution State has been switched. When calling from AArch64, *PC hi* must be 0.
|
||||
|
||||
When execution starts at the supplied entry point after Execution State has been
|
||||
switched, the parameters *Cookie hi* and *Cookie lo* are passed in CPU registers
|
||||
0 and 1, respectively. When calling from AArch64, *Cookie hi* must be 0.
|
||||
|
||||
This call can only be made on the primary CPU, before any secondaries were
|
||||
brought up with ``CPU_ON`` PSCI call. Otherwise, the call will always fail.
|
||||
|
||||
The effect of switching execution state is as if the Exception Level were
|
||||
entered for the first time, following power on. This means CPU registers that
|
||||
have a defined reset value by the Architecture will assume that value. Other
|
||||
registers should not be expected to hold their values before the call was made.
|
||||
CPU endianness, however, is preserved from the previous execution state. Note
|
||||
that this switches the execution state of the calling CPU only. This is not a
|
||||
substitute for PSCI ``SYSTEM_RESET``.
|
||||
|
||||
The service may return the following error codes:
|
||||
|
||||
- ``STATE_SW_E_PARAM``: If any of the parameters were deemed invalid for
|
||||
a specific request.
|
||||
- ``STATE_SW_E_DENIED``: If the call is not successful, or when TF-A is
|
||||
built for AArch32.
|
||||
|
||||
If the call is successful, the caller wouldn't observe the SMC returning.
|
||||
Instead, execution starts at the supplied entry point, with the CPU registers 0
|
||||
and 1 populated with the supplied *Cookie hi* and *Cookie lo* values,
|
||||
respectively.
|
||||
|
||||
DebugFS interface
|
||||
-----------------
|
||||
|
||||
The optional DebugFS interface is accessed through an SMC SiP service. Refer
|
||||
to the component documentation for details.
|
||||
|
||||
String parameters are passed through a shared buffer using a specific union:
|
||||
|
||||
.. code:: c
|
||||
|
||||
union debugfs_parms {
|
||||
struct {
|
||||
char fname[MAX_PATH_LEN];
|
||||
} open;
|
||||
|
||||
struct mount {
|
||||
char srv[MAX_PATH_LEN];
|
||||
char where[MAX_PATH_LEN];
|
||||
char spec[MAX_PATH_LEN];
|
||||
} mount;
|
||||
|
||||
struct {
|
||||
char path[MAX_PATH_LEN];
|
||||
dir_t dir;
|
||||
} stat;
|
||||
|
||||
struct {
|
||||
char oldpath[MAX_PATH_LEN];
|
||||
char newpath[MAX_PATH_LEN];
|
||||
} bind;
|
||||
};
|
||||
|
||||
Format of the dir_t structure as such:
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef struct {
|
||||
char name[NAMELEN];
|
||||
long length;
|
||||
unsigned char mode;
|
||||
unsigned char index;
|
||||
unsigned char dev;
|
||||
qid_t qid;
|
||||
} dir_t;
|
||||
|
||||
|
||||
* Identifiers
|
||||
|
||||
======================== =============================================
|
||||
SMC_OK 0
|
||||
SMC_UNK -1
|
||||
DEBUGFS_E_INVALID_PARAMS -2
|
||||
======================== =============================================
|
||||
|
||||
======================== =============================================
|
||||
MOUNT 0
|
||||
CREATE 1
|
||||
OPEN 2
|
||||
CLOSE 3
|
||||
READ 4
|
||||
WRITE 5
|
||||
SEEK 6
|
||||
BIND 7
|
||||
STAT 8
|
||||
INIT 10
|
||||
VERSION 11
|
||||
======================== =============================================
|
||||
|
||||
MOUNT
|
||||
~~~~~
|
||||
|
||||
Description
|
||||
^^^^^^^^^^^
|
||||
This operation mounts a blob of data pointed to by path stored in `src`, at
|
||||
filesystem location pointed to by path stored in `where`, using driver pointed
|
||||
to by path in `spec`.
|
||||
|
||||
Parameters
|
||||
^^^^^^^^^^
|
||||
======== ============================================================
|
||||
uint32_t FunctionID (0x82000030 / 0xC2000030)
|
||||
uint32_t ``MOUNT``
|
||||
======== ============================================================
|
||||
|
||||
Return values
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
=============== ==========================================================
|
||||
int32_t w0 == SMC_OK on success
|
||||
|
||||
w0 == DEBUGFS_E_INVALID_PARAMS if mount operation failed
|
||||
=============== ==========================================================
|
||||
|
||||
OPEN
|
||||
~~~~
|
||||
|
||||
Description
|
||||
^^^^^^^^^^^
|
||||
This operation opens the file path pointed to by `fname`.
|
||||
|
||||
Parameters
|
||||
^^^^^^^^^^
|
||||
|
||||
======== ============================================================
|
||||
uint32_t FunctionID (0x82000030 / 0xC2000030)
|
||||
uint32_t ``OPEN``
|
||||
uint32_t mode
|
||||
======== ============================================================
|
||||
|
||||
mode can be one of:
|
||||
|
||||
.. code:: c
|
||||
|
||||
enum mode {
|
||||
O_READ = 1 << 0,
|
||||
O_WRITE = 1 << 1,
|
||||
O_RDWR = 1 << 2,
|
||||
O_BIND = 1 << 3,
|
||||
O_DIR = 1 << 4,
|
||||
O_STAT = 1 << 5
|
||||
};
|
||||
|
||||
Return values
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
=============== ==========================================================
|
||||
int32_t w0 == SMC_OK on success
|
||||
|
||||
w0 == DEBUGFS_E_INVALID_PARAMS if open operation failed
|
||||
|
||||
uint32_t w1: file descriptor id on success.
|
||||
=============== ==========================================================
|
||||
|
||||
CLOSE
|
||||
~~~~~
|
||||
|
||||
Description
|
||||
^^^^^^^^^^^
|
||||
|
||||
This operation closes a file described by a file descriptor obtained by a
|
||||
previous call to OPEN.
|
||||
|
||||
Parameters
|
||||
^^^^^^^^^^
|
||||
|
||||
======== ============================================================
|
||||
uint32_t FunctionID (0x82000030 / 0xC2000030)
|
||||
uint32_t ``CLOSE``
|
||||
uint32_t File descriptor id returned by OPEN
|
||||
======== ============================================================
|
||||
|
||||
Return values
|
||||
^^^^^^^^^^^^^
|
||||
=============== ==========================================================
|
||||
int32_t w0 == SMC_OK on success
|
||||
|
||||
w0 == DEBUGFS_E_INVALID_PARAMS if close operation failed
|
||||
=============== ==========================================================
|
||||
|
||||
READ
|
||||
~~~~
|
||||
|
||||
Description
|
||||
^^^^^^^^^^^
|
||||
|
||||
This operation reads a number of bytes from a file descriptor obtained by
|
||||
a previous call to OPEN.
|
||||
|
||||
Parameters
|
||||
^^^^^^^^^^
|
||||
|
||||
======== ============================================================
|
||||
uint32_t FunctionID (0x82000030 / 0xC2000030)
|
||||
uint32_t ``READ``
|
||||
uint32_t File descriptor id returned by OPEN
|
||||
uint32_t Number of bytes to read
|
||||
======== ============================================================
|
||||
|
||||
Return values
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
On success, the read data is retrieved from the shared buffer after the
|
||||
operation.
|
||||
|
||||
=============== ==========================================================
|
||||
int32_t w0 == SMC_OK on success
|
||||
|
||||
w0 == DEBUGFS_E_INVALID_PARAMS if read operation failed
|
||||
|
||||
uint32_t w1: number of bytes read on success.
|
||||
=============== ==========================================================
|
||||
|
||||
SEEK
|
||||
~~~~
|
||||
|
||||
Description
|
||||
^^^^^^^^^^^
|
||||
|
||||
Move file pointer for file described by given `file descriptor` of given
|
||||
`offset` related to `whence`.
|
||||
|
||||
Parameters
|
||||
^^^^^^^^^^
|
||||
|
||||
======== ============================================================
|
||||
uint32_t FunctionID (0x82000030 / 0xC2000030)
|
||||
uint32_t ``SEEK``
|
||||
uint32_t File descriptor id returned by OPEN
|
||||
sint32_t offset in the file relative to whence
|
||||
uint32_t whence
|
||||
======== ============================================================
|
||||
|
||||
whence can be one of:
|
||||
|
||||
========= ============================================================
|
||||
KSEEK_SET 0
|
||||
KSEEK_CUR 1
|
||||
KSEEK_END 2
|
||||
========= ============================================================
|
||||
|
||||
Return values
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
=============== ==========================================================
|
||||
int32_t w0 == SMC_OK on success
|
||||
|
||||
w0 == DEBUGFS_E_INVALID_PARAMS if seek operation failed
|
||||
=============== ==========================================================
|
||||
|
||||
BIND
|
||||
~~~~
|
||||
|
||||
Description
|
||||
^^^^^^^^^^^
|
||||
|
||||
Create a link from `oldpath` to `newpath`.
|
||||
|
||||
Parameters
|
||||
^^^^^^^^^^
|
||||
|
||||
======== ============================================================
|
||||
uint32_t FunctionID (0x82000030 / 0xC2000030)
|
||||
uint32_t ``BIND``
|
||||
======== ============================================================
|
||||
|
||||
Return values
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
=============== ==========================================================
|
||||
int32_t w0 == SMC_OK on success
|
||||
|
||||
w0 == DEBUGFS_E_INVALID_PARAMS if bind operation failed
|
||||
=============== ==========================================================
|
||||
|
||||
STAT
|
||||
~~~~
|
||||
|
||||
Description
|
||||
^^^^^^^^^^^
|
||||
|
||||
Perform a stat operation on provided file `name` and returns the directory
|
||||
entry statistics into `dir`.
|
||||
|
||||
Parameters
|
||||
^^^^^^^^^^
|
||||
|
||||
======== ============================================================
|
||||
uint32_t FunctionID (0x82000030 / 0xC2000030)
|
||||
uint32_t ``STAT``
|
||||
======== ============================================================
|
||||
|
||||
Return values
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
=============== ==========================================================
|
||||
int32_t w0 == SMC_OK on success
|
||||
|
||||
w0 == DEBUGFS_E_INVALID_PARAMS if stat operation failed
|
||||
=============== ==========================================================
|
||||
|
||||
INIT
|
||||
~~~~
|
||||
|
||||
Description
|
||||
^^^^^^^^^^^
|
||||
Initial call to setup the shared exchange buffer. Notice if successful once,
|
||||
subsequent calls fail after a first initialization. The caller maps the same
|
||||
page frame in its virtual space and uses this buffer to exchange string
|
||||
parameters with filesystem primitives.
|
||||
|
||||
Parameters
|
||||
^^^^^^^^^^
|
||||
|
||||
======== ============================================================
|
||||
uint32_t FunctionID (0x82000030 / 0xC2000030)
|
||||
uint32_t ``INIT``
|
||||
uint64_t Physical address of the shared buffer.
|
||||
======== ============================================================
|
||||
|
||||
Return values
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
=============== ======================================================
|
||||
int32_t w0 == SMC_OK on success
|
||||
|
||||
w0 == DEBUGFS_E_INVALID_PARAMS if already initialized,
|
||||
or internal error occurred.
|
||||
=============== ======================================================
|
||||
|
||||
VERSION
|
||||
~~~~~~~
|
||||
|
||||
Description
|
||||
^^^^^^^^^^^
|
||||
Returns the debugfs interface version if implemented in TF-A.
|
||||
|
||||
Parameters
|
||||
^^^^^^^^^^
|
||||
|
||||
======== ============================================================
|
||||
uint32_t FunctionID (0x82000030 / 0xC2000030)
|
||||
uint32_t ``VERSION``
|
||||
======== ============================================================
|
||||
|
||||
Return values
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
=============== ======================================================
|
||||
int32_t w0 == SMC_OK on success
|
||||
|
||||
w0 == SMC_UNK if interface is not implemented
|
||||
|
||||
uint32_t w1: On success, debugfs interface version, 32 bits
|
||||
value with major version number in upper 16 bits and
|
||||
minor version in lower 16 bits.
|
||||
=============== ======================================================
|
||||
|
||||
* CREATE(1) and WRITE (5) command identifiers are unimplemented and
|
||||
return `SMC_UNK`.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
|
||||
332
arm-trusted-firmware/docs/components/cot-binding.rst
Normal file
332
arm-trusted-firmware/docs/components/cot-binding.rst
Normal file
@@ -0,0 +1,332 @@
|
||||
Chain of trust bindings
|
||||
=======================
|
||||
|
||||
The device tree allows to describe the chain of trust with the help of
|
||||
'cot' node which contain 'manifests' and 'images' as sub-nodes.
|
||||
'manifests' and 'images' nodes contains number of sub-nodes (i.e. 'certificate'
|
||||
and 'image' nodes) mentioning properties of the certificate and image respectively.
|
||||
|
||||
Also, device tree describes 'non-volatile-counters' node which contains number of
|
||||
sub-nodes mentioning properties of all non-volatile-counters used in the chain of trust.
|
||||
|
||||
cot
|
||||
------------------------------------------------------------------
|
||||
This is root node which contains 'manifests' and 'images' as sub-nodes
|
||||
|
||||
|
||||
Manifests and Certificate node bindings definition
|
||||
----------------------------------------------------------------
|
||||
|
||||
- Manifests node
|
||||
Description: Container of certificate nodes.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
|
||||
Value type: <string>
|
||||
|
||||
Definition: must be "arm, cert-descs"
|
||||
|
||||
- Certificate node
|
||||
Description:
|
||||
|
||||
Describes certificate properties which are used
|
||||
during the authentication process.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- root-certificate
|
||||
Usage:
|
||||
|
||||
Required for the certificate with no parent.
|
||||
In other words, certificates which are validated
|
||||
using root of trust public key.
|
||||
|
||||
Value type: <boolean>
|
||||
|
||||
- image-id
|
||||
Usage: Required for every certificate with unique id.
|
||||
|
||||
Value type: <u32>
|
||||
|
||||
- parent
|
||||
Usage:
|
||||
|
||||
It refers to their parent image, which typically contains
|
||||
information to authenticate the certificate.
|
||||
This property is required for all non-root certificates.
|
||||
|
||||
This property is not required for root-certificates
|
||||
as root-certificates are validated using root of trust
|
||||
public key provided by platform.
|
||||
|
||||
Value type: <phandle>
|
||||
|
||||
- signing-key
|
||||
Usage:
|
||||
|
||||
This property is used to refer public key node present in
|
||||
parent certificate node and it is required property for all
|
||||
non-root certificates which are authenticated using public-key
|
||||
present in parent certificate.
|
||||
|
||||
This property is not required for root-certificates
|
||||
as root-certificates are validated using root of trust
|
||||
public key provided by platform.
|
||||
|
||||
Value type: <phandle>
|
||||
|
||||
- antirollback-counter
|
||||
Usage:
|
||||
|
||||
This property is used by all certificates which are
|
||||
protected against rollback attacks using a non-volatile
|
||||
counter and it is an optional property.
|
||||
|
||||
This property is used to refer one of the non-volatile
|
||||
counter sub-node present in 'non-volatile counters' node.
|
||||
|
||||
Value type: <phandle>
|
||||
|
||||
|
||||
SUBNODES
|
||||
- Description:
|
||||
|
||||
Hash and public key information present in the certificate
|
||||
are shown by these nodes.
|
||||
|
||||
- public key node
|
||||
Description: Provide public key information in the certificate.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- oid
|
||||
Usage:
|
||||
|
||||
This property provides the Object ID of public key
|
||||
provided in the certificate which the help of which
|
||||
public key information can be extracted.
|
||||
|
||||
Value type: <string>
|
||||
|
||||
- hash node
|
||||
Description: Provide the hash information in the certificate.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- oid
|
||||
Usage:
|
||||
|
||||
This property provides the Object ID of hash provided in
|
||||
the certificate which the help of which hash information
|
||||
can be extracted.
|
||||
|
||||
Value type: <string>
|
||||
|
||||
Example:
|
||||
|
||||
.. code:: c
|
||||
|
||||
cot {
|
||||
manifests {
|
||||
compatible = "arm, cert-descs”
|
||||
|
||||
trusted-key-cert: trusted-key-cert {
|
||||
root-certificate;
|
||||
image-id = <TRUSTED_KEY_CERT_ID>;
|
||||
antirollback-counter = <&trusted_nv_counter>;
|
||||
|
||||
trusted-world-pk: trusted-world-pk {
|
||||
oid = TRUSTED_WORLD_PK_OID;
|
||||
};
|
||||
non-trusted-world-pk: non-trusted-world-pk {
|
||||
oid = NON_TRUSTED_WORLD_PK_OID;
|
||||
};
|
||||
};
|
||||
|
||||
scp_fw_key_cert: scp_fw_key_cert {
|
||||
image-id = <SCP_FW_KEY_CERT_ID>;
|
||||
parent = <&trusted-key-cert>;
|
||||
signing-key = <&trusted_world_pk>;
|
||||
antirollback-counter = <&trusted_nv_counter>;
|
||||
|
||||
scp_fw_content_pk: scp_fw_content_pk {
|
||||
oid = SCP_FW_CONTENT_CERT_PK_OID;
|
||||
};
|
||||
};
|
||||
.
|
||||
.
|
||||
.
|
||||
|
||||
next-certificate {
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Images and Image node bindings definition
|
||||
-----------------------------------------
|
||||
|
||||
- Images node
|
||||
Description: Container of image nodes
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
|
||||
Value type: <string>
|
||||
|
||||
Definition: must be "arm, img-descs"
|
||||
|
||||
- Image node
|
||||
Description:
|
||||
|
||||
Describes image properties which will be used during
|
||||
authentication process.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- image-id
|
||||
Usage: Required for every image with unique id.
|
||||
|
||||
Value type: <u32>
|
||||
|
||||
- parent
|
||||
Usage:
|
||||
|
||||
Required for every image to provide a reference to
|
||||
its parent image, which contains the necessary information
|
||||
to authenticate it.
|
||||
|
||||
Value type: <phandle>
|
||||
|
||||
- hash
|
||||
Usage:
|
||||
|
||||
Required for all images which are validated using
|
||||
hash method. This property is used to refer hash
|
||||
node present in parent certificate node.
|
||||
|
||||
Value type: <phandle>
|
||||
|
||||
Note:
|
||||
|
||||
Currently, all images are validated using 'hash'
|
||||
method. In future, there may be multiple methods can
|
||||
be used to validate the image.
|
||||
|
||||
Example:
|
||||
|
||||
.. code:: c
|
||||
|
||||
cot {
|
||||
images {
|
||||
compatible = "arm, img-descs";
|
||||
|
||||
scp_bl2_image {
|
||||
image-id = <SCP_BL2_IMAGE_ID>;
|
||||
parent = <&scp_fw_content_cert>;
|
||||
hash = <&scp_fw_hash>;
|
||||
};
|
||||
|
||||
.
|
||||
.
|
||||
.
|
||||
|
||||
next-img {
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
non-volatile counter node binding definition
|
||||
--------------------------------------------
|
||||
|
||||
- non-volatile counters node
|
||||
Description: Contains properties for non-volatile counters.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
|
||||
Value type: <string>
|
||||
|
||||
Definition: must be "arm, non-volatile-counter"
|
||||
|
||||
- #address-cells
|
||||
Usage: required
|
||||
|
||||
Value type: <u32>
|
||||
|
||||
Definition:
|
||||
|
||||
Must be set according to address size
|
||||
of non-volatile counter register
|
||||
|
||||
- #size-cells
|
||||
Usage: required
|
||||
|
||||
Value type: <u32>
|
||||
|
||||
Definition: must be set to 0
|
||||
|
||||
SUBNODE
|
||||
- counters node
|
||||
Description: Contains various non-volatile counters present in the platform.
|
||||
|
||||
PROPERTIES
|
||||
- id
|
||||
Usage: Required for every nv-counter with unique id.
|
||||
|
||||
Value type: <u32>
|
||||
|
||||
- reg
|
||||
Usage:
|
||||
|
||||
Register base address of non-volatile counter and it is required
|
||||
property.
|
||||
|
||||
Value type: <u32>
|
||||
|
||||
- oid
|
||||
Usage:
|
||||
|
||||
This property provides the Object ID of non-volatile counter
|
||||
provided in the certificate and it is required property.
|
||||
|
||||
Value type: <string>
|
||||
|
||||
Example:
|
||||
Below is non-volatile counters example for ARM platform
|
||||
|
||||
.. code:: c
|
||||
|
||||
non_volatile_counters: non_volatile_counters {
|
||||
compatible = "arm, non-volatile-counter";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
trusted-nv-counter: trusted_nv_counter {
|
||||
id = <TRUSTED_NV_CTR_ID>;
|
||||
reg = <TFW_NVCTR_BASE>;
|
||||
oid = TRUSTED_FW_NVCOUNTER_OID;
|
||||
};
|
||||
|
||||
non_trusted_nv_counter: non_trusted_nv_counter {
|
||||
id = <NON_TRUSTED_NV_CTR_ID>;
|
||||
reg = <NTFW_CTR_BASE>;
|
||||
oid = NON_TRUSTED_FW_NVCOUNTER_OID;
|
||||
};
|
||||
};
|
||||
|
||||
Future update to chain of trust binding
|
||||
---------------------------------------
|
||||
|
||||
This binding document needs to be revisited to generalise some terminologies
|
||||
which are currently specific to X.509 certificates for e.g. Object IDs.
|
||||
|
||||
*Copyright (c) 2020, Arm Limited. All rights reserved.*
|
||||
125
arm-trusted-firmware/docs/components/debugfs-design.rst
Normal file
125
arm-trusted-firmware/docs/components/debugfs-design.rst
Normal file
@@ -0,0 +1,125 @@
|
||||
========
|
||||
Debug FS
|
||||
========
|
||||
|
||||
.. contents::
|
||||
|
||||
Overview
|
||||
--------
|
||||
|
||||
The *DebugFS* feature is primarily aimed at exposing firmware debug data to
|
||||
higher SW layers such as a non-secure component. Such component can be the
|
||||
TFTF test payload or a Linux kernel module.
|
||||
|
||||
Virtual filesystem
|
||||
------------------
|
||||
|
||||
The core functionality lies in a virtual file system based on a 9p file server
|
||||
interface (`Notes on the Plan 9 Kernel Source`_ and
|
||||
`Linux 9p remote filesystem protocol`_).
|
||||
The implementation permits exposing virtual files, firmware drivers, and file blobs.
|
||||
|
||||
Namespace
|
||||
~~~~~~~~~
|
||||
|
||||
Two namespaces are exposed:
|
||||
|
||||
- # is used as root for drivers (e.g. #t0 is the first uart)
|
||||
- / is used as root for virtual "files" (e.g. /fip, or /dev/uart)
|
||||
|
||||
9p interface
|
||||
~~~~~~~~~~~~
|
||||
|
||||
The associated primitives are:
|
||||
|
||||
- Unix-like:
|
||||
|
||||
- open(): create a file descriptor that acts as a handle to the file passed as
|
||||
an argument.
|
||||
- close(): close the file descriptor created by open().
|
||||
- read(): read from a file to a buffer.
|
||||
- write(): write from a buffer to a file.
|
||||
- seek(): set the file position indicator of a file descriptor either to a
|
||||
relative or an absolute offset.
|
||||
- stat(): get information about a file (type, mode, size, ...).
|
||||
|
||||
.. code:: c
|
||||
|
||||
int open(const char *name, int flags);
|
||||
int close(int fd);
|
||||
int read(int fd, void *buf, int n);
|
||||
int write(int fd, void *buf, int n);
|
||||
int seek(int fd, long off, int whence);
|
||||
int stat(char *path, dir_t *dir);
|
||||
|
||||
- Specific primitives :
|
||||
|
||||
- mount(): create a link between a driver and spec.
|
||||
- create(): create a file in a specific location.
|
||||
- bind(): expose the content of a directory to another directory.
|
||||
|
||||
.. code:: c
|
||||
|
||||
int mount(char *srv, char *mnt, char *spec);
|
||||
int create(const char *name, int flags);
|
||||
int bind(char *path, char *where);
|
||||
|
||||
This interface is embedded into the BL31 run-time payload when selected by build
|
||||
options. The interface multiplexes drivers or emulated "files":
|
||||
|
||||
- Debug data can be partitioned into different virtual files e.g. expose PMF
|
||||
measurements through a file, and internal firmware state counters through
|
||||
another file.
|
||||
- This permits direct access to a firmware driver, mainly for test purposes
|
||||
(e.g. a hardware device that may not be accessible to non-privileged/
|
||||
non-secure layers, or for which no support exists in the NS side).
|
||||
|
||||
SMC interface
|
||||
-------------
|
||||
|
||||
The communication with the 9p layer in BL31 is made through an SMC conduit
|
||||
(`SMC Calling Convention`_), using a specific SiP Function Id. An NS
|
||||
shared buffer is used to pass path string parameters, or e.g. to exchange
|
||||
data on a read operation. Refer to :ref:`ARM SiP Services <arm sip services>`
|
||||
for a description of the SMC interface.
|
||||
|
||||
Security considerations
|
||||
-----------------------
|
||||
|
||||
- Due to the nature of the exposed data, the feature is considered experimental
|
||||
and importantly **shall only be used in debug builds**.
|
||||
- Several primitive imply string manipulations and usage of string formats.
|
||||
- Special care is taken with the shared buffer to avoid TOCTOU attacks.
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
- In order to setup the shared buffer, the component consuming the interface
|
||||
needs to allocate a physical page frame and transmit its address.
|
||||
- In order to map the shared buffer, BL31 requires enabling the dynamic xlat
|
||||
table option.
|
||||
- Data exchange is limited by the shared buffer length. A large read operation
|
||||
might be split into multiple read operations of smaller chunks.
|
||||
- On concurrent access, a spinlock is implemented in the BL31 service to protect
|
||||
the internal work buffer, and re-entrancy into the filesystem layers.
|
||||
- Notice, a physical device driver if exposed by the firmware may conflict with
|
||||
the higher level OS if the latter implements its own driver for the same
|
||||
physical device.
|
||||
|
||||
Applications
|
||||
------------
|
||||
|
||||
The SMC interface is accessible from an NS environment, that is:
|
||||
|
||||
- a test payload, bootloader or hypervisor running at NS-EL2
|
||||
- a Linux kernel driver running at NS-EL1
|
||||
- a Linux userspace application through the kernel driver
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
|
||||
.. _Notes on the Plan 9 Kernel Source: http://lsub.org/who/nemo/9.pdf
|
||||
.. _Linux 9p remote filesystem protocol: https://www.kernel.org/doc/Documentation/filesystems/9p.txt
|
||||
.. _ARM SiP Services: arm-sip-service.rst
|
||||
597
arm-trusted-firmware/docs/components/el3-spmc.rst
Normal file
597
arm-trusted-firmware/docs/components/el3-spmc.rst
Normal file
@@ -0,0 +1,597 @@
|
||||
EL3 Secure Partition Manager
|
||||
****************************
|
||||
|
||||
.. contents::
|
||||
|
||||
Foreword
|
||||
========
|
||||
|
||||
This document describes the design of the EL3 SPMC based on the FF-A specification.
|
||||
EL3 SPMC provides reference FF-A compliant implementation without S-EL2 virtualization support,
|
||||
to help adopt and migrate to FF-A early.
|
||||
EL3 SPMC implementation in TF-A:
|
||||
|
||||
- Manages a single S-EL1 Secure Partition
|
||||
- Provides a standard protocol for communication and memory sharing between FF-A endpoints.
|
||||
- Provides support for EL3 Logical Partitions to support easy migration from EL3 to S-EL1.
|
||||
|
||||
Sample reference stack
|
||||
======================
|
||||
|
||||
The following diagram illustrates a possible configuration when the
|
||||
FEAT_SEL2 architecture extension is not implemented, showing the SPMD
|
||||
and SPMC at EL3, one S-EL1 secure partition, with an optional
|
||||
Hypervisor:
|
||||
|
||||
.. image:: ../resources/diagrams/ff-a-spm-at-el3.png
|
||||
|
||||
TF-A build options
|
||||
==================
|
||||
|
||||
This section explains the TF-A build options involved in building
|
||||
an FF-A based SPM where the SPMD and SPMC are located at EL3:
|
||||
|
||||
- **SPD=spmd**: this option selects the SPMD component to relay the FF-A
|
||||
protocol from NWd to SWd back and forth. It is not possible to
|
||||
enable another Secure Payload Dispatcher when this option is chosen.
|
||||
- **SPMC_AT_EL3**: this option adjusts the SPMC exception level to being
|
||||
at EL3.
|
||||
- **ARM_SPMC_MANIFEST_DTS**: this option specifies a manifest file
|
||||
providing SP description. It is required when
|
||||
``SPMC_AT_EL3`` is enabled, the secure partitions are loaded
|
||||
by BL2 on behalf of the SPMC.
|
||||
|
||||
Notes:
|
||||
|
||||
- BL32 option is re-purposed to specify the S-EL1 TEE or SP image.
|
||||
BL32 option can be omitted if using TF-A Test Secure Payload as SP.
|
||||
- BL33 option can specify the TFTF binary or a normal world loader
|
||||
such as U-Boot or the UEFI framework payload.
|
||||
|
||||
Sample TF-A build command line when the SPMC is located at EL3:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make \
|
||||
CROSS_COMPILE=aarch64-none-elf- \
|
||||
SPD=spmd \
|
||||
SPMD_SPM_AT_SEL2=0 \
|
||||
SPMC_AT_EL3=1 \
|
||||
BL32=<path-to-tee-binary> (opt for TSP) \
|
||||
BL33=<path-to-bl33-binary> \
|
||||
PLAT=fvp \
|
||||
all fip
|
||||
|
||||
FVP model invocation
|
||||
====================
|
||||
|
||||
Sample FVP command line invocation:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to-fvp-model>/FVP_Base_RevC-2xAEMvA -C pctl.startup=0.0.0.0 \
|
||||
-C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \
|
||||
-C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \
|
||||
-C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \
|
||||
-C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \
|
||||
-C bp.pl011_uart2.out_file=fvp-uart2.log -C bp.vis.disable_visualisation=1
|
||||
|
||||
|
||||
Platform Guide
|
||||
==============
|
||||
|
||||
- Platform Hooks See - `[4]`_
|
||||
|
||||
- plat_spmc_shmem_begin
|
||||
- plat_spmc_shmem_reclaim
|
||||
|
||||
SPMC provides platform hooks related to memory management interfaces.
|
||||
These hooks can be used for platform specific implementations like
|
||||
for managing access control, programming TZ Controller or MPUs.
|
||||
These hooks are called by SPMC before the initial share request completes,
|
||||
and after the final reclaim has been completed.
|
||||
|
||||
- Datastore
|
||||
|
||||
- plat_spmc_shmem_datastore_get
|
||||
|
||||
EL3 SPMC uses datastore for tracking memory transaction descriptors.
|
||||
On FVP platform datastore is allocated from TZC DRAM section.
|
||||
Other platforms need to allocate a similar secure memory region
|
||||
to be used as shared memory datastore.
|
||||
|
||||
The accessor function is used during SPMC initialization to obtain
|
||||
address and size of the datastore.
|
||||
SPMC will also zero out the provided memory region.
|
||||
|
||||
- Platform Defines See - `[5]`_
|
||||
|
||||
- SECURE_PARTITION_COUNT
|
||||
Number of Secure Partitions supported: must be 1.
|
||||
|
||||
- NS_PARTITION_COUNT
|
||||
Number of NWd Partitions supported.
|
||||
|
||||
- MAX_EL3_LP_DESCS_COUNT
|
||||
Number of Logical Partitions supported.
|
||||
|
||||
Logical Secure Partition (LSP)
|
||||
==============================
|
||||
|
||||
- The SPMC provides support for statically allocated EL3 Logical Secure Partitions
|
||||
as per FF-A v1.1 specification.
|
||||
- The DECLARE_LOGICAL_PARTITION macro can be used to add a LSP.
|
||||
- For reference implementation See - `[2]`_
|
||||
|
||||
.. image:: ../resources/diagrams/ff-a-lsp-at-el3.png
|
||||
|
||||
SPMC boot
|
||||
=========
|
||||
|
||||
The SPMD and SPMC are built into the BL31 image along with TF-A's runtime components.
|
||||
BL2 loads the BL31 image as a part of (secure) boot process.
|
||||
|
||||
The SPMC manifest is loaded by BL2 as the ``TOS_FW_CONFIG`` image `[9]`_.
|
||||
|
||||
BL2 passes the SPMC manifest address to BL31 through a register.
|
||||
|
||||
At boot time, the SPMD in BL31 runs from the primary core, initializes the core
|
||||
contexts and launches the SPMC passing the following information through
|
||||
registers:
|
||||
|
||||
- X0 holds the SPMC manifest blob address.
|
||||
- X4 holds the currently running core linear id.
|
||||
|
||||
Parsing SP partition manifests
|
||||
------------------------------
|
||||
|
||||
SPMC consumes the SP manifest, as defined in `[7]`_.
|
||||
SP manifest fields align with Hafnium SP manifest for easy porting.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
compatible = "arm,ffa-manifest-1.0";
|
||||
|
||||
ffa-version = <0x00010001>; /* 31:16 - Major, 15:0 - Minor */
|
||||
id = <0x8001>;
|
||||
uuid = <0x6b43b460 0x74a24b78 0xade24502 0x40682886>;
|
||||
messaging-method = <0x3>; /* Direct Messaging Only */
|
||||
exception-level = <0x2>; /* S-EL1 */
|
||||
execution-state = <0>;
|
||||
execution-ctx-count = <8>;
|
||||
gp-register-num = <0>;
|
||||
power-management-messages = <0x7>;
|
||||
|
||||
|
||||
Passing boot data to the SP
|
||||
---------------------------
|
||||
|
||||
In `[1]`_ , the section "Boot information protocol" defines a method for passing
|
||||
data to the SPs at boot time. It specifies the format for the boot information
|
||||
descriptor and boot information header structures, which describe the data to be
|
||||
exchanged between SPMC and SP.
|
||||
The specification also defines the types of data that can be passed.
|
||||
The aggregate of both the boot info structures and the data itself is designated
|
||||
the boot information blob, and is passed to a Partition as a contiguous memory
|
||||
region.
|
||||
|
||||
Currently, the SPM implementation supports the FDT type which is used to pass the
|
||||
partition's DTB manifest.
|
||||
|
||||
The region for the boot information blob is statically allocated (4K) by SPMC.
|
||||
BLOB contains Boot Info Header, followed by SP Manifest contents.
|
||||
|
||||
The configuration of the boot protocol is done in the SP manifest. As defined by
|
||||
the specification, the manifest field 'gp-register-num' configures the GP register
|
||||
which shall be used to pass the address to the partitions boot information blob when
|
||||
booting the partition.
|
||||
|
||||
Supported interfaces
|
||||
====================
|
||||
|
||||
The following interfaces are exposed to SPs only:
|
||||
|
||||
- ``FFA_MSG_WAIT``
|
||||
- ``FFA_MEM_RETRIEVE_REQ``
|
||||
- ``FFA_MEM_RETRIEVE_RESP``
|
||||
- ``FFA_MEM_RELINQUISH``
|
||||
- ``FFA_SECONDARY_EP_REGISTER``
|
||||
|
||||
The following interfaces are exposed to both NS Client and SPs:
|
||||
|
||||
- ``FFA_VERSION``
|
||||
- ``FFA_FEATURES``
|
||||
- ``FFA_RX_RELEASE``
|
||||
- ``FFA_RXTX_MAP``
|
||||
- ``FFA_RXTX_UNMAP``
|
||||
- ``FFA_PARTITION_INFO_GET``
|
||||
- ``FFA_ID_GET``
|
||||
- ``FFA_MSG_SEND_DIRECT_REQ``
|
||||
- ``FFA_MSG_SEND_DIRECT_RESP``
|
||||
- ``FFA_MEM_FRAG_TX``
|
||||
- ``FFA_SPM_ID_GET``
|
||||
|
||||
The following additional interfaces are forwarded from SPMD to support NS Client:
|
||||
|
||||
- ``FFA_RUN``
|
||||
- ``FFA_MEM_LEND``
|
||||
- ``FFA_MEM_SHARE``
|
||||
- ``FFA_MEM_FRAG_RX``
|
||||
- ``FFA_MEM_RECLAIM``
|
||||
|
||||
|
||||
FFA_VERSION
|
||||
-----------
|
||||
|
||||
``FFA_VERSION`` requires a *requested_version* parameter from the caller.
|
||||
SPMD forwards call to SPMC, the SPMC returns its own implemented version.
|
||||
SPMC asserts SP and SPMC are at same FF-A Version.
|
||||
|
||||
FFA_FEATURES
|
||||
------------
|
||||
|
||||
FF-A features supported by the SPMC may be discovered by secure partitions at
|
||||
boot (that is prior to NWd is booted) or run-time.
|
||||
|
||||
The SPMC calling FFA_FEATURES at secure physical FF-A instance always get
|
||||
FFA_SUCCESS from the SPMD.
|
||||
|
||||
The request made by an Hypervisor or OS kernel is forwarded to the SPMC and
|
||||
the response relayed back to the NWd.
|
||||
|
||||
|
||||
FFA_RXTX_MAP
|
||||
------------
|
||||
|
||||
FFA_RXTX_UNMAP
|
||||
--------------
|
||||
|
||||
When invoked from a secure partition FFA_RXTX_MAP maps the provided send and
|
||||
receive buffers described by their PAs to the EL3 translation regime
|
||||
as secure buffers in the MMU descriptors.
|
||||
|
||||
When invoked from the Hypervisor or OS kernel, the buffers are mapped into the
|
||||
SPMC EL3 translation regime and marked as NS buffers in the MMU
|
||||
descriptors.
|
||||
|
||||
The FFA_RXTX_UNMAP unmaps the RX/TX pair from the translation regime of the
|
||||
caller, either it being the Hypervisor or OS kernel, as well as a secure
|
||||
partition.
|
||||
|
||||
FFA_PARTITION_INFO_GET
|
||||
----------------------
|
||||
|
||||
Partition info get call can originate:
|
||||
|
||||
- from SP to SPMC
|
||||
- from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD.
|
||||
|
||||
The format (v1.0 or v1.1) of the populated data structure returned is based upon the
|
||||
FFA version of the calling entity.
|
||||
|
||||
EL3 SPMC also supports returning only the count of partitions deployed.
|
||||
|
||||
All LSPs and SP are discoverable from FFA_PARTITION_INFO_GET call made by
|
||||
either SP or NWd entities.
|
||||
|
||||
FFA_ID_GET
|
||||
----------
|
||||
|
||||
The FF-A ID space is split into a non-secure space and secure space:
|
||||
|
||||
- FF-A ID with bit 15 clear relates to VMs.
|
||||
- FF-A ID with bit 15 set related to SPs or LSPs.
|
||||
- FF-A IDs 0, 0xffff, 0x8000 are assigned respectively to the Hypervisor
|
||||
(or OS Kernel if Hyp is absent), SPMD and SPMC.
|
||||
|
||||
This convention helps the SPM to determine the origin and destination worlds in
|
||||
an FF-A ABI invocation. In particular the SPM shall filter unauthorized
|
||||
transactions in its world switch routine. It must not be permitted for a VM to
|
||||
use a secure FF-A ID as origin world by spoofing:
|
||||
|
||||
- A VM-to-SP direct request/response shall set the origin world to be non-secure
|
||||
(FF-A ID bit 15 clear) and destination world to be secure (FF-A ID bit 15
|
||||
set).
|
||||
- Similarly, an SP-to-LSP direct request/response shall set the FF-A ID bit 15
|
||||
for both origin and destination IDs.
|
||||
|
||||
An incoming direct message request arriving at SPMD from NWd is forwarded to
|
||||
SPMC without a specific check. The SPMC is resumed through eret and "knows" the
|
||||
message is coming from normal world in this specific code path. Thus the origin
|
||||
endpoint ID must be checked by SPMC for being a normal world ID.
|
||||
|
||||
An SP sending a direct message request must have bit 15 set in its origin
|
||||
endpoint ID and this can be checked by the SPMC when the SP invokes the ABI.
|
||||
|
||||
The SPMC shall reject the direct message if the claimed world in origin endpoint
|
||||
ID is not consistent:
|
||||
|
||||
- It is either forwarded by SPMD and thus origin endpoint ID must be a "normal
|
||||
world ID",
|
||||
- or initiated by an SP and thus origin endpoint ID must be a "secure world ID".
|
||||
|
||||
|
||||
FFA_MSG_SEND_DIRECT_REQ
|
||||
-----------------------
|
||||
|
||||
FFA_MSG_SEND_DIRECT_RESP
|
||||
------------------------
|
||||
|
||||
This is a mandatory interface for secure partitions participating in direct request
|
||||
and responses with the following rules:
|
||||
|
||||
- An SP can send a direct request to LSP.
|
||||
- An LSP can send a direct response to SP.
|
||||
- An SP cannot send a direct request to an Hypervisor or OS kernel.
|
||||
- An Hypervisor or OS kernel can send a direct request to an SP or LSP.
|
||||
- An SP and LSP can send a direct response to an Hypervisor or OS kernel.
|
||||
- SPMD can send direct request to SPMC.
|
||||
|
||||
FFA_SPM_ID_GET
|
||||
--------------
|
||||
|
||||
Returns the FF-A ID allocated to an SPM component which can be one of SPMD
|
||||
or SPMC.
|
||||
|
||||
At initialization, the SPMC queries the SPMD for the SPMC ID, using the
|
||||
FFA_ID_GET interface, and records it. The SPMC can also query the SPMD ID using
|
||||
the FFA_SPM_ID_GET interface at the secure physical FF-A instance.
|
||||
|
||||
Secure partitions call this interface at the virtual FF-A instance, to which
|
||||
the SPMC returns the SPMC ID.
|
||||
|
||||
The Hypervisor or OS kernel can issue the FFA_SPM_ID_GET call handled by the
|
||||
SPMD, which returns the SPMC ID.
|
||||
|
||||
FFA_ID_GET
|
||||
----------
|
||||
|
||||
Returns the FF-A ID of the calling endpoint.
|
||||
|
||||
FFA_MEM_SHARE
|
||||
-------------
|
||||
|
||||
FFA_MEM_LEND
|
||||
------------
|
||||
|
||||
- If SP is borrower in the memory transaction, these calls are forwarded to SPMC.
|
||||
SPMC performs Relayer responsibilities, caches the memory descriptors in the datastore,
|
||||
and allocates FF-A memory handle.
|
||||
- If format of descriptor was v1.0, SPMC converts the descriptor to v1.1 before caching.
|
||||
In case of fragmented sharing, conversion of memory descriptors happens after last
|
||||
fragment has been received.
|
||||
- Multiple borrowers (including NWd endpoint) and fragmented memory sharing are supported.
|
||||
|
||||
FFA_MEM_RETRIEVE_REQ
|
||||
--------------------
|
||||
|
||||
FFA_MEM_RETRIEVE_RESP
|
||||
---------------------
|
||||
|
||||
- Memory retrieve is supported only from SP.
|
||||
- SPMC fetches the cached memory descriptor from the datastore,
|
||||
- Performs Relayer responsiilities and sends FFA_MEM_RETRIEVE_RESP back to SP.
|
||||
- If descriptor size is more than RX buffer size, SPMC will send the descriptor in fragments.
|
||||
- SPMC will set NS Bit to 1 in memory descriptor response.
|
||||
|
||||
FFA_MEM_FRAG_RX
|
||||
---------------
|
||||
|
||||
FFA_MEM_FRAG_TX
|
||||
---------------
|
||||
|
||||
FFA_MEM_FRAG_RX is to be used by:
|
||||
|
||||
- SP if FFA_MEM_RETRIEVE_RESP returned descriptor with fragment length less than total length.
|
||||
- or by SPMC if FFA_MEM_SHARE/FFA_MEM_LEND is called with fragment length less than total length.
|
||||
|
||||
SPMC validates handle and Endpoint ID and returns response with FFA_MEM_FRAG_TX.
|
||||
|
||||
FFA_SECONDARY_EP_REGISTER
|
||||
-------------------------
|
||||
|
||||
When the SPMC boots, secure partition is initialized on its primary
|
||||
Execution Context.
|
||||
|
||||
The FFA_SECONDARY_EP_REGISTER interface is to be used by a secure partition
|
||||
from its first execution context, to provide the entry point address for
|
||||
secondary execution contexts.
|
||||
|
||||
A secondary EC is first resumed either upon invocation of PSCI_CPU_ON from
|
||||
the NWd or by invocation of FFA_RUN.
|
||||
|
||||
Power management
|
||||
================
|
||||
|
||||
In platforms with or without secure virtualization:
|
||||
|
||||
- The NWd owns the platform PM policy.
|
||||
- The Hypervisor or OS kernel is the component initiating PSCI service calls.
|
||||
- The EL3 PSCI library is in charge of the PM coordination and control
|
||||
(eventually writing to platform registers).
|
||||
- While coordinating PM events, the PSCI library calls backs into the Secure
|
||||
Payload Dispatcher for events the latter has statically registered to.
|
||||
|
||||
When using the SPMD as a Secure Payload Dispatcher:
|
||||
|
||||
- A power management event is relayed through the SPD hook to the SPMC.
|
||||
- In the current implementation CPU_ON (svc_on_finish), CPU_OFF
|
||||
(svc_off), CPU_SUSPEND (svc_suspend) and CPU_SUSPEND_RESUME (svc_suspend_finish)
|
||||
hooks are registered.
|
||||
|
||||
Secure partitions scheduling
|
||||
============================
|
||||
|
||||
The FF-A specification `[1]`_ provides two ways to relinquinsh CPU time to
|
||||
secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of:
|
||||
|
||||
- the FFA_MSG_SEND_DIRECT_REQ interface.
|
||||
- the FFA_RUN interface.
|
||||
|
||||
Additionally a secure interrupt can pre-empt the normal world execution and give
|
||||
CPU cycles by transitioning to EL3.
|
||||
|
||||
Partition Runtime State and Model
|
||||
=================================
|
||||
|
||||
EL3 SPMC implements Partition runtime states are described in v1.1 FF-A specification `[1]`_
|
||||
|
||||
An SP can be in one of the following state:
|
||||
|
||||
- RT_STATE_WAITING
|
||||
- RT_STATE_RUNNING
|
||||
- RT_STATE_PREEMPTED
|
||||
- RT_STATE_BLOCKED
|
||||
|
||||
An SP will transition to one of the following runtime model when not in waiting state:
|
||||
|
||||
- RT_MODEL_DIR_REQ
|
||||
- RT_MODEL_RUN
|
||||
- RT_MODEL_INIT
|
||||
- RT_MODEL_INTR
|
||||
|
||||
Platform topology
|
||||
=================
|
||||
|
||||
SPMC only supports a single Pinned MP S-EL1 SP. The *execution-ctx-count*
|
||||
SP manifest field should match the number of physical PE.
|
||||
|
||||
Interrupt handling
|
||||
==================
|
||||
|
||||
Secure Interrupt handling
|
||||
-------------------------
|
||||
|
||||
- SPMC is capable of forwarding Secure interrupt to S-EL1 SP
|
||||
which has preempted the normal world.
|
||||
- Interrupt is forwarded to SP using FFA_INTERRUPT interface.
|
||||
- Interrupt Number is not passed, S-EL1 SP can access the GIC registers directly.
|
||||
- Upon completion of Interrupt handling SP is expected to return to
|
||||
SPMC using FFA_MSG_WAIT interface.
|
||||
- SPMC returns to normal world after interrupt handling is completed.
|
||||
|
||||
In the scenario when secure interrupt occurs while the secure partition is running,
|
||||
the SPMC is not involved and the handling is implementation defined in the TOS.
|
||||
|
||||
Non-Secure Interrupt handling
|
||||
-----------------------------
|
||||
|
||||
The 'managed exit' scenario is the responsibility of the TOS and the SPMC is not involved.
|
||||
|
||||
Test Secure Payload (TSP)
|
||||
=========================
|
||||
|
||||
- TSP provides reference implementation of FF-A programming model.
|
||||
- TSP has the following support:
|
||||
|
||||
- SP initialization on all CPUs.
|
||||
- Consuming Power Messages including CPU_ON, CPU_OFF, CPU_SUSPEND, CPU_SUSPEND_RESUME.
|
||||
- Event Loop to receive Direct Requests.
|
||||
- Sending Direct Response.
|
||||
- Memory Sharing helper library.
|
||||
- Ability to handle secure interrupt (timer).
|
||||
|
||||
TSP Tests in CI
|
||||
---------------
|
||||
|
||||
- TSP Tests are exercised in the TF-A CI using prebuilt FF-A Linux Test driver in NWd.
|
||||
- Expected output:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
#ioctl 255
|
||||
Test: Echo Message to SP.
|
||||
Status: Completed Test Case: 1
|
||||
Test Executed Successfully
|
||||
|
||||
Test: Message Relay vis SP to EL3 LSP.
|
||||
Status: Completed Test Case: 2
|
||||
Test Executed Successfully
|
||||
|
||||
Test: Memory Send.
|
||||
Verified 1 constituents successfully
|
||||
Status: Completed Test Case: 3
|
||||
Test Executed Successfully
|
||||
|
||||
Test: Memory Send in Fragments.
|
||||
Verified 256 constituents successfully
|
||||
Status: Completed Test Case: 4
|
||||
Test Executed Successfully
|
||||
|
||||
Test: Memory Lend.
|
||||
Verified 1 constituents successfully
|
||||
Status: Completed Test Case: 5
|
||||
Test Executed Successfully
|
||||
|
||||
Test: Memory Lend in Fragments.
|
||||
Verified 256 constituents successfully
|
||||
Status: Completed Test Case: 6
|
||||
Test Executed Successfully
|
||||
|
||||
Test: Memory Send with Multiple Endpoints.
|
||||
random: fast init done
|
||||
Verified 256 constituents successfully
|
||||
Status: Completed Test Case: 7
|
||||
Test Executed Successfully
|
||||
|
||||
Test: Memory Lend with Multiple Endpoints.
|
||||
Verified 256 constituents successfully
|
||||
Status: Completed Test Case: 8
|
||||
Test Executed Successfully
|
||||
|
||||
Test: Ensure Duplicate Memory Send Requests are Rejected.
|
||||
Status: Completed Test Case: 9
|
||||
Test Executed Successfully
|
||||
|
||||
Test: Ensure Duplicate Memory Lend Requests are Rejected.
|
||||
Status: Completed Test Case: 10
|
||||
Test Executed Successfully
|
||||
|
||||
0 Tests Failed
|
||||
|
||||
Exiting Test Application - Total Failures: 0
|
||||
|
||||
|
||||
References
|
||||
==========
|
||||
|
||||
.. _[1]:
|
||||
|
||||
[1] `Arm Firmware Framework for Arm A-profile <https://developer.arm.com/docs/den0077/latest>`__
|
||||
|
||||
.. _[2]:
|
||||
|
||||
[2] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fvp_el3_spmc_logical_sp.c
|
||||
|
||||
.. _[3]:
|
||||
|
||||
[3] `Trusted Boot Board Requirements
|
||||
Client <https://developer.arm.com/documentation/den0006/d/>`__
|
||||
|
||||
.. _[4]:
|
||||
|
||||
[4] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fvp_el3_spmc.c
|
||||
|
||||
.. _[5]:
|
||||
|
||||
[5] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/include/platform_def.h
|
||||
|
||||
.. _[6]:
|
||||
|
||||
[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html
|
||||
|
||||
.. _[7]:
|
||||
|
||||
[7] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts
|
||||
|
||||
.. _[8]:
|
||||
|
||||
[8] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/CFQFGU6H2D5GZYMUYGTGUSXIU3OYZP6U/
|
||||
|
||||
.. _[9]:
|
||||
|
||||
[9] https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#dynamic-configuration-during-cold-boot
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.*
|
||||
619
arm-trusted-firmware/docs/components/exception-handling.rst
Normal file
619
arm-trusted-firmware/docs/components/exception-handling.rst
Normal file
@@ -0,0 +1,619 @@
|
||||
Exception Handling Framework
|
||||
============================
|
||||
|
||||
This document describes various aspects of handling exceptions by Runtime
|
||||
Firmware (BL31) that are targeted at EL3, other than SMCs. The |EHF| takes care
|
||||
of the following exceptions when targeted at EL3:
|
||||
|
||||
- Interrupts
|
||||
- Synchronous External Aborts
|
||||
- Asynchronous External Aborts
|
||||
|
||||
|TF-A|'s handling of synchronous ``SMC`` exceptions raised from lower ELs is
|
||||
described in the :ref:`Firmware Design document <handling-an-smc>`. However, the
|
||||
|EHF| changes the semantics of `Interrupt handling`_ and :ref:`synchronous
|
||||
exceptions <Effect on SMC calls>` other than SMCs.
|
||||
|
||||
The |EHF| is selected by setting the build option ``EL3_EXCEPTION_HANDLING`` to
|
||||
``1``, and is only available for AArch64 systems.
|
||||
|
||||
Introduction
|
||||
------------
|
||||
|
||||
Through various control bits in the ``SCR_EL3`` register, the Arm architecture
|
||||
allows for asynchronous exceptions to be routed to EL3. As described in the
|
||||
:ref:`Interrupt Management Framework` document, depending on the chosen
|
||||
interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of
|
||||
``SCR_EL3`` register to effect this routing. For most use cases, other than for
|
||||
the purpose of facilitating context switch between Normal and Secure worlds,
|
||||
FIQs and IRQs routed to EL3 are not required to be handled in EL3.
|
||||
|
||||
However, the evolving system and standards landscape demands that various
|
||||
exceptions are targeted at and handled in EL3. For instance:
|
||||
|
||||
- Starting with ARMv8.2 architecture extension, many RAS features have been
|
||||
introduced to the Arm architecture. With RAS features implemented, various
|
||||
components of the system may use one of the asynchronous exceptions to signal
|
||||
error conditions to PEs. These error conditions are of critical nature, and
|
||||
it's imperative that corrective or remedial actions are taken at the earliest
|
||||
opportunity. Therefore, a *Firmware-first Handling* approach is generally
|
||||
followed in response to RAS events in the system.
|
||||
|
||||
- The Arm `SDEI specification`_ defines interfaces through which Normal world
|
||||
interacts with the Runtime Firmware in order to request notification of
|
||||
system events. The |SDEI| specification requires that these events are
|
||||
notified even when the Normal world executes with the exceptions masked. This
|
||||
too implies that firmware-first handling is required, where the events are
|
||||
first received by the EL3 firmware, and then dispatched to Normal world
|
||||
through purely software mechanism.
|
||||
|
||||
For |TF-A|, firmware-first handling means that asynchronous exceptions are
|
||||
suitably routed to EL3, and the Runtime Firmware (BL31) is extended to include
|
||||
software components that are capable of handling those exceptions that target
|
||||
EL3. These components—referred to as *dispatchers* [#spd]_ in general—may
|
||||
choose to:
|
||||
|
||||
.. _delegation-use-cases:
|
||||
|
||||
- Receive and handle exceptions entirely in EL3, meaning the exceptions
|
||||
handling terminates in EL3.
|
||||
|
||||
- Receive exceptions, but handle part of the exception in EL3, and delegate the
|
||||
rest of the handling to a dedicated software stack running at lower Secure
|
||||
ELs. In this scheme, the handling spans various secure ELs.
|
||||
|
||||
- Receive exceptions, but handle part of the exception in EL3, and delegate
|
||||
processing of the error to dedicated software stack running at lower secure
|
||||
ELs (as above); additionally, the Normal world may also be required to
|
||||
participate in the handling, or be notified of such events (for example, as
|
||||
an |SDEI| event). In this scheme, exception handling potentially and
|
||||
maximally spans all ELs in both Secure and Normal worlds.
|
||||
|
||||
On any given system, all of the above handling models may be employed
|
||||
independently depending on platform choice and the nature of the exception
|
||||
received.
|
||||
|
||||
.. [#spd] Not to be confused with :ref:`Secure Payload Dispatcher
|
||||
<firmware_design_sel1_spd>`, which is an EL3 component that operates in EL3
|
||||
on behalf of Secure OS.
|
||||
|
||||
The role of Exception Handling Framework
|
||||
----------------------------------------
|
||||
|
||||
Corollary to the use cases cited above, the primary role of the |EHF| is to
|
||||
facilitate firmware-first handling of exceptions on Arm systems. The |EHF| thus
|
||||
enables multiple exception dispatchers in runtime firmware to co-exist, register
|
||||
for, and handle exceptions targeted at EL3. This section outlines the basics,
|
||||
and the rest of this document expands the various aspects of the |EHF|.
|
||||
|
||||
In order to arbitrate exception handling among dispatchers, the |EHF| operation
|
||||
is based on a priority scheme. This priority scheme is closely tied to how the
|
||||
Arm GIC architecture defines it, although it's applied to non-interrupt
|
||||
exceptions too (SErrors, for example).
|
||||
|
||||
The platform is required to `partition`__ the Secure priority space into
|
||||
priority levels as applicable for the Secure software stack. It then assigns the
|
||||
dispatchers to one or more priority levels. The dispatchers then register
|
||||
handlers for the priority levels at runtime. A dispatcher can register handlers
|
||||
for more than one priority level.
|
||||
|
||||
.. __: `Partitioning priority levels`_
|
||||
|
||||
|
||||
.. _ehf-figure:
|
||||
|
||||
.. image:: ../resources/diagrams/draw.io/ehf.svg
|
||||
|
||||
A priority level is *active* when a handler at that priority level is currently
|
||||
executing in EL3, or has delegated the execution to a lower EL. For interrupts,
|
||||
this is implicit when an interrupt is targeted and acknowledged at EL3, and the
|
||||
priority of the acknowledged interrupt is used to match its registered handler.
|
||||
The priority level is likewise implicitly deactivated when the interrupt
|
||||
handling concludes by EOIing the interrupt.
|
||||
|
||||
Non-interrupt exceptions (SErrors, for example) don't have a notion of priority.
|
||||
In order for the priority arbitration to work, the |EHF| provides APIs in order
|
||||
for these non-interrupt exceptions to assume a priority, and to interwork with
|
||||
interrupts. Dispatchers handling such exceptions must therefore explicitly
|
||||
activate and deactivate the respective priority level as and when they're
|
||||
handled or delegated.
|
||||
|
||||
Because priority activation and deactivation for interrupt handling is implicit
|
||||
and involves GIC priority masking, it's impossible for a lower priority
|
||||
interrupt to preempt a higher priority one. By extension, this means that a
|
||||
lower priority dispatcher cannot preempt a higher-priority one. Priority
|
||||
activation and deactivation for non-interrupt exceptions, however, has to be
|
||||
explicit. The |EHF| therefore disallows for lower priority level to be activated
|
||||
whilst a higher priority level is active, and would result in a panic.
|
||||
Likewise, a panic would result if it's attempted to deactivate a lower priority
|
||||
level when a higher priority level is active.
|
||||
|
||||
In essence, priority level activation and deactivation conceptually works like a
|
||||
stack—priority levels stack up in strictly increasing fashion, and need to be
|
||||
unstacked in strictly the reverse order. For interrupts, the GIC ensures this is
|
||||
the case; for non-interrupts, the |EHF| monitors and asserts this. See
|
||||
`Transition of priority levels`_.
|
||||
|
||||
.. _interrupt-handling:
|
||||
|
||||
Interrupt handling
|
||||
------------------
|
||||
|
||||
The |EHF| is a client of *Interrupt Management Framework*, and registers the
|
||||
top-level handler for interrupts that target EL3, as described in the
|
||||
:ref:`Interrupt Management Framework` document. This has the following
|
||||
implications:
|
||||
|
||||
- On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of
|
||||
sufficient priority are signalled as FIQs, and therefore will be routed to
|
||||
EL3. As a result, S-EL1 software cannot expect to handle Non-secure
|
||||
interrupts at S-EL1. Essentially, this deprecates the routing mode described
|
||||
as :ref:`CSS=0, TEL3=0 <EL3 interrupts>`.
|
||||
|
||||
In order for S-EL1 software to handle Non-secure interrupts while having
|
||||
|EHF| enabled, the dispatcher must adopt a model where Non-secure interrupts
|
||||
are received at EL3, but are then :ref:`synchronously <sp-synchronous-int>`
|
||||
handled over to S-EL1.
|
||||
|
||||
- On GICv2 systems, it's required that the build option ``GICV2_G0_FOR_EL3`` is
|
||||
set to ``1`` so that *Group 0* interrupts target EL3.
|
||||
|
||||
- While executing in Secure world, |EHF| sets GIC Priority Mask Register to the
|
||||
lowest Secure priority. This means that no Non-secure interrupts can preempt
|
||||
Secure execution. See `Effect on SMC calls`_ for more details.
|
||||
|
||||
As mentioned above, with |EHF|, the platform is required to partition *Group 0*
|
||||
interrupts into distinct priority levels. A dispatcher that chooses to receive
|
||||
interrupts can then *own* one or more priority levels, and register interrupt
|
||||
handlers for them. A given priority level can be assigned to only one handler. A
|
||||
dispatcher may register more than one priority level.
|
||||
|
||||
Dispatchers are assigned interrupt priority levels in two steps:
|
||||
|
||||
.. _Partitioning priority levels:
|
||||
|
||||
Partitioning priority levels
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Interrupts are associated to dispatchers by way of grouping and assigning
|
||||
interrupts to a priority level. In other words, all interrupts that are to
|
||||
target a particular dispatcher should fall in a particular priority level. For
|
||||
priority assignment:
|
||||
|
||||
- Of the 8 bits of priority that Arm GIC architecture permits, bit 7 must be 0
|
||||
(secure space).
|
||||
|
||||
- Depending on the number of dispatchers to support, the platform must choose
|
||||
to use the top *n* of the 7 remaining bits to identify and assign interrupts
|
||||
to individual dispatchers. Choosing *n* bits supports up to 2\ :sup:`n`
|
||||
distinct dispatchers. For example, by choosing 2 additional bits (i.e., bits
|
||||
6 and 5), the platform can partition into 4 secure priority ranges: ``0x0``,
|
||||
``0x20``, ``0x40``, and ``0x60``. See `Interrupt handling example`_.
|
||||
|
||||
.. note::
|
||||
|
||||
The Arm GIC architecture requires that a GIC implementation that supports two
|
||||
security states must implement at least 32 priority levels; i.e., at least 5
|
||||
upper bits of the 8 bits are writeable. In the scheme described above, when
|
||||
choosing *n* bits for priority range assignment, the platform must ensure
|
||||
that at least ``n+1`` top bits of GIC priority are writeable.
|
||||
|
||||
The priority thus assigned to an interrupt is also used to determine the
|
||||
priority of delegated execution in lower ELs. Delegated execution in lower EL is
|
||||
associated with a priority level chosen with ``ehf_activate_priority()`` API
|
||||
(described `later`__). The chosen priority level also determines the interrupts
|
||||
masked while executing in a lower EL, therefore controls preemption of delegated
|
||||
execution.
|
||||
|
||||
.. __: `ehf-apis`_
|
||||
|
||||
The platform expresses the chosen priority levels by declaring an array of
|
||||
priority level descriptors. Each entry in the array is of type
|
||||
``ehf_pri_desc_t``, and declares a priority level, and shall be populated by the
|
||||
``EHF_PRI_DESC()`` macro.
|
||||
|
||||
.. warning::
|
||||
|
||||
The macro ``EHF_PRI_DESC()`` installs the descriptors in the array at a
|
||||
computed index, and not necessarily where the macro is placed in the array.
|
||||
The size of the array might therefore be larger than what it appears to be.
|
||||
The ``ARRAY_SIZE()`` macro therefore should be used to determine the size of
|
||||
array.
|
||||
|
||||
Finally, this array of descriptors is exposed to |EHF| via the
|
||||
``EHF_REGISTER_PRIORITIES()`` macro.
|
||||
|
||||
Refer to the `Interrupt handling example`_ for usage. See also: `Interrupt
|
||||
Prioritisation Considerations`_.
|
||||
|
||||
Programming priority
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The text in `Partitioning priority levels`_ only describes how the platform
|
||||
expresses the required levels of priority. It however doesn't choose interrupts
|
||||
nor program the required priority in GIC.
|
||||
|
||||
The :ref:`Firmware Design guide<configuring-secure-interrupts>` explains methods
|
||||
for configuring secure interrupts. |EHF| requires the platform to enumerate
|
||||
interrupt properties (as opposed to just numbers) of Secure interrupts. The
|
||||
priority of secure interrupts must match that as determined in the
|
||||
`Partitioning priority levels`_ section above.
|
||||
|
||||
See `Limitations`_, and also refer to `Interrupt handling example`_ for
|
||||
illustration.
|
||||
|
||||
Registering handler
|
||||
-------------------
|
||||
|
||||
Dispatchers register handlers for their priority levels through the following
|
||||
API:
|
||||
|
||||
.. code:: c
|
||||
|
||||
int ehf_register_priority_handler(int pri, ehf_handler_t handler)
|
||||
|
||||
The API takes two arguments:
|
||||
|
||||
- The priority level for which the handler is being registered;
|
||||
|
||||
- The handler to be registered. The handler must be aligned to 4 bytes.
|
||||
|
||||
If a dispatcher owns more than one priority levels, it has to call the API for
|
||||
each of them.
|
||||
|
||||
The API will succeed, and return ``0``, only if:
|
||||
|
||||
- There exists a descriptor with the priority level requested.
|
||||
|
||||
- There are no handlers already registered by a previous call to the API.
|
||||
|
||||
Otherwise, the API returns ``-1``.
|
||||
|
||||
The interrupt handler should have the following signature:
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef int (*ehf_handler_t)(uint32_t intr_raw, uint32_t flags, void *handle,
|
||||
void *cookie);
|
||||
|
||||
The parameters are as obtained from the top-level :ref:`EL3 interrupt handler
|
||||
<el3-runtime-firmware>`.
|
||||
|
||||
The :ref:`SDEI dispatcher<SDEI: Software Delegated Exception Interface>`, for
|
||||
example, expects the platform to allocate two different priority levels—
|
||||
``PLAT_SDEI_CRITICAL_PRI``, and ``PLAT_SDEI_NORMAL_PRI`` —and registers the
|
||||
same handler to handle both levels.
|
||||
|
||||
Interrupt handling example
|
||||
--------------------------
|
||||
|
||||
The following annotated snippet demonstrates how a platform might choose to
|
||||
assign interrupts to fictitious dispatchers:
|
||||
|
||||
.. code:: c
|
||||
|
||||
#include <common/interrupt_props.h>
|
||||
#include <drivers/arm/gic_common.h>
|
||||
#include <exception_mgmt.h>
|
||||
|
||||
...
|
||||
|
||||
/*
|
||||
* This platform uses 2 bits for interrupt association. In total, 3 upper
|
||||
* bits are in use.
|
||||
*
|
||||
* 7 6 5 3 0
|
||||
* .-.-.-.----------.
|
||||
* |0|b|b| ..0.. |
|
||||
* '-'-'-'----------'
|
||||
*/
|
||||
#define PLAT_PRI_BITS 2
|
||||
|
||||
/* Priorities for individual dispatchers */
|
||||
#define DISP0_PRIO 0x00 /* Not used */
|
||||
#define DISP1_PRIO 0x20
|
||||
#define DISP2_PRIO 0x40
|
||||
#define DISP3_PRIO 0x60
|
||||
|
||||
/* Install priority level descriptors for each dispatcher */
|
||||
ehf_pri_desc_t plat_exceptions[] = {
|
||||
EHF_PRI_DESC(PLAT_PRI_BITS, DISP1_PRIO),
|
||||
EHF_PRI_DESC(PLAT_PRI_BITS, DISP2_PRIO),
|
||||
EHF_PRI_DESC(PLAT_PRI_BITS, DISP3_PRIO),
|
||||
};
|
||||
|
||||
/* Expose priority descriptors to Exception Handling Framework */
|
||||
EHF_REGISTER_PRIORITIES(plat_exceptions, ARRAY_SIZE(plat_exceptions),
|
||||
PLAT_PRI_BITS);
|
||||
|
||||
...
|
||||
|
||||
/* List interrupt properties for GIC driver. All interrupts target EL3 */
|
||||
const interrupt_prop_t plat_interrupts[] = {
|
||||
/* Dispatcher 1 owns interrupts d1_0 and d1_1, so assigns priority DISP1_PRIO */
|
||||
INTR_PROP_DESC(d1_0, DISP1_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(d1_1, DISP1_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL),
|
||||
|
||||
/* Dispatcher 2 owns interrupts d2_0 and d2_1, so assigns priority DISP2_PRIO */
|
||||
INTR_PROP_DESC(d2_0, DISP2_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(d2_1, DISP2_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL),
|
||||
|
||||
/* Dispatcher 3 owns interrupts d3_0 and d3_1, so assigns priority DISP3_PRIO */
|
||||
INTR_PROP_DESC(d3_0, DISP3_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL),
|
||||
INTR_PROP_DESC(d3_1, DISP3_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL),
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
/* Dispatcher 1 registers its handler */
|
||||
ehf_register_priority_handler(DISP1_PRIO, disp1_handler);
|
||||
|
||||
/* Dispatcher 2 registers its handler */
|
||||
ehf_register_priority_handler(DISP2_PRIO, disp2_handler);
|
||||
|
||||
/* Dispatcher 3 registers its handler */
|
||||
ehf_register_priority_handler(DISP3_PRIO, disp3_handler);
|
||||
|
||||
...
|
||||
|
||||
See also the `Build-time flow`_ and the `Run-time flow`_.
|
||||
|
||||
.. _Activating and Deactivating priorities:
|
||||
|
||||
Activating and Deactivating priorities
|
||||
--------------------------------------
|
||||
|
||||
A priority level is said to be *active* when an exception of that priority is
|
||||
being handled: for interrupts, this is implied when the interrupt is
|
||||
acknowledged; for non-interrupt exceptions, such as SErrors or :ref:`SDEI
|
||||
explicit dispatches <explicit-dispatch-of-events>`, this has to be done via
|
||||
calling ``ehf_activate_priority()``. See `Run-time flow`_.
|
||||
|
||||
Conversely, when the dispatcher has reached a logical resolution for the cause
|
||||
of the exception, the corresponding priority level ought to be deactivated. As
|
||||
above, for interrupts, this is implied when the interrupt is EOId in the GIC;
|
||||
for other exceptions, this has to be done via calling
|
||||
``ehf_deactivate_priority()``.
|
||||
|
||||
Thanks to `different provisions`__ for exception delegation, there are
|
||||
potentially more than one work flow for deactivation:
|
||||
|
||||
.. __: `delegation-use-cases`_
|
||||
|
||||
.. _deactivation workflows:
|
||||
|
||||
- The dispatcher has addressed the cause of the exception, and decided to take
|
||||
no further action. In this case, the dispatcher's handler deactivates the
|
||||
priority level before returning to the |EHF|. Runtime firmware, upon exit
|
||||
through an ``ERET``, resumes execution before the interrupt occurred.
|
||||
|
||||
- The dispatcher has to delegate the execution to lower ELs, and the cause of
|
||||
the exception can be considered resolved only when the lower EL returns
|
||||
signals complete (via an ``SMC``) at a future point in time. The following
|
||||
sequence ensues:
|
||||
|
||||
#. The dispatcher calls ``setjmp()`` to setup a jump point, and arranges to
|
||||
enter a lower EL upon the next ``ERET``.
|
||||
|
||||
#. Through the ensuing ``ERET`` from runtime firmware, execution is delegated
|
||||
to a lower EL.
|
||||
|
||||
#. The lower EL completes its execution, and signals completion via an
|
||||
``SMC``.
|
||||
|
||||
#. The ``SMC`` is handled by the same dispatcher that handled the exception
|
||||
previously. Noticing the conclusion of exception handling, the dispatcher
|
||||
does ``longjmp()`` to resume beyond the previous jump point.
|
||||
|
||||
As mentioned above, the |EHF| provides the following APIs for activating and
|
||||
deactivating interrupt:
|
||||
|
||||
.. _ehf-apis:
|
||||
|
||||
- ``ehf_activate_priority()`` activates the supplied priority level, but only
|
||||
if the current active priority is higher than the given one; otherwise
|
||||
panics. Also, to prevent interruption by physical interrupts of lower
|
||||
priority, the |EHF| programs the *Priority Mask Register* corresponding to
|
||||
the PE to the priority being activated. Dispatchers typically only need to
|
||||
call this when handling exceptions other than interrupts, and it needs to
|
||||
delegate execution to a lower EL at a desired priority level.
|
||||
|
||||
- ``ehf_deactivate_priority()`` deactivates a given priority, but only if the
|
||||
current active priority is equal to the given one; otherwise panics. |EHF|
|
||||
also restores the *Priority Mask Register* corresponding to the PE to the
|
||||
priority before the call to ``ehf_activate_priority()``. Dispatchers
|
||||
typically only need to call this after handling exceptions other than
|
||||
interrupts.
|
||||
|
||||
The calling of APIs are subject to allowed `transitions`__. See also the
|
||||
`Run-time flow`_.
|
||||
|
||||
.. __: `Transition of priority levels`_
|
||||
|
||||
Transition of priority levels
|
||||
-----------------------------
|
||||
|
||||
The |EHF| APIs ``ehf_activate_priority()`` and ``ehf_deactivate_priority()`` can
|
||||
be called to transition the current priority level on a PE. A given sequence of
|
||||
calls to these APIs are subject to the following conditions:
|
||||
|
||||
- For activation, the |EHF| only allows for the priority to increase (i.e.
|
||||
numeric value decreases);
|
||||
|
||||
- For deactivation, the |EHF| only allows for the priority to decrease (i.e.
|
||||
numeric value increases). Additionally, the priority being deactivated is
|
||||
required to be the current priority.
|
||||
|
||||
If these are violated, a panic will result.
|
||||
|
||||
.. _Effect on SMC calls:
|
||||
|
||||
Effect on SMC calls
|
||||
-------------------
|
||||
|
||||
In general, Secure execution is regarded as more important than Non-secure
|
||||
execution. As discussed elsewhere in this document, EL3 execution, and any
|
||||
delegated execution thereafter, has the effect of raising GIC's priority
|
||||
mask—either implicitly by acknowledging Secure interrupts, or when dispatchers
|
||||
call ``ehf_activate_priority()``. As a result, Non-secure interrupts cannot
|
||||
preempt any Secure execution.
|
||||
|
||||
SMCs from Non-secure world are synchronous exceptions, and are mechanisms for
|
||||
Non-secure world to request Secure services. They're broadly classified as
|
||||
*Fast* or *Yielding* (see `SMCCC`__).
|
||||
|
||||
.. __: https://developer.arm.com/docs/den0028/latest
|
||||
|
||||
- *Fast* SMCs are atomic from the caller's point of view. I.e., they return
|
||||
to the caller only when the Secure world has finished serving the request.
|
||||
Any Non-secure interrupts that become pending meanwhile cannot preempt Secure
|
||||
execution.
|
||||
|
||||
- *Yielding* SMCs carry the semantics of a preemptible, lower-priority request.
|
||||
A pending Non-secure interrupt can preempt Secure execution handling a
|
||||
Yielding SMC. I.e., the caller might observe a Yielding SMC returning when
|
||||
either:
|
||||
|
||||
#. Secure world completes the request, and the caller would find ``SMC_OK``
|
||||
as the return code.
|
||||
|
||||
#. A Non-secure interrupt preempts Secure execution. Non-secure interrupt is
|
||||
handled, and Non-secure execution resumes after ``SMC`` instruction.
|
||||
|
||||
The dispatcher handling a Yielding SMC must provide a different return code
|
||||
to the Non-secure caller to distinguish the latter case. This return code,
|
||||
however, is not standardised (unlike ``SMC_UNKNOWN`` or ``SMC_OK``, for
|
||||
example), so will vary across dispatchers that handle the request.
|
||||
|
||||
For the latter case above, dispatchers before |EHF| expect Non-secure interrupts
|
||||
to be taken to S-EL1 [#irq]_, so would get a chance to populate the designated
|
||||
preempted error code before yielding to Non-secure world.
|
||||
|
||||
The introduction of |EHF| changes the behaviour as described in `Interrupt
|
||||
handling`_.
|
||||
|
||||
When |EHF| is enabled, in order to allow Non-secure interrupts to preempt
|
||||
Yielding SMC handling, the dispatcher must call ``ehf_allow_ns_preemption()``
|
||||
API. The API takes one argument, the error code to be returned to the Non-secure
|
||||
world upon getting preempted.
|
||||
|
||||
.. [#irq] In case of GICv2, Non-secure interrupts while in S-EL1 were signalled
|
||||
as IRQs, and in case of GICv3, FIQs.
|
||||
|
||||
Build-time flow
|
||||
---------------
|
||||
|
||||
Please refer to the `figure`__ above.
|
||||
|
||||
.. __: `ehf-figure`_
|
||||
|
||||
The build-time flow involves the following steps:
|
||||
|
||||
#. Platform assigns priorities by installing priority level descriptors for
|
||||
individual dispatchers, as described in `Partitioning priority levels`_.
|
||||
|
||||
#. Platform provides interrupt properties to GIC driver, as described in
|
||||
`Programming priority`_.
|
||||
|
||||
#. Dispatcher calling ``ehf_register_priority_handler()`` to register an
|
||||
interrupt handler.
|
||||
|
||||
Also refer to the `Interrupt handling example`_.
|
||||
|
||||
Run-time flow
|
||||
-------------
|
||||
|
||||
.. _interrupt-flow:
|
||||
|
||||
The following is an example flow for interrupts:
|
||||
|
||||
#. The GIC driver, during initialization, iterates through the platform-supplied
|
||||
interrupt properties (see `Programming priority`_), and configures the
|
||||
interrupts. This programs the appropriate priority and group (Group 0) on
|
||||
interrupts belonging to different dispatchers.
|
||||
|
||||
#. The |EHF|, during its initialisation, registers a top-level interrupt handler
|
||||
with the :ref:`Interrupt Management Framework<el3-runtime-firmware>` for EL3
|
||||
interrupts. This also results in setting the routing bits in ``SCR_EL3``.
|
||||
|
||||
#. When an interrupt belonging to a dispatcher fires, GIC raises an EL3/Group 0
|
||||
interrupt, and is taken to EL3.
|
||||
|
||||
#. The top-level EL3 interrupt handler executes. The handler acknowledges the
|
||||
interrupt, reads its *Running Priority*, and from that, determines the
|
||||
dispatcher handler.
|
||||
|
||||
#. The |EHF| programs the *Priority Mask Register* of the PE to the priority of
|
||||
the interrupt received.
|
||||
|
||||
#. The |EHF| marks that priority level *active*, and jumps to the dispatcher
|
||||
handler.
|
||||
|
||||
#. Once the dispatcher handler finishes its job, it has to immediately
|
||||
*deactivate* the priority level before returning to the |EHF|. See
|
||||
`deactivation workflows`_.
|
||||
|
||||
.. _non-interrupt-flow:
|
||||
|
||||
The following is an example flow for exceptions that targets EL3 other than
|
||||
interrupt:
|
||||
|
||||
#. The platform provides handlers for the specific kind of exception.
|
||||
|
||||
#. The exception arrives, and the corresponding handler is executed.
|
||||
|
||||
#. The handler calls ``ehf_activate_priority()`` to activate the required
|
||||
priority level. This also has the effect of raising GIC priority mask, thus
|
||||
preventing interrupts of lower priority from preempting the handling. The
|
||||
handler may choose to do the handling entirely in EL3 or delegate to a lower
|
||||
EL.
|
||||
|
||||
#. Once exception handling concludes, the handler calls
|
||||
``ehf_deactivate_priority()`` to deactivate the priority level activated
|
||||
earlier. This also has the effect of lowering GIC priority mask to what it
|
||||
was before.
|
||||
|
||||
Interrupt Prioritisation Considerations
|
||||
---------------------------------------
|
||||
|
||||
The GIC priority scheme, by design, prioritises Secure interrupts over Normal
|
||||
world ones. The platform further assigns relative priorities amongst Secure
|
||||
dispatchers through |EHF|.
|
||||
|
||||
As mentioned in `Partitioning priority levels`_, interrupts targeting distinct
|
||||
dispatchers fall in distinct priority levels. Because they're routed via the
|
||||
GIC, interrupt delivery to the PE is subject to GIC prioritisation rules. In
|
||||
particular, when an interrupt is being handled by the PE (i.e., the interrupt is
|
||||
in *Active* state), only interrupts of higher priority are signalled to the PE,
|
||||
even if interrupts of same or lower priority are pending. This has the side
|
||||
effect of one dispatcher being starved of interrupts by virtue of another
|
||||
dispatcher handling its (higher priority) interrupts.
|
||||
|
||||
The |EHF| doesn't enforce a particular prioritisation policy, but the platform
|
||||
should carefully consider the assignment of priorities to dispatchers integrated
|
||||
into runtime firmware. The platform should sensibly delineate priority to
|
||||
various dispatchers according to their nature. In particular, dispatchers of
|
||||
critical nature (RAS, for example) should be assigned higher priority than
|
||||
others (|SDEI|, for example); and within |SDEI|, Critical priority
|
||||
|SDEI| should be assigned higher priority than Normal ones.
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
The |EHF| has the following limitations:
|
||||
|
||||
- Although there could be up to 128 Secure dispatchers supported by the GIC
|
||||
priority scheme, the size of descriptor array exposed with
|
||||
``EHF_REGISTER_PRIORITIES()`` macro is currently limited to 32. This serves most
|
||||
expected use cases. This may be expanded in the future, should use cases
|
||||
demand so.
|
||||
|
||||
- The platform must ensure that the priority assigned to the dispatcher in the
|
||||
exception descriptor and the programmed priority of interrupts handled by the
|
||||
dispatcher match. The |EHF| cannot verify that this has been followed.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _SDEI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
|
||||
142
arm-trusted-firmware/docs/components/fconf/amu-bindings.rst
Normal file
142
arm-trusted-firmware/docs/components/fconf/amu-bindings.rst
Normal file
@@ -0,0 +1,142 @@
|
||||
Activity Monitor Unit (AMU) Bindings
|
||||
====================================
|
||||
|
||||
To support platform-defined Activity Monitor Unit (|AMU|) auxiliary counters
|
||||
through FCONF, the ``HW_CONFIG`` device tree accepts several |AMU|-specific
|
||||
nodes and properties.
|
||||
|
||||
Bindings
|
||||
^^^^^^^^
|
||||
|
||||
.. contents::
|
||||
:local:
|
||||
|
||||
``/cpus/cpus/cpu*`` node properties
|
||||
"""""""""""""""""""""""""""""""""""
|
||||
|
||||
The ``cpu`` node has been augmented to support a handle to an associated |AMU|
|
||||
view, which should describe the counters offered by the core.
|
||||
|
||||
+---------------+-------+---------------+-------------------------------------+
|
||||
| Property name | Usage | Value type | Description |
|
||||
+===============+=======+===============+=====================================+
|
||||
| ``amu`` | O | ``<phandle>`` | If present, indicates that an |AMU| |
|
||||
| | | | is available and its counters are |
|
||||
| | | | described by the node provided. |
|
||||
+---------------+-------+---------------+-------------------------------------+
|
||||
|
||||
``/cpus/amus`` node properties
|
||||
""""""""""""""""""""""""""""""
|
||||
|
||||
The ``amus`` node describes the |AMUs| implemented by the cores in the system.
|
||||
This node does not have any properties.
|
||||
|
||||
``/cpus/amus/amu*`` node properties
|
||||
"""""""""""""""""""""""""""""""""""
|
||||
|
||||
An ``amu`` node describes the layout and meaning of the auxiliary counter
|
||||
registers of one or more |AMUs|, and may be shared by multiple cores.
|
||||
|
||||
+--------------------+-------+------------+------------------------------------+
|
||||
| Property name | Usage | Value type | Description |
|
||||
+====================+=======+============+====================================+
|
||||
| ``#address-cells`` | R | ``<u32>`` | Value shall be 1. Specifies that |
|
||||
| | | | the ``reg`` property array of |
|
||||
| | | | children of this node uses a |
|
||||
| | | | single cell. |
|
||||
+--------------------+-------+------------+------------------------------------+
|
||||
| ``#size-cells`` | R | ``<u32>`` | Value shall be 0. Specifies that |
|
||||
| | | | no size is required in the ``reg`` |
|
||||
| | | | property in children of this node. |
|
||||
+--------------------+-------+------------+------------------------------------+
|
||||
|
||||
``/cpus/amus/amu*/counter*`` node properties
|
||||
""""""""""""""""""""""""""""""""""""""""""""
|
||||
|
||||
A ``counter`` node describes an auxiliary counter belonging to the parent |AMU|
|
||||
view.
|
||||
|
||||
+-------------------+-------+-------------+------------------------------------+
|
||||
| Property name | Usage | Value type | Description |
|
||||
+===================+=======+=============+====================================+
|
||||
| ``reg`` | R | array | Represents the counter register |
|
||||
| | | | index, and must be a single cell. |
|
||||
+-------------------+-------+-------------+------------------------------------+
|
||||
| ``enable-at-el3`` | O | ``<empty>`` | The presence of this property |
|
||||
| | | | indicates that this counter should |
|
||||
| | | | be enabled prior to EL3 exit. |
|
||||
+-------------------+-------+-------------+------------------------------------+
|
||||
|
||||
Example
|
||||
^^^^^^^
|
||||
|
||||
An example system offering four cores made up of two clusters, where the cores
|
||||
of each cluster share different |AMUs|, may use something like the following:
|
||||
|
||||
.. code-block::
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
amus {
|
||||
amu0: amu-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
counterX: counter@0 {
|
||||
reg = <0>;
|
||||
|
||||
enable-at-el3;
|
||||
};
|
||||
|
||||
counterY: counter@1 {
|
||||
reg = <1>;
|
||||
|
||||
enable-at-el3;
|
||||
};
|
||||
};
|
||||
|
||||
amu1: amu-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
counterZ: counter@0 {
|
||||
reg = <0>;
|
||||
|
||||
enable-at-el3;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0@00000 {
|
||||
...
|
||||
|
||||
amu = <&amu0>;
|
||||
};
|
||||
|
||||
cpu1@00100 {
|
||||
...
|
||||
|
||||
amu = <&amu0>;
|
||||
};
|
||||
|
||||
cpu2@10000 {
|
||||
...
|
||||
|
||||
amu = <&amu1>;
|
||||
};
|
||||
|
||||
cpu3@10100 {
|
||||
...
|
||||
|
||||
amu = <&amu1>;
|
||||
};
|
||||
}
|
||||
|
||||
In this situation, ``cpu0`` and ``cpu1`` (the two cores in the first cluster),
|
||||
share the view of their AMUs defined by ``amu0``. Likewise, ``cpu2`` and
|
||||
``cpu3`` (the two cores in the second cluster), share the view of their |AMUs|
|
||||
defined by ``amu1``. This will cause ``counterX`` and ``counterY`` to be enabled
|
||||
for both ``cpu0`` and ``cpu1``, and ``counterZ`` to be enabled for both ``cpu2``
|
||||
and ``cpu3``.
|
||||
@@ -0,0 +1,39 @@
|
||||
DTB binding for FCONF properties
|
||||
================================
|
||||
|
||||
This document describes the device tree format of |FCONF| properties. These
|
||||
properties are not related to a specific platform and can be queried from
|
||||
common code.
|
||||
|
||||
Dynamic configuration
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The |FCONF| framework expects a *dtb-registry* node with the following field:
|
||||
|
||||
- compatible [mandatory]
|
||||
- value type: <string>
|
||||
- Must be the string "fconf,dyn_cfg-dtb_registry".
|
||||
|
||||
Then a list of subnodes representing a configuration |DTB|, which can be used
|
||||
by |FCONF|. Each subnode should be named according to the information it
|
||||
contains, and must be formed with the following fields:
|
||||
|
||||
- load-address [mandatory]
|
||||
- value type: <u64>
|
||||
- Physical loading base address of the configuration.
|
||||
|
||||
- max-size [mandatory]
|
||||
- value type: <u32>
|
||||
- Maximum size of the configuration.
|
||||
|
||||
- id [mandatory]
|
||||
- value type: <u32>
|
||||
- Image ID of the configuration.
|
||||
|
||||
- ns-load-address [optional]
|
||||
- value type: <u64>
|
||||
- Physical loading base address of the configuration in the non-secure
|
||||
memory.
|
||||
Only needed by those configuration files which require being loaded
|
||||
in secure memory (at load-address) as well as in non-secure memory
|
||||
e.g. HW_CONFIG
|
||||
149
arm-trusted-firmware/docs/components/fconf/index.rst
Normal file
149
arm-trusted-firmware/docs/components/fconf/index.rst
Normal file
@@ -0,0 +1,149 @@
|
||||
Firmware Configuration Framework
|
||||
================================
|
||||
|
||||
This document provides an overview of the |FCONF| framework.
|
||||
|
||||
Introduction
|
||||
~~~~~~~~~~~~
|
||||
|
||||
The Firmware CONfiguration Framework (|FCONF|) is an abstraction layer for
|
||||
platform specific data, allowing a "property" to be queried and a value
|
||||
retrieved without the requesting entity knowing what backing store is being used
|
||||
to hold the data.
|
||||
|
||||
It is used to bridge new and old ways of providing platform-specific data.
|
||||
Today, information like the Chain of Trust is held within several, nested
|
||||
platform-defined tables. In the future, it may be provided as part of a device
|
||||
blob, along with the rest of the information about images to load.
|
||||
Introducing this abstraction layer will make migration easier and will preserve
|
||||
functionality for platforms that cannot / don't want to use device tree.
|
||||
|
||||
Accessing properties
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Properties defined in the |FCONF| are grouped around namespaces and
|
||||
sub-namespaces: a.b.property.
|
||||
Examples namespace can be:
|
||||
|
||||
- (|TBBR|) Chain of Trust data: tbbr.cot.trusted_boot_fw_cert
|
||||
- (|TBBR|) dynamic configuration info: tbbr.dyn_config.disable_auth
|
||||
- Arm io policies: arm.io_policies.bl2_image
|
||||
- GICv3 properties: hw_config.gicv3_config.gicr_base
|
||||
|
||||
Properties can be accessed with the ``FCONF_GET_PROPERTY(a,b,property)`` macro.
|
||||
|
||||
Defining properties
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Properties composing the |FCONF| have to be stored in C structures. If
|
||||
properties originate from a different backend source such as a device tree,
|
||||
then the platform has to provide a ``populate()`` function which essentially
|
||||
captures the property and stores them into a corresponding |FCONF| based C
|
||||
structure.
|
||||
|
||||
Such a ``populate()`` function is usually platform specific and is associated
|
||||
with a specific backend source. For example, a populator function which
|
||||
captures the hardware topology of the platform from the HW_CONFIG device tree.
|
||||
Hence each ``populate()`` function must be registered with a specific
|
||||
``config_type`` identifier. It broadly represents a logical grouping of
|
||||
configuration properties which is usually a device tree file.
|
||||
|
||||
Example:
|
||||
- FW_CONFIG: properties related to base address, maximum size and image id
|
||||
of other DTBs etc.
|
||||
- TB_FW: properties related to trusted firmware such as IO policies,
|
||||
mbedtls heap info etc.
|
||||
- HW_CONFIG: properties related to hardware configuration of the SoC
|
||||
such as topology, GIC controller, PSCI hooks, CPU ID etc.
|
||||
|
||||
Hence the ``populate()`` callback must be registered to the (|FCONF|) framework
|
||||
with the ``FCONF_REGISTER_POPULATOR()`` macro. This ensures that the function
|
||||
would be called inside the generic ``fconf_populate()`` function during
|
||||
initialization.
|
||||
|
||||
::
|
||||
|
||||
int fconf_populate_topology(uintptr_t config)
|
||||
{
|
||||
/* read hw config dtb and fill soc_topology struct */
|
||||
}
|
||||
|
||||
FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
|
||||
|
||||
Then, a wrapper has to be provided to match the ``FCONF_GET_PROPERTY()`` macro:
|
||||
|
||||
::
|
||||
|
||||
/* generic getter */
|
||||
#define FCONF_GET_PROPERTY(a,b,property) a##__##b##_getter(property)
|
||||
|
||||
/* my specific getter */
|
||||
#define hw_config__topology_getter(prop) soc_topology.prop
|
||||
|
||||
This second level wrapper can be used to remap the ``FCONF_GET_PROPERTY()`` to
|
||||
anything appropriate: structure, array, function, etc..
|
||||
|
||||
To ensure a good interpretation of the properties, this documentation must
|
||||
explain how the properties are described for a specific backend. Refer to the
|
||||
:ref:`binding-document` section for more information and example.
|
||||
|
||||
Loading the property device tree
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The ``fconf_load_config(image_id)`` must be called to load fw_config and
|
||||
tb_fw_config devices tree containing the properties' values. This must be done
|
||||
after the io layer is initialized, as the |DTB| is stored on an external
|
||||
device (FIP).
|
||||
|
||||
.. uml:: ../../resources/diagrams/plantuml/fconf_bl1_load_config.puml
|
||||
|
||||
Populating the properties
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Once a valid device tree is available, the ``fconf_populate(config)`` function
|
||||
can be used to fill the C data structure with the data from the config |DTB|.
|
||||
This function will call all the ``populate()`` callbacks which have been
|
||||
registered with ``FCONF_REGISTER_POPULATOR()`` as described above.
|
||||
|
||||
.. uml:: ../../resources/diagrams/plantuml/fconf_bl2_populate.puml
|
||||
|
||||
Namespace guidance
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
As mentioned above, properties are logically grouped around namespaces and
|
||||
sub-namespaces. The following concepts should be considered when adding new
|
||||
properties/namespaces.
|
||||
The framework differentiates two types of properties:
|
||||
|
||||
- Properties used inside common code.
|
||||
- Properties used inside platform specific code.
|
||||
|
||||
The first category applies to properties being part of the firmware and shared
|
||||
across multiple platforms. They should be globally accessible and defined
|
||||
inside the ``lib/fconf`` directory. The namespace must be chosen to reflect the
|
||||
feature/data abstracted.
|
||||
|
||||
Example:
|
||||
- |TBBR| related properties: tbbr.cot.bl2_id
|
||||
- Dynamic configuration information: dyn_cfg.dtb_info.hw_config_id
|
||||
|
||||
The second category should represent the majority of the properties defined
|
||||
within the framework: Platform specific properties. They must be accessed only
|
||||
within the platform API and are defined only inside the platform scope. The
|
||||
namespace must contain the platform name under which the properties defined
|
||||
belong.
|
||||
|
||||
Example:
|
||||
- Arm io framework: arm.io_policies.bl31_id
|
||||
|
||||
.. _binding-document:
|
||||
|
||||
Properties binding information
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
fconf_properties
|
||||
amu-bindings
|
||||
mpmm-bindings
|
||||
48
arm-trusted-firmware/docs/components/fconf/mpmm-bindings.rst
Normal file
48
arm-trusted-firmware/docs/components/fconf/mpmm-bindings.rst
Normal file
@@ -0,0 +1,48 @@
|
||||
Maximum Power Mitigation Mechanism (MPMM) Bindings
|
||||
==================================================
|
||||
|
||||
|MPMM| support cannot be determined at runtime by the firmware. Instead, these
|
||||
DTB bindings allow the platform to communicate per-core support for |MPMM| via
|
||||
the ``HW_CONFIG`` device tree blob.
|
||||
|
||||
Bindings
|
||||
^^^^^^^^
|
||||
|
||||
.. contents::
|
||||
:local:
|
||||
|
||||
``/cpus/cpus/cpu*`` node properties
|
||||
"""""""""""""""""""""""""""""""""""
|
||||
|
||||
The ``cpu`` node has been augmented to allow the platform to indicate support
|
||||
for |MPMM| on a given core.
|
||||
|
||||
+-------------------+-------+-------------+------------------------------------+
|
||||
| Property name | Usage | Value type | Description |
|
||||
+===================+=======+=============+====================================+
|
||||
| ``supports-mpmm`` | O | ``<empty>`` | If present, indicates that |MPMM| |
|
||||
| | | | is available on this core. |
|
||||
+-------------------+-------+-------------+------------------------------------+
|
||||
|
||||
Example
|
||||
^^^^^^^
|
||||
|
||||
An example system offering two cores, one with support for |MPMM| and one
|
||||
without, can be described as follows:
|
||||
|
||||
.. code-block::
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0@00000 {
|
||||
...
|
||||
|
||||
supports-mpmm;
|
||||
};
|
||||
|
||||
cpu1@00100 {
|
||||
...
|
||||
};
|
||||
}
|
||||
296
arm-trusted-firmware/docs/components/ffa-manifest-binding.rst
Normal file
296
arm-trusted-firmware/docs/components/ffa-manifest-binding.rst
Normal file
@@ -0,0 +1,296 @@
|
||||
FF-A manifest binding to device tree
|
||||
========================================
|
||||
|
||||
This document defines the nodes and properties used to define a partition,
|
||||
according to the FF-A specification.
|
||||
|
||||
Partition Properties
|
||||
--------------------
|
||||
|
||||
- compatible [mandatory]
|
||||
- value type: <string>
|
||||
- Must be the string "arm,ffa-manifest-X.Y" which specifies the major and
|
||||
minor versions of the device tree binding for the FFA manifest represented
|
||||
by this node. The minor number is incremented if the binding changes in a
|
||||
backwards compatible manner.
|
||||
|
||||
- X is an integer representing the major version number of this document.
|
||||
- Y is an integer representing the minor version number of this document.
|
||||
|
||||
- ffa-version [mandatory]
|
||||
- value type: <u32>
|
||||
- Must be two 16 bits values (X, Y), concatenated as 31:16 -> X,
|
||||
15:0 -> Y, where:
|
||||
|
||||
- X is the major version of FF-A expected by the partition at the FFA
|
||||
instance it will execute.
|
||||
- Y is the minor version of FF-A expected by the partition at the FFA
|
||||
instance it will execute.
|
||||
|
||||
- uuid [mandatory]
|
||||
- value type: <prop-encoded-array>
|
||||
- An array consisting of 4 <u32> values, identifying the UUID of the service
|
||||
implemented by this partition. The UUID format is described in RFC 4122.
|
||||
|
||||
- id
|
||||
- value type: <u32>
|
||||
- Pre-allocated partition ID.
|
||||
|
||||
- auxiliary-id
|
||||
- value type: <u32>
|
||||
- Pre-allocated ID that could be used in memory management transactions.
|
||||
|
||||
- description
|
||||
- value type: <string>
|
||||
- Name of the partition e.g. for debugging purposes.
|
||||
|
||||
- execution-ctx-count [mandatory]
|
||||
- value type: <u32>
|
||||
- Number of vCPUs that a VM or SP wants to instantiate.
|
||||
|
||||
- In the absence of virtualization, this is the number of execution
|
||||
contexts that a partition implements.
|
||||
- If value of this field = 1 and number of PEs > 1 then the partition is
|
||||
treated as UP & migrate capable.
|
||||
- If the value of this field > 1 then the partition is treated as a MP
|
||||
capable partition irrespective of the number of PEs.
|
||||
|
||||
- exception-level [mandatory]
|
||||
- value type: <u32>
|
||||
- The target exception level for the partition:
|
||||
|
||||
- 0x0: EL1
|
||||
- 0x1: S_EL0
|
||||
- 0x2: S_EL1
|
||||
|
||||
- execution-state [mandatory]
|
||||
- value type: <u32>
|
||||
- The target execution state of the partition:
|
||||
|
||||
- 0: AArch64
|
||||
- 1: AArch32
|
||||
|
||||
- load-address
|
||||
- value type: <u64>
|
||||
- Physical base address of the partition in memory. Absence of this field
|
||||
indicates that the partition is position independent and can be loaded at
|
||||
any address chosen at boot time.
|
||||
|
||||
- entrypoint-offset
|
||||
- value type: <u64>
|
||||
- Offset from the base of the partition's binary image to the entry point of
|
||||
the partition. Absence of this field indicates that the entry point is at
|
||||
offset 0x0 from the base of the partition's binary.
|
||||
|
||||
- xlat-granule [mandatory]
|
||||
- value type: <u32>
|
||||
- Translation granule used with the partition:
|
||||
|
||||
- 0x0: 4k
|
||||
- 0x1: 16k
|
||||
- 0x2: 64k
|
||||
|
||||
- boot-order
|
||||
- value type: <u32>
|
||||
- A unique number amongst all partitions that specifies if this partition
|
||||
must be booted before others. The partition with the smaller number will be
|
||||
booted first.
|
||||
|
||||
- rx-tx-buffer
|
||||
- value type: "memory-regions" node
|
||||
- Specific "memory-regions" nodes that describe the RX/TX buffers expected
|
||||
by the partition.
|
||||
The "compatible" must be the string "arm,ffa-manifest-rx_tx-buffer".
|
||||
|
||||
- messaging-method [mandatory]
|
||||
- value type: <u8>
|
||||
- Specifies which messaging methods are supported by the partition, set bit
|
||||
means the feature is supported, clear bit - not supported:
|
||||
|
||||
- Bit[0]: partition can receive direct requests if set
|
||||
- Bit[1]: partition can send direct requests if set
|
||||
- Bit[2]: partition can send and receive indirect messages
|
||||
|
||||
- managed-exit
|
||||
- value type: <empty>
|
||||
- Specifies if managed exit is supported.
|
||||
- This field is deprecated in favor of ns-interrupts-action field in the FF-A
|
||||
v1.1 EAC0 spec.
|
||||
|
||||
- ns-interrupts-action [mandatory]
|
||||
- value type: <u32>
|
||||
- Specifies the action that the SPMC must take in response to a Non-secure
|
||||
physical interrupt.
|
||||
|
||||
- 0x0: Non-secure interrupt is queued
|
||||
- 0x1: Non-secure interrupt is signaled after a managed exit
|
||||
- 0x2: Non-secure interrupt is signaled
|
||||
|
||||
- This field supersedes the managed-exit field in the FF-A v1.0 spec.
|
||||
|
||||
- has-primary-scheduler
|
||||
- value type: <empty>
|
||||
- Presence of this field indicates that the partition implements the primary
|
||||
scheduler. If so, run-time EL must be EL1.
|
||||
|
||||
- run-time-model
|
||||
- value type: <u32>
|
||||
- Run time model that the SPM must enforce for this SP:
|
||||
|
||||
- 0x0: Run to completion
|
||||
- 0x1: Preemptible
|
||||
|
||||
- time-slice-mem
|
||||
- value type: <empty>
|
||||
- Presence of this field indicates that the partition doesn't expect the
|
||||
partition manager to time slice long running memory management functions.
|
||||
|
||||
- gp-register-num
|
||||
- value type: <u32>
|
||||
- The field specifies the general purpose register number but not its width.
|
||||
The width is derived from the partition's execution state, as specified in
|
||||
the partition properties. For example, if the number value is 1 then the
|
||||
general-purpose register used will be x1 in AArch64 state and w1 in AArch32
|
||||
state.
|
||||
Presence of this field indicates that the partition expects the address of
|
||||
the FF-A boot information blob to be passed in the specified general purpose
|
||||
register.
|
||||
|
||||
- stream-endpoint-ids
|
||||
- value type: <prop-encoded-array>
|
||||
- List of <u32> tuples, identifying the IDs this partition is acting as
|
||||
proxy for.
|
||||
|
||||
- power-management-messages
|
||||
- value type: <u32>
|
||||
- Specifies which power management messages a partition subscribes to.
|
||||
A set bit means the partition should be informed of the power event, clear
|
||||
bit - should not be informed of event:
|
||||
|
||||
- Bit[0]: CPU_OFF
|
||||
- Bit[1]: CPU_SUSPEND
|
||||
- Bit[2]: CPU_SUSPEND_RESUME
|
||||
|
||||
Memory Regions
|
||||
--------------
|
||||
|
||||
- compatible [mandatory]
|
||||
- value type: <string>
|
||||
- Must be the string "arm,ffa-manifest-memory-regions".
|
||||
|
||||
- description
|
||||
- value type: <string>
|
||||
- Name of the memory region e.g. for debugging purposes.
|
||||
|
||||
- pages-count [mandatory]
|
||||
- value type: <u32>
|
||||
- Count of pages of memory region as a multiple of the translation granule
|
||||
size
|
||||
|
||||
- attributes [mandatory]
|
||||
- value type: <u32>
|
||||
- Mapping modes: ORed to get required permission
|
||||
|
||||
- 0x1: Read
|
||||
- 0x2: Write
|
||||
- 0x4: Execute
|
||||
- 0x8: Security state
|
||||
|
||||
- base-address
|
||||
- value type: <u64>
|
||||
- Base address of the region. The address must be aligned to the translation
|
||||
granule size.
|
||||
The address given may be a Physical Address (PA), Virtual Address (VA), or
|
||||
Intermediate Physical Address (IPA). Refer to the FF-A specification for
|
||||
more information on the restrictions around the address type.
|
||||
If the base address is omitted then the partition manager must map a memory
|
||||
region of the specified size into the partition's translation regime and
|
||||
then communicate the region properties (including the base address chosen
|
||||
by the partition manager) to the partition.
|
||||
|
||||
Device Regions
|
||||
--------------
|
||||
|
||||
- compatible [mandatory]
|
||||
- value type: <string>
|
||||
- Must be the string "arm,ffa-manifest-device-regions".
|
||||
|
||||
- description
|
||||
- value type: <string>
|
||||
- Name of the device region e.g. for debugging purposes.
|
||||
|
||||
- pages-count [mandatory]
|
||||
- value type: <u32>
|
||||
- Count of pages of memory region as a multiple of the translation granule
|
||||
size
|
||||
|
||||
- attributes [mandatory]
|
||||
- value type: <u32>
|
||||
- Mapping modes: ORed to get required permission
|
||||
|
||||
- 0x1: Read
|
||||
- 0x2: Write
|
||||
- 0x4: Execute
|
||||
- 0x8: Security state
|
||||
|
||||
- base-address [mandatory]
|
||||
- value type: <u64>
|
||||
- Base address of the region. The address must be aligned to the translation
|
||||
granule size.
|
||||
The address given may be a Physical Address (PA), Virtual Address (VA), or
|
||||
Intermediate Physical Address (IPA). Refer to the FF-A specification for
|
||||
more information on the restrictions around the address type.
|
||||
|
||||
- smmu-id
|
||||
- value type: <u32>
|
||||
- On systems with multiple System Memory Management Units (SMMUs) this
|
||||
identifier is used to inform the partition manager which SMMU the device is
|
||||
upstream of. If the field is omitted then it is assumed that the device is
|
||||
not upstream of any SMMU.
|
||||
|
||||
- stream-ids
|
||||
- value type: <prop-encoded-array>
|
||||
- A list of (id, mem-manage) pair, where:
|
||||
|
||||
- id: A unique <u32> value amongst all devices assigned to the partition.
|
||||
|
||||
- interrupts [mandatory]
|
||||
- value type: <prop-encoded-array>
|
||||
- A list of (id, attributes) pair describing the device interrupts, where:
|
||||
|
||||
- id: The <u32> interrupt IDs.
|
||||
- attributes: A <u32> value, containing attributes for each interrupt ID:
|
||||
|
||||
+----------------------+----------+
|
||||
|Field | Bit(s) |
|
||||
+----------------------+----------+
|
||||
| Priority | 7:0 |
|
||||
+----------------------+----------+
|
||||
| Security state | 8 |
|
||||
+----------------------+----------+
|
||||
| Config(Edge/Level) | 9 |
|
||||
+----------------------+----------+
|
||||
| Type(SPI/PPI/SGI) | 11:10 |
|
||||
+----------------------+----------+
|
||||
|
||||
Security state:
|
||||
- Secure: 1
|
||||
- Non-secure: 0
|
||||
|
||||
Configuration:
|
||||
- Edge triggered: 0
|
||||
- Level triggered: 1
|
||||
|
||||
Type:
|
||||
- SPI: 0b10
|
||||
- PPI: 0b01
|
||||
- SGI: 0b00
|
||||
|
||||
- exclusive-access
|
||||
- value type: <empty>
|
||||
- Presence of this field implies that this endpoint must be granted exclusive
|
||||
access and ownership of this device's MMIO region.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved.*
|
||||
497
arm-trusted-firmware/docs/components/firmware-update.rst
Normal file
497
arm-trusted-firmware/docs/components/firmware-update.rst
Normal file
@@ -0,0 +1,497 @@
|
||||
Firmware Update (FWU)
|
||||
=====================
|
||||
|
||||
This document describes the design of the various Firmware Update (FWU)
|
||||
mechanisms available in TF-A.
|
||||
|
||||
1. PSA Firmware Update (PSA FWU)
|
||||
2. TBBR Firmware Update (TBBR FWU)
|
||||
|
||||
PSA Firmware Update implements the specification of the same name (Arm document
|
||||
IHI 0093), which defines a standard firmware interface for installing firmware
|
||||
updates.
|
||||
On the other hand, TBBR Firmware Update only covers firmware recovery. Arguably,
|
||||
its name is somewhat misleading but the TBBR specification and terminology
|
||||
predates PSA FWU. Both mechanisms are complementary in the sense that PSA FWU
|
||||
assumes that the device has a backup or recovery capability in the event of a
|
||||
failed update, which can be fulfilled with TBBR FWU implementation.
|
||||
|
||||
.. _PSA Firmware Update:
|
||||
|
||||
PSA Firmware Update (PSA FWU)
|
||||
-----------------------------
|
||||
|
||||
Introduction
|
||||
~~~~~~~~~~~~
|
||||
The `PSA FW update specification`_ defines the concepts of ``Firmware Update
|
||||
Client`` and ``Firmware Update Agent``.
|
||||
The new firmware images are provided by the ``Client`` to the ``Update Agent``
|
||||
to flash them in non-volatile storage.
|
||||
|
||||
A common system design will place the ``Update Agent`` in the Secure-world
|
||||
while the ``Client`` executes in the Normal-world.
|
||||
The `PSA FW update specification`_ provides ABIs meant for a Normal-world
|
||||
entity aka ``Client`` to transmit the firmware images to the ``Update Agent``.
|
||||
|
||||
Scope
|
||||
~~~~~
|
||||
The design of the ``Client`` and ``Update Agent`` is out of scope of this
|
||||
document.
|
||||
This document mainly covers ``Platform Boot`` details i.e. the role of
|
||||
the second stage Bootloader after FWU has been done by ``Client`` and
|
||||
``Update Agent``.
|
||||
|
||||
Overview
|
||||
~~~~~~~~
|
||||
|
||||
There are active and update banks in the non-volatile storage identified
|
||||
by the ``active_index`` and the ``update_index`` respectively.
|
||||
An active bank stores running firmware, whereas an update bank contains
|
||||
firmware updates.
|
||||
|
||||
Once Firmwares are updated in the update bank of the non-volatile
|
||||
storage, then ``Update Agent`` marks the update bank as the active bank,
|
||||
and write updated FWU metadata in non-volatile storage.
|
||||
On subsequent reboot, the second stage Bootloader (BL2) performs the
|
||||
following actions:
|
||||
|
||||
- Read FWU metadata in memory
|
||||
- Retrieve the image specification (offset and length) of updated images
|
||||
present in non-volatile storage with the help of FWU metadata
|
||||
- Set these image specification in the corresponding I/O policies of the
|
||||
updated images using the FWU platform functions
|
||||
``plat_fwu_set_images_source()`` and ``plat_fwu_set_metadata_image_source()``,
|
||||
please refer :ref:`Porting Guide`
|
||||
- Use these I/O policies to read the images from this address into the memory
|
||||
|
||||
By default, the platform uses the active bank of non-volatile storage to boot
|
||||
the images in ``trial state``. If images pass through the authentication check
|
||||
and also if the system successfully booted the Normal-world image then
|
||||
``Update Agent`` marks this update as accepted after further sanitisation
|
||||
checking at Normal-world.
|
||||
|
||||
The second stage Bootloader (BL2) avoids upgrading the platform NV-counter until
|
||||
it's been confirmed that given update is accepted.
|
||||
|
||||
The following sequence diagram shows platform-boot flow:
|
||||
|
||||
.. image:: ../resources/diagrams/PSA-FWU.png
|
||||
|
||||
If the platform fails to boot from active bank due to any reasons such
|
||||
as authentication failure or non-fuctionality of Normal-world software then the
|
||||
watchdog will reset to give a chance to the platform to fix the issue. This
|
||||
boot failure & reset sequence might be repeated up to ``trial state`` times.
|
||||
After that, the platform can decide to boot from the ``previous_active_index``
|
||||
bank.
|
||||
|
||||
If the images still does not boot successfully from the ``previous_active_index``
|
||||
bank (e.g. due to ageing effect of non-volatile storage) then the platform can
|
||||
choose firmware recovery mechanism :ref:`TBBR Firmware Update` to bring system
|
||||
back to life.
|
||||
|
||||
.. _TBBR Firmware Update:
|
||||
|
||||
TBBR Firmware Update (TBBR FWU)
|
||||
-------------------------------
|
||||
|
||||
Introduction
|
||||
~~~~~~~~~~~~
|
||||
|
||||
This technique enables authenticated firmware to update firmware images from
|
||||
external interfaces such as USB, UART, SD-eMMC, NAND, NOR or Ethernet to SoC
|
||||
Non-Volatile memories such as NAND Flash, LPDDR2-NVM or any memory determined
|
||||
by the platform.
|
||||
This feature functions even when the current firmware in the system is corrupt
|
||||
or missing; it therefore may be used as a recovery mode. It may also be
|
||||
complemented by other, higher level firmware update software.
|
||||
|
||||
FWU implements a specific part of the Trusted Board Boot Requirements (TBBR)
|
||||
specification, Arm DEN0006C-1. It should be used in conjunction with the
|
||||
:ref:`Trusted Board Boot` design document, which describes the image
|
||||
authentication parts of the Trusted Firmware-A (TF-A) TBBR implementation.
|
||||
|
||||
It can be used as a last resort when all firmware updates that are carried out
|
||||
as part of the :ref:`PSA Firmware Update` procedure have failed to function.
|
||||
|
||||
Scope
|
||||
~~~~~
|
||||
|
||||
This document describes the secure world FWU design. It is beyond its scope to
|
||||
describe how normal world FWU images should operate. To implement normal world
|
||||
FWU images, please refer to the "Non-Trusted Firmware Updater" requirements in
|
||||
the TBBR.
|
||||
|
||||
Overview
|
||||
~~~~~~~~
|
||||
|
||||
The FWU boot flow is primarily mediated by BL1. Since BL1 executes in ROM, and
|
||||
it is usually desirable to minimize the amount of ROM code, the design allows
|
||||
some parts of FWU to be implemented in other secure and normal world images.
|
||||
Platform code may choose which parts are implemented in which images but the
|
||||
general expectation is:
|
||||
|
||||
- BL1 handles:
|
||||
|
||||
- Detection and initiation of the FWU boot flow.
|
||||
- Copying images from non-secure to secure memory
|
||||
- FWU image authentication
|
||||
- Context switching between the normal and secure world during the FWU
|
||||
process.
|
||||
|
||||
- Other secure world FWU images handle platform initialization required by
|
||||
the FWU process.
|
||||
- Normal world FWU images handle loading of firmware images from external
|
||||
interfaces to non-secure memory.
|
||||
|
||||
The primary requirements of the FWU feature are:
|
||||
|
||||
#. Export a BL1 SMC interface to interoperate with other FWU images executing
|
||||
at other Exception Levels.
|
||||
#. Export a platform interface to provide FWU common code with the information
|
||||
it needs, and to enable platform specific FWU functionality. See the
|
||||
:ref:`Porting Guide` for details of this interface.
|
||||
|
||||
TF-A uses abbreviated image terminology for FWU images like for other TF-A
|
||||
images. See the :ref:`Image Terminology` document for an explanation of these
|
||||
terms.
|
||||
|
||||
The following diagram shows the FWU boot flow for Arm development platforms.
|
||||
Arm CSS platforms like Juno have a System Control Processor (SCP), and these
|
||||
use all defined FWU images. Other platforms may use a subset of these.
|
||||
|
||||
|Flow Diagram|
|
||||
|
||||
Image Identification
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Each FWU image and certificate is identified by a unique ID, defined by the
|
||||
platform, which BL1 uses to fetch an image descriptor (``image_desc_t``) via a
|
||||
call to ``bl1_plat_get_image_desc()``. The same ID is also used to prepare the
|
||||
Chain of Trust (Refer to the :ref:`Authentication Framework & Chain of Trust`
|
||||
document for more information).
|
||||
|
||||
The image descriptor includes the following information:
|
||||
|
||||
- Executable or non-executable image. This indicates whether the normal world
|
||||
is permitted to request execution of a secure world FWU image (after
|
||||
authentication). Secure world certificates and non-AP images are examples
|
||||
of non-executable images.
|
||||
- Secure or non-secure image. This indicates whether the image is
|
||||
authenticated/executed in secure or non-secure memory.
|
||||
- Image base address and size.
|
||||
- Image entry point configuration (an ``entry_point_info_t``).
|
||||
- FWU image state.
|
||||
|
||||
BL1 uses the FWU image descriptors to:
|
||||
|
||||
- Validate the arguments of FWU SMCs
|
||||
- Manage the state of the FWU process
|
||||
- Initialize the execution state of the next FWU image.
|
||||
|
||||
FWU State Machine
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
BL1 maintains state for each FWU image during FWU execution. FWU images at lower
|
||||
Exception Levels raise SMCs to invoke FWU functionality in BL1, which causes
|
||||
BL1 to update its FWU image state. The BL1 image states and valid state
|
||||
transitions are shown in the diagram below. Note that secure images have a more
|
||||
complex state machine than non-secure images.
|
||||
|
||||
|FWU state machine|
|
||||
|
||||
The following is a brief description of the supported states:
|
||||
|
||||
- RESET: This is the initial state of every image at the start of FWU.
|
||||
Authentication failure also leads to this state. A secure
|
||||
image may yield to this state if it has completed execution.
|
||||
It can also be reached by using ``FWU_SMC_IMAGE_RESET``.
|
||||
|
||||
- COPYING: This is the state of a secure image while BL1 is copying it
|
||||
in blocks from non-secure to secure memory.
|
||||
|
||||
- COPIED: This is the state of a secure image when BL1 has completed
|
||||
copying it to secure memory.
|
||||
|
||||
- AUTHENTICATED: This is the state of an image when BL1 has successfully
|
||||
authenticated it.
|
||||
|
||||
- EXECUTED: This is the state of a secure, executable image when BL1 has
|
||||
passed execution control to it.
|
||||
|
||||
- INTERRUPTED: This is the state of a secure, executable image after it has
|
||||
requested BL1 to resume normal world execution.
|
||||
|
||||
BL1 SMC Interface
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
BL1_SMC_CALL_COUNT
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x0
|
||||
|
||||
Return:
|
||||
uint32_t
|
||||
|
||||
This SMC returns the number of SMCs supported by BL1.
|
||||
|
||||
BL1_SMC_UID
|
||||
^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x1
|
||||
|
||||
Return:
|
||||
UUID : 32 bits in each of w0-w3 (or r0-r3 for AArch32 callers)
|
||||
|
||||
This SMC returns the 128-bit `Universally Unique Identifier`_ for the
|
||||
BL1 SMC service.
|
||||
|
||||
BL1_SMC_VERSION
|
||||
^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Argument:
|
||||
uint32_t function ID : 0x3
|
||||
|
||||
Return:
|
||||
uint32_t : Bits [31:16] Major Version
|
||||
Bits [15:0] Minor Version
|
||||
|
||||
This SMC returns the current version of the BL1 SMC service.
|
||||
|
||||
BL1_SMC_RUN_IMAGE
|
||||
^^^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x4
|
||||
entry_point_info_t *ep_info
|
||||
|
||||
Return:
|
||||
void
|
||||
|
||||
Pre-conditions:
|
||||
if (normal world caller) synchronous exception
|
||||
if (ep_info not EL3) synchronous exception
|
||||
|
||||
This SMC passes execution control to an EL3 image described by the provided
|
||||
``entry_point_info_t`` structure. In the normal TF-A boot flow, BL2 invokes
|
||||
this SMC for BL1 to pass execution control to BL31.
|
||||
|
||||
FWU_SMC_IMAGE_COPY
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x10
|
||||
unsigned int image_id
|
||||
uintptr_t image_addr
|
||||
unsigned int block_size
|
||||
unsigned int image_size
|
||||
|
||||
Return:
|
||||
int : 0 (Success)
|
||||
: -ENOMEM
|
||||
: -EPERM
|
||||
|
||||
Pre-conditions:
|
||||
if (image_id is invalid) return -EPERM
|
||||
if (image_id is non-secure image) return -EPERM
|
||||
if (image_id state is not (RESET or COPYING)) return -EPERM
|
||||
if (secure world caller) return -EPERM
|
||||
if (image_addr + block_size overflows) return -ENOMEM
|
||||
if (image destination address + image_size overflows) return -ENOMEM
|
||||
if (source block is in secure memory) return -ENOMEM
|
||||
if (source block is not mapped into BL1) return -ENOMEM
|
||||
if (image_size > free secure memory) return -ENOMEM
|
||||
if (image overlaps another image) return -EPERM
|
||||
|
||||
This SMC copies the secure image indicated by ``image_id`` from non-secure memory
|
||||
to secure memory for later authentication. The image may be copied in a single
|
||||
block or multiple blocks. In either case, the total size of the image must be
|
||||
provided in ``image_size`` when invoking this SMC for the first time for each
|
||||
image; it is ignored in subsequent calls (if any) for the same image.
|
||||
|
||||
The ``image_addr`` and ``block_size`` specify the source memory block to copy from.
|
||||
The destination address is provided by the platform code.
|
||||
|
||||
If ``block_size`` is greater than the amount of remaining bytes to copy for this
|
||||
image then the former is truncated to the latter. The copy operation is then
|
||||
considered as complete and the FWU state machine transitions to the "COPIED"
|
||||
state. If there is still more to copy, the FWU state machine stays in or
|
||||
transitions to the COPYING state (depending on the previous state).
|
||||
|
||||
When using multiple blocks, the source blocks do not necessarily need to be in
|
||||
contiguous memory.
|
||||
|
||||
Once the SMC is handled, BL1 returns from exception to the normal world caller.
|
||||
|
||||
FWU_SMC_IMAGE_AUTH
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x11
|
||||
unsigned int image_id
|
||||
uintptr_t image_addr
|
||||
unsigned int image_size
|
||||
|
||||
Return:
|
||||
int : 0 (Success)
|
||||
: -ENOMEM
|
||||
: -EPERM
|
||||
: -EAUTH
|
||||
|
||||
Pre-conditions:
|
||||
if (image_id is invalid) return -EPERM
|
||||
if (secure world caller)
|
||||
if (image_id state is not RESET) return -EPERM
|
||||
if (image_addr/image_size is not mapped into BL1) return -ENOMEM
|
||||
else // normal world caller
|
||||
if (image_id is secure image)
|
||||
if (image_id state is not COPIED) return -EPERM
|
||||
else // image_id is non-secure image
|
||||
if (image_id state is not RESET) return -EPERM
|
||||
if (image_addr/image_size is in secure memory) return -ENOMEM
|
||||
if (image_addr/image_size not mapped into BL1) return -ENOMEM
|
||||
|
||||
This SMC authenticates the image specified by ``image_id``. If the image is in the
|
||||
RESET state, BL1 authenticates the image in place using the provided
|
||||
``image_addr`` and ``image_size``. If the image is a secure image in the COPIED
|
||||
state, BL1 authenticates the image from the secure memory that BL1 previously
|
||||
copied the image into.
|
||||
|
||||
BL1 returns from exception to the caller. If authentication succeeds then BL1
|
||||
sets the image state to AUTHENTICATED. If authentication fails then BL1 returns
|
||||
the -EAUTH error and sets the image state back to RESET.
|
||||
|
||||
FWU_SMC_IMAGE_EXECUTE
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x12
|
||||
unsigned int image_id
|
||||
|
||||
Return:
|
||||
int : 0 (Success)
|
||||
: -EPERM
|
||||
|
||||
Pre-conditions:
|
||||
if (image_id is invalid) return -EPERM
|
||||
if (secure world caller) return -EPERM
|
||||
if (image_id is non-secure image) return -EPERM
|
||||
if (image_id is non-executable image) return -EPERM
|
||||
if (image_id state is not AUTHENTICATED) return -EPERM
|
||||
|
||||
This SMC initiates execution of a previously authenticated image specified by
|
||||
``image_id``, in the other security world to the caller. The current
|
||||
implementation only supports normal world callers initiating execution of a
|
||||
secure world image.
|
||||
|
||||
BL1 saves the normal world caller's context, sets the secure image state to
|
||||
EXECUTED, and returns from exception to the secure image.
|
||||
|
||||
FWU_SMC_IMAGE_RESUME
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x13
|
||||
register_t image_param
|
||||
|
||||
Return:
|
||||
register_t : image_param (Success)
|
||||
: -EPERM
|
||||
|
||||
Pre-conditions:
|
||||
if (normal world caller and no INTERRUPTED secure image) return -EPERM
|
||||
|
||||
This SMC resumes execution in the other security world while there is a secure
|
||||
image in the EXECUTED/INTERRUPTED state.
|
||||
|
||||
For normal world callers, BL1 sets the previously interrupted secure image state
|
||||
to EXECUTED. For secure world callers, BL1 sets the previously executing secure
|
||||
image state to INTERRUPTED. In either case, BL1 saves the calling world's
|
||||
context, restores the resuming world's context and returns from exception into
|
||||
the resuming world. If the call is successful then the caller provided
|
||||
``image_param`` is returned to the resumed world, otherwise an error code is
|
||||
returned to the caller.
|
||||
|
||||
FWU_SMC_SEC_IMAGE_DONE
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x14
|
||||
|
||||
Return:
|
||||
int : 0 (Success)
|
||||
: -EPERM
|
||||
|
||||
Pre-conditions:
|
||||
if (normal world caller) return -EPERM
|
||||
|
||||
This SMC indicates completion of a previously executing secure image.
|
||||
|
||||
BL1 sets the previously executing secure image state to the RESET state,
|
||||
restores the normal world context and returns from exception into the normal
|
||||
world.
|
||||
|
||||
FWU_SMC_UPDATE_DONE
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x15
|
||||
register_t client_cookie
|
||||
|
||||
Return:
|
||||
N/A
|
||||
|
||||
This SMC completes the firmware update process. BL1 calls the platform specific
|
||||
function ``bl1_plat_fwu_done``, passing the optional argument ``client_cookie`` as
|
||||
a ``void *``. The SMC does not return.
|
||||
|
||||
FWU_SMC_IMAGE_RESET
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
::
|
||||
|
||||
Arguments:
|
||||
uint32_t function ID : 0x16
|
||||
unsigned int image_id
|
||||
|
||||
Return:
|
||||
int : 0 (Success)
|
||||
: -EPERM
|
||||
|
||||
Pre-conditions:
|
||||
if (secure world caller) return -EPERM
|
||||
if (image in EXECUTED) return -EPERM
|
||||
|
||||
This SMC sets the state of an image to RESET and zeroes the memory used by it.
|
||||
|
||||
This is only allowed if the image is not being executed.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _Universally Unique Identifier: https://tools.ietf.org/rfc/rfc4122.txt
|
||||
.. |Flow Diagram| image:: ../resources/diagrams/fwu_flow.png
|
||||
.. |FWU state machine| image:: ../resources/diagrams/fwu_states.png
|
||||
.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
|
||||
@@ -0,0 +1,235 @@
|
||||
Granule Protection Tables Library
|
||||
=================================
|
||||
|
||||
This document describes the design of the granule protection tables (GPT)
|
||||
library used by Trusted Firmware-A (TF-A). This library provides the APIs needed
|
||||
to initialize the GPTs based on a data structure containing information about
|
||||
the systems memory layout, configure the system registers to enable granule
|
||||
protection checks based on these tables, and transition granules between
|
||||
different PAS (physical address spaces) at runtime.
|
||||
|
||||
Arm CCA adds two new security states for a total of four: root, realm, secure, and
|
||||
non-secure. In addition to new security states, corresponding physical address
|
||||
spaces have been added to control memory access for each state. The PAS access
|
||||
allowed to each security state can be seen in the table below.
|
||||
|
||||
.. list-table:: Security states and PAS access rights
|
||||
:widths: 25 25 25 25 25
|
||||
:header-rows: 1
|
||||
|
||||
* -
|
||||
- Root state
|
||||
- Realm state
|
||||
- Secure state
|
||||
- Non-secure state
|
||||
* - Root PAS
|
||||
- yes
|
||||
- no
|
||||
- no
|
||||
- no
|
||||
* - Realm PAS
|
||||
- yes
|
||||
- yes
|
||||
- no
|
||||
- no
|
||||
* - Secure PAS
|
||||
- yes
|
||||
- no
|
||||
- yes
|
||||
- no
|
||||
* - Non-secure PAS
|
||||
- yes
|
||||
- yes
|
||||
- yes
|
||||
- yes
|
||||
|
||||
The GPT can function as either a 1 level or 2 level lookup depending on how a
|
||||
PAS region is configured. The first step is the level 0 table, each entry in the
|
||||
level 0 table controls access to a relatively large region in memory (block
|
||||
descriptor), and the entire region can belong to a single PAS when a one step
|
||||
mapping is used, or a level 0 entry can link to a level 1 table where relatively
|
||||
small regions (granules) of memory can be assigned to different PAS with a 2
|
||||
step mapping. The type of mapping used for each PAS is determined by the user
|
||||
when setting up the configuration structure.
|
||||
|
||||
Design Concepts and Interfaces
|
||||
------------------------------
|
||||
|
||||
This section covers some important concepts and data structures used in the GPT
|
||||
library.
|
||||
|
||||
There are three main parameters that determine how the tables are organized and
|
||||
function: the PPS (protected physical space) which is the total amount of
|
||||
protected physical address space in the system, PGS (physical granule size)
|
||||
which is how large each level 1 granule is, and L0GPTSZ (level 0 GPT size) which
|
||||
determines how much physical memory is governed by each level 0 entry. A granule
|
||||
is the smallest unit of memory that can be independently assigned to a PAS.
|
||||
|
||||
L0GPTSZ is determined by the hardware and is read from the GPCCR_EL3 register.
|
||||
PPS and PGS are passed into the APIs at runtime and can be determined in
|
||||
whatever way is best for a given platform, either through some algorithm or hard
|
||||
coded in the firmware.
|
||||
|
||||
GPT setup is split into two parts: table creation and runtime initialization. In
|
||||
the table creation step, a data structure containing information about the
|
||||
desired PAS regions is passed into the library which validates the mappings,
|
||||
creates the tables in memory, and enables granule protection checks. In the
|
||||
runtime initialization step, the runtime firmware locates the existing tables in
|
||||
memory using the GPT register configuration and saves important data to a
|
||||
structure used by the granule transition service which will be covered more
|
||||
below.
|
||||
|
||||
In the reference implementation for FVP models, you can find an example of PAS
|
||||
region definitions in the file ``include/plat/arm/common/arm_pas_def.h``. Table
|
||||
creation API calls can be found in ``plat/arm/common/arm_bl2_setup.c`` and
|
||||
runtime initialization API calls can be seen in
|
||||
``plat/arm/common/arm_bl31_setup.c``.
|
||||
|
||||
Defining PAS regions
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
A ``pas_region_t`` structure is a way to represent a physical address space and
|
||||
its attributes that can be used by the GPT library to initialize the tables.
|
||||
|
||||
This structure is composed of the following:
|
||||
|
||||
#. The base physical address
|
||||
#. The region size
|
||||
#. The desired attributes of this memory region (mapping type, PAS type)
|
||||
|
||||
See the ``pas_region_t`` type in ``include/lib/gpt_rme/gpt_rme.h``.
|
||||
|
||||
The programmer should provide the API with an array containing ``pas_region_t``
|
||||
structures, then the library will check the desired memory access layout for
|
||||
validity and create tables to implement it.
|
||||
|
||||
``pas_region_t`` is a public type, however it is recommended that the macros
|
||||
``GPT_MAP_REGION_BLOCK`` and ``GPT_MAP_REGION_GRANULE`` be used to populate
|
||||
these structures instead of doing it manually to reduce the risk of future
|
||||
compatibility issues. These macros take the base physical address, region size,
|
||||
and PAS type as arguments to generate the pas_region_t structure. As the names
|
||||
imply, ``GPT_MAP_REGION_BLOCK`` creates a region using only L0 mapping while
|
||||
``GPT_MAP_REGION_GRANULE`` creates a region using L0 and L1 mappings.
|
||||
|
||||
Level 0 and Level 1 Tables
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The GPT initialization APIs require memory to be passed in for the tables to be
|
||||
constructed, ``gpt_init_l0_tables`` takes a memory address and size for building
|
||||
the level 0 tables and ``gpt_init_pas_l1_tables`` takes an address and size for
|
||||
building the level 1 tables which are linked from level 0 descriptors. The
|
||||
tables should have PAS type ``GPT_GPI_ROOT`` and a typical system might place
|
||||
its level 0 table in SRAM and its level 1 table(s) in DRAM.
|
||||
|
||||
Granule Transition Service
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The Granule Transition Service allows memory mapped with GPT_MAP_REGION_GRANULE
|
||||
ownership to be changed using SMC calls. Non-secure granules can be transitioned
|
||||
to either realm or secure space, and realm and secure granules can be
|
||||
transitioned back to non-secure. This library only allows memory mapped as
|
||||
granules to be transitioned, memory mapped as blocks have their GPIs fixed after
|
||||
table creation.
|
||||
|
||||
Library APIs
|
||||
------------
|
||||
|
||||
The public APIs and types can be found in ``include/lib/gpt_rme/gpt_rme.h`` and this
|
||||
section is intended to provide additional details and clarifications.
|
||||
|
||||
To create the GPTs and enable granule protection checks the APIs need to be
|
||||
called in the correct order and at the correct time during the system boot
|
||||
process.
|
||||
|
||||
#. Firmware must enable the MMU.
|
||||
#. Firmware must call ``gpt_init_l0_tables`` to initialize the level 0 tables to
|
||||
a default state, that is, initializing all of the L0 descriptors to allow all
|
||||
accesses to all memory. The PPS is provided to this function as an argument.
|
||||
#. DDR discovery and initialization by the system, the discovered DDR region(s)
|
||||
are then added to the L1 PAS regions to be initialized in the next step and
|
||||
used by the GTSI at runtime.
|
||||
#. Firmware must call ``gpt_init_pas_l1_tables`` with a pointer to an array of
|
||||
``pas_region_t`` structures containing the desired memory access layout. The
|
||||
PGS is provided to this function as an argument.
|
||||
#. Firmware must call ``gpt_enable`` to enable granule protection checks by
|
||||
setting the correct register values.
|
||||
#. In systems that make use of the granule transition service, runtime
|
||||
firmware must call ``gpt_runtime_init`` to set up the data structures needed
|
||||
by the GTSI to find the tables and transition granules between PAS types.
|
||||
|
||||
API Constraints
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
The values allowed by the API for PPS and PGS are enumerated types
|
||||
defined in the file ``include/lib/gpt_rme/gpt_rme.h``.
|
||||
|
||||
Allowable values for PPS along with their corresponding size.
|
||||
|
||||
* ``GPCCR_PPS_4GB`` (4GB protected space, 0x100000000 bytes)
|
||||
* ``GPCCR_PPS_64GB`` (64GB protected space, 0x1000000000 bytes)
|
||||
* ``GPCCR_PPS_1TB`` (1TB protected space, 0x10000000000 bytes)
|
||||
* ``GPCCR_PPS_4TB`` (4TB protected space, 0x40000000000 bytes)
|
||||
* ``GPCCR_PPS_16TB`` (16TB protected space, 0x100000000000 bytes)
|
||||
* ``GPCCR_PPS_256TB`` (256TB protected space, 0x1000000000000 bytes)
|
||||
* ``GPCCR_PPS_4PB`` (4PB protected space, 0x10000000000000 bytes)
|
||||
|
||||
Allowable values for PGS along with their corresponding size.
|
||||
|
||||
* ``GPCCR_PGS_4K`` (4KB granules, 0x1000 bytes)
|
||||
* ``GPCCR_PGS_16K`` (16KB granules, 0x4000 bytes)
|
||||
* ``GPCCR_PGS_64K`` (64KB granules, 0x10000 bytes)
|
||||
|
||||
Allowable values for L0GPTSZ along with the corresponding size.
|
||||
|
||||
* ``GPCCR_L0GPTSZ_30BITS`` (1GB regions, 0x40000000 bytes)
|
||||
* ``GPCCR_L0GPTSZ_34BITS`` (16GB regions, 0x400000000 bytes)
|
||||
* ``GPCCR_L0GPTSZ_36BITS`` (64GB regions, 0x1000000000 bytes)
|
||||
* ``GPCCR_L0GPTSZ_39BITS`` (512GB regions, 0x8000000000 bytes)
|
||||
|
||||
Note that the value of the PPS, PGS, and L0GPTSZ definitions is an encoded value
|
||||
corresponding to the size, not the size itself. The decoded hex representations
|
||||
of the sizes have been provided for convenience.
|
||||
|
||||
The L0 table memory has some constraints that must be taken into account.
|
||||
|
||||
* The L0 table must be aligned to either the table size or 4096 bytes, whichever
|
||||
is greater. L0 table size is the total protected space (PPS) divided by the
|
||||
size of each L0 region (L0GPTSZ) multiplied by the size of each L0 descriptor
|
||||
(8 bytes). ((PPS / L0GPTSZ) * 8)
|
||||
* The L0 memory size must be greater than or equal to the table size.
|
||||
* The L0 memory must fall within a PAS of type GPT_GPI_ROOT.
|
||||
|
||||
The L1 memory also has some constraints.
|
||||
|
||||
* The L1 tables must be aligned to their size. The size of each L1 table is the
|
||||
size of each L0 region (L0GPTSZ) divided by the granule size (PGS) divided by
|
||||
the granules controlled in each byte (2). ((L0GPTSZ / PGS) / 2)
|
||||
* There must be enough L1 memory supplied to build all requested L1 tables.
|
||||
* The L1 memory must fall within a PAS of type GPT_GPI_ROOT.
|
||||
|
||||
If an invalid combination of parameters is supplied, the APIs will print an
|
||||
error message and return a negative value. The return values of APIs should be
|
||||
checked to ensure successful configuration.
|
||||
|
||||
Sample Calculation for L0 memory size and alignment
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Let PPS=GPCCR_PPS_4GB and L0GPTSZ=GPCCR_L0GPTSZ_30BITS
|
||||
|
||||
We can find the total L0 table size with ((PPS / L0GPTSZ) * 8)
|
||||
|
||||
Substitute values to get this: ((0x100000000 / 0x40000000) * 8)
|
||||
|
||||
And solve to get 32 bytes. In this case, 4096 is greater than 32, so the L0
|
||||
tables must be aligned to 4096 bytes.
|
||||
|
||||
Sample calculation for L1 table size and alignment
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Let PGS=GPCCR_PGS_4K and L0GPTSZ=GPCCR_L0GPTSZ_30BITS
|
||||
|
||||
We can find the size of each L1 table with ((L0GPTSZ / PGS) / 2).
|
||||
|
||||
Substitute values: ((0x40000000 / 0x1000) / 2)
|
||||
|
||||
And solve to get 0x20000 bytes per L1 table.
|
||||
28
arm-trusted-firmware/docs/components/index.rst
Normal file
28
arm-trusted-firmware/docs/components/index.rst
Normal file
@@ -0,0 +1,28 @@
|
||||
Components
|
||||
==========
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Contents
|
||||
|
||||
spd/index
|
||||
activity-monitors
|
||||
arm-sip-service
|
||||
debugfs-design
|
||||
exception-handling
|
||||
fconf/index
|
||||
firmware-update
|
||||
measured_boot/index
|
||||
mpmm
|
||||
platform-interrupt-controller-API
|
||||
ras
|
||||
romlib-design
|
||||
sdei
|
||||
secure-partition-manager
|
||||
el3-spmc
|
||||
secure-partition-manager-mm
|
||||
xlat-tables-lib-v2-design
|
||||
cot-binding
|
||||
realm-management-extension
|
||||
rmm-el3-comms-spec
|
||||
granule-protection-tables-design
|
||||
@@ -0,0 +1,35 @@
|
||||
DTB binding for Event Log properties
|
||||
====================================
|
||||
|
||||
This document describes the device tree format of Event Log properties.
|
||||
These properties are not related to a specific platform and can be queried
|
||||
from common code.
|
||||
|
||||
Dynamic configuration for Event Log
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Measured Boot driver expects a *tpm_event_log* node with the following field
|
||||
in 'tb_fw_config', 'nt_fw_config' and 'tsp_fw_config' DTS files:
|
||||
|
||||
- compatible [mandatory]
|
||||
- value type: <string>
|
||||
- Must be the string "arm,tpm_event_log".
|
||||
|
||||
Then a list of properties representing Event Log configuration, which
|
||||
can be used by Measured Boot driver. Each property is named according
|
||||
to the information it contains:
|
||||
|
||||
- tpm_event_log_sm_addr [fvp_nt_fw_config.dts with OP-TEE]
|
||||
- value type: <u64>
|
||||
- Event Log base address in secure memory.
|
||||
|
||||
Note. Currently OP-TEE does not support reading DTBs from Secure memory
|
||||
and this property should be removed when this feature is supported.
|
||||
|
||||
- tpm_event_log_addr [mandatory]
|
||||
- value type: <u64>
|
||||
- Event Log base address in non-secure memory.
|
||||
|
||||
- tpm_event_log_size [mandatory]
|
||||
- value type: <u32>
|
||||
- Event Log size.
|
||||
12
arm-trusted-firmware/docs/components/measured_boot/index.rst
Normal file
12
arm-trusted-firmware/docs/components/measured_boot/index.rst
Normal file
@@ -0,0 +1,12 @@
|
||||
Measured Boot Driver (MBD)
|
||||
==========================
|
||||
|
||||
.. _measured-boot-document:
|
||||
|
||||
Properties binding information
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
event_log
|
||||
30
arm-trusted-firmware/docs/components/mpmm.rst
Normal file
30
arm-trusted-firmware/docs/components/mpmm.rst
Normal file
@@ -0,0 +1,30 @@
|
||||
Maximum Power Mitigation Mechanism (MPMM)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
|MPMM| is an optional microarchitectural power management mechanism supported by
|
||||
some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and
|
||||
Cortex-A510 cores. This mechanism detects and limits high-activity events to
|
||||
assist in |SoC| processor power domain dynamic power budgeting and limit the
|
||||
triggering of whole-rail (i.e. clock chopping) responses to overcurrent
|
||||
conditions.
|
||||
|
||||
|MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
|
||||
of |MPMM| cannot be determined at runtime by the firmware, and therefore the
|
||||
platform must expose this information through one of two possible mechanisms:
|
||||
|
||||
- |FCONF|, controlled by the ``ENABLE_MPMM_FCONF`` build option.
|
||||
- A platform implementation of the ``plat_mpmm_topology`` function (the
|
||||
default).
|
||||
|
||||
See :ref:`Maximum Power Mitigation Mechanism (MPMM) Bindings` for documentation
|
||||
on the |FCONF| device tree bindings.
|
||||
|
||||
.. warning::
|
||||
|
||||
|MPMM| exposes gear metrics through the auxiliary |AMU| counters. An
|
||||
external power controller can use these metrics to budget SoC power by
|
||||
limiting the number of cores that can execute higher-activity workloads or
|
||||
switching to a different DVFS operating point. When this is the case, the
|
||||
|AMU| counters that make up the |MPMM| gears must be enabled by the EL3
|
||||
runtime firmware - please see :ref:`Activity Monitor Auxiliary Counters` for
|
||||
documentation on enabling auxiliary |AMU| counters.
|
||||
@@ -0,0 +1,309 @@
|
||||
Platform Interrupt Controller API
|
||||
=================================
|
||||
|
||||
This document lists the optional platform interrupt controller API that
|
||||
abstracts the runtime configuration and control of interrupt controller from the
|
||||
generic code. The mandatory APIs are described in the
|
||||
:ref:`Porting Guide <porting_guide_imf_in_bl31>`.
|
||||
|
||||
Function: unsigned int plat_ic_get_running_priority(void); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : void
|
||||
Return : unsigned int
|
||||
|
||||
This API should return the priority of the interrupt the PE is currently
|
||||
servicing. This must be be called only after an interrupt has already been
|
||||
acknowledged via ``plat_ic_acknowledge_interrupt``.
|
||||
|
||||
In the case of Arm standard platforms using GIC, the *Running Priority Register*
|
||||
is read to determine the priority of the interrupt.
|
||||
|
||||
Function: int plat_ic_is_spi(unsigned int id); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : int
|
||||
|
||||
The API should return whether the interrupt ID (first parameter) is categorized
|
||||
as a Shared Peripheral Interrupt. Shared Peripheral Interrupts are typically
|
||||
associated to system-wide peripherals, and these interrupts can target any PE in
|
||||
the system.
|
||||
|
||||
Function: int plat_ic_is_ppi(unsigned int id); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : int
|
||||
|
||||
The API should return whether the interrupt ID (first parameter) is categorized
|
||||
as a Private Peripheral Interrupt. Private Peripheral Interrupts are typically
|
||||
associated with peripherals that are private to each PE. Interrupts from private
|
||||
peripherals target to that PE only.
|
||||
|
||||
Function: int plat_ic_is_sgi(unsigned int id); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : int
|
||||
|
||||
The API should return whether the interrupt ID (first parameter) is categorized
|
||||
as a Software Generated Interrupt. Software Generated Interrupts are raised by
|
||||
explicit programming by software, and are typically used in inter-PE
|
||||
communication. Secure SGIs are reserved for use by Secure world software.
|
||||
|
||||
Function: unsigned int plat_ic_get_interrupt_active(unsigned int id); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : int
|
||||
|
||||
This API should return the *active* status of the interrupt ID specified by the
|
||||
first parameter, ``id``.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API reads
|
||||
the GIC *Set Active Register* to read and return the active status of the
|
||||
interrupt.
|
||||
|
||||
Function: void plat_ic_enable_interrupt(unsigned int id); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : void
|
||||
|
||||
This API should enable the interrupt ID specified by the first parameter,
|
||||
``id``. PEs in the system are expected to receive only enabled interrupts.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
inserts barrier to make memory updates visible before enabling interrupt, and
|
||||
then writes to GIC *Set Enable Register* to enable the interrupt.
|
||||
|
||||
Function: void plat_ic_disable_interrupt(unsigned int id); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : void
|
||||
|
||||
This API should disable the interrupt ID specified by the first parameter,
|
||||
``id``. PEs in the system are not expected to receive disabled interrupts.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
writes to GIC *Clear Enable Register* to disable the interrupt, and inserts
|
||||
barrier to make memory updates visible afterwards.
|
||||
|
||||
Function: void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Argument : unsigned int
|
||||
Return : void
|
||||
|
||||
This API should set the priority of the interrupt specified by first parameter
|
||||
``id`` to the value set by the second parameter ``priority``.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
writes to GIC *Priority Register* set interrupt priority.
|
||||
|
||||
Function: int plat_ic_has_interrupt_type(unsigned int type); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : int
|
||||
|
||||
This API should return whether the platform supports a given interrupt type. The
|
||||
parameter ``type`` shall be one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, or
|
||||
``INTR_TYPE_NS``.
|
||||
|
||||
In case of Arm standard platforms using GICv3, the implementation of the API
|
||||
returns ``1`` for all interrupt types.
|
||||
|
||||
In case of Arm standard platforms using GICv2, the API always return ``1`` for
|
||||
``INTR_TYPE_NS``. Return value for other types depends on the value of build
|
||||
option ``GICV2_G0_FOR_EL3``:
|
||||
|
||||
- For interrupt type ``INTR_TYPE_EL3``:
|
||||
|
||||
- When ``GICV2_G0_FOR_EL3`` is ``0``, it returns ``0``, indicating no support
|
||||
for EL3 interrupts.
|
||||
|
||||
- When ``GICV2_G0_FOR_EL3`` is ``1``, it returns ``1``, indicating support for
|
||||
EL3 interrupts.
|
||||
|
||||
- For interrupt type ``INTR_TYPE_S_EL1``:
|
||||
|
||||
- When ``GICV2_G0_FOR_EL3`` is ``0``, it returns ``1``, indicating support for
|
||||
Secure EL1 interrupts.
|
||||
|
||||
- When ``GICV2_G0_FOR_EL3`` is ``1``, it returns ``0``, indicating no support
|
||||
for Secure EL1 interrupts.
|
||||
|
||||
Function: void plat_ic_set_interrupt_type(unsigned int id, unsigned int type); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Argument : unsigned int
|
||||
Return : void
|
||||
|
||||
This API should set the interrupt specified by first parameter ``id`` to the
|
||||
type specified by second parameter ``type``. The ``type`` parameter can be
|
||||
one of:
|
||||
|
||||
- ``INTR_TYPE_NS``: interrupt is meant to be consumed by the Non-secure world.
|
||||
|
||||
- ``INTR_TYPE_S_EL1``: interrupt is meant to be consumed by Secure EL1.
|
||||
|
||||
- ``INTR_TYPE_EL3``: interrupt is meant to be consumed by EL3.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
writes to the GIC *Group Register* and *Group Modifier Register* (only GICv3) to
|
||||
assign the interrupt to the right group.
|
||||
|
||||
For GICv3:
|
||||
|
||||
- ``INTR_TYPE_NS`` maps to Group 1 interrupt.
|
||||
|
||||
- ``INTR_TYPE_S_EL1`` maps to Secure Group 1 interrupt.
|
||||
|
||||
- ``INTR_TYPE_EL3`` maps to Secure Group 0 interrupt.
|
||||
|
||||
For GICv2:
|
||||
|
||||
- ``INTR_TYPE_NS`` maps to Group 1 interrupt.
|
||||
|
||||
- When the build option ``GICV2_G0_FOR_EL3`` is set to ``0`` (the default),
|
||||
``INTR_TYPE_S_EL1`` maps to Group 0. Otherwise, ``INTR_TYPE_EL3`` maps to
|
||||
Group 0 interrupt.
|
||||
|
||||
Function: void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : int
|
||||
Argument : u_register_t
|
||||
Return : void
|
||||
|
||||
This API should raise an EL3 SGI. The first parameter, ``sgi_num``, specifies
|
||||
the ID of the SGI. The second parameter, ``target``, must be the MPIDR of the
|
||||
target PE.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
inserts barrier to make memory updates visible before raising SGI, then writes
|
||||
to appropriate *SGI Register* in order to raise the EL3 SGI.
|
||||
|
||||
Function: void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, u_register_t mpidr); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Argument : unsigned int
|
||||
Argument : u_register_t
|
||||
Return : void
|
||||
|
||||
This API should set the routing mode of Share Peripheral Interrupt (SPI)
|
||||
specified by first parameter ``id`` to that specified by the second parameter
|
||||
``routing_mode``.
|
||||
|
||||
The ``routing_mode`` parameter can be one of:
|
||||
|
||||
- ``INTR_ROUTING_MODE_ANY`` means the interrupt can be routed to any PE in the
|
||||
system. The ``mpidr`` parameter is ignored in this case.
|
||||
|
||||
- ``INTR_ROUTING_MODE_PE`` means the interrupt is routed to the PE whose MPIDR
|
||||
value is specified by the parameter ``mpidr``.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
writes to the GIC *Target Register* (GICv2) or *Route Register* (GICv3) to set
|
||||
the routing.
|
||||
|
||||
Function: void plat_ic_set_interrupt_pending(unsigned int id); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : void
|
||||
|
||||
This API should set the interrupt specified by first parameter ``id`` to
|
||||
*Pending*.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
inserts barrier to make memory updates visible before setting interrupt pending,
|
||||
and writes to the GIC *Set Pending Register* to set the interrupt pending
|
||||
status.
|
||||
|
||||
Function: void plat_ic_clear_interrupt_pending(unsigned int id); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : void
|
||||
|
||||
This API should clear the *Pending* status of the interrupt specified by first
|
||||
parameter ``id``.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
writes to the GIC *Clear Pending Register* to clear the interrupt pending
|
||||
status, and inserts barrier to make memory updates visible afterwards.
|
||||
|
||||
Function: unsigned int plat_ic_set_priority_mask(unsigned int id); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : int
|
||||
|
||||
This API should set the priority mask (first parameter) in the interrupt
|
||||
controller such that only interrupts of higher priority than the supplied one
|
||||
may be signalled to the PE. The API should return the current priority value
|
||||
that it's overwriting.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
inserts to order memory updates before updating mask, then writes to the GIC
|
||||
*Priority Mask Register*, and make sure memory updates are visible before
|
||||
potential trigger due to mask update.
|
||||
|
||||
.. _plat_ic_get_interrupt_id:
|
||||
|
||||
Function: unsigned int plat_ic_get_interrupt_id(unsigned int raw); [optional]
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int
|
||||
Return : unsigned int
|
||||
|
||||
This API should extract and return the interrupt number from the raw value
|
||||
obtained by the acknowledging the interrupt (read using
|
||||
``plat_ic_acknowledge_interrupt()``). If the interrupt ID is invalid, this API
|
||||
should return ``INTR_ID_UNAVAILABLE``.
|
||||
|
||||
In case of Arm standard platforms using GIC, the implementation of the API
|
||||
masks out the interrupt ID field from the acknowledged value from GIC.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.*
|
||||
242
arm-trusted-firmware/docs/components/ras.rst
Normal file
242
arm-trusted-firmware/docs/components/ras.rst
Normal file
@@ -0,0 +1,242 @@
|
||||
Reliability, Availability, and Serviceability (RAS) Extensions
|
||||
==============================================================
|
||||
|
||||
This document describes |TF-A| support for Arm Reliability, Availability, and
|
||||
Serviceability (RAS) extensions. RAS is a mandatory extension for Armv8.2 and
|
||||
later CPUs, and also an optional extension to the base Armv8.0 architecture.
|
||||
|
||||
In conjunction with the |EHF|, support for RAS extension enables firmware-first
|
||||
paradigm for handling platform errors: exceptions resulting from errors in
|
||||
Non-secure world are routed to and handled in EL3.
|
||||
Said errors are Synchronous External Abort (SEA), Asynchronous External Abort
|
||||
(signalled as SErrors), Fault Handling and Error Recovery interrupts.
|
||||
The |EHF| document mentions various :ref:`error handling
|
||||
use-cases <delegation-use-cases>` .
|
||||
|
||||
For the description of Arm RAS extensions, Standard Error Records, and the
|
||||
precise definition of RAS terminology, please refer to the Arm Architecture
|
||||
Reference Manual. The rest of this document assumes familiarity with
|
||||
architecture and terminology.
|
||||
|
||||
Overview
|
||||
--------
|
||||
|
||||
As mentioned above, the RAS support in |TF-A| enables routing to and handling of
|
||||
exceptions resulting from platform errors in EL3. It allows the platform to
|
||||
define an External Abort handler, and to register RAS nodes and interrupts. RAS
|
||||
framework also provides `helpers`__ for accessing Standard Error Records as
|
||||
introduced by the RAS extensions.
|
||||
|
||||
.. __: `Standard Error Record helpers`_
|
||||
|
||||
The build option ``RAS_EXTENSION`` when set to ``1`` includes the RAS in run
|
||||
time firmware; ``EL3_EXCEPTION_HANDLING`` and ``HANDLE_EA_EL3_FIRST_NS`` must also
|
||||
be set ``1``. ``RAS_TRAP_NS_ERR_REC_ACCESS`` controls the access to the RAS
|
||||
error record registers from Non-secure.
|
||||
|
||||
.. _ras-figure:
|
||||
|
||||
.. image:: ../resources/diagrams/draw.io/ras.svg
|
||||
|
||||
See more on `Engaging the RAS framework`_.
|
||||
|
||||
Platform APIs
|
||||
-------------
|
||||
|
||||
The RAS framework allows the platform to define handlers for External Abort,
|
||||
Uncontainable Errors, Double Fault, and errors rising from EL3 execution. Please
|
||||
refer to :ref:`RAS Porting Guide <External Abort handling and RAS Support>`.
|
||||
|
||||
Registering RAS error records
|
||||
-----------------------------
|
||||
|
||||
RAS nodes are components in the system capable of signalling errors to PEs
|
||||
through one one of the notification mechanisms—SEAs, SErrors, or interrupts. RAS
|
||||
nodes contain one or more error records, which are registers through which the
|
||||
nodes advertise various properties of the signalled error. Arm recommends that
|
||||
error records are implemented in the Standard Error Record format. The RAS
|
||||
architecture allows for error records to be accessible via system or
|
||||
memory-mapped registers.
|
||||
|
||||
The platform should enumerate the error records providing for each of them:
|
||||
|
||||
- A handler to probe error records for errors;
|
||||
- When the probing identifies an error, a handler to handle it;
|
||||
- For memory-mapped error record, its base address and size in KB; for a system
|
||||
register-accessed record, the start index of the record and number of
|
||||
continuous records from that index;
|
||||
- Any node-specific auxiliary data.
|
||||
|
||||
With this information supplied, when the run time firmware receives one of the
|
||||
notification mechanisms, the RAS framework can iterate through and probe error
|
||||
records for error, and invoke the appropriate handler to handle it.
|
||||
|
||||
The RAS framework provides the macros to populate error record information. The
|
||||
macros are versioned, and the latest version as of this writing is 1. These
|
||||
macros create a structure of type ``struct err_record_info`` from its arguments,
|
||||
which are later passed to probe and error handlers.
|
||||
|
||||
For memory-mapped error records:
|
||||
|
||||
.. code:: c
|
||||
|
||||
ERR_RECORD_MEMMAP_V1(base_addr, size_num_k, probe, handler, aux)
|
||||
|
||||
And, for system register ones:
|
||||
|
||||
.. code:: c
|
||||
|
||||
ERR_RECORD_SYSREG_V1(idx_start, num_idx, probe, handler, aux)
|
||||
|
||||
The probe handler must have the following prototype:
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef int (*err_record_probe_t)(const struct err_record_info *info,
|
||||
int *probe_data);
|
||||
|
||||
The probe handler must return a non-zero value if an error was detected, or 0
|
||||
otherwise. The ``probe_data`` output parameter can be used to pass any useful
|
||||
information resulting from probe to the error handler (see `below`__). For
|
||||
example, it could return the index of the record.
|
||||
|
||||
.. __: `Standard Error Record helpers`_
|
||||
|
||||
The error handler must have the following prototype:
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef int (*err_record_handler_t)(const struct err_record_info *info,
|
||||
int probe_data, const struct err_handler_data *const data);
|
||||
|
||||
The ``data`` constant parameter describes the various properties of the error,
|
||||
including the reason for the error, exception syndrome, and also ``flags``,
|
||||
``cookie``, and ``handle`` parameters from the :ref:`top-level exception handler
|
||||
<EL3 interrupts>`.
|
||||
|
||||
The platform is expected populate an array using the macros above, and register
|
||||
the it with the RAS framework using the macro ``REGISTER_ERR_RECORD_INFO()``,
|
||||
passing it the name of the array describing the records. Note that the macro
|
||||
must be used in the same file where the array is defined.
|
||||
|
||||
Standard Error Record helpers
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The |TF-A| RAS framework provides probe handlers for Standard Error Records, for
|
||||
both memory-mapped and System Register accesses:
|
||||
|
||||
.. code:: c
|
||||
|
||||
int ras_err_ser_probe_memmap(const struct err_record_info *info,
|
||||
int *probe_data);
|
||||
|
||||
int ras_err_ser_probe_sysreg(const struct err_record_info *info,
|
||||
int *probe_data);
|
||||
|
||||
When the platform enumerates error records, for those records in the Standard
|
||||
Error Record format, these helpers maybe used instead of rolling out their own.
|
||||
Both helpers above:
|
||||
|
||||
- Return non-zero value when an error is detected in a Standard Error Record;
|
||||
- Set ``probe_data`` to the index of the error record upon detecting an error.
|
||||
|
||||
Registering RAS interrupts
|
||||
--------------------------
|
||||
|
||||
RAS nodes can signal errors to the PE by raising Fault Handling and/or Error
|
||||
Recovery interrupts. For the firmware-first handling paradigm for interrupts to
|
||||
work, the platform must setup and register with |EHF|. See `Interaction with
|
||||
Exception Handling Framework`_.
|
||||
|
||||
For each RAS interrupt, the platform has to provide structure of type ``struct
|
||||
ras_interrupt``:
|
||||
|
||||
- Interrupt number;
|
||||
- The associated error record information (pointer to the corresponding
|
||||
``struct err_record_info``);
|
||||
- Optionally, a cookie.
|
||||
|
||||
The platform is expected to define an array of ``struct ras_interrupt``, and
|
||||
register it with the RAS framework using the macro
|
||||
``REGISTER_RAS_INTERRUPTS()``, passing it the name of the array. Note that the
|
||||
macro must be used in the same file where the array is defined.
|
||||
|
||||
The array of ``struct ras_interrupt`` must be sorted in the increasing order of
|
||||
interrupt number. This allows for fast look of handlers in order to service RAS
|
||||
interrupts.
|
||||
|
||||
Double-fault handling
|
||||
---------------------
|
||||
|
||||
A Double Fault condition arises when an error is signalled to the PE while
|
||||
handling of a previously signalled error is still underway. When a Double Fault
|
||||
condition arises, the Arm RAS extensions only require for handler to perform
|
||||
orderly shutdown of the system, as recovery may be impossible.
|
||||
|
||||
The RAS extensions part of Armv8.4 introduced new architectural features to deal
|
||||
with Double Fault conditions, specifically, the introduction of ``NMEA`` and
|
||||
``EASE`` bits to ``SCR_EL3`` register. These were introduced to assist EL3
|
||||
software which runs part of its entry/exit routines with exceptions momentarily
|
||||
masked—meaning, in such systems, External Aborts/SErrors are not immediately
|
||||
handled when they occur, but only after the exceptions are unmasked again.
|
||||
|
||||
|TF-A|, for legacy reasons, executes entire EL3 with all exceptions unmasked.
|
||||
This means that all exceptions routed to EL3 are handled immediately. |TF-A|
|
||||
thus is able to detect a Double Fault conditions in software, without needing
|
||||
the intended advantages of Armv8.4 Double Fault architecture extensions.
|
||||
|
||||
Double faults are fatal, and terminate at the platform double fault handler, and
|
||||
doesn't return.
|
||||
|
||||
Engaging the RAS framework
|
||||
--------------------------
|
||||
|
||||
Enabling RAS support is a platform choice constructed from three distinct, but
|
||||
related, build options:
|
||||
|
||||
- ``RAS_EXTENSION=1`` includes the RAS framework in the run time firmware;
|
||||
|
||||
- ``EL3_EXCEPTION_HANDLING=1`` enables handling of exceptions at EL3. See
|
||||
`Interaction with Exception Handling Framework`_;
|
||||
|
||||
- ``HANDLE_EA_EL3_FIRST_NS=1`` enables routing of External Aborts and SErrors,
|
||||
resulting from errors in NS world, to EL3.
|
||||
|
||||
The RAS support in |TF-A| introduces a default implementation of
|
||||
``plat_ea_handler``, the External Abort handler in EL3. When ``RAS_EXTENSION``
|
||||
is set to ``1``, it'll first call ``ras_ea_handler()`` function, which is the
|
||||
top-level RAS exception handler. ``ras_ea_handler`` is responsible for iterating
|
||||
to through platform-supplied error records, probe them, and when an error is
|
||||
identified, look up and invoke the corresponding error handler.
|
||||
|
||||
Note that, if the platform chooses to override the ``plat_ea_handler`` function
|
||||
and intend to use the RAS framework, it must explicitly call
|
||||
``ras_ea_handler()`` from within.
|
||||
|
||||
Similarly, for RAS interrupts, the framework defines
|
||||
``ras_interrupt_handler()``. The RAS framework arranges for it to be invoked
|
||||
when a RAS interrupt taken at EL3. The function bisects the platform-supplied
|
||||
sorted array of interrupts to look up the error record information associated
|
||||
with the interrupt number. That error handler for that record is then invoked to
|
||||
handle the error.
|
||||
|
||||
Interaction with Exception Handling Framework
|
||||
---------------------------------------------
|
||||
|
||||
As mentioned in earlier sections, RAS framework interacts with the |EHF| to
|
||||
arbitrate handling of RAS exceptions with others that are routed to EL3. This
|
||||
means that the platform must partition a :ref:`priority level <Partitioning
|
||||
priority levels>` for handling RAS exceptions. The platform must then define
|
||||
the macro ``PLAT_RAS_PRI`` to the priority level used for RAS exceptions.
|
||||
Platforms would typically want to allocate the highest secure priority for
|
||||
RAS handling.
|
||||
|
||||
Handling of both :ref:`interrupt <interrupt-flow>` and :ref:`non-interrupt
|
||||
<non-interrupt-flow>` exceptions follow the sequences outlined in the |EHF|
|
||||
documentation. I.e., for interrupts, the priority management is implicit; but
|
||||
for non-interrupt exceptions, they're explicit using :ref:`EHF APIs
|
||||
<Activating and Deactivating priorities>`.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.*
|
||||
@@ -0,0 +1,391 @@
|
||||
|
||||
Realm Management Extension (RME)
|
||||
====================================
|
||||
|
||||
FEAT_RME (or RME for short) is an Armv9-A extension and is one component of the
|
||||
`Arm Confidential Compute Architecture (Arm CCA)`_. TF-A supports RME starting
|
||||
from version 2.6. This chapter discusses the changes to TF-A to support RME and
|
||||
provides instructions on how to build and run TF-A with RME.
|
||||
|
||||
RME support in TF-A
|
||||
---------------------
|
||||
|
||||
The following diagram shows an Arm CCA software architecture with TF-A as the
|
||||
EL3 firmware. In the Arm CCA architecture there are two additional security
|
||||
states and address spaces: ``Root`` and ``Realm``. TF-A firmware runs in the
|
||||
Root world. In the realm world, a Realm Management Monitor firmware (RMM)
|
||||
manages the execution of Realm VMs and their interaction with the hypervisor.
|
||||
|
||||
.. image:: ../resources/diagrams/arm-cca-software-arch.png
|
||||
|
||||
RME is the hardware extension to support Arm CCA. To support RME, various
|
||||
changes have been introduced to TF-A. We discuss those changes below.
|
||||
|
||||
Changes to translation tables library
|
||||
***************************************
|
||||
RME adds Root and Realm Physical address spaces. To support this, two new
|
||||
memory type macros, ``MT_ROOT`` and ``MT_REALM``, have been added to the
|
||||
:ref:`Translation (XLAT) Tables Library`. These macros are used to configure
|
||||
memory regions as Root or Realm respectively.
|
||||
|
||||
.. note::
|
||||
|
||||
Only version 2 of the translation tables library supports the new memory
|
||||
types.
|
||||
|
||||
Changes to context management
|
||||
*******************************
|
||||
A new CPU context for the Realm world has been added. The existing
|
||||
:ref:`CPU context management API<PSCI Library Integration guide for Armv8-A
|
||||
AArch32 systems>` can be used to manage Realm context.
|
||||
|
||||
Boot flow changes
|
||||
*******************
|
||||
In a typical TF-A boot flow, BL2 runs at Secure-EL1. However when RME is
|
||||
enabled, TF-A runs in the Root world at EL3. Therefore, the boot flow is
|
||||
modified to run BL2 at EL3 when RME is enabled. In addition to this, a
|
||||
Realm-world firmware (RMM) is loaded by BL2 in the Realm physical address
|
||||
space.
|
||||
|
||||
The boot flow when RME is enabled looks like the following:
|
||||
|
||||
1. BL1 loads and executes BL2 at EL3
|
||||
2. BL2 loads images including RMM
|
||||
3. BL2 transfers control to BL31
|
||||
4. BL31 initializes SPM (if SPM is enabled)
|
||||
5. BL31 initializes RMM
|
||||
6. BL31 transfers control to Normal-world software
|
||||
|
||||
Granule Protection Tables (GPT) library
|
||||
*****************************************
|
||||
Isolation between the four physical address spaces is enforced by a process
|
||||
called Granule Protection Check (GPC) performed by the MMU downstream any
|
||||
address translation. GPC makes use of Granule Protection Table (GPT) in the
|
||||
Root world that describes the physical address space assignment of every
|
||||
page (granule). A GPT library that provides APIs to initialize GPTs and to
|
||||
transition granules between different physical address spaces has been added.
|
||||
More information about the GPT library can be found in the
|
||||
:ref:`Granule Protection Tables Library` chapter.
|
||||
|
||||
RMM Dispatcher (RMMD)
|
||||
************************
|
||||
RMMD is a new standard runtime service that handles the switch to the Realm
|
||||
world. It initializes the RMM and handles Realm Management Interface (RMI)
|
||||
SMC calls from Non-secure and Realm worlds.
|
||||
|
||||
There is a contract between RMM and RMMD that defines the arguments that the
|
||||
former needs to take in order to initialize and also the possible return values.
|
||||
This contract is defined in the RMM Boot Interface, which can be found at
|
||||
:ref:`rmm_el3_boot_interface`.
|
||||
|
||||
There is also a specification of the runtime services provided by TF-A
|
||||
to RMM. This can be found at :ref:`runtime_services_and_interface`.
|
||||
|
||||
Test Realm Payload (TRP)
|
||||
*************************
|
||||
TRP is a small test payload that runs at R-EL2 and implements a subset of
|
||||
the Realm Management Interface (RMI) commands to primarily test EL3 firmware
|
||||
and the interface between R-EL2 and EL3. When building TF-A with RME enabled,
|
||||
if a path to an RMM image is not provided, TF-A builds the TRP by default
|
||||
and uses it as RMM image.
|
||||
|
||||
Building and running TF-A with RME
|
||||
------------------------------------
|
||||
|
||||
This section describes how you can build and run TF-A with RME enabled.
|
||||
We assume you have all the :ref:`Prerequisites` to build TF-A.
|
||||
|
||||
The following instructions show you how to build and run TF-A with RME
|
||||
for two scenarios:
|
||||
|
||||
- Three-world execution: TF-A with TF-A Tests or Linux.
|
||||
|
||||
- NS (TF-A Test or Linux),
|
||||
- Root (TF-A)
|
||||
- Realm (RMM or TRP)
|
||||
|
||||
- Four-world execution: TF-A, Hafnium and TF-A Tests or Linux.
|
||||
|
||||
- NS (TF-A Test or Linux),
|
||||
- Root (TF-A)
|
||||
- Realm (RMM or TRP)
|
||||
- SPM (Hafnium)
|
||||
|
||||
To run the tests, you need an FVP model. Please use the :ref:`latest version
|
||||
<Arm Fixed Virtual Platforms (FVP)>` of *FVP_Base_RevC-2xAEMvA* model.
|
||||
|
||||
Three World Testing with TF-A Tests
|
||||
*************************************
|
||||
|
||||
**1. Obtain and build TF-A Tests with Realm Payload**
|
||||
|
||||
The full set of instructions to setup build host and build options for
|
||||
TF-A-Tests can be found in the `TFTF Getting Started`_.
|
||||
|
||||
Use the following instructions to build TF-A with `TF-A Tests`_ as the
|
||||
non-secure payload (BL33).
|
||||
|
||||
.. code:: shell
|
||||
|
||||
git clone https://git.trustedfirmware.org/TF-A/tf-a-tests.git
|
||||
cd tf-a-tests
|
||||
make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 all pack_realm
|
||||
|
||||
This produces a TF-A Tests binary (**tftf.bin**) with Realm payload packaged
|
||||
and **sp_layout.json** in the **build/fvp/debug** directory.
|
||||
|
||||
**2. Obtain and build RMM Image**
|
||||
|
||||
Please refer to the `RMM Getting Started`_ on how to setup
|
||||
Host Environment and build RMM.
|
||||
|
||||
The below command shows how to build RMM using the default build options for FVP.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
git clone --recursive https://git.trustedfirmware.org/TF-RMM/tf-rmm.git
|
||||
cd tf-rmm
|
||||
cmake -DRMM_CONFIG=fvp_defcfg -S . -B build
|
||||
cmake --build build
|
||||
|
||||
This will generate **rmm.img** in **build** folder.
|
||||
|
||||
**3. Build TF-A**
|
||||
|
||||
The `TF-A Getting Started`_ has the necessary instructions to setup Host
|
||||
machine and build TF-A.
|
||||
|
||||
To build for RME, set ``ENABLE_RME`` build option to 1 and provide the path to
|
||||
the RMM binary using the ``RMM`` build option.
|
||||
Currently, this feature is only supported for the FVP platform.
|
||||
|
||||
.. note::
|
||||
|
||||
ENABLE_RME build option is currently experimental.
|
||||
|
||||
If the ``RMM`` option is not used, then the Test Realm Payload (TRP) in TF-A
|
||||
will be built and used as the RMM.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
|
||||
cd trusted-firmware-a
|
||||
make CROSS_COMPILE=aarch64-none-elf- \
|
||||
PLAT=fvp \
|
||||
ENABLE_RME=1 \
|
||||
RMM=<path/to/rmm.img> \
|
||||
FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts \
|
||||
DEBUG=1 \
|
||||
BL33=<path/to/tftf.bin> \
|
||||
all fip
|
||||
|
||||
This produces **bl1.bin** and **fip.bin** binaries in the **build/fvp/debug** directory.
|
||||
|
||||
Running the tests for a 3 world FVP setup
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Use the following command to run the tests on FVP. TF-A Tests should boot
|
||||
and run the default tests including Realm world tests.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
FVP_Base_RevC-2xAEMvA \
|
||||
-C bp.refcounter.non_arch_start_at_default=1 \
|
||||
-C bp.secureflashloader.fname=<path/to/bl1.bin> \
|
||||
-C bp.flashloader0.fname=<path/to/fip.bin> \
|
||||
-C bp.refcounter.use_real_time=0 \
|
||||
-C bp.ve_sysregs.exit_on_shutdown=1 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C bp.dram_size=2 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C pci.pci_smmuv3.mmu.SMMU_ROOT_IDR0=3 \
|
||||
-C pci.pci_smmuv3.mmu.SMMU_ROOT_IIDR=0x43B \
|
||||
-C pci.pci_smmuv3.mmu.root_register_page_offset=0x20000 \
|
||||
-C cluster0.NUM_CORES=4 \
|
||||
-C cluster0.PA_SIZE=48 \
|
||||
-C cluster0.ecv_support_level=2 \
|
||||
-C cluster0.gicv3.cpuintf-mmap-access-level=2 \
|
||||
-C cluster0.gicv3.without-DS-support=1 \
|
||||
-C cluster0.gicv4.mask-virtual-interrupt=1 \
|
||||
-C cluster0.has_arm_v8-6=1 \
|
||||
-C cluster0.has_amu=1 \
|
||||
-C cluster0.has_branch_target_exception=1 \
|
||||
-C cluster0.rme_support_level=2 \
|
||||
-C cluster0.has_rndr=1 \
|
||||
-C cluster0.has_v8_7_pmu_extension=2 \
|
||||
-C cluster0.max_32bit_el=-1 \
|
||||
-C cluster0.stage12_tlb_size=1024 \
|
||||
-C cluster0.check_memory_attributes=0 \
|
||||
-C cluster0.ish_is_osh=1 \
|
||||
-C cluster0.restriction_on_speculative_execution=2 \
|
||||
-C cluster0.restriction_on_speculative_execution_aarch32=2 \
|
||||
-C cluster1.NUM_CORES=4 \
|
||||
-C cluster1.PA_SIZE=48 \
|
||||
-C cluster1.ecv_support_level=2 \
|
||||
-C cluster1.gicv3.cpuintf-mmap-access-level=2 \
|
||||
-C cluster1.gicv3.without-DS-support=1 \
|
||||
-C cluster1.gicv4.mask-virtual-interrupt=1 \
|
||||
-C cluster1.has_arm_v8-6=1 \
|
||||
-C cluster1.has_amu=1 \
|
||||
-C cluster1.has_branch_target_exception=1 \
|
||||
-C cluster1.rme_support_level=2 \
|
||||
-C cluster1.has_rndr=1 \
|
||||
-C cluster1.has_v8_7_pmu_extension=2 \
|
||||
-C cluster1.max_32bit_el=-1 \
|
||||
-C cluster1.stage12_tlb_size=1024 \
|
||||
-C cluster1.check_memory_attributes=0 \
|
||||
-C cluster1.ish_is_osh=1 \
|
||||
-C cluster1.restriction_on_speculative_execution=2 \
|
||||
-C cluster1.restriction_on_speculative_execution_aarch32=2 \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.smsc_91c111.enabled=1 \
|
||||
-C bp.hostbridge.userNetworking=1
|
||||
|
||||
The bottom of the output from *uart0* should look something like the following.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
...
|
||||
|
||||
> Test suite 'FF-A Interrupt'
|
||||
Passed
|
||||
> Test suite 'SMMUv3 tests'
|
||||
Passed
|
||||
> Test suite 'PMU Leakage'
|
||||
Passed
|
||||
> Test suite 'DebugFS'
|
||||
Passed
|
||||
> Test suite 'RMI and SPM tests'
|
||||
Passed
|
||||
> Test suite 'Realm payload at EL1'
|
||||
Passed
|
||||
> Test suite 'Invalid memory access'
|
||||
Passed
|
||||
...
|
||||
|
||||
Building TF-A with RME enabled Linux Kernel
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
If an RME enabled Linux kernel and filesystem is available for testing,
|
||||
and a suitable NS boot loader is not available, then this option can be used to
|
||||
launch kernel directly after BL31:
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
cd trusted-firmware-a
|
||||
make CROSS_COMPILE=aarch64-none-elf- \
|
||||
PLAT=fvp \
|
||||
ENABLE_RME=1 \
|
||||
RMM=<path/to/rmm.img> \
|
||||
FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts \
|
||||
DEBUG=1 \
|
||||
ARM_LINUX_KERNEL_AS_BL33=1 \
|
||||
PRELOADED_BL33_BASE=0x84000000 \
|
||||
all fip
|
||||
|
||||
Boot and run the RME enabled Linux Kernel
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Use the following additional arguments to boot the kernel on FVP.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
--data cluster0.cpu0=<path_to_kernel_Image>@0x84000000 \
|
||||
-C bp.virtioblockdevice.image_path=<path_to_rootfs.ext4>
|
||||
|
||||
.. tip::
|
||||
|
||||
Set the FVP option `cache_state_modelled=0` to run Linux based tests much faster.
|
||||
|
||||
Four-world execution with Hafnium and TF-A Tests
|
||||
*************************************************
|
||||
|
||||
Four-world execution involves software components in each security state: root,
|
||||
secure, realm and non-secure. This section describes how to build TF-A
|
||||
with four-world support.
|
||||
|
||||
We use TF-A as the root firmware, `Hafnium SPM`_ is the reference Secure world component
|
||||
and the software components for the other 2 worlds (Realm and Non-Secure)
|
||||
are as described in the previous section.
|
||||
|
||||
**1. Obtain and build Hafnium**
|
||||
|
||||
.. code:: shell
|
||||
|
||||
git clone --recurse-submodules https://git.trustedfirmware.org/hafnium/hafnium.git
|
||||
cd hafnium
|
||||
# Use the default prebuilt LLVM/clang toolchain
|
||||
PATH=$PWD/prebuilts/linux-x64/clang/bin:$PWD/prebuilts/linux-x64/dtc:$PATH
|
||||
|
||||
Feature MTE needs to be disabled in Hafnium build, apply following patch to
|
||||
project/reference submodule
|
||||
|
||||
.. code:: diff
|
||||
|
||||
diff --git a/BUILD.gn b/BUILD.gn
|
||||
index cc6a78f..234b20a 100644
|
||||
--- a/BUILD.gn
|
||||
+++ b/BUILD.gn
|
||||
@@ -83,7 +83,6 @@ aarch64_toolchains("secure_aem_v8a_fvp") {
|
||||
pl011_base_address = "0x1c090000"
|
||||
smmu_base_address = "0x2b400000"
|
||||
smmu_memory_size = "0x100000"
|
||||
- enable_mte = "1"
|
||||
plat_log_level = "LOG_LEVEL_INFO"
|
||||
}
|
||||
}
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PROJECT=reference
|
||||
|
||||
The Hafnium binary should be located at
|
||||
*out/reference/secure_aem_v8a_fvp_clang/hafnium.bin*
|
||||
|
||||
**2. Build TF-A**
|
||||
|
||||
Build TF-A with RME as well as SPM enabled.
|
||||
|
||||
Use sp_layout.json previously generated in tf-a-test build.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make CROSS_COMPILE=aarch64-none-elf- \
|
||||
PLAT=fvp \
|
||||
ENABLE_RME=1 \
|
||||
FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts \
|
||||
SPD=spmd \
|
||||
SPMD_SPM_AT_SEL2=1 \
|
||||
BRANCH_PROTECTION=1 \
|
||||
CTX_INCLUDE_PAUTH_REGS=1 \
|
||||
DEBUG=1 \
|
||||
SP_LAYOUT_FILE=<path/to/sp_layout.json> \
|
||||
BL32=<path/to/hafnium.bin> \
|
||||
BL33=<path/to/tftf.bin> \
|
||||
RMM=<path/to/rmm.img> \
|
||||
all fip
|
||||
|
||||
Running the tests for a 4 world FVP setup
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Use the following arguments in addition to
|
||||
`Running the tests for a 3 world FVP setup`_ to run tests for 4 world setup.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
-C pci.pci_smmuv3.mmu.SMMU_AIDR=2 \
|
||||
-C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B \
|
||||
-C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 \
|
||||
-C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 \
|
||||
-C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0475 \
|
||||
-C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 \
|
||||
-C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 \
|
||||
-C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0
|
||||
|
||||
.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture
|
||||
.. _Arm Architecture Models website: https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models
|
||||
.. _TF-A Getting Started: https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/index.html
|
||||
.. _TF-A Tests: https://trustedfirmware-a-tests.readthedocs.io/en/latest
|
||||
.. _TFTF Getting Started: https://trustedfirmware-a-tests.readthedocs.io/en/latest/getting_started/index.html
|
||||
.. _Hafnium SPM: https://www.trustedfirmware.org/projects/hafnium
|
||||
.. _RMM Getting Started: https://git.trustedfirmware.org/TF-RMM/tf-rmm.git/tree/docs/getting_started/index.rst
|
||||
543
arm-trusted-firmware/docs/components/rmm-el3-comms-spec.rst
Normal file
543
arm-trusted-firmware/docs/components/rmm-el3-comms-spec.rst
Normal file
@@ -0,0 +1,543 @@
|
||||
RMM-EL3 Communication interface
|
||||
*******************************
|
||||
|
||||
This document defines the communication interface between RMM and EL3.
|
||||
There are two parts in this interface: the boot interface and the runtime
|
||||
interface.
|
||||
|
||||
The Boot Interface defines the ABI between EL3 and RMM when the CPU enters
|
||||
R-EL2 for the first time after boot. The cold boot interface defines the ABI
|
||||
for the cold boot path and the warm boot interface defines the same for the
|
||||
warm path.
|
||||
|
||||
The RMM-EL3 runtime interface defines the ABI for EL3 services which can be
|
||||
invoked by RMM as well as the register save-restore convention when handling an
|
||||
SMC call from NS.
|
||||
|
||||
The below sections discuss these interfaces more in detail.
|
||||
|
||||
.. _rmm_el3_ifc_versioning:
|
||||
|
||||
RMM-EL3 Interface versioning
|
||||
____________________________
|
||||
|
||||
The RMM Boot and Runtime Interface uses a version number to check
|
||||
compatibility with the register arguments passed as part of Boot Interface and
|
||||
RMM-EL3 runtime interface.
|
||||
|
||||
The Boot Manifest, discussed later in section :ref:`rmm_el3_boot_manifest`,
|
||||
uses a separate version number but with the same scheme.
|
||||
|
||||
The version number is a 32-bit type with the following fields:
|
||||
|
||||
.. csv-table::
|
||||
:header: "Bits", "Value"
|
||||
|
||||
[0:15],``VERSION_MINOR``
|
||||
[16:30],``VERSION_MAJOR``
|
||||
[31],RES0
|
||||
|
||||
The version numbers are sequentially increased and the rules for updating them
|
||||
are explained below:
|
||||
|
||||
- ``VERSION_MAJOR``: This value is increased when changes break
|
||||
compatibility with previous versions. If the changes
|
||||
on the ABI are compatible with the previous one, ``VERSION_MAJOR``
|
||||
remains unchanged.
|
||||
|
||||
- ``VERSION_MINOR``: This value is increased on any change that is backwards
|
||||
compatible with the previous version. When ``VERSION_MAJOR`` is increased,
|
||||
``VERSION_MINOR`` must be set to 0.
|
||||
|
||||
- ``RES0``: Bit 31 of the version number is reserved 0 as to maintain
|
||||
consistency with the versioning schemes used in other parts of RMM.
|
||||
|
||||
This document specifies the 0.1 version of Boot Interface ABI and RMM-EL3
|
||||
services specification and the 0.1 version of the Boot Manifest.
|
||||
|
||||
.. _rmm_el3_boot_interface:
|
||||
|
||||
RMM Boot Interface
|
||||
__________________
|
||||
|
||||
This section deals with the Boot Interface part of the specification.
|
||||
|
||||
One of the goals of the Boot Interface is to allow EL3 firmware to pass
|
||||
down into RMM certain platform specific information dynamically. This allows
|
||||
RMM to be less platform dependent and be more generic across platform
|
||||
variations. It also allows RMM to be decoupled from the other boot loader
|
||||
images in the boot sequence and remain agnostic of any particular format used
|
||||
for configuration files.
|
||||
|
||||
The Boot Interface ABI defines a set of register conventions and
|
||||
also a memory based manifest file to pass information from EL3 to RMM. The
|
||||
boot manifest and the associated platform data in it can be dynamically created
|
||||
by EL3 and there is no restriction on how the data can be obtained (e.g by DTB,
|
||||
hoblist or other).
|
||||
|
||||
The register convention and the manifest are versioned separately to manage
|
||||
future enhancements and compatibility.
|
||||
|
||||
RMM completes the boot by issuing the ``RMM_BOOT_COMPLETE`` SMC (0xC40001CF)
|
||||
back to EL3. After the RMM has finished the boot process, it can only be
|
||||
entered from EL3 as part of RMI handling.
|
||||
|
||||
If RMM returns an error during boot (in any CPU), then RMM must not be entered
|
||||
from any CPU.
|
||||
|
||||
.. _rmm_cold_boot_interface:
|
||||
|
||||
Cold Boot Interface
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
During cold boot RMM expects the following register values:
|
||||
|
||||
.. csv-table::
|
||||
:header: "Register", "Value"
|
||||
:widths: 1, 5
|
||||
|
||||
x0,Linear index of this PE. This index starts from 0 and must be less than the maximum number of CPUs to be supported at runtime (see x2).
|
||||
x1,Version for this Boot Interface as defined in :ref:`rmm_el3_ifc_versioning`.
|
||||
x2,Maximum number of CPUs to be supported at runtime. RMM should ensure that it can support this maximum number.
|
||||
x3,Base address for the shared buffer used for communication between EL3 firmware and RMM. This buffer must be of 4KB size (1 page). The boot manifest must be present at the base of this shared buffer during cold boot.
|
||||
|
||||
During cold boot, EL3 firmware needs to allocate a 4K page that will be
|
||||
passed to RMM in x3. This memory will be used as shared buffer for communication
|
||||
between EL3 and RMM. It must be assigned to Realm world and must be mapped with
|
||||
Normal memory attributes (IWB-OWB-ISH) at EL3. At boot, this memory will be
|
||||
used to populate the Boot Manifest. Since the Boot Manifest can be accessed by
|
||||
RMM prior to enabling its MMU, EL3 must ensure that proper cache maintenance
|
||||
operations are performed after the Boot Manifest is populated.
|
||||
|
||||
EL3 should also ensure that this shared buffer is always available for use by RMM
|
||||
during the lifetime of the system and that it can be used for runtime
|
||||
communication between RMM and EL3. For example, when RMM invokes attestation
|
||||
service commands in EL3, this buffer can be used to exchange data between RMM
|
||||
and EL3. It is also allowed for RMM to invoke runtime services provided by EL3
|
||||
utilizing this buffer during the boot phase, prior to return back to EL3 via
|
||||
RMM_BOOT_COMPLETE SMC.
|
||||
|
||||
RMM should map this memory page into its Stage 1 page-tables using Normal
|
||||
memory attributes.
|
||||
|
||||
During runtime, it is the RMM which initiates any communication with EL3. If that
|
||||
communication requires the use of the shared area, it is expected that RMM needs
|
||||
to do the necessary concurrency protection to prevent the use of the same buffer
|
||||
by other PEs.
|
||||
|
||||
The following sequence diagram shows how a generic EL3 Firmware would boot RMM.
|
||||
|
||||
.. image:: ../resources/diagrams/rmm_cold_boot_generic.png
|
||||
|
||||
Warm Boot Interface
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
At warm boot, RMM is already initialized and only some per-CPU initialization
|
||||
is still pending. The only argument that is required by RMM at this stage is
|
||||
the CPU Id, which will be passed through register x0 whilst x1 to x3 are RES0.
|
||||
This is summarized in the following table:
|
||||
|
||||
.. csv-table::
|
||||
:header: "Register", "Value"
|
||||
:widths: 1, 5
|
||||
|
||||
x0,Linear index of this PE. This index starts from 0 and must be less than the maximum number of CPUs to be supported at runtime (see x2).
|
||||
x1 - x3,RES0
|
||||
|
||||
Boot error handling and return values
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
After boot up and initialization, RMM returns control back to EL3 through a
|
||||
``RMM_BOOT_COMPLETE`` SMC call. The only argument of this SMC call will
|
||||
be returned in x1 and it will encode a signed integer with the error reason
|
||||
as per the following table:
|
||||
|
||||
.. csv-table::
|
||||
:header: "Error code", "Description", "ID"
|
||||
:widths: 2 4 1
|
||||
|
||||
``E_RMM_BOOT_SUCCESS``,Boot successful,0
|
||||
``E_RMM_BOOT_ERR_UNKNOWN``,Unknown error,-1
|
||||
``E_RMM_BOOT_VERSION_NOT_VALID``,Boot Interface version reported by EL3 is not supported by RMM,-2
|
||||
``E_RMM_BOOT_CPUS_OUT_OF_RAGE``,Number of CPUs reported by EL3 larger than maximum supported by RMM,-3
|
||||
``E_RMM_BOOT_CPU_ID_OUT_OF_RAGE``,Current CPU Id is higher or equal than the number of CPUs supported by RMM,-4
|
||||
``E_RMM_BOOT_INVALID_SHARED_BUFFER``,Invalid pointer to shared memory area,-5
|
||||
``E_RMM_BOOT_MANIFEST_VERSION_NOT_SUPPORTED``,Version reported by the boot manifest not supported by RMM,-6
|
||||
``E_RMM_BOOT_MANIFEST_DATA_ERROR``,Error parsing core boot manifest,-7
|
||||
|
||||
For any error detected in RMM during cold or warm boot, RMM will return back to
|
||||
EL3 using ``RMM_BOOT_COMPLETE`` SMC with an appropriate error code. It is
|
||||
expected that EL3 will take necessary action to disable Realm world for further
|
||||
entry from NS Host on receiving an error. This will be done across all the PEs
|
||||
in the system so as to present a symmetric view to the NS Host. Any further
|
||||
warm boot by any PE should not enter RMM using the warm boot interface.
|
||||
|
||||
.. _rmm_el3_boot_manifest:
|
||||
|
||||
Boot Manifest
|
||||
~~~~~~~~~~~~~
|
||||
|
||||
During cold boot, EL3 Firmware passes a memory boot manifest to RMM containing
|
||||
platform information.
|
||||
|
||||
This boot manifest is versioned independently of the boot interface, to help
|
||||
evolve the boot manifest independent of the rest of Boot Manifest.
|
||||
The current version for the boot manifest is ``v0.1`` and the rules explained
|
||||
in :ref:`rmm_el3_ifc_versioning` apply on this version as well.
|
||||
|
||||
The boot manifest is divided into two different components:
|
||||
|
||||
- Core Manifest: This is the generic parameters passed to RMM by EL3 common to all platforms.
|
||||
- Platform data: This is defined by the platform owner and contains information specific to that platform.
|
||||
|
||||
For the current version of the manifest, the core manifest contains a pointer
|
||||
to the platform data. EL3 must ensure that the whole boot manifest,
|
||||
including the platform data, if available, fits inside the RMM EL3 shared
|
||||
buffer.
|
||||
|
||||
For the type specification of the RMM Boot Manifest v0.1, refer to
|
||||
:ref:`rmm_el3_manifest_struct`
|
||||
|
||||
.. _runtime_services_and_interface:
|
||||
|
||||
RMM-EL3 Runtime Interface
|
||||
__________________________
|
||||
|
||||
This section defines the RMM-EL3 runtime interface which specifies the ABI for
|
||||
EL3 services expected by RMM at runtime as well as the register save and
|
||||
restore convention between EL3 and RMM as part of RMI call handling. It is
|
||||
important to note that RMM is allowed to invoke EL3-RMM runtime interface
|
||||
services during the boot phase as well. The EL3 runtime service handling must
|
||||
not result in a world switch to another world unless specified. Both the RMM
|
||||
and EL3 are allowed to make suitable optimizations based on this assumption.
|
||||
|
||||
If the interface requires the use of memory, then the memory references should
|
||||
be within the shared buffer communicated as part of the boot interface. See
|
||||
:ref:`rmm_cold_boot_interface` for properties of this shared buffer which both
|
||||
EL3 and RMM must adhere to.
|
||||
|
||||
RMM-EL3 runtime service return codes
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The return codes from EL3 to RMM is a 32 bit signed integer which encapsulates
|
||||
error condition as described in the following table:
|
||||
|
||||
.. csv-table::
|
||||
:header: "Error code", "Description", "ID"
|
||||
:widths: 2 4 1
|
||||
|
||||
``E_RMM_OK``,No errors detected,0
|
||||
``E_RMM_UNK``,Unknown/Generic error,-1
|
||||
``E_RMM_BAD_ADDR``,The value of an address used as argument was invalid,-2
|
||||
``E_RMM_BAD_PAS``,Incorrect PAS,-3
|
||||
``E_RMM_NOMEM``,Not enough memory to perform an operation,-4
|
||||
``E_RMM_INVAL``,The value of an argument was invalid,-5
|
||||
|
||||
If multiple failure conditions are detected in an RMM to EL3 command, then EL3
|
||||
is allowed to return an error code corresponding to any of the failure
|
||||
conditions.
|
||||
|
||||
RMM-EL3 runtime services
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The following table summarizes the RMM runtime services that need to be
|
||||
implemented by EL3 Firmware.
|
||||
|
||||
.. csv-table::
|
||||
:header: "FID", "Command"
|
||||
:widths: 2 5
|
||||
|
||||
0xC400018F,``RMM_RMI_REQ_COMPLETE``
|
||||
0xC40001B0,``RMM_GTSI_DELEGATE``
|
||||
0xC40001B1,``RMM_GTSI_UNDELEGATE``
|
||||
0xC40001B2,``RMM_ATTEST_GET_REALM_KEY``
|
||||
0xC40001B3,``RMM_ATTEST_GET_PLAT_TOKEN``
|
||||
|
||||
RMM_RMI_REQ_COMPLETE command
|
||||
============================
|
||||
|
||||
Notifies the completion of an RMI call to the Non-Secure world.
|
||||
|
||||
This call is the only function currently in RMM-EL3 runtime interface which
|
||||
results in a world switch to NS. This call is the reply to the original RMI
|
||||
call and it is forwarded by EL3 to the NS world.
|
||||
|
||||
FID
|
||||
---
|
||||
|
||||
``0xC400018F``
|
||||
|
||||
Input values
|
||||
------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Register", "Field", "Type", "Description"
|
||||
:widths: 1 1 1 1 5
|
||||
|
||||
fid,x0,[63:0],UInt64,Command FID
|
||||
err_code,x1,[63:0],RmiCommandReturnCode,Error code returned by the RMI service invoked by NS World. See Realm Management Monitor specification for more info
|
||||
|
||||
Output values
|
||||
-------------
|
||||
|
||||
This call does not return.
|
||||
|
||||
Failure conditions
|
||||
------------------
|
||||
|
||||
Since this call does not return to RMM, there is no failure condition which
|
||||
can be notified back to RMM.
|
||||
|
||||
RMM_GTSI_DELEGATE command
|
||||
=========================
|
||||
|
||||
Delegate a memory granule by changing its PAS from Non-Secure to Realm.
|
||||
|
||||
FID
|
||||
---
|
||||
|
||||
``0xC40001B0``
|
||||
|
||||
Input values
|
||||
------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Register", "Field", "Type", "Description"
|
||||
:widths: 1 1 1 1 5
|
||||
|
||||
fid,x0,[63:0],UInt64,Command FID
|
||||
base_pa,x1,[63:0],Address,PA of the start of the granule to be delegated
|
||||
|
||||
Output values
|
||||
-------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Register", "Field", "Type", "Description"
|
||||
:widths: 1 1 1 2 4
|
||||
|
||||
Result,x0,[63:0],Error Code,Command return status
|
||||
|
||||
Failure conditions
|
||||
------------------
|
||||
|
||||
The table below shows all the possible error codes returned in ``Result`` upon
|
||||
a failure. The errors are ordered by condition check.
|
||||
|
||||
.. csv-table::
|
||||
:header: "ID", "Condition"
|
||||
:widths: 1 5
|
||||
|
||||
``E_RMM_BAD_ADDR``,``PA`` does not correspond to a valid granule address
|
||||
``E_RMM_BAD_PAS``,The granule pointed by ``PA`` does not belong to Non-Secure PAS
|
||||
``E_RMM_OK``,No errors detected
|
||||
|
||||
RMM_GTSI_UNDELEGATE command
|
||||
===========================
|
||||
|
||||
Undelegate a memory granule by changing its PAS from Realm to Non-Secure.
|
||||
|
||||
FID
|
||||
---
|
||||
|
||||
``0xC40001B1``
|
||||
|
||||
Input values
|
||||
------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Register", "Field", "Type", "Description"
|
||||
:widths: 1 1 1 1 5
|
||||
|
||||
fid,x0,[63:0],UInt64,Command FID
|
||||
base_pa,x1,[63:0],Address,PA of the start of the granule to be undelegated
|
||||
|
||||
Output values
|
||||
-------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Register", "Field", "Type", "Description"
|
||||
:widths: 1 1 1 2 4
|
||||
|
||||
Result,x0,[63:0],Error Code,Command return status
|
||||
|
||||
Failure conditions
|
||||
------------------
|
||||
|
||||
The table below shows all the possible error codes returned in ``Result`` upon
|
||||
a failure. The errors are ordered by condition check.
|
||||
|
||||
.. csv-table::
|
||||
:header: "ID", "Condition"
|
||||
:widths: 1 5
|
||||
|
||||
``E_RMM_BAD_ADDR``,``PA`` does not correspond to a valid granule address
|
||||
``E_RMM_BAD_PAS``,The granule pointed by ``PA`` does not belong to Realm PAS
|
||||
``E_RMM_OK``,No errors detected
|
||||
|
||||
RMM_ATTEST_GET_REALM_KEY command
|
||||
================================
|
||||
|
||||
Retrieve the Realm Attestation Token Signing key from EL3.
|
||||
|
||||
FID
|
||||
---
|
||||
|
||||
``0xC40001B2``
|
||||
|
||||
Input values
|
||||
------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Register", "Field", "Type", "Description"
|
||||
:widths: 1 1 1 1 5
|
||||
|
||||
fid,x0,[63:0],UInt64,Command FID
|
||||
buf_pa,x1,[63:0],Address,PA where the Realm Attestation Key must be stored by EL3. The PA must belong to the shared buffer
|
||||
buf_size,x2,[63:0],Size,Size in bytes of the Realm Attestation Key buffer. ``bufPa + bufSize`` must lie within the shared buffer
|
||||
ecc_curve,x3,[63:0],Enum,Type of the elliptic curve to which the requested attestation key belongs to. See :ref:`ecc_curves`
|
||||
|
||||
Output values
|
||||
-------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Register", "Field", "Type", "Description"
|
||||
:widths: 1 1 1 1 5
|
||||
|
||||
Result,x0,[63:0],Error Code,Command return status
|
||||
keySize,x1,[63:0],Size,Size of the Realm Attestation Key
|
||||
|
||||
Failure conditions
|
||||
------------------
|
||||
|
||||
The table below shows all the possible error codes returned in ``Result`` upon
|
||||
a failure. The errors are ordered by condition check.
|
||||
|
||||
.. csv-table::
|
||||
:header: "ID", "Condition"
|
||||
:widths: 1 5
|
||||
|
||||
``E_RMM_BAD_ADDR``,``PA`` is outside the shared buffer
|
||||
``E_RMM_INVAL``,``PA + BSize`` is outside the shared buffer
|
||||
``E_RMM_INVAL``,``Curve`` is not one of the listed in :ref:`ecc_curves`
|
||||
``E_RMM_UNK``,An unknown error occurred whilst processing the command
|
||||
``E_RMM_OK``,No errors detected
|
||||
|
||||
.. _ecc_curves:
|
||||
|
||||
Supported ECC Curves
|
||||
--------------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "ID", "Curve"
|
||||
:widths: 1 5
|
||||
|
||||
0,ECC SECP384R1
|
||||
|
||||
RMM_ATTEST_GET_PLAT_TOKEN command
|
||||
=================================
|
||||
|
||||
Retrieve the Platform Token from EL3.
|
||||
|
||||
FID
|
||||
---
|
||||
|
||||
``0xC40001B3``
|
||||
|
||||
Input values
|
||||
------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Register", "Field", "Type", "Description"
|
||||
:widths: 1 1 1 1 5
|
||||
|
||||
fid,x0,[63:0],UInt64,Command FID
|
||||
buf_pa,x1,[63:0],Address,PA of the platform attestation token. The challenge object is passed in this buffer. The PA must belong to the shared buffer
|
||||
buf_size,x2,[63:0],Size,Size in bytes of the platform attestation token buffer. ``bufPa + bufSize`` must lie within the shared buffer
|
||||
c_size,x3,[63:0],Size,Size in bytes of the challenge object. It corresponds to the size of one of the defined SHA algorithms
|
||||
|
||||
Output values
|
||||
-------------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Register", "Field", "Type", "Description"
|
||||
:widths: 1 1 1 1 5
|
||||
|
||||
Result,x0,[63:0],Error Code,Command return status
|
||||
tokenSize,x1,[63:0],Size,Size of the platform token
|
||||
|
||||
Failure conditions
|
||||
------------------
|
||||
|
||||
The table below shows all the possible error codes returned in ``Result`` upon
|
||||
a failure. The errors are ordered by condition check.
|
||||
|
||||
.. csv-table::
|
||||
:header: "ID", "Condition"
|
||||
:widths: 1 5
|
||||
|
||||
``E_RMM_BAD_ADDR``,``PA`` is outside the shared buffer
|
||||
``E_RMM_INVAL``,``PA + BSize`` is outside the shared buffer
|
||||
``E_RMM_INVAL``,``CSize`` does not represent the size of a supported SHA algorithm
|
||||
``E_RMM_UNK``,An unknown error occurred whilst processing the command
|
||||
``E_RMM_OK``,No errors detected
|
||||
|
||||
RMM-EL3 world switch register save restore convention
|
||||
_____________________________________________________
|
||||
|
||||
As part of NS world switch, EL3 is expected to maintain a register context
|
||||
specific to each world and will save and restore the registers
|
||||
appropriately. This section captures the contract between EL3 and RMM on the
|
||||
register set to be saved and restored.
|
||||
|
||||
EL3 must maintain a separate register context for the following:
|
||||
|
||||
#. General purpose registers (x0-x30) and ``sp_el0``, ``sp_el2`` stack pointers
|
||||
#. EL2 system register context for all enabled features by EL3. These include system registers with the ``_EL2`` prefix. The EL2 physical and virtual timer registers must not be included in this.
|
||||
|
||||
As part of SMC forwarding between the NS world and Realm world, EL3 allows x0-x7 to be passed
|
||||
as arguments to Realm and x0-x4 to be used for return arguments back to Non Secure.
|
||||
As per SMCCCv1.2, x4 must be preserved if not being used as return argument by the SMC function
|
||||
and it is the responsibility of RMM to preserve this or use this as a return argument.
|
||||
EL3 will always copy x0-x4 from Realm context to NS Context.
|
||||
|
||||
EL3 will not save some registers as mentioned in the below list. It is the
|
||||
responsibility of RMM to ensure that these are appropriately saved if the
|
||||
Realm World makes use of them:
|
||||
|
||||
#. FP/SIMD registers
|
||||
#. SVE registers
|
||||
#. SME registers
|
||||
#. EL1/0 registers
|
||||
|
||||
It is the responsibility of EL3 that any other registers other than the ones mentioned above
|
||||
will not be leaked to the NS Host and to maintain the confidentiality of the Realm World.
|
||||
|
||||
SMCCC v1.3 allows NS world to specify whether SVE context is in use. In this
|
||||
case, RMM could choose to not save the incoming SVE context but must ensure
|
||||
to clear SVE registers if they have been used in Realm World. The same applies
|
||||
to SME registers.
|
||||
|
||||
Types
|
||||
_____
|
||||
|
||||
.. _rmm_el3_manifest_struct:
|
||||
|
||||
RMM-EL3 Boot Manifest Version
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The RMM-EL3 Boot Manifest structure contains platform boot information passed
|
||||
from EL3 to RMM. The width of the Boot Manifest is 128 bits
|
||||
|
||||
.. image:: ../resources/diagrams/rmm_el3_manifest_struct.png
|
||||
|
||||
The members of the RMM-EL3 Boot Manifest structure are shown in the following
|
||||
table:
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Range", "Type", Description
|
||||
:widths: 2 1 1 4
|
||||
|
||||
``Version Minor``,15:0,uint16_t,Version Minor part of the Boot Manifest Version.
|
||||
``Version Major``,30:16,uint16_t,Version Major part of the Boot Manifest Version.
|
||||
``RES0``,31,bit,Reserved. Set to 0.
|
||||
``Platform Data``,127:64,Address,Pointer to the Platform Data section of the Boot Manifest.
|
||||
155
arm-trusted-firmware/docs/components/romlib-design.rst
Normal file
155
arm-trusted-firmware/docs/components/romlib-design.rst
Normal file
@@ -0,0 +1,155 @@
|
||||
Library at ROM
|
||||
==============
|
||||
|
||||
This document provides an overview of the "library at ROM" implementation in
|
||||
Trusted Firmware-A (TF-A).
|
||||
|
||||
Introduction
|
||||
~~~~~~~~~~~~
|
||||
|
||||
The "library at ROM" feature allows platforms to build a library of functions to
|
||||
be placed in ROM. This reduces SRAM usage by utilising the available space in
|
||||
ROM. The "library at ROM" contains a jump table with the list of functions that
|
||||
are placed in ROM. The capabilities of the "library at ROM" are:
|
||||
|
||||
1. Functions can be from one or several libraries.
|
||||
|
||||
2. Functions can be patched after they have been programmed into ROM.
|
||||
|
||||
3. Platform-specific libraries can be placed in ROM.
|
||||
|
||||
4. Functions can be accessed by one or more BL images.
|
||||
|
||||
Index file
|
||||
~~~~~~~~~~
|
||||
|
||||
.. image:: ../resources/diagrams/romlib_design.png
|
||||
:width: 600
|
||||
|
||||
Library at ROM is described by an index file with the list of functions to be
|
||||
placed in ROM. The index file is platform specific and its format is:
|
||||
|
||||
::
|
||||
|
||||
lib function [patch]
|
||||
|
||||
lib -- Name of the library the function belongs to
|
||||
function -- Name of the function to be placed in library at ROM
|
||||
[patch] -- Option to patch the function
|
||||
|
||||
It is also possible to insert reserved spaces in the list by using the keyword
|
||||
"reserved" rather than the "lib" and "function" names as shown below:
|
||||
|
||||
::
|
||||
|
||||
reserved
|
||||
|
||||
The reserved spaces can be used to add more functions in the future without
|
||||
affecting the order and location of functions already existing in the jump
|
||||
table. Also, for additional flexibility and modularity, the index file can
|
||||
include other index files.
|
||||
|
||||
For an index file example, refer to ``lib/romlib/jmptbl.i``.
|
||||
|
||||
Wrapper functions
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
.. image:: ../resources/diagrams/romlib_wrapper.png
|
||||
:width: 600
|
||||
|
||||
When invoking a function of the "library at ROM", the calling sequence is as
|
||||
follows:
|
||||
|
||||
BL image --> wrapper function --> jump table entry --> library at ROM
|
||||
|
||||
The index file is used to create a jump table which is placed in ROM. Then, the
|
||||
wrappers refer to the jump table to call the "library at ROM" functions. The
|
||||
wrappers essentially contain a branch instruction to the jump table entry
|
||||
corresponding to the original function. Finally, the original function in the BL
|
||||
image(s) is replaced with the wrapper function.
|
||||
|
||||
The "library at ROM" contains a necessary init function that initialises the
|
||||
global variables defined by the functions inside "library at ROM".
|
||||
|
||||
Script
|
||||
~~~~~~
|
||||
|
||||
There is a ``romlib_generate.py`` Python script that generates the necessary
|
||||
files for the "library at ROM" to work. It implements multiple functions:
|
||||
|
||||
1. ``romlib_generate.py gentbl [args]`` - Generates the jump table by parsing
|
||||
the index file.
|
||||
|
||||
2. ``romlib_generator.py genvar [args]`` - Generates the jump table global
|
||||
variable (**not** the jump table itself) with the absolute address in ROM.
|
||||
This global variable is, basically, a pointer to the jump table.
|
||||
|
||||
3. ``romlib_generator.py genwrappers [args]`` - Generates a wrapper function for
|
||||
each entry in the index file except for the ones that contain the keyword
|
||||
``patch``. The generated wrapper file is called ``<fn_name>.s``.
|
||||
|
||||
4. ``romlib_generator.py pre [args]`` - Preprocesses the index file which means
|
||||
it resolves all the include commands in the file recursively. It can also
|
||||
generate a dependency file of the included index files which can be directly
|
||||
used in makefiles.
|
||||
|
||||
Each ``romlib_generate.py`` function has its own manual which is accessible by
|
||||
runing ``romlib_generator.py [function] --help``.
|
||||
|
||||
``romlib_generate.py`` requires Python 3 environment.
|
||||
|
||||
|
||||
Patching of functions in library at ROM
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The ``romlib_generator.py genwrappers`` does not generate wrappers for the
|
||||
entries in the index file that contain the keyword ``patch``. Thus, it allows
|
||||
calling the function from the actual library by breaking the link to the
|
||||
"library at ROM" version of this function.
|
||||
|
||||
The calling sequence for a patched function is as follows:
|
||||
|
||||
BL image --> function
|
||||
|
||||
Memory impact
|
||||
~~~~~~~~~~~~~
|
||||
|
||||
Using library at ROM will modify the memory layout of the BL images:
|
||||
|
||||
- The ROM library needs a page aligned RAM section to hold the RW data. This
|
||||
section is defined by the ROMLIB_RW_BASE and ROMLIB_RW_END macros.
|
||||
On Arm platforms a section of 1 page (0x1000) is allocated at the top of SRAM.
|
||||
This will have for effect to shift down all the BL images by 1 page.
|
||||
|
||||
- Depending on the functions moved to the ROM library, the size of the BL images
|
||||
will be reduced.
|
||||
For example: moving MbedTLS function into the ROM library reduces BL1 and
|
||||
BL2, but not BL31.
|
||||
|
||||
- This change in BL images size can be taken into consideration to optimize the
|
||||
memory layout when defining the BLx_BASE macros.
|
||||
|
||||
Build library at ROM
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The environment variable ``CROSS_COMPILE`` must be set appropriately. Refer to
|
||||
:ref:`Performing an Initial Build` for more information about setting this
|
||||
variable.
|
||||
|
||||
In the below example the usage of ROMLIB together with mbed TLS is demonstrated
|
||||
to showcase the benefits of library at ROM - it's not mandatory.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=fvp \
|
||||
MBEDTLS_DIR=</path/to/mbedtls/> \
|
||||
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
|
||||
ARM_ROTPK_LOCATION=devel_rsa \
|
||||
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
|
||||
BL33=</path/to/bl33.bin> \
|
||||
USE_ROMLIB=1 \
|
||||
all fip
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019, Arm Limited. All rights reserved.*
|
||||
369
arm-trusted-firmware/docs/components/sdei.rst
Normal file
369
arm-trusted-firmware/docs/components/sdei.rst
Normal file
@@ -0,0 +1,369 @@
|
||||
SDEI: Software Delegated Exception Interface
|
||||
============================================
|
||||
|
||||
This document provides an overview of the SDEI dispatcher implementation in
|
||||
Trusted Firmware-A (TF-A).
|
||||
|
||||
Introduction
|
||||
------------
|
||||
|
||||
Software Delegated Exception Interface (|SDEI|) is an Arm specification for
|
||||
Non-secure world to register handlers with firmware to receive notifications
|
||||
about system events. Firmware will first receive the system events by way of
|
||||
asynchronous exceptions and, in response, arranges for the registered handler to
|
||||
execute in the Non-secure EL.
|
||||
|
||||
Normal world software that interacts with the SDEI dispatcher (makes SDEI
|
||||
requests and receives notifications) is referred to as the *SDEI Client*. A
|
||||
client receives the event notification at the registered handler even when it
|
||||
was executing with exceptions masked. The list of SDEI events available to the
|
||||
client are specific to the platform [#std-event]_. See also `Determining client
|
||||
EL`_.
|
||||
|
||||
.. _general SDEI dispatch:
|
||||
|
||||
The following figure depicts a general sequence involving SDEI client executing
|
||||
at EL2 and an event dispatch resulting from the triggering of a bound interrupt.
|
||||
A commentary is provided below:
|
||||
|
||||
.. uml:: ../resources/diagrams/plantuml/sdei_general.puml
|
||||
|
||||
As part of initialisation, the SDEI client binds a Non-secure interrupt [1], and
|
||||
the SDEI dispatcher returns a platform dynamic event number [2]. The client then
|
||||
registers a handler for that event [3], enables the event [5], and unmasks all
|
||||
events on the current PE [7]. This sequence is typical of an SDEI client, but it
|
||||
may involve additional SDEI calls.
|
||||
|
||||
At a later point in time, when the bound interrupt triggers [9], it's trapped to
|
||||
EL3. The interrupt is handed over to the SDEI dispatcher, which then arranges to
|
||||
execute the registered handler [10]. The client terminates its execution with
|
||||
``SDEI_EVENT_COMPLETE`` [11], following which the dispatcher resumes the
|
||||
original EL2 execution [13]. Note that the SDEI interrupt remains active until
|
||||
the client handler completes, at which point EL3 does EOI [12].
|
||||
|
||||
Other than events bound to interrupts, as depicted in the sequence above, SDEI
|
||||
events can be explicitly dispatched in response to other exceptions, for
|
||||
example, upon receiving an *SError* or *Synchronous External Abort*. See
|
||||
`Explicit dispatch of events`_.
|
||||
|
||||
The remainder of this document only discusses the design and implementation of
|
||||
SDEI dispatcher in TF-A, and assumes that the reader is familiar with the SDEI
|
||||
specification, the interfaces, and their requirements.
|
||||
|
||||
Defining events
|
||||
---------------
|
||||
|
||||
A platform choosing to include the SDEI dispatcher must also define the events
|
||||
available on the platform, along with their attributes.
|
||||
|
||||
The platform is expected to provide two arrays of event descriptors: one for
|
||||
private events, and another for shared events. The SDEI dispatcher provides
|
||||
``SDEI_PRIVATE_EVENT()`` and ``SDEI_SHARED_EVENT()`` macros to populate the
|
||||
event descriptors. Both macros take 3 arguments:
|
||||
|
||||
- The event number: this must be a positive 32-bit integer.
|
||||
|
||||
- For an event that has a backing interrupt, the interrupt number the event is
|
||||
bound to:
|
||||
|
||||
- If it's not applicable to an event, this shall be left as ``0``.
|
||||
|
||||
- If the event is dynamic, this should be specified as ``SDEI_DYN_IRQ``.
|
||||
|
||||
- A bit map of `Event flags`_.
|
||||
|
||||
To define event 0, the macro ``SDEI_DEFINE_EVENT_0()`` should be used. This
|
||||
macro takes only one parameter: an SGI number to signal other PEs.
|
||||
|
||||
To define an event that's meant to be explicitly dispatched (i.e., not as a
|
||||
result of receiving an SDEI interrupt), the macro ``SDEI_EXPLICIT_EVENT()``
|
||||
should be used. It accepts two parameters:
|
||||
|
||||
- The event number (as above);
|
||||
|
||||
- Event priority: ``SDEI_MAPF_CRITICAL`` or ``SDEI_MAPF_NORMAL``, as described
|
||||
below.
|
||||
|
||||
Once the event descriptor arrays are defined, they should be exported to the
|
||||
SDEI dispatcher using the ``REGISTER_SDEI_MAP()`` macro, passing it the pointers
|
||||
to the private and shared event descriptor arrays, respectively. Note that the
|
||||
``REGISTER_SDEI_MAP()`` macro must be used in the same file where the arrays are
|
||||
defined.
|
||||
|
||||
Regarding event descriptors:
|
||||
|
||||
- For Event 0:
|
||||
|
||||
- There must be exactly one descriptor in the private array, and none in the
|
||||
shared array.
|
||||
|
||||
- The event should be defined using ``SDEI_DEFINE_EVENT_0()``.
|
||||
|
||||
- Must be bound to a Secure SGI on the platform.
|
||||
|
||||
- Explicit events should only be used in the private array.
|
||||
|
||||
- Statically bound shared and private interrupts must be bound to shared and
|
||||
private interrupts on the platform, respectively. See the section on
|
||||
`Configuration within Exception Handling Framework`_.
|
||||
|
||||
- Both arrays should be one-dimensional. The ``REGISTER_SDEI_MAP()`` macro
|
||||
takes care of replicating private events for each PE on the platform.
|
||||
|
||||
- Both arrays must be sorted in the increasing order of event number.
|
||||
|
||||
The SDEI specification doesn't have provisions for discovery of available events
|
||||
on the platform. The list of events made available to the client, along with
|
||||
their semantics, have to be communicated out of band; for example, through
|
||||
Device Trees or firmware configuration tables.
|
||||
|
||||
See also `Event definition example`_.
|
||||
|
||||
Event flags
|
||||
~~~~~~~~~~~
|
||||
|
||||
Event flags describe the properties of the event. They are bit maps that can be
|
||||
``OR``\ ed to form parameters to macros that define events (see
|
||||
`Defining events`_).
|
||||
|
||||
- ``SDEI_MAPF_DYNAMIC``: Marks the event as dynamic. Dynamic events can be
|
||||
bound to (or released from) any Non-secure interrupt at runtime via the
|
||||
``SDEI_INTERRUPT_BIND`` and ``SDEI_INTERRUPT_RELEASE`` calls.
|
||||
|
||||
- ``SDEI_MAPF_BOUND``: Marks the event as statically bound to an interrupt.
|
||||
These events cannot be re-bound at runtime.
|
||||
|
||||
- ``SDEI_MAPF_NORMAL``: Marks the event as having *Normal* priority. This is
|
||||
the default priority.
|
||||
|
||||
- ``SDEI_MAPF_CRITICAL``: Marks the event as having *Critical* priority.
|
||||
|
||||
Event definition example
|
||||
------------------------
|
||||
|
||||
.. code:: c
|
||||
|
||||
static sdei_ev_map_t plat_private_sdei[] = {
|
||||
/* Event 0 definition */
|
||||
SDEI_DEFINE_EVENT_0(8),
|
||||
|
||||
/* PPI */
|
||||
SDEI_PRIVATE_EVENT(8, 23, SDEI_MAPF_BOUND),
|
||||
|
||||
/* Dynamic private events */
|
||||
SDEI_PRIVATE_EVENT(100, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
|
||||
SDEI_PRIVATE_EVENT(101, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
|
||||
|
||||
/* Events for explicit dispatch */
|
||||
SDEI_EXPLICIT_EVENT(2000, SDEI_MAPF_NORMAL);
|
||||
SDEI_EXPLICIT_EVENT(2000, SDEI_MAPF_CRITICAL);
|
||||
};
|
||||
|
||||
/* Shared event mappings */
|
||||
static sdei_ev_map_t plat_shared_sdei[] = {
|
||||
SDEI_SHARED_EVENT(804, 0, SDEI_MAPF_DYNAMIC),
|
||||
|
||||
/* Dynamic shared events */
|
||||
SDEI_SHARED_EVENT(3000, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
|
||||
SDEI_SHARED_EVENT(3001, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
|
||||
};
|
||||
|
||||
/* Export SDEI events */
|
||||
REGISTER_SDEI_MAP(plat_private_sdei, plat_shared_sdei);
|
||||
|
||||
Configuration within Exception Handling Framework
|
||||
-------------------------------------------------
|
||||
|
||||
The SDEI dispatcher functions alongside the Exception Handling Framework. This
|
||||
means that the platform must assign priorities to both Normal and Critical SDEI
|
||||
interrupts for the platform:
|
||||
|
||||
- Install priority descriptors for Normal and Critical SDEI interrupts.
|
||||
|
||||
- For those interrupts that are statically bound (i.e. events defined as having
|
||||
the ``SDEI_MAPF_BOUND`` property), enumerate their properties for the GIC
|
||||
driver to configure interrupts accordingly.
|
||||
|
||||
The interrupts must be configured to target EL3. This means that they should
|
||||
be configured as *Group 0*. Additionally, on GICv2 systems, the build option
|
||||
``GICV2_G0_FOR_EL3`` must be set to ``1``.
|
||||
|
||||
See also :ref:`porting_guide_sdei_requirements`.
|
||||
|
||||
Determining client EL
|
||||
---------------------
|
||||
|
||||
The SDEI specification requires that the *physical* SDEI client executes in the
|
||||
highest Non-secure EL implemented on the system. This means that the dispatcher
|
||||
will only allow SDEI calls to be made from:
|
||||
|
||||
- EL2, if EL2 is implemented. The Hypervisor is expected to implement a
|
||||
*virtual* SDEI dispatcher to support SDEI clients in Guest Operating Systems
|
||||
executing in Non-secure EL1.
|
||||
|
||||
- Non-secure EL1, if EL2 is not implemented or disabled.
|
||||
|
||||
See the function ``sdei_client_el()`` in ``sdei_private.h``.
|
||||
|
||||
.. _explicit-dispatch-of-events:
|
||||
|
||||
Explicit dispatch of events
|
||||
---------------------------
|
||||
|
||||
Typically, an SDEI event dispatch is caused by the PE receiving interrupts that
|
||||
are bound to an SDEI event. However, there are cases where the Secure world
|
||||
requires dispatch of an SDEI event as a direct or indirect result of a past
|
||||
activity, such as receiving a Secure interrupt or an exception.
|
||||
|
||||
The SDEI dispatcher implementation provides ``sdei_dispatch_event()`` API for
|
||||
this purpose. The API has the following signature:
|
||||
|
||||
.. code:: c
|
||||
|
||||
int sdei_dispatch_event(int ev_num);
|
||||
|
||||
The parameter ``ev_num`` is the event number to dispatch. The API returns ``0``
|
||||
on success, or ``-1`` on failure.
|
||||
|
||||
The following figure depicts a scenario involving explicit dispatch of SDEI
|
||||
event. A commentary is provided below:
|
||||
|
||||
.. uml:: ../resources/diagrams/plantuml/sdei_explicit_dispatch.puml
|
||||
|
||||
As part of initialisation, the SDEI client registers a handler for a platform
|
||||
event [1], enables the event [3], and unmasks the current PE [5]. Note that,
|
||||
unlike in `general SDEI dispatch`_, this doesn't involve interrupt binding, as
|
||||
bound or dynamic events can't be explicitly dispatched (see the section below).
|
||||
|
||||
At a later point in time, a critical event [#critical-event]_ is trapped into
|
||||
EL3 [7]. EL3 performs a first-level triage of the event, and a RAS component
|
||||
assumes further handling [8]. The dispatch completes, but intends to involve
|
||||
Non-secure world in further handling, and therefore decides to explicitly
|
||||
dispatch an event [10] (which the client had already registered for [1]). The
|
||||
rest of the sequence is similar to that in the `general SDEI dispatch`_: the
|
||||
requested event is dispatched to the client (assuming all the conditions are
|
||||
met), and when the handler completes, the preempted execution resumes.
|
||||
|
||||
Conditions for event dispatch
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
All of the following requirements must be met for the API to return ``0`` and
|
||||
event to be dispatched:
|
||||
|
||||
- SDEI events must be unmasked on the PE. I.e. the client must have called
|
||||
``PE_UNMASK`` beforehand.
|
||||
|
||||
- Event 0 can't be dispatched.
|
||||
|
||||
- The event must be declared using the ``SDEI_EXPLICIT_EVENT()`` macro
|
||||
described above.
|
||||
|
||||
- The event must be private to the PE.
|
||||
|
||||
- The event must have been registered for and enabled.
|
||||
|
||||
- A dispatch for the same event must not be outstanding. I.e. it hasn't already
|
||||
been dispatched and is yet to be completed.
|
||||
|
||||
- The priority of the event (either Critical or Normal, as configured by the
|
||||
platform at build-time) shouldn't cause priority inversion. This means:
|
||||
|
||||
- If it's of Normal priority, neither Normal nor Critical priority dispatch
|
||||
must be outstanding on the PE.
|
||||
|
||||
- If it's of a Critical priority, no Critical priority dispatch must be
|
||||
outstanding on the PE.
|
||||
|
||||
Further, the caller should be aware of the following assumptions made by the
|
||||
dispatcher:
|
||||
|
||||
- The caller of the API is a component running in EL3; for example, a RAS
|
||||
driver.
|
||||
|
||||
- The requested dispatch will be permitted by the Exception Handling Framework.
|
||||
I.e. the caller must make sure that the requested dispatch has sufficient
|
||||
priority so as not to cause priority level inversion within Exception
|
||||
Handling Framework.
|
||||
|
||||
- The caller must be prepared for the SDEI dispatcher to restore the Non-secure
|
||||
context, and mark that the active context.
|
||||
|
||||
- The call will block until the SDEI client completes the event (i.e. when the
|
||||
client calls either ``SDEI_EVENT_COMPLETE`` or ``SDEI_COMPLETE_AND_RESUME``).
|
||||
|
||||
- The caller must be prepared for this API to return failure and handle
|
||||
accordingly.
|
||||
|
||||
Porting requirements
|
||||
--------------------
|
||||
|
||||
The porting requirements of the SDEI dispatcher are outlined in the
|
||||
:ref:`Porting Guide <porting_guide_sdei_requirements>`.
|
||||
|
||||
Note on writing SDEI event handlers
|
||||
-----------------------------------
|
||||
|
||||
*This section pertains to SDEI event handlers in general, not just when using
|
||||
the TF-A SDEI dispatcher.*
|
||||
|
||||
The SDEI specification requires that event handlers preserve the contents of all
|
||||
registers except ``x0`` to ``x17``. This has significance if event handler is
|
||||
written in C: compilers typically adjust the stack frame at the beginning and
|
||||
end of C functions. For example, AArch64 GCC typically produces the following
|
||||
function prologue and epilogue:
|
||||
|
||||
::
|
||||
|
||||
c_event_handler:
|
||||
stp x29, x30, [sp,#-32]!
|
||||
mov x29, sp
|
||||
|
||||
...
|
||||
|
||||
bl ...
|
||||
|
||||
...
|
||||
|
||||
ldp x29, x30, [sp],#32
|
||||
ret
|
||||
|
||||
The register ``x29`` is used as frame pointer in the prologue. Because neither a
|
||||
valid ``SDEI_EVENT_COMPLETE`` nor ``SDEI_EVENT_COMPLETE_AND_RESUME`` calls
|
||||
return to the handler, the epilogue never gets executed, and registers ``x29``
|
||||
and ``x30`` (in the case above) are inadvertently corrupted. This violates the
|
||||
SDEI specification, and the normal execution thereafter will result in
|
||||
unexpected behaviour.
|
||||
|
||||
To work this around, it's advised that the top-level event handlers are
|
||||
implemented in assembly, following a similar pattern as below:
|
||||
|
||||
::
|
||||
|
||||
asm_event_handler:
|
||||
/* Save link register whilst maintaining stack alignment */
|
||||
stp xzr, x30, [sp, #-16]!
|
||||
bl c_event_handler
|
||||
|
||||
/* Restore link register */
|
||||
ldp xzr, x30, [sp], #16
|
||||
|
||||
/* Complete call */
|
||||
ldr x0, =SDEI_EVENT_COMPLETE
|
||||
smc #0
|
||||
b .
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. rubric:: Footnotes
|
||||
|
||||
.. [#std-event] Except event 0, which is defined by the SDEI specification as a
|
||||
standard event.
|
||||
|
||||
.. [#critical-event] Examples of critical events are *SError*, *Synchronous
|
||||
External Abort*, *Fault Handling interrupt* or *Error
|
||||
Recovery interrupt* from one of RAS nodes in the system.
|
||||
|
||||
.. _SDEI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
|
||||
.. _Software Delegated Exception Interface: `SDEI specification`_
|
||||
@@ -0,0 +1,834 @@
|
||||
Secure Partition Manager (MM)
|
||||
*****************************
|
||||
|
||||
Foreword
|
||||
========
|
||||
|
||||
Two implementations of a Secure Partition Manager co-exist in the TF-A codebase:
|
||||
|
||||
- SPM based on the FF-A specification (:ref:`Secure Partition Manager`).
|
||||
- SPM based on the MM interface.
|
||||
|
||||
Both implementations differ in their architectures and only one can be selected
|
||||
at build time.
|
||||
|
||||
This document describes the latter implementation where the Secure Partition Manager
|
||||
resides at EL3 and management services run from isolated Secure Partitions at S-EL0.
|
||||
The communication protocol is established through the Management Mode (MM) interface.
|
||||
|
||||
Background
|
||||
==========
|
||||
|
||||
In some market segments that primarily deal with client-side devices like mobile
|
||||
phones, tablets, STBs and embedded devices, a Trusted OS instantiates trusted
|
||||
applications to provide security services like DRM, secure payment and
|
||||
authentication. The Global Platform TEE Client API specification defines the API
|
||||
used by Non-secure world applications to access these services. A Trusted OS
|
||||
fulfils the requirements of a security service as described above.
|
||||
|
||||
Management services are typically implemented at the highest level of privilege
|
||||
in the system, i.e. EL3 in Trusted Firmware-A (TF-A). The service requirements are
|
||||
fulfilled by the execution environment provided by TF-A.
|
||||
|
||||
The following diagram illustrates the corresponding software stack:
|
||||
|
||||
|Image 1|
|
||||
|
||||
In other market segments that primarily deal with server-side devices (e.g. data
|
||||
centres and enterprise servers) the secure software stack typically does not
|
||||
include a Global Platform Trusted OS. Security functions are accessed through
|
||||
other interfaces (e.g. ACPI TCG TPM interface, UEFI runtime variable service).
|
||||
|
||||
Placement of management and security functions with diverse requirements in a
|
||||
privileged Exception Level (i.e. EL3 or S-EL1) makes security auditing of
|
||||
firmware more difficult and does not allow isolation of unrelated services from
|
||||
each other either.
|
||||
|
||||
Introduction
|
||||
============
|
||||
|
||||
A **Secure Partition** is a software execution environment instantiated in
|
||||
S-EL0 that can be used to implement simple management and security services.
|
||||
Since S-EL0 is an unprivileged Exception Level, a Secure Partition relies on
|
||||
privileged firmware (i.e. TF-A) to be granted access to system and processor
|
||||
resources. Essentially, it is a software sandbox in the Secure world that runs
|
||||
under the control of privileged software, provides one or more services and
|
||||
accesses the following system resources:
|
||||
|
||||
- Memory and device regions in the system address map.
|
||||
|
||||
- PE system registers.
|
||||
|
||||
- A range of synchronous exceptions (e.g. SMC function identifiers).
|
||||
|
||||
Note that currently TF-A only supports handling one Secure Partition.
|
||||
|
||||
A Secure Partition enables TF-A to implement only the essential secure
|
||||
services in EL3 and instantiate the rest in a partition in S-EL0.
|
||||
Furthermore, multiple Secure Partitions can be used to isolate unrelated
|
||||
services from each other.
|
||||
|
||||
The following diagram illustrates the place of a Secure Partition in a typical
|
||||
Armv8-A software stack. A single or multiple Secure Partitions provide secure
|
||||
services to software components in the Non-secure world and other Secure
|
||||
Partitions.
|
||||
|
||||
|Image 2|
|
||||
|
||||
The TF-A build system is responsible for including the Secure Partition image
|
||||
in the FIP. During boot, BL2 includes support to authenticate and load the
|
||||
Secure Partition image. A BL31 component called **Secure Partition Manager
|
||||
(SPM)** is responsible for managing the partition. This is semantically
|
||||
similar to a hypervisor managing a virtual machine.
|
||||
|
||||
The SPM is responsible for the following actions during boot:
|
||||
|
||||
- Allocate resources requested by the Secure Partition.
|
||||
|
||||
- Perform architectural and system setup required by the Secure Partition to
|
||||
fulfil a service request.
|
||||
|
||||
- Implement a standard interface that is used for initialising a Secure
|
||||
Partition.
|
||||
|
||||
The SPM is responsible for the following actions during runtime:
|
||||
|
||||
- Implement a standard interface that is used by a Secure Partition to fulfil
|
||||
service requests.
|
||||
|
||||
- Implement a standard interface that is used by the Non-secure world for
|
||||
accessing the services exported by a Secure Partition. A service can be
|
||||
invoked through a SMC.
|
||||
|
||||
Alternatively, a partition can be viewed as a thread of execution running under
|
||||
the control of the SPM. Hence common programming concepts described below are
|
||||
applicable to a partition.
|
||||
|
||||
Description
|
||||
===========
|
||||
|
||||
The previous section introduced some general aspects of the software
|
||||
architecture of a Secure Partition. This section describes the specific choices
|
||||
made in the current implementation of this software architecture. Subsequent
|
||||
revisions of the implementation will include a richer set of features that
|
||||
enable a more flexible architecture.
|
||||
|
||||
Building TF-A with Secure Partition support
|
||||
-------------------------------------------
|
||||
|
||||
SPM is supported on the Arm FVP exclusively at the moment. The current
|
||||
implementation supports inclusion of only a single Secure Partition in which a
|
||||
service always runs to completion (e.g. the requested services cannot be
|
||||
preempted to give control back to the Normal world).
|
||||
|
||||
It is not currently possible for BL31 to integrate SPM support and a Secure
|
||||
Payload Dispatcher (SPD) at the same time; they are mutually exclusive. In the
|
||||
SPM bootflow, a Secure Partition image executing at S-EL0 replaces the Secure
|
||||
Payload image executing at S-EL1 (e.g. a Trusted OS). Both are referred to as
|
||||
BL32.
|
||||
|
||||
A working prototype of a SP has been implemented by re-purposing the EDK2 code
|
||||
and tools, leveraging the concept of the *Standalone Management Mode (MM)* in
|
||||
the UEFI specification (see the PI v1.6 Volume 4: Management Mode Core
|
||||
Interface). This will be referred to as the *Standalone MM Secure Partition* in
|
||||
the rest of this document.
|
||||
|
||||
To enable SPM support in TF-A, the source code must be compiled with the build
|
||||
flag ``SPM_MM=1``, along with ``EL3_EXCEPTION_HANDLING=1`` and ``ENABLE_SVE_FOR_NS=0``.
|
||||
On Arm platforms the build option ``ARM_BL31_IN_DRAM`` must be set to 1. Also, the
|
||||
location of the binary that contains the BL32 image
|
||||
(``BL32=path/to/image.bin``) must be specified.
|
||||
|
||||
First, build the Standalone MM Secure Partition. To build it, refer to the
|
||||
`instructions in the EDK2 repository`_.
|
||||
|
||||
Then build TF-A with SPM support and include the Standalone MM Secure Partition
|
||||
image in the FIP:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
BL32=path/to/standalone/mm/sp BL33=path/to/bl33.bin \
|
||||
make PLAT=fvp SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 ARM_BL31_IN_DRAM=1 all fip
|
||||
|
||||
Describing Secure Partition resources
|
||||
-------------------------------------
|
||||
|
||||
TF-A exports a porting interface that enables a platform to specify the system
|
||||
resources required by the Secure Partition. Some instructions are given below.
|
||||
However, this interface is under development and it may change as new features
|
||||
are implemented.
|
||||
|
||||
- A Secure Partition is considered a BL32 image, so the same defines that apply
|
||||
to BL32 images apply to a Secure Partition: ``BL32_BASE`` and ``BL32_LIMIT``.
|
||||
|
||||
- The following defines are needed to allocate space for the translation tables
|
||||
used by the Secure Partition: ``PLAT_SP_IMAGE_MMAP_REGIONS`` and
|
||||
``PLAT_SP_IMAGE_MAX_XLAT_TABLES``.
|
||||
|
||||
- The functions ``plat_get_secure_partition_mmap()`` and
|
||||
``plat_get_secure_partition_boot_info()`` have to be implemented. The file
|
||||
``plat/arm/board/fvp/fvp_common.c`` can be used as an example. It uses the
|
||||
defines in ``include/plat/arm/common/arm_spm_def.h``.
|
||||
|
||||
- ``plat_get_secure_partition_mmap()`` returns an array of mmap regions that
|
||||
describe the memory regions that the SPM needs to allocate for a Secure
|
||||
Partition.
|
||||
|
||||
- ``plat_get_secure_partition_boot_info()`` returns a
|
||||
``spm_mm_boot_info_t`` struct that is populated by the platform
|
||||
with information about the memory map of the Secure Partition.
|
||||
|
||||
For an example of all the changes in context, you may refer to commit
|
||||
``e29efeb1b4``, in which the port for FVP was introduced.
|
||||
|
||||
Accessing Secure Partition services
|
||||
-----------------------------------
|
||||
|
||||
The `SMC Calling Convention`_ (*Arm DEN 0028B*) describes SMCs as a conduit for
|
||||
accessing services implemented in the Secure world. The ``MM_COMMUNICATE``
|
||||
interface defined in the `Management Mode Interface Specification`_ (*Arm DEN
|
||||
0060A*) is used to invoke a Secure Partition service as a Fast Call.
|
||||
|
||||
The mechanism used to identify a service within the partition depends on the
|
||||
service implementation. It is assumed that the caller of the service will be
|
||||
able to discover this mechanism through standard platform discovery mechanisms
|
||||
like ACPI and Device Trees. For example, *Volume 4: Platform Initialisation
|
||||
Specification v1.6. Management Mode Core Interface* specifies that a GUID is
|
||||
used to identify a management mode service. A client populates the GUID in the
|
||||
``EFI_MM_COMMUNICATE_HEADER``. The header is populated in the communication
|
||||
buffer shared with the Secure Partition.
|
||||
|
||||
A Fast Call appears to be atomic from the perspective of the caller and returns
|
||||
when the requested operation has completed. A service invoked through the
|
||||
``MM_COMMUNICATE`` SMC will run to completion in the partition on a given CPU.
|
||||
The SPM is responsible for guaranteeing this behaviour. This means that there
|
||||
can only be a single outstanding Fast Call in a partition on a given CPU.
|
||||
|
||||
Exchanging data with the Secure Partition
|
||||
-----------------------------------------
|
||||
|
||||
The exchange of data between the Non-secure world and the partition takes place
|
||||
through a shared memory region. The location of data in the shared memory area
|
||||
is passed as a parameter to the ``MM_COMMUNICATE`` SMC. The shared memory area
|
||||
is statically allocated by the SPM and is expected to be either implicitly known
|
||||
to the Non-secure world or discovered through a platform discovery mechanism
|
||||
e.g. ACPI table or device tree. It is possible for the Non-secure world to
|
||||
exchange data with a partition only if it has been populated in this shared
|
||||
memory area. The shared memory area is implemented as per the guidelines
|
||||
specified in Section 3.2.3 of the `Management Mode Interface Specification`_
|
||||
(*Arm DEN 0060A*).
|
||||
|
||||
The format of data structures used to encapsulate data in the shared memory is
|
||||
agreed between the Non-secure world and the Secure Partition. For example, in
|
||||
the `Management Mode Interface specification`_ (*Arm DEN 0060A*), Section 4
|
||||
describes that the communication buffer shared between the Non-secure world and
|
||||
the Management Mode (MM) in the Secure world must be of the type
|
||||
``EFI_MM_COMMUNICATE_HEADER``. This data structure is defined in *Volume 4:
|
||||
Platform Initialisation Specification v1.6. Management Mode Core Interface*.
|
||||
Any caller of a MM service will have to use the ``EFI_MM_COMMUNICATE_HEADER``
|
||||
data structure.
|
||||
|
||||
Runtime model of the Secure Partition
|
||||
=====================================
|
||||
|
||||
This section describes how the Secure Partition interfaces with the SPM.
|
||||
|
||||
Interface with SPM
|
||||
------------------
|
||||
|
||||
In order to instantiate one or more secure services in the Secure Partition in
|
||||
S-EL0, the SPM should define the following types of interfaces:
|
||||
|
||||
- Interfaces that enable access to privileged operations from S-EL0. These
|
||||
operations typically require access to system resources that are either shared
|
||||
amongst multiple software components in the Secure world or cannot be directly
|
||||
accessed from an unprivileged Exception Level.
|
||||
|
||||
- Interfaces that establish the control path between the SPM and the Secure
|
||||
Partition.
|
||||
|
||||
This section describes the APIs currently exported by the SPM that enable a
|
||||
Secure Partition to initialise itself and export its services in S-EL0. These
|
||||
interfaces are not accessible from the Non-secure world.
|
||||
|
||||
Conduit
|
||||
^^^^^^^
|
||||
|
||||
The `SMC Calling Convention`_ (*Arm DEN 0028B*) specification describes the SMC
|
||||
and HVC conduits for accessing firmware services and their availability
|
||||
depending on the implemented Exception levels. In S-EL0, the Supervisor Call
|
||||
exception (SVC) is the only architectural mechanism available for unprivileged
|
||||
software to make a request for an operation implemented in privileged software.
|
||||
Hence, the SVC conduit must be used by the Secure Partition to access interfaces
|
||||
implemented by the SPM.
|
||||
|
||||
A SVC causes an exception to be taken to S-EL1. TF-A assumes ownership of S-EL1
|
||||
and installs a simple exception vector table in S-EL1 that relays a SVC request
|
||||
from a Secure Partition as a SMC request to the SPM in EL3. Upon servicing the
|
||||
SMC request, Trusted Firmware-A returns control directly to S-EL0 through an
|
||||
ERET instruction.
|
||||
|
||||
Calling conventions
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The `SMC Calling Convention`_ (*Arm DEN 0028B*) specification describes the
|
||||
32-bit and 64-bit calling conventions for the SMC and HVC conduits. The SVC
|
||||
conduit introduces the concept of SVC32 and SVC64 calling conventions. The SVC32
|
||||
and SVC64 calling conventions are equivalent to the 32-bit (SMC32) and the
|
||||
64-bit (SMC64) calling conventions respectively.
|
||||
|
||||
Communication initiated by SPM
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
A service request is initiated from the SPM through an exception return
|
||||
instruction (ERET) to S-EL0. Later, the Secure Partition issues an SVC
|
||||
instruction to signal completion of the request. Some example use cases are
|
||||
given below:
|
||||
|
||||
- A request to initialise the Secure Partition during system boot.
|
||||
|
||||
- A request to handle a runtime service request.
|
||||
|
||||
Communication initiated by Secure Partition
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
A request is initiated from the Secure Partition by executing a SVC instruction.
|
||||
An ERET instruction is used by TF-A to return to S-EL0 with the result of the
|
||||
request.
|
||||
|
||||
For instance, a request to perform privileged operations on behalf of a
|
||||
partition (e.g. management of memory attributes in the translation tables for
|
||||
the Secure EL1&0 translation regime).
|
||||
|
||||
Interfaces
|
||||
^^^^^^^^^^
|
||||
|
||||
The current implementation reserves function IDs for Fast Calls in the Standard
|
||||
Secure Service calls range (see `SMC Calling Convention`_ (*Arm DEN 0028B*)
|
||||
specification) for each API exported by the SPM. This section defines the
|
||||
function prototypes for each function ID. The function IDs specify whether one
|
||||
or both of the SVC32 and SVC64 calling conventions can be used to invoke the
|
||||
corresponding interface.
|
||||
|
||||
Secure Partition Event Management
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The Secure Partition provides an Event Management interface that is used by the
|
||||
SPM to delegate service requests to the Secure Partition. The interface also
|
||||
allows the Secure Partition to:
|
||||
|
||||
- Register with the SPM a service that it provides.
|
||||
- Indicate completion of a service request delegated by the SPM
|
||||
|
||||
Miscellaneous interfaces
|
||||
------------------------
|
||||
|
||||
``SPM_MM_VERSION_AARCH32``
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- Description
|
||||
|
||||
Returns the version of the interface exported by SPM.
|
||||
|
||||
- Parameters
|
||||
|
||||
- **uint32** - Function ID
|
||||
|
||||
- SVC32 Version: **0x84000060**
|
||||
|
||||
- Return parameters
|
||||
|
||||
- **int32** - Status
|
||||
|
||||
On success, the format of the value is as follows:
|
||||
|
||||
- Bit [31]: Must be 0
|
||||
- Bits [30:16]: Major Version. Must be 0 for this revision of the SPM
|
||||
interface.
|
||||
- Bits [15:0]: Minor Version. Must be 1 for this revision of the SPM
|
||||
interface.
|
||||
|
||||
On error, the format of the value is as follows:
|
||||
|
||||
- ``NOT_SUPPORTED``: SPM interface is not supported or not available for the
|
||||
client.
|
||||
|
||||
- Usage
|
||||
|
||||
This function returns the version of the Secure Partition Manager
|
||||
implementation. The major version is 0 and the minor version is 1. The version
|
||||
number is a 31-bit unsigned integer, with the upper 15 bits denoting the major
|
||||
revision, and the lower 16 bits denoting the minor revision. The following
|
||||
rules apply to the version numbering:
|
||||
|
||||
- Different major revision values indicate possibly incompatible functions.
|
||||
|
||||
- For two revisions, A and B, for which the major revision values are
|
||||
identical, if the minor revision value of revision B is greater than the
|
||||
minor revision value of revision A, then every function in revision A must
|
||||
work in a compatible way with revision B. However, it is possible for
|
||||
revision B to have a higher function count than revision A.
|
||||
|
||||
- Implementation responsibilities
|
||||
|
||||
If this function returns a valid version number, all the functions that are
|
||||
described subsequently must be implemented, unless it is explicitly stated
|
||||
that a function is optional.
|
||||
|
||||
See `Error Codes`_ for integer values that are associated with each return
|
||||
code.
|
||||
|
||||
Secure Partition Initialisation
|
||||
-------------------------------
|
||||
|
||||
The SPM is responsible for initialising the architectural execution context to
|
||||
enable initialisation of a service in S-EL0. The responsibilities of the SPM are
|
||||
listed below. At the end of initialisation, the partition issues a
|
||||
``MM_SP_EVENT_COMPLETE_AARCH64`` call (described later) to signal readiness for
|
||||
handling requests for services implemented by the Secure Partition. The
|
||||
initialisation event is executed as a Fast Call.
|
||||
|
||||
Entry point invocation
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The entry point for service requests that should be handled as Fast Calls is
|
||||
used as the target of the ERET instruction to start initialisation of the Secure
|
||||
Partition.
|
||||
|
||||
Architectural Setup
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
At cold boot, system registers accessible from S-EL0 will be in their reset
|
||||
state unless otherwise specified. The SPM will perform the following
|
||||
architectural setup to enable execution in S-EL0
|
||||
|
||||
MMU setup
|
||||
^^^^^^^^^
|
||||
|
||||
The platform port of a Secure Partition specifies to the SPM a list of regions
|
||||
that it needs access to and their attributes. The SPM validates this resource
|
||||
description and initialises the Secure EL1&0 translation regime as follows.
|
||||
|
||||
1. Device regions are mapped with nGnRE attributes and Execute Never
|
||||
instruction access permissions.
|
||||
|
||||
2. Code memory regions are mapped with RO data and Executable instruction access
|
||||
permissions.
|
||||
|
||||
3. Read Only data memory regions are mapped with RO data and Execute Never
|
||||
instruction access permissions.
|
||||
|
||||
4. Read Write data memory regions are mapped with RW data and Execute Never
|
||||
instruction access permissions.
|
||||
|
||||
5. If the resource description does not explicitly describe the type of memory
|
||||
regions then all memory regions will be marked with Code memory region
|
||||
attributes.
|
||||
|
||||
6. The ``UXN`` and ``PXN`` bits are set for regions that are not executable by
|
||||
S-EL0 or S-EL1.
|
||||
|
||||
System Register Setup
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
System registers that influence software execution in S-EL0 are setup by the SPM
|
||||
as follows:
|
||||
|
||||
1. ``SCTLR_EL1``
|
||||
|
||||
- ``UCI=1``
|
||||
- ``EOE=0``
|
||||
- ``WXN=1``
|
||||
- ``nTWE=1``
|
||||
- ``nTWI=1``
|
||||
- ``UCT=1``
|
||||
- ``DZE=1``
|
||||
- ``I=1``
|
||||
- ``UMA=0``
|
||||
- ``SA0=1``
|
||||
- ``C=1``
|
||||
- ``A=1``
|
||||
- ``M=1``
|
||||
|
||||
2. ``CPACR_EL1``
|
||||
|
||||
- ``FPEN=b'11``
|
||||
|
||||
3. ``PSTATE``
|
||||
|
||||
- ``D,A,I,F=1``
|
||||
- ``CurrentEL=0`` (EL0)
|
||||
- ``SpSel=0`` (Thread mode)
|
||||
- ``NRW=0`` (AArch64)
|
||||
|
||||
General Purpose Register Setup
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
SPM will invoke the entry point of a service by executing an ERET instruction.
|
||||
This transition into S-EL0 is special since it is not in response to a previous
|
||||
request through a SVC instruction. This is the first entry into S-EL0. The
|
||||
general purpose register usage at the time of entry will be as specified in the
|
||||
"Return State" column of Table 3-1 in Section 3.1 "Register use in AArch64 SMC
|
||||
calls" of the `SMC Calling Convention`_ (*Arm DEN 0028B*) specification. In
|
||||
addition, certain other restrictions will be applied as described below.
|
||||
|
||||
1. ``SP_EL0``
|
||||
|
||||
A non-zero value will indicate that the SPM has initialised the stack pointer
|
||||
for the current CPU.
|
||||
|
||||
The value will be 0 otherwise.
|
||||
|
||||
2. ``X4-X30``
|
||||
|
||||
The values of these registers will be 0.
|
||||
|
||||
3. ``X0-X3``
|
||||
|
||||
Parameters passed by the SPM.
|
||||
|
||||
- ``X0``: Virtual address of a buffer shared between EL3 and S-EL0. The
|
||||
buffer will be mapped in the Secure EL1&0 translation regime with read-only
|
||||
memory attributes described earlier.
|
||||
|
||||
- ``X1``: Size of the buffer in bytes.
|
||||
|
||||
- ``X2``: Cookie value (*IMPLEMENTATION DEFINED*).
|
||||
|
||||
- ``X3``: Cookie value (*IMPLEMENTATION DEFINED*).
|
||||
|
||||
Runtime Event Delegation
|
||||
------------------------
|
||||
|
||||
The SPM receives requests for Secure Partition services through a synchronous
|
||||
invocation (i.e. a SMC from the Non-secure world). These requests are delegated
|
||||
to the partition by programming a return from the last
|
||||
``MM_SP_EVENT_COMPLETE_AARCH64`` call received from the partition. The last call
|
||||
was made to signal either completion of Secure Partition initialisation or
|
||||
completion of a partition service request.
|
||||
|
||||
``MM_SP_EVENT_COMPLETE_AARCH64``
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- Description
|
||||
|
||||
Signal completion of the last SP service request.
|
||||
|
||||
- Parameters
|
||||
|
||||
- **uint32** - Function ID
|
||||
|
||||
- SVC64 Version: **0xC4000061**
|
||||
|
||||
- **int32** - Event Status Code
|
||||
|
||||
Zero or a positive value indicates that the event was handled successfully.
|
||||
The values depend upon the original event that was delegated to the Secure
|
||||
partition. They are described as follows.
|
||||
|
||||
- ``SUCCESS`` : Used to indicate that the Secure Partition was initialised
|
||||
or a runtime request was handled successfully.
|
||||
|
||||
- Any other value greater than 0 is used to pass a specific Event Status
|
||||
code in response to a runtime event.
|
||||
|
||||
A negative value indicates an error. The values of Event Status code depend
|
||||
on the original event.
|
||||
|
||||
- Return parameters
|
||||
|
||||
- **int32** - Event ID/Return Code
|
||||
|
||||
Zero or a positive value specifies the unique ID of the event being
|
||||
delegated to the partition by the SPM.
|
||||
|
||||
In the current implementation, this parameter contains the function ID of
|
||||
the ``MM_COMMUNICATE`` SMC. This value indicates to the partition that an
|
||||
event has been delegated to it in response to an ``MM_COMMUNICATE`` request
|
||||
from the Non-secure world.
|
||||
|
||||
A negative value indicates an error. The format of the value is as follows:
|
||||
|
||||
- ``NOT_SUPPORTED``: Function was called from the Non-secure world.
|
||||
|
||||
See `Error Codes`_ for integer values that are associated with each return
|
||||
code.
|
||||
|
||||
- **uint32** - Event Context Address
|
||||
|
||||
Address of a buffer shared between the SPM and Secure Partition to pass
|
||||
event specific information. The format of the data populated in the buffer
|
||||
is implementation defined.
|
||||
|
||||
The buffer is mapped in the Secure EL1&0 translation regime with read-only
|
||||
memory attributes described earlier.
|
||||
|
||||
For the SVC64 version, this parameter is a 64-bit Virtual Address (VA).
|
||||
|
||||
For the SVC32 version, this parameter is a 32-bit Virtual Address (VA).
|
||||
|
||||
- **uint32** - Event context size
|
||||
|
||||
Size of the memory starting at Event Address.
|
||||
|
||||
- **uint32/uint64** - Event Cookie
|
||||
|
||||
This is an optional parameter. If unused its value is SBZ.
|
||||
|
||||
- Usage
|
||||
|
||||
This function signals to the SPM that the handling of the last event delegated
|
||||
to a partition has completed. The partition is ready to handle its next event.
|
||||
A return from this function is in response to the next event that will be
|
||||
delegated to the partition. The return parameters describe the next event.
|
||||
|
||||
- Caller responsibilities
|
||||
|
||||
A Secure Partition must only call ``MM_SP_EVENT_COMPLETE_AARCH64`` to signal
|
||||
completion of a request that was delegated to it by the SPM.
|
||||
|
||||
- Callee responsibilities
|
||||
|
||||
When the SPM receives this call from a Secure Partition, the corresponding
|
||||
syndrome information can be used to return control through an ERET
|
||||
instruction, to the instruction immediately after the call in the Secure
|
||||
Partition context. This syndrome information comprises of general purpose and
|
||||
system register values when the call was made.
|
||||
|
||||
The SPM must save this syndrome information and use it to delegate the next
|
||||
event to the Secure Partition. The return parameters of this interface must
|
||||
specify the properties of the event and be populated in ``X0-X3/W0-W3``
|
||||
registers.
|
||||
|
||||
Secure Partition Memory Management
|
||||
----------------------------------
|
||||
|
||||
A Secure Partition executes at S-EL0, which is an unprivileged Exception Level.
|
||||
The SPM is responsible for enabling access to regions of memory in the system
|
||||
address map from a Secure Partition. This is done by mapping these regions in
|
||||
the Secure EL1&0 Translation regime with appropriate memory attributes.
|
||||
Attributes refer to memory type, permission, cacheability and shareability
|
||||
attributes used in the Translation tables. The definitions of these attributes
|
||||
and their usage can be found in the `Armv8-A ARM`_ (*Arm DDI 0487*).
|
||||
|
||||
All memory required by the Secure Partition is allocated upfront in the SPM,
|
||||
even before handing over to the Secure Partition for the first time. The initial
|
||||
access permissions of the memory regions are statically provided by the platform
|
||||
port and should allow the Secure Partition to run its initialisation code.
|
||||
|
||||
However, they might not suit the final needs of the Secure Partition because its
|
||||
final memory layout might not be known until the Secure Partition initialises
|
||||
itself. As the Secure Partition initialises its runtime environment it might,
|
||||
for example, load dynamically some modules. For instance, a Secure Partition
|
||||
could implement a loader for a standard executable file format (e.g. an PE-COFF
|
||||
loader for loading executable files at runtime). These executable files will be
|
||||
a part of the Secure Partition image. The location of various sections in an
|
||||
executable file and their permission attributes (e.g. read-write data, read-only
|
||||
data and code) will be known only when the file is loaded into memory.
|
||||
|
||||
In this case, the Secure Partition needs a way to change the access permissions
|
||||
of its memory regions. The SPM provides this feature through the
|
||||
``MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64`` SVC interface. This interface is
|
||||
available to the Secure Partition during a specific time window: from the first
|
||||
entry into the Secure Partition up to the first ``SP_EVENT_COMPLETE`` call that
|
||||
signals the Secure Partition has finished its initialisation. Once the
|
||||
initialisation is complete, the SPM does not allow changes to the memory
|
||||
attributes.
|
||||
|
||||
This section describes the standard SVC interface that is implemented by the SPM
|
||||
to determine and change permission attributes of memory regions that belong to a
|
||||
Secure Partition.
|
||||
|
||||
``MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64``
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- Description
|
||||
|
||||
Request the permission attributes of a memory region from S-EL0.
|
||||
|
||||
- Parameters
|
||||
|
||||
- **uint32** Function ID
|
||||
|
||||
- SVC64 Version: **0xC4000064**
|
||||
|
||||
- **uint64** Base Address
|
||||
|
||||
This parameter is a 64-bit Virtual Address (VA).
|
||||
|
||||
There are no alignment restrictions on the Base Address. The permission
|
||||
attributes of the translation granule it lies in are returned.
|
||||
|
||||
- Return parameters
|
||||
|
||||
- **int32** - Memory Attributes/Return Code
|
||||
|
||||
On success the format of the Return Code is as follows:
|
||||
|
||||
- Bits[1:0] : Data access permission
|
||||
|
||||
- b'00 : No access
|
||||
- b'01 : Read-Write access
|
||||
- b'10 : Reserved
|
||||
- b'11 : Read-only access
|
||||
|
||||
- Bit[2]: Instruction access permission
|
||||
|
||||
- b'0 : Executable
|
||||
- b'1 : Non-executable
|
||||
|
||||
- Bit[30:3] : Reserved. SBZ.
|
||||
|
||||
- Bit[31] : Must be 0
|
||||
|
||||
On failure the following error codes are returned:
|
||||
|
||||
- ``INVALID_PARAMETERS``: The Secure Partition is not allowed to access the
|
||||
memory region the Base Address lies in.
|
||||
|
||||
- ``NOT_SUPPORTED`` : The SPM does not support retrieval of attributes of
|
||||
any memory page that is accessible by the Secure Partition, or the
|
||||
function was called from the Non-secure world. Also returned if it is
|
||||
used after ``MM_SP_EVENT_COMPLETE_AARCH64``.
|
||||
|
||||
See `Error Codes`_ for integer values that are associated with each return
|
||||
code.
|
||||
|
||||
- Usage
|
||||
|
||||
This function is used to request the permission attributes for S-EL0 on a
|
||||
memory region accessible from a Secure Partition. The size of the memory
|
||||
region is equal to the Translation Granule size used in the Secure EL1&0
|
||||
translation regime. Requests to retrieve other memory region attributes are
|
||||
not currently supported.
|
||||
|
||||
- Caller responsibilities
|
||||
|
||||
The caller must obtain the Translation Granule Size of the Secure EL1&0
|
||||
translation regime from the SPM through an implementation defined method.
|
||||
|
||||
- Callee responsibilities
|
||||
|
||||
The SPM must not return the memory access controls for a page of memory that
|
||||
is not accessible from a Secure Partition.
|
||||
|
||||
``MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64``
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- Description
|
||||
|
||||
Set the permission attributes of a memory region from S-EL0.
|
||||
|
||||
- Parameters
|
||||
|
||||
- **uint32** - Function ID
|
||||
|
||||
- SVC64 Version: **0xC4000065**
|
||||
|
||||
- **uint64** - Base Address
|
||||
|
||||
This parameter is a 64-bit Virtual Address (VA).
|
||||
|
||||
The alignment of the Base Address must be greater than or equal to the size
|
||||
of the Translation Granule Size used in the Secure EL1&0 translation
|
||||
regime.
|
||||
|
||||
- **uint32** - Page count
|
||||
|
||||
Number of pages starting from the Base Address whose memory attributes
|
||||
should be changed. The page size is equal to the Translation Granule Size.
|
||||
|
||||
- **uint32** - Memory Access Controls
|
||||
|
||||
- Bits[1:0] : Data access permission
|
||||
|
||||
- b'00 : No access
|
||||
- b'01 : Read-Write access
|
||||
- b'10 : Reserved
|
||||
- b'11 : Read-only access
|
||||
|
||||
- Bit[2] : Instruction access permission
|
||||
|
||||
- b'0 : Executable
|
||||
- b'1 : Non-executable
|
||||
|
||||
- Bits[31:3] : Reserved. SBZ.
|
||||
|
||||
A combination of attributes that mark the region with RW and Executable
|
||||
permissions is prohibited. A request to mark a device memory region with
|
||||
Executable permissions is prohibited.
|
||||
|
||||
- Return parameters
|
||||
|
||||
- **int32** - Return Code
|
||||
|
||||
- ``SUCCESS``: The Memory Access Controls were changed successfully.
|
||||
|
||||
- ``DENIED``: The SPM is servicing a request to change the attributes of a
|
||||
memory region that overlaps with the region specified in this request.
|
||||
|
||||
- ``INVALID_PARAMETER``: An invalid combination of Memory Access Controls
|
||||
has been specified. The Base Address is not correctly aligned. The Secure
|
||||
Partition is not allowed to access part or all of the memory region
|
||||
specified in the call.
|
||||
|
||||
- ``NO_MEMORY``: The SPM does not have memory resources to change the
|
||||
attributes of the memory region in the translation tables.
|
||||
|
||||
- ``NOT_SUPPORTED``: The SPM does not permit change of attributes of any
|
||||
memory region that is accessible by the Secure Partition. Function was
|
||||
called from the Non-secure world. Also returned if it is used after
|
||||
``MM_SP_EVENT_COMPLETE_AARCH64``.
|
||||
|
||||
See `Error Codes`_ for integer values that are associated with each return
|
||||
code.
|
||||
|
||||
- Usage
|
||||
|
||||
This function is used to change the permission attributes for S-EL0 on a
|
||||
memory region accessible from a Secure Partition. The size of the memory
|
||||
region is equal to the Translation Granule size used in the Secure EL1&0
|
||||
translation regime. Requests to change other memory region attributes are not
|
||||
currently supported.
|
||||
|
||||
This function is only available at boot time. This interface is revoked after
|
||||
the Secure Partition sends the first ``MM_SP_EVENT_COMPLETE_AARCH64`` to
|
||||
signal that it is initialised and ready to receive run-time requests.
|
||||
|
||||
- Caller responsibilities
|
||||
|
||||
The caller must obtain the Translation Granule Size of the Secure EL1&0
|
||||
translation regime from the SPM through an implementation defined method.
|
||||
|
||||
- Callee responsibilities
|
||||
|
||||
The SPM must preserve the original memory access controls of the region of
|
||||
memory in case of an unsuccessful call. The SPM must preserve the consistency
|
||||
of the S-EL1 translation regime if this function is called on different PEs
|
||||
concurrently and the memory regions specified overlap.
|
||||
|
||||
Error Codes
|
||||
-----------
|
||||
|
||||
.. csv-table::
|
||||
:header: "Name", "Value"
|
||||
|
||||
``SUCCESS``,0
|
||||
``NOT_SUPPORTED``,-1
|
||||
``INVALID_PARAMETER``,-2
|
||||
``DENIED``,-3
|
||||
``NO_MEMORY``,-5
|
||||
``NOT_PRESENT``,-7
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _Armv8-A ARM: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
|
||||
.. _instructions in the EDK2 repository: https://github.com/tianocore/edk2-staging/blob/AArch64StandaloneMm/HowtoBuild.MD
|
||||
.. _Management Mode Interface Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0060a/DEN0060A_ARM_MM_Interface_Specification.pdf
|
||||
.. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
|
||||
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
|
||||
|
||||
.. |Image 1| image:: ../resources/diagrams/secure_sw_stack_tos.png
|
||||
.. |Image 2| image:: ../resources/diagrams/secure_sw_stack_sp.png
|
||||
1565
arm-trusted-firmware/docs/components/secure-partition-manager.rst
Normal file
1565
arm-trusted-firmware/docs/components/secure-partition-manager.rst
Normal file
File diff suppressed because it is too large
Load Diff
11
arm-trusted-firmware/docs/components/spd/index.rst
Normal file
11
arm-trusted-firmware/docs/components/spd/index.rst
Normal file
@@ -0,0 +1,11 @@
|
||||
Secure Payload Dispatcher (SPD)
|
||||
===============================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Contents
|
||||
|
||||
optee-dispatcher
|
||||
tlk-dispatcher
|
||||
trusty-dispatcher
|
||||
pnc-dispatcher
|
||||
@@ -0,0 +1,14 @@
|
||||
OP-TEE Dispatcher
|
||||
=================
|
||||
|
||||
`OP-TEE OS`_ is a Trusted OS running as Secure EL1.
|
||||
|
||||
To build and execute OP-TEE follow the instructions at
|
||||
`OP-TEE build.git`_
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _OP-TEE OS: https://github.com/OP-TEE/build
|
||||
.. _OP-TEE build.git: https://github.com/OP-TEE/build
|
||||
10
arm-trusted-firmware/docs/components/spd/pnc-dispatcher.rst
Normal file
10
arm-trusted-firmware/docs/components/spd/pnc-dispatcher.rst
Normal file
@@ -0,0 +1,10 @@
|
||||
ProvenCore Dispatcher
|
||||
=====================
|
||||
|
||||
ProvenCore dispatcher (PnC-D) adds support for ProvenRun's ProvenCore micro-kernel
|
||||
to work with Trusted Firmware-A (TF-A).
|
||||
|
||||
ProvenCore is a secure OS developed by ProvenRun S.A.S. using deductive formal methods.
|
||||
|
||||
Once a BL32 is ready, PnC-D can be included in the image by adding "SPD=pncd"
|
||||
to the build command.
|
||||
76
arm-trusted-firmware/docs/components/spd/tlk-dispatcher.rst
Normal file
76
arm-trusted-firmware/docs/components/spd/tlk-dispatcher.rst
Normal file
@@ -0,0 +1,76 @@
|
||||
Trusted Little Kernel (TLK) Dispatcher
|
||||
======================================
|
||||
|
||||
TLK dispatcher (TLK-D) adds support for NVIDIA's Trusted Little Kernel (TLK)
|
||||
to work with Trusted Firmware-A (TF-A). TLK-D can be compiled by including it
|
||||
in the platform's makefile. TLK is primarily meant to work with Tegra SoCs,
|
||||
so while TF-A only supports TLK on Tegra, the dispatcher code can only be
|
||||
compiled for other platforms.
|
||||
|
||||
In order to compile TLK-D, we need a BL32 image to be present. Since, TLKD
|
||||
just needs to compile, any BL32 image would do. To use TLK as the BL32, please
|
||||
refer to the "Build TLK" section.
|
||||
|
||||
Once a BL32 is ready, TLKD can be included in the image by adding "SPD=tlkd"
|
||||
to the build command.
|
||||
|
||||
Trusted Little Kernel (TLK)
|
||||
---------------------------
|
||||
|
||||
TLK is a Trusted OS running as Secure EL1. It is a Free Open Source Software
|
||||
(FOSS) release of the NVIDIA® Trusted Little Kernel (TLK) technology, which
|
||||
extends technology made available with the development of the Little Kernel (LK).
|
||||
You can download the LK modular embedded preemptive kernel for use on Arm,
|
||||
x86, and AVR32 systems from https://github.com/travisg/lk
|
||||
|
||||
NVIDIA implemented its Trusted Little Kernel (TLK) technology, designed as a
|
||||
free and open-source trusted execution environment (OTE).
|
||||
|
||||
TLK features include:
|
||||
|
||||
• Small, pre-emptive kernel
|
||||
• Supports multi-threading, IPCs, and thread scheduling
|
||||
• Added TrustZone features
|
||||
• Added Secure Storage
|
||||
• Under MIT/FreeBSD license
|
||||
|
||||
NVIDIA extensions to Little Kernel (LK) include:
|
||||
|
||||
• User mode
|
||||
• Address-space separation for TAs
|
||||
• TLK Client Application (CA) library
|
||||
• TLK TA library
|
||||
• Crypto library (encrypt/decrypt, key handling) via OpenSSL
|
||||
• Linux kernel driver
|
||||
• Cortex A9/A15 support
|
||||
• Power Management
|
||||
• TrustZone memory carve-out (reconfigurable)
|
||||
• Page table management
|
||||
• Debugging support over UART (USB planned)
|
||||
|
||||
TLK is hosted by NVIDIA on http://nv-tegra.nvidia.com under the
|
||||
3rdparty/ote\_partner/tlk.git repository. Detailed information about
|
||||
TLK and OTE can be found in the Tegra\_BSP\_for\_Android\_TLK\_FOSS\_Reference.pdf
|
||||
manual located under the "documentation" directory\_.
|
||||
|
||||
Build TLK
|
||||
---------
|
||||
|
||||
To build and execute TLK, follow the instructions from "Building a TLK Device"
|
||||
section from Tegra\_BSP\_for\_Android\_TLK\_FOSS\_Reference.pdf manual.
|
||||
|
||||
Input parameters to TLK
|
||||
-----------------------
|
||||
|
||||
TLK expects the TZDRAM size and a structure containing the boot arguments. BL2
|
||||
passes this information to the EL3 software as members of the bl32\_ep\_info
|
||||
struct, where bl32\_ep\_info is part of bl31\_params\_t (passed by BL2 in X0)
|
||||
|
||||
Example
|
||||
~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
bl32_ep_info->args.arg0 = TZDRAM size available for BL32
|
||||
bl32_ep_info->args.arg1 = unused (used only on Armv7-A)
|
||||
bl32_ep_info->args.arg2 = pointer to boot args
|
||||
@@ -0,0 +1,32 @@
|
||||
Trusty Dispatcher
|
||||
=================
|
||||
|
||||
Trusty is a a set of software components, supporting a Trusted Execution
|
||||
Environment (TEE) on mobile devices, published and maintained by Google.
|
||||
|
||||
Detailed information and build instructions can be found on the Android
|
||||
Open Source Project (AOSP) webpage for Trusty hosted at
|
||||
https://source.android.com/security/trusty
|
||||
|
||||
Boot parameters
|
||||
---------------
|
||||
|
||||
Custom boot parameters can be passed to Trusty by providing a platform
|
||||
specific function:
|
||||
|
||||
.. code:: c
|
||||
|
||||
void plat_trusty_set_boot_args(aapcs64_params_t *args)
|
||||
|
||||
If this function is provided ``args->arg0`` must be set to the memory
|
||||
size allocated to trusty. If the platform does not provide this
|
||||
function, but defines ``TSP_SEC_MEM_SIZE``, a default implementation
|
||||
will pass the memory size from ``TSP_SEC_MEM_SIZE``. ``args->arg1``
|
||||
can be set to a platform specific parameter block, and ``args->arg2``
|
||||
should then be set to the size of that block.
|
||||
|
||||
Supported platforms
|
||||
-------------------
|
||||
|
||||
Out of all the platforms supported by Trusted Firmware-A, Trusty is only
|
||||
verified and supported by NVIDIA's Tegra SoCs.
|
||||
@@ -0,0 +1,442 @@
|
||||
Translation (XLAT) Tables Library
|
||||
=================================
|
||||
|
||||
This document describes the design of the translation tables library (version 2)
|
||||
used by Trusted Firmware-A (TF-A). This library provides APIs to create page
|
||||
tables based on a description of the memory layout, as well as setting up system
|
||||
registers related to the Memory Management Unit (MMU) and performing the
|
||||
required Translation Lookaside Buffer (TLB) maintenance operations.
|
||||
|
||||
More specifically, some use cases that this library aims to support are:
|
||||
|
||||
#. Statically allocate translation tables and populate them (at run-time) based
|
||||
upon a description of the memory layout. The memory layout is typically
|
||||
provided by the platform port as a list of memory regions;
|
||||
|
||||
#. Support for generating translation tables pertaining to a different
|
||||
translation regime than the exception level the library code is executing at;
|
||||
|
||||
#. Support for dynamic mapping and unmapping of regions, even while the MMU is
|
||||
on. This can be used to temporarily map some memory regions and unmap them
|
||||
later on when no longer needed;
|
||||
|
||||
#. Support for non-identity virtual to physical mappings to compress the virtual
|
||||
address space;
|
||||
|
||||
#. Support for changing memory attributes of memory regions at run-time.
|
||||
|
||||
|
||||
About version 1, version 2 and MPU libraries
|
||||
--------------------------------------------
|
||||
|
||||
This document focuses on version 2 of the library, whose sources are available
|
||||
in the ``lib/xlat_tables_v2`` directory. Version 1 of the library can still be
|
||||
found in ``lib/xlat_tables`` directory but it is less flexible and doesn't
|
||||
support dynamic mapping. ``lib/xlat_mpu``, which configures Arm's MPU
|
||||
equivalently, is also addressed here. The ``lib/xlat_mpu`` is experimental,
|
||||
meaning that its API may change. It currently strives for consistency and
|
||||
code-reuse with xlat_tables_v2. Future versions may be more MPU-specific (e.g.,
|
||||
removing all mentions of virtual addresses). Although potential bug fixes will
|
||||
be applied to all versions of the xlat_* libs, future feature enhancements will
|
||||
focus on version 2 and might not be back-ported to version 1 and MPU versions.
|
||||
Therefore, it is recommended to use version 2, especially for new platform
|
||||
ports (unless the platform uses an MPU).
|
||||
|
||||
However, please note that version 2 and the MPU version are still in active
|
||||
development and is not considered stable yet. Hence, compatibility breaks might
|
||||
be introduced.
|
||||
|
||||
From this point onwards, this document will implicitly refer to version 2 of the
|
||||
library, unless stated otherwise.
|
||||
|
||||
|
||||
Design concepts and interfaces
|
||||
------------------------------
|
||||
|
||||
This section presents some of the key concepts and data structures used in the
|
||||
translation tables library.
|
||||
|
||||
`mmap` regions
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
An ``mmap_region`` is an abstract, concise way to represent a memory region to
|
||||
map. It is one of the key interfaces to the library. It is identified by:
|
||||
|
||||
- its physical base address;
|
||||
- its virtual base address;
|
||||
- its size;
|
||||
- its attributes;
|
||||
- its mapping granularity (optional).
|
||||
|
||||
See the ``struct mmap_region`` type in ``xlat_tables_v2.h``.
|
||||
|
||||
The user usually provides a list of such mmap regions to map and lets the
|
||||
library transpose that in a set of translation tables. As a result, the library
|
||||
might create new translation tables, update or split existing ones.
|
||||
|
||||
The region attributes specify the type of memory (for example device or cached
|
||||
normal memory) as well as the memory access permissions (read-only or
|
||||
read-write, executable or not, secure or non-secure, and so on). In the case of
|
||||
the EL1&0 translation regime, the attributes also specify whether the region is
|
||||
a User region (EL0) or Privileged region (EL1). See the ``MT_xxx`` definitions
|
||||
in ``xlat_tables_v2.h``. Note that for the EL1&0 translation regime the Execute
|
||||
Never attribute is set simultaneously for both EL1 and EL0.
|
||||
|
||||
The granularity controls the translation table level to go down to when mapping
|
||||
the region. For example, assuming the MMU has been configured to use a 4KB
|
||||
granule size, the library might map a 2MB memory region using either of the two
|
||||
following options:
|
||||
|
||||
- using a single level-2 translation table entry;
|
||||
- using a level-2 intermediate entry to a level-3 translation table (which
|
||||
contains 512 entries, each mapping 4KB).
|
||||
|
||||
The first solution potentially requires less translation tables, hence
|
||||
potentially less memory. However, if part of this 2MB region is later remapped
|
||||
with different memory attributes, the library might need to split the existing
|
||||
page tables to refine the mappings. If a single level-2 entry has been used
|
||||
here, a level-3 table will need to be allocated on the fly and the level-2
|
||||
modified to point to this new level-3 table. This has a performance cost at
|
||||
run-time.
|
||||
|
||||
If the user knows upfront that such a remapping operation is likely to happen
|
||||
then they might enforce a 4KB mapping granularity for this 2MB region from the
|
||||
beginning; remapping some of these 4KB pages on the fly then becomes a
|
||||
lightweight operation.
|
||||
|
||||
The region's granularity is an optional field; if it is not specified the
|
||||
library will choose the mapping granularity for this region as it sees fit (more
|
||||
details can be found in `The memory mapping algorithm`_ section below).
|
||||
|
||||
The MPU library also uses ``struct mmap_region`` to specify translations, but
|
||||
the MPU's translations are limited to specification of valid addresses and
|
||||
access permissions. If the requested virtual and physical addresses mismatch
|
||||
the system will panic. Being register-based for deterministic memory-reference
|
||||
timing, the MPU hardware does not involve memory-resident translation tables.
|
||||
|
||||
Currently, the MPU library is also limited to MPU translation at EL2 with no
|
||||
MMU translation at other ELs. These limitations, however, are expected to be
|
||||
overcome in future library versions.
|
||||
|
||||
Translation Context
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The library can create or modify translation tables pertaining to a different
|
||||
translation regime than the exception level the library code is executing at.
|
||||
For example, the library might be used by EL3 software (for instance BL31) to
|
||||
create translation tables pertaining to the S-EL1&0 translation regime.
|
||||
|
||||
This flexibility comes from the use of *translation contexts*. A *translation
|
||||
context* constitutes the superset of information used by the library to track
|
||||
the status of a set of translation tables for a given translation regime.
|
||||
|
||||
The library internally allocates a default translation context, which pertains
|
||||
to the translation regime of the current exception level. Additional contexts
|
||||
may be explicitly allocated and initialized using the
|
||||
``REGISTER_XLAT_CONTEXT()`` macro. Separate APIs are provided to act either on
|
||||
the default translation context or on an alternative one.
|
||||
|
||||
To register a translation context, the user must provide the library with the
|
||||
following information:
|
||||
|
||||
* A name.
|
||||
|
||||
The resulting translation context variable will be called after this name, to
|
||||
which ``_xlat_ctx`` is appended. For example, if the macro name parameter is
|
||||
``foo``, the context variable name will be ``foo_xlat_ctx``.
|
||||
|
||||
* The maximum number of `mmap` regions to map.
|
||||
|
||||
Should account for both static and dynamic regions, if applicable.
|
||||
|
||||
* The number of sub-translation tables to allocate.
|
||||
|
||||
Number of translation tables to statically allocate for this context,
|
||||
excluding the initial lookup level translation table, which is always
|
||||
allocated. For example, if the initial lookup level is 1, this parameter would
|
||||
specify the number of level-2 and level-3 translation tables to pre-allocate
|
||||
for this context.
|
||||
|
||||
* The size of the virtual address space.
|
||||
|
||||
Size in bytes of the virtual address space to map using this context. This
|
||||
will incidentally determine the number of entries in the initial lookup level
|
||||
translation table : the library will allocate as many entries as is required
|
||||
to map the entire virtual address space.
|
||||
|
||||
* The size of the physical address space.
|
||||
|
||||
Size in bytes of the physical address space to map using this context.
|
||||
|
||||
The default translation context is internally initialized using information
|
||||
coming (for the most part) from platform-specific defines:
|
||||
|
||||
- name: hard-coded to ``tf`` ; hence the name of the default context variable is
|
||||
``tf_xlat_ctx``;
|
||||
- number of `mmap` regions: ``MAX_MMAP_REGIONS``;
|
||||
- number of sub-translation tables: ``MAX_XLAT_TABLES``;
|
||||
- size of the virtual address space: ``PLAT_VIRT_ADDR_SPACE_SIZE``;
|
||||
- size of the physical address space: ``PLAT_PHY_ADDR_SPACE_SIZE``.
|
||||
|
||||
Please refer to the :ref:`Porting Guide` for more details about these macros.
|
||||
|
||||
|
||||
Static and dynamic memory regions
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The library optionally supports dynamic memory mapping. This feature may be
|
||||
enabled using the ``PLAT_XLAT_TABLES_DYNAMIC`` platform build flag.
|
||||
|
||||
When dynamic memory mapping is enabled, the library categorises mmap regions as
|
||||
*static* or *dynamic*.
|
||||
|
||||
- *Static regions* are fixed for the lifetime of the system. They can only be
|
||||
added early on, before the translation tables are created and populated. They
|
||||
cannot be removed afterwards.
|
||||
|
||||
- *Dynamic regions* can be added or removed any time.
|
||||
|
||||
When the dynamic memory mapping feature is disabled, only static regions exist.
|
||||
|
||||
The dynamic memory mapping feature may be used to map and unmap transient memory
|
||||
areas. This is useful when the user needs to access some memory for a fixed
|
||||
period of time, after which the memory may be discarded and reclaimed. For
|
||||
example, a memory region that is only required at boot time while the system is
|
||||
initializing, or to temporarily share a memory buffer between the normal world
|
||||
and trusted world. Note that it is up to the caller to ensure that these regions
|
||||
are not accessed concurrently while the regions are being added or removed.
|
||||
|
||||
Although this feature provides some level of dynamic memory allocation, this
|
||||
does not allow dynamically allocating an arbitrary amount of memory at an
|
||||
arbitrary memory location. The user is still required to declare at compile-time
|
||||
the limits of these allocations ; the library will deny any mapping request that
|
||||
does not fit within this pre-allocated pool of memory.
|
||||
|
||||
|
||||
Library APIs
|
||||
------------
|
||||
|
||||
The external APIs exposed by this library are declared and documented in the
|
||||
``xlat_tables_v2.h`` header file. This should be the reference point for
|
||||
getting information about the usage of the different APIs this library
|
||||
provides. This section just provides some extra details and clarifications.
|
||||
|
||||
Although the ``mmap_region`` structure is a publicly visible type, it is not
|
||||
recommended to populate these structures by hand. Instead, wherever APIs expect
|
||||
function arguments of type ``mmap_region_t``, these should be constructed using
|
||||
the ``MAP_REGION*()`` family of helper macros. This is to limit the risk of
|
||||
compatibility breaks, should the ``mmap_region`` structure type evolve in the
|
||||
future.
|
||||
|
||||
The ``MAP_REGION()`` and ``MAP_REGION_FLAT()`` macros do not allow specifying a
|
||||
mapping granularity, which leaves the library implementation free to choose
|
||||
it. However, in cases where a specific granularity is required, the
|
||||
``MAP_REGION2()`` macro might be used instead. Using ``MAP_REGION_FLAT()`` only
|
||||
to define regions for the MPU library is strongly recommended.
|
||||
|
||||
As explained earlier in this document, when the dynamic mapping feature is
|
||||
disabled, there is no notion of dynamic regions. Conceptually, there are only
|
||||
static regions. For this reason (and to retain backward compatibility with the
|
||||
version 1 of the library), the APIs that map static regions do not embed the
|
||||
word *static* in their functions names (for example ``mmap_add_region()``), in
|
||||
contrast with the dynamic regions APIs (for example
|
||||
``mmap_add_dynamic_region()``).
|
||||
|
||||
Although the definition of static and dynamic regions is not based on the state
|
||||
of the MMU, the two are still related in some way. Static regions can only be
|
||||
added before ``init_xlat_tables()`` is called and ``init_xlat_tables()`` must be
|
||||
called while the MMU is still off. As a result, static regions cannot be added
|
||||
once the MMU has been enabled. Dynamic regions can be added with the MMU on or
|
||||
off. In practice, the usual call flow would look like this:
|
||||
|
||||
#. The MMU is initially off.
|
||||
|
||||
#. Add some static regions, add some dynamic regions.
|
||||
|
||||
#. Initialize translation tables based on the list of mmap regions (using one of
|
||||
the ``init_xlat_tables*()`` APIs).
|
||||
|
||||
#. At this point, it is no longer possible to add static regions. Dynamic
|
||||
regions can still be added or removed.
|
||||
|
||||
#. Enable the MMU.
|
||||
|
||||
#. Dynamic regions can continue to be added or removed.
|
||||
|
||||
Because static regions are added early on at boot time and are all in the
|
||||
control of the platform initialization code, the ``mmap_add*()`` family of APIs
|
||||
are not expected to fail. They do not return any error code.
|
||||
|
||||
Nonetheless, these APIs will check upfront whether the region can be
|
||||
successfully added before updating the translation context structure. If the
|
||||
library detects that there is insufficient memory to meet the request, or that
|
||||
the new region will overlap another one in an invalid way, or if any other
|
||||
unexpected error is encountered, they will print an error message on the UART.
|
||||
Additionally, when asserts are enabled (typically in debug builds), an assertion
|
||||
will be triggered. Otherwise, the function call will just return straight away,
|
||||
without adding the offending memory region.
|
||||
|
||||
|
||||
Library limitations
|
||||
-------------------
|
||||
|
||||
Dynamic regions are not allowed to overlap each other. Static regions are
|
||||
allowed to overlap as long as one of them is fully contained inside the other
|
||||
one. This is allowed for backwards compatibility with the previous behaviour in
|
||||
the version 1 of the library.
|
||||
|
||||
|
||||
Implementation details
|
||||
----------------------
|
||||
|
||||
Code structure
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
The library is divided into 4 modules:
|
||||
|
||||
- **Core module**
|
||||
|
||||
Provides the main functionality of the library, such as the initialization of
|
||||
translation tables contexts and mapping/unmapping memory regions. This module
|
||||
provides functions such as ``mmap_add_region_ctx`` that let the caller specify
|
||||
the translation tables context affected by them.
|
||||
|
||||
See ``xlat_tables_core.c``.
|
||||
|
||||
- **Active context module**
|
||||
|
||||
Instantiates the context that is used by the current BL image and provides
|
||||
helpers to manipulate it, abstracting it from the rest of the code.
|
||||
This module provides functions such as ``mmap_add_region``, that directly
|
||||
affect the BL image using them.
|
||||
|
||||
See ``xlat_tables_context.c``.
|
||||
|
||||
- **Utilities module**
|
||||
|
||||
Provides additional functionality like debug print of the current state of the
|
||||
translation tables and helpers to query memory attributes and to modify them.
|
||||
|
||||
See ``xlat_tables_utils.c``.
|
||||
|
||||
- **Architectural module**
|
||||
|
||||
Provides functions that are dependent on the current execution state
|
||||
(AArch32/AArch64), such as the functions used for TLB invalidation, setup the
|
||||
MMU, or calculate the Physical Address Space size. They do not need a
|
||||
translation context to work on.
|
||||
|
||||
See ``aarch32/xlat_tables_arch.c`` and ``aarch64/xlat_tables_arch.c``.
|
||||
|
||||
From mmap regions to translation tables
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
A translation context contains a list of ``mmap_region_t``, which holds the
|
||||
information of all the regions that are mapped at any given time. Whenever there
|
||||
is a request to map (resp. unmap) a memory region, it is added to (resp. removed
|
||||
from) the ``mmap_region_t`` list.
|
||||
|
||||
The mmap regions list is a conceptual way to represent the memory layout. At
|
||||
some point, the library has to convert this information into actual translation
|
||||
tables to program into the MMU.
|
||||
|
||||
Before the ``init_xlat_tables()`` API is called, the library only acts on the
|
||||
mmap regions list. Adding a static or dynamic region at this point through one
|
||||
of the ``mmap_add*()`` APIs does not affect the translation tables in any way,
|
||||
they only get registered in the internal mmap region list. It is only when the
|
||||
user calls the ``init_xlat_tables()`` that the translation tables are populated
|
||||
in memory based on the list of mmap regions registered so far. This is an
|
||||
optimization that allows creation of the initial set of translation tables in
|
||||
one go, rather than having to edit them every time while the MMU is disabled.
|
||||
|
||||
After the ``init_xlat_tables()`` API has been called, only dynamic regions can
|
||||
be added. Changes to the translation tables (as well as the mmap regions list)
|
||||
will take effect immediately.
|
||||
|
||||
The memory mapping algorithm
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The mapping function is implemented as a recursive algorithm. It is however
|
||||
bound by the level of depth of the translation tables (the Armv8-A architecture
|
||||
allows up to 4 lookup levels).
|
||||
|
||||
By default [#granularity]_, the algorithm will attempt to minimize the
|
||||
number of translation tables created to satisfy the user's request. It will
|
||||
favour mapping a region using the biggest possible blocks, only creating a
|
||||
sub-table if it is strictly necessary. This is to reduce the memory footprint of
|
||||
the firmware.
|
||||
|
||||
The most common reason for needing a sub-table is when a specific mapping
|
||||
requires a finer granularity. Misaligned regions also require a finer
|
||||
granularity than what the user may had originally expected, using a lot more
|
||||
memory than expected. The reason is that all levels of translation are
|
||||
restricted to address translations of the same granularity as the size of the
|
||||
blocks of that level. For example, for a 4 KiB page size, a level 2 block entry
|
||||
can only translate up to a granularity of 2 MiB. If the Physical Address is not
|
||||
aligned to 2 MiB then additional level 3 tables are also needed.
|
||||
|
||||
Note that not every translation level allows any type of descriptor. Depending
|
||||
on the page size, levels 0 and 1 of translation may only allow table
|
||||
descriptors. If a block entry could be able to describe a translation, but that
|
||||
level does not allow block descriptors, a table descriptor will have to be used
|
||||
instead, as well as additional tables at the next level.
|
||||
|
||||
|Alignment Example|
|
||||
|
||||
The mmap regions are sorted in a way that simplifies the code that maps
|
||||
them. Even though this ordering is only strictly needed for overlapping static
|
||||
regions, it must also be applied for dynamic regions to maintain a consistent
|
||||
order of all regions at all times. As each new region is mapped, existing
|
||||
entries in the translation tables are checked to ensure consistency. Please
|
||||
refer to the comments in the source code of the core module for more details
|
||||
about the sorting algorithm in use.
|
||||
|
||||
This mapping algorithm does not apply to the MPU library, since the MPU hardware
|
||||
directly maps regions by "base" and "limit" (bottom and top) addresses.
|
||||
|
||||
TLB maintenance operations
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The library takes care of performing TLB maintenance operations when required.
|
||||
For example, when the user requests removing a dynamic region, the library
|
||||
invalidates all TLB entries associated to that region to ensure that these
|
||||
changes are visible to subsequent execution, including speculative execution,
|
||||
that uses the changed translation table entries.
|
||||
|
||||
A counter-example is the initialization of translation tables. In this case,
|
||||
explicit TLB maintenance is not required. The Armv8-A architecture guarantees
|
||||
that all TLBs are disabled from reset and their contents have no effect on
|
||||
address translation at reset [#tlb-reset-ref]_. Therefore, the TLBs invalidation
|
||||
is deferred to the ``enable_mmu*()`` family of functions, just before the MMU is
|
||||
turned on.
|
||||
|
||||
Regarding enabling and disabling memory management, for the MPU library, to
|
||||
reduce confusion, calls to enable or disable the MPU use ``mpu`` in their names
|
||||
in place of ``mmu``. For example, the ``enable_mmu_el2()`` call is changed to
|
||||
``enable_mpu_el2()``.
|
||||
|
||||
TLB invalidation is not required when adding dynamic regions either. Dynamic
|
||||
regions are not allowed to overlap existing memory region. Therefore, if the
|
||||
dynamic mapping request is deemed legitimate, it automatically concerns memory
|
||||
that was not mapped in this translation regime and the library will have
|
||||
initialized its corresponding translation table entry to an invalid
|
||||
descriptor. Given that the TLBs are not architecturally permitted to hold any
|
||||
invalid translation table entry [#tlb-no-invalid-entry]_, this means that this
|
||||
mapping cannot be cached in the TLBs.
|
||||
|
||||
.. rubric:: Footnotes
|
||||
|
||||
.. [#granularity] That is, when mmap regions do not enforce their mapping
|
||||
granularity.
|
||||
|
||||
.. [#tlb-reset-ref] See section D4.9 ``Translation Lookaside Buffers (TLBs)``,
|
||||
subsection ``TLB behavior at reset`` in Armv8-A, rev C.a.
|
||||
|
||||
.. [#tlb-no-invalid-entry] See section D4.10.1 ``General TLB maintenance
|
||||
requirements`` in Armv8-A, rev C.a.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. |Alignment Example| image:: ../resources/diagrams/xlat_align.png
|
||||
95
arm-trusted-firmware/docs/conf.py
Normal file
95
arm-trusted-firmware/docs/conf.py
Normal file
@@ -0,0 +1,95 @@
|
||||
# -*- coding: utf-8 -*-
|
||||
#
|
||||
# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
#
|
||||
# Configuration file for the Sphinx documentation builder.
|
||||
#
|
||||
# See the options documentation at http://www.sphinx-doc.org/en/master/config
|
||||
|
||||
import os
|
||||
|
||||
# -- Project information -----------------------------------------------------
|
||||
|
||||
project = 'Trusted Firmware-A'
|
||||
|
||||
# -- General configuration ---------------------------------------------------
|
||||
|
||||
# Add any Sphinx extension module names here, as strings. They can be
|
||||
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
|
||||
# ones.
|
||||
extensions = ['myst_parser', 'sphinx.ext.autosectionlabel', 'sphinxcontrib.plantuml']
|
||||
|
||||
# Add any paths that contain templates here, relative to this directory.
|
||||
templates_path = ['_templates']
|
||||
|
||||
# The suffix(es) of source filenames.
|
||||
source_suffix = ['.md', '.rst']
|
||||
|
||||
# The master toctree document.
|
||||
master_doc = 'index'
|
||||
|
||||
# The language for content autogenerated by Sphinx. Refer to documentation
|
||||
# for a list of supported languages.
|
||||
#
|
||||
# This is also used if you do content translation via gettext catalogs.
|
||||
# Usually you set "language" from the command line for these cases.
|
||||
language = "en"
|
||||
|
||||
# List of patterns, relative to source directory, that match files and
|
||||
# directories to ignore when looking for source files.
|
||||
# This pattern also affects html_static_path and html_extra_path .
|
||||
# Don't try to build the venv in case it's placed with the sources
|
||||
exclude_patterns = [".env", "env", ".venv", "venv"]
|
||||
|
||||
# The name of the Pygments (syntax highlighting) style to use.
|
||||
pygments_style = 'sphinx'
|
||||
|
||||
# Load the contents of the global substitutions file into the 'rst_prolog'
|
||||
# variable. This ensures that the substitutions are all inserted into each page.
|
||||
with open('global_substitutions.txt', 'r') as subs:
|
||||
rst_prolog = subs.read()
|
||||
|
||||
# Minimum version of sphinx required
|
||||
needs_sphinx = '2.0'
|
||||
|
||||
# -- Options for HTML output -------------------------------------------------
|
||||
|
||||
# Don't show the "Built with Sphinx" footer
|
||||
html_show_sphinx = False
|
||||
|
||||
# Don't show copyright info in the footer (we have this content in the page)
|
||||
html_show_copyright = False
|
||||
|
||||
# The theme to use for HTML and HTML Help pages. See the documentation for
|
||||
# a list of builtin themes.
|
||||
html_theme = "sphinx_rtd_theme"
|
||||
|
||||
# The logo to display in the sidebar
|
||||
html_logo = 'resources/TrustedFirmware-Logo_standard-white.png'
|
||||
|
||||
# Options for the "sphinx-rtd-theme" theme
|
||||
html_theme_options = {
|
||||
'collapse_navigation': False, # Can expand and collapse sidebar entries
|
||||
'prev_next_buttons_location': 'both', # Top and bottom of the page
|
||||
'style_external_links': True # Display an icon next to external links
|
||||
}
|
||||
|
||||
# Path to _static directory
|
||||
html_static_path = ['_static']
|
||||
|
||||
# Path to css file relative to html_static_path
|
||||
html_css_files = [
|
||||
'css/custom.css',
|
||||
]
|
||||
|
||||
# -- Options for autosectionlabel --------------------------------------------
|
||||
|
||||
# Only generate automatic section labels for document titles
|
||||
autosectionlabel_maxdepth = 1
|
||||
|
||||
# -- Options for plantuml ----------------------------------------------------
|
||||
|
||||
plantuml_output_format = 'svg_img'
|
||||
84
arm-trusted-firmware/docs/design/alt-boot-flows.rst
Normal file
84
arm-trusted-firmware/docs/design/alt-boot-flows.rst
Normal file
@@ -0,0 +1,84 @@
|
||||
Alternative Boot Flows
|
||||
======================
|
||||
|
||||
EL3 payloads alternative boot flow
|
||||
----------------------------------
|
||||
|
||||
On a pre-production system, the ability to execute arbitrary, bare-metal code at
|
||||
the highest exception level is required. It allows full, direct access to the
|
||||
hardware, for example to run silicon soak tests.
|
||||
|
||||
Although it is possible to implement some baremetal secure firmware from
|
||||
scratch, this is a complex task on some platforms, depending on the level of
|
||||
configuration required to put the system in the expected state.
|
||||
|
||||
Rather than booting a baremetal application, a possible compromise is to boot
|
||||
``EL3 payloads`` through TF-A instead. This is implemented as an alternative
|
||||
boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
|
||||
other BL images and passing control to BL31. It reduces the complexity of
|
||||
developing EL3 baremetal code by:
|
||||
|
||||
- putting the system into a known architectural state;
|
||||
- taking care of platform secure world initialization;
|
||||
- loading the SCP_BL2 image if required by the platform.
|
||||
|
||||
When booting an EL3 payload on Arm standard platforms, the configuration of the
|
||||
TrustZone controller is simplified such that only region 0 is enabled and is
|
||||
configured to permit secure access only. This gives full access to the whole
|
||||
DRAM to the EL3 payload.
|
||||
|
||||
The system is left in the same state as when entering BL31 in the default boot
|
||||
flow. In particular:
|
||||
|
||||
- Running in EL3;
|
||||
- Current state is AArch64;
|
||||
- Little-endian data access;
|
||||
- All exceptions disabled;
|
||||
- MMU disabled;
|
||||
- Caches disabled.
|
||||
|
||||
.. _alt_boot_flows_el3_payload:
|
||||
|
||||
Booting an EL3 payload
|
||||
~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The EL3 payload image is a standalone image and is not part of the FIP. It is
|
||||
not loaded by TF-A. Therefore, there are 2 possible scenarios:
|
||||
|
||||
- The EL3 payload may reside in non-volatile memory (NVM) and execute in
|
||||
place. In this case, booting it is just a matter of specifying the right
|
||||
address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
|
||||
|
||||
- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
|
||||
run-time.
|
||||
|
||||
To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
|
||||
used. The infinite loop that it introduces in BL1 stops execution at the right
|
||||
moment for a debugger to take control of the target and load the payload (for
|
||||
example, over JTAG).
|
||||
|
||||
It is expected that this loading method will work in most cases, as a debugger
|
||||
connection is usually available in a pre-production system. The user is free to
|
||||
use any other platform-specific mechanism to load the EL3 payload, though.
|
||||
|
||||
|
||||
Preloaded BL33 alternative boot flow
|
||||
------------------------------------
|
||||
|
||||
Some platforms have the ability to preload BL33 into memory instead of relying
|
||||
on TF-A to load it. This may simplify packaging of the normal world code and
|
||||
improve performance in a development environment. When secure world cold boot
|
||||
is complete, TF-A simply jumps to a BL33 base address provided at build time.
|
||||
|
||||
For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
|
||||
used when compiling TF-A. For example, the following command will create a FIP
|
||||
without a BL33 and prepare to jump to a BL33 image loaded at address
|
||||
0x80000000:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019, Arm Limited. All rights reserved.*
|
||||
980
arm-trusted-firmware/docs/design/auth-framework.rst
Normal file
980
arm-trusted-firmware/docs/design/auth-framework.rst
Normal file
@@ -0,0 +1,980 @@
|
||||
Authentication Framework & Chain of Trust
|
||||
=========================================
|
||||
|
||||
The aim of this document is to describe the authentication framework
|
||||
implemented in Trusted Firmware-A (TF-A). This framework fulfills the
|
||||
following requirements:
|
||||
|
||||
#. It should be possible for a platform port to specify the Chain of Trust in
|
||||
terms of certificate hierarchy and the mechanisms used to verify a
|
||||
particular image/certificate.
|
||||
|
||||
#. The framework should distinguish between:
|
||||
|
||||
- The mechanism used to encode and transport information, e.g. DER encoded
|
||||
X.509v3 certificates to ferry Subject Public Keys, hashes and non-volatile
|
||||
counters.
|
||||
|
||||
- The mechanism used to verify the transported information i.e. the
|
||||
cryptographic libraries.
|
||||
|
||||
The framework has been designed following a modular approach illustrated in the
|
||||
next diagram:
|
||||
|
||||
::
|
||||
|
||||
+---------------+---------------+------------+
|
||||
| Trusted | Trusted | Trusted |
|
||||
| Firmware | Firmware | Firmware |
|
||||
| Generic | IO Framework | Platform |
|
||||
| Code i.e. | (IO) | Port |
|
||||
| BL1/BL2 (GEN) | | (PP) |
|
||||
+---------------+---------------+------------+
|
||||
^ ^ ^
|
||||
| | |
|
||||
v v v
|
||||
+-----------+ +-----------+ +-----------+
|
||||
| | | | | Image |
|
||||
| Crypto | | Auth | | Parser |
|
||||
| Module |<->| Module |<->| Module |
|
||||
| (CM) | | (AM) | | (IPM) |
|
||||
| | | | | |
|
||||
+-----------+ +-----------+ +-----------+
|
||||
^ ^
|
||||
| |
|
||||
v v
|
||||
+----------------+ +-----------------+
|
||||
| Cryptographic | | Image Parser |
|
||||
| Libraries (CL) | | Libraries (IPL) |
|
||||
+----------------+ +-----------------+
|
||||
| |
|
||||
| |
|
||||
| |
|
||||
v v
|
||||
+-----------------+
|
||||
| Misc. Libs e.g. |
|
||||
| ASN.1 decoder |
|
||||
| |
|
||||
+-----------------+
|
||||
|
||||
DIAGRAM 1.
|
||||
|
||||
This document describes the inner details of the authentication framework and
|
||||
the abstraction mechanisms available to specify a Chain of Trust.
|
||||
|
||||
Framework design
|
||||
----------------
|
||||
|
||||
This section describes some aspects of the framework design and the rationale
|
||||
behind them. These aspects are key to verify a Chain of Trust.
|
||||
|
||||
Chain of Trust
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
A CoT is basically a sequence of authentication images which usually starts with
|
||||
a root of trust and culminates in a single data image. The following diagram
|
||||
illustrates how this maps to a CoT for the BL31 image described in the
|
||||
`TBBR-Client specification`_.
|
||||
|
||||
::
|
||||
|
||||
+------------------+ +-------------------+
|
||||
| ROTPK/ROTPK Hash |------>| Trusted Key |
|
||||
+------------------+ | Certificate |
|
||||
| (Auth Image) |
|
||||
/+-------------------+
|
||||
/ |
|
||||
/ |
|
||||
/ |
|
||||
/ |
|
||||
L v
|
||||
+------------------+ +-------------------+
|
||||
| Trusted World |------>| BL31 Key |
|
||||
| Public Key | | Certificate |
|
||||
+------------------+ | (Auth Image) |
|
||||
+-------------------+
|
||||
/ |
|
||||
/ |
|
||||
/ |
|
||||
/ |
|
||||
/ v
|
||||
+------------------+ L +-------------------+
|
||||
| BL31 Content |------>| BL31 Content |
|
||||
| Certificate PK | | Certificate |
|
||||
+------------------+ | (Auth Image) |
|
||||
+-------------------+
|
||||
/ |
|
||||
/ |
|
||||
/ |
|
||||
/ |
|
||||
/ v
|
||||
+------------------+ L +-------------------+
|
||||
| BL31 Hash |------>| BL31 Image |
|
||||
| | | (Data Image) |
|
||||
+------------------+ | |
|
||||
+-------------------+
|
||||
|
||||
DIAGRAM 2.
|
||||
|
||||
The root of trust is usually a public key (ROTPK) that has been burnt in the
|
||||
platform and cannot be modified.
|
||||
|
||||
Image types
|
||||
~~~~~~~~~~~
|
||||
|
||||
Images in a CoT are categorised as authentication and data images. An
|
||||
authentication image contains information to authenticate a data image or
|
||||
another authentication image. A data image is usually a boot loader binary, but
|
||||
it could be any other data that requires authentication.
|
||||
|
||||
Component responsibilities
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
For every image in a Chain of Trust, the following high level operations are
|
||||
performed to verify it:
|
||||
|
||||
#. Allocate memory for the image either statically or at runtime.
|
||||
|
||||
#. Identify the image and load it in the allocated memory.
|
||||
|
||||
#. Check the integrity of the image as per its type.
|
||||
|
||||
#. Authenticate the image as per the cryptographic algorithms used.
|
||||
|
||||
#. If the image is an authentication image, extract the information that will
|
||||
be used to authenticate the next image in the CoT.
|
||||
|
||||
In Diagram 1, each component is responsible for one or more of these operations.
|
||||
The responsibilities are briefly described below.
|
||||
|
||||
TF-A Generic code and IO framework (GEN/IO)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
These components are responsible for initiating the authentication process for a
|
||||
particular image in BL1 or BL2. For each BL image that requires authentication,
|
||||
the Generic code asks recursively the Authentication module what is the parent
|
||||
image until either an authenticated image or the ROT is reached. Then the
|
||||
Generic code calls the IO framework to load the image and calls the
|
||||
Authentication module to authenticate it, following the CoT from ROT to Image.
|
||||
|
||||
TF-A Platform Port (PP)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The platform is responsible for:
|
||||
|
||||
#. Specifying the CoT for each image that needs to be authenticated. Details of
|
||||
how a CoT can be specified by the platform are explained later. The platform
|
||||
also specifies the authentication methods and the parsing method used for
|
||||
each image.
|
||||
|
||||
#. Statically allocating memory for each parameter in each image which is
|
||||
used for verifying the CoT, e.g. memory for public keys, hashes etc.
|
||||
|
||||
#. Providing the ROTPK or a hash of it.
|
||||
|
||||
#. Providing additional information to the IPM to enable it to identify and
|
||||
extract authentication parameters contained in an image, e.g. if the
|
||||
parameters are stored as X509v3 extensions, the corresponding OID must be
|
||||
provided.
|
||||
|
||||
#. Fulfill any other memory requirements of the IPM and the CM (not currently
|
||||
described in this document).
|
||||
|
||||
#. Export functions to verify an image which uses an authentication method that
|
||||
cannot be interpreted by the CM, e.g. if an image has to be verified using a
|
||||
NV counter, then the value of the counter to compare with can only be
|
||||
provided by the platform.
|
||||
|
||||
#. Export a custom IPM if a proprietary image format is being used (described
|
||||
later).
|
||||
|
||||
Authentication Module (AM)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
It is responsible for:
|
||||
|
||||
#. Providing the necessary abstraction mechanisms to describe a CoT. Amongst
|
||||
other things, the authentication and image parsing methods must be specified
|
||||
by the PP in the CoT.
|
||||
|
||||
#. Verifying the CoT passed by GEN by utilising functionality exported by the
|
||||
PP, IPM and CM.
|
||||
|
||||
#. Tracking which images have been verified. In case an image is a part of
|
||||
multiple CoTs then it should be verified only once e.g. the Trusted World
|
||||
Key Certificate in the TBBR-Client spec. contains information to verify
|
||||
SCP_BL2, BL31, BL32 each of which have a separate CoT. (This
|
||||
responsibility has not been described in this document but should be
|
||||
trivial to implement).
|
||||
|
||||
#. Reusing memory meant for a data image to verify authentication images e.g.
|
||||
in the CoT described in Diagram 2, each certificate can be loaded and
|
||||
verified in the memory reserved by the platform for the BL31 image. By the
|
||||
time BL31 (the data image) is loaded, all information to authenticate it
|
||||
will have been extracted from the parent image i.e. BL31 content
|
||||
certificate. It is assumed that the size of an authentication image will
|
||||
never exceed the size of a data image. It should be possible to verify this
|
||||
at build time using asserts.
|
||||
|
||||
Cryptographic Module (CM)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The CM is responsible for providing an API to:
|
||||
|
||||
#. Verify a digital signature.
|
||||
#. Verify a hash.
|
||||
|
||||
The CM does not include any cryptography related code, but it relies on an
|
||||
external library to perform the cryptographic operations. A Crypto-Library (CL)
|
||||
linking the CM and the external library must be implemented. The following
|
||||
functions must be provided by the CL:
|
||||
|
||||
.. code:: c
|
||||
|
||||
void (*init)(void);
|
||||
int (*verify_signature)(void *data_ptr, unsigned int data_len,
|
||||
void *sig_ptr, unsigned int sig_len,
|
||||
void *sig_alg, unsigned int sig_alg_len,
|
||||
void *pk_ptr, unsigned int pk_len);
|
||||
int (*verify_hash)(void *data_ptr, unsigned int data_len,
|
||||
void *digest_info_ptr, unsigned int digest_info_len);
|
||||
|
||||
These functions are registered in the CM using the macro:
|
||||
|
||||
.. code:: c
|
||||
|
||||
REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash);
|
||||
|
||||
``_name`` must be a string containing the name of the CL. This name is used for
|
||||
debugging purposes.
|
||||
|
||||
Image Parser Module (IPM)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The IPM is responsible for:
|
||||
|
||||
#. Checking the integrity of each image loaded by the IO framework.
|
||||
#. Extracting parameters used for authenticating an image based upon a
|
||||
description provided by the platform in the CoT descriptor.
|
||||
|
||||
Images may have different formats (for example, authentication images could be
|
||||
x509v3 certificates, signed ELF files or any other platform specific format).
|
||||
The IPM allows to register an Image Parser Library (IPL) for every image format
|
||||
used in the CoT. This library must implement the specific methods to parse the
|
||||
image. The IPM obtains the image format from the CoT and calls the right IPL to
|
||||
check the image integrity and extract the authentication parameters.
|
||||
|
||||
See Section "Describing the image parsing methods" for more details about the
|
||||
mechanism the IPM provides to define and register IPLs.
|
||||
|
||||
Authentication methods
|
||||
~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The AM supports the following authentication methods:
|
||||
|
||||
#. Hash
|
||||
#. Digital signature
|
||||
|
||||
The platform may specify these methods in the CoT in case it decides to define
|
||||
a custom CoT instead of reusing a predefined one.
|
||||
|
||||
If a data image uses multiple methods, then all the methods must be a part of
|
||||
the same CoT. The number and type of parameters are method specific. These
|
||||
parameters should be obtained from the parent image using the IPM.
|
||||
|
||||
#. Hash
|
||||
|
||||
Parameters:
|
||||
|
||||
#. A pointer to data to hash
|
||||
#. Length of the data
|
||||
#. A pointer to the hash
|
||||
#. Length of the hash
|
||||
|
||||
The hash will be represented by the DER encoding of the following ASN.1
|
||||
type:
|
||||
|
||||
::
|
||||
|
||||
DigestInfo ::= SEQUENCE {
|
||||
digestAlgorithm DigestAlgorithmIdentifier,
|
||||
digest Digest
|
||||
}
|
||||
|
||||
This ASN.1 structure makes it possible to remove any assumption about the
|
||||
type of hash algorithm used as this information accompanies the hash. This
|
||||
should allow the Cryptography Library (CL) to support multiple hash
|
||||
algorithm implementations.
|
||||
|
||||
#. Digital Signature
|
||||
|
||||
Parameters:
|
||||
|
||||
#. A pointer to data to sign
|
||||
#. Length of the data
|
||||
#. Public Key Algorithm
|
||||
#. Public Key value
|
||||
#. Digital Signature Algorithm
|
||||
#. Digital Signature value
|
||||
|
||||
The Public Key parameters will be represented by the DER encoding of the
|
||||
following ASN.1 type:
|
||||
|
||||
::
|
||||
|
||||
SubjectPublicKeyInfo ::= SEQUENCE {
|
||||
algorithm AlgorithmIdentifier{PUBLIC-KEY,{PublicKeyAlgorithms}},
|
||||
subjectPublicKey BIT STRING }
|
||||
|
||||
The Digital Signature Algorithm will be represented by the DER encoding of
|
||||
the following ASN.1 types.
|
||||
|
||||
::
|
||||
|
||||
AlgorithmIdentifier {ALGORITHM:IOSet } ::= SEQUENCE {
|
||||
algorithm ALGORITHM.&id({IOSet}),
|
||||
parameters ALGORITHM.&Type({IOSet}{@algorithm}) OPTIONAL
|
||||
}
|
||||
|
||||
The digital signature will be represented by:
|
||||
|
||||
::
|
||||
|
||||
signature ::= BIT STRING
|
||||
|
||||
The authentication framework will use the image descriptor to extract all the
|
||||
information related to authentication.
|
||||
|
||||
Specifying a Chain of Trust
|
||||
---------------------------
|
||||
|
||||
A CoT can be described as a set of image descriptors linked together in a
|
||||
particular order. The order dictates the sequence in which they must be
|
||||
verified. Each image has a set of properties which allow the AM to verify it.
|
||||
These properties are described below.
|
||||
|
||||
The PP is responsible for defining a single or multiple CoTs for a data image.
|
||||
Unless otherwise specified, the data structures described in the following
|
||||
sections are populated by the PP statically.
|
||||
|
||||
Describing the image parsing methods
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The parsing method refers to the format of a particular image. For example, an
|
||||
authentication image that represents a certificate could be in the X.509v3
|
||||
format. A data image that represents a boot loader stage could be in raw binary
|
||||
or ELF format. The IPM supports three parsing methods. An image has to use one
|
||||
of the three methods described below. An IPL is responsible for interpreting a
|
||||
single parsing method. There has to be one IPL for every method used by the
|
||||
platform.
|
||||
|
||||
#. Raw format: This format is effectively a nop as an image using this method
|
||||
is treated as being in raw binary format e.g. boot loader images used by
|
||||
TF-A. This method should only be used by data images.
|
||||
|
||||
#. X509V3 method: This method uses industry standards like X.509 to represent
|
||||
PKI certificates (authentication images). It is expected that open source
|
||||
libraries will be available which can be used to parse an image represented
|
||||
by this method. Such libraries can be used to write the corresponding IPL
|
||||
e.g. the X.509 parsing library code in mbed TLS.
|
||||
|
||||
#. Platform defined method: This method caters for platform specific
|
||||
proprietary standards to represent authentication or data images. For
|
||||
example, The signature of a data image could be appended to the data image
|
||||
raw binary. A header could be prepended to the combined blob to specify the
|
||||
extents of each component. The platform will have to implement the
|
||||
corresponding IPL to interpret such a format.
|
||||
|
||||
The following enum can be used to define these three methods.
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef enum img_type_enum {
|
||||
IMG_RAW, /* Binary image */
|
||||
IMG_PLAT, /* Platform specific format */
|
||||
IMG_CERT, /* X509v3 certificate */
|
||||
IMG_MAX_TYPES,
|
||||
} img_type_t;
|
||||
|
||||
An IPL must provide functions with the following prototypes:
|
||||
|
||||
.. code:: c
|
||||
|
||||
void init(void);
|
||||
int check_integrity(void *img, unsigned int img_len);
|
||||
int get_auth_param(const auth_param_type_desc_t *type_desc,
|
||||
void *img, unsigned int img_len,
|
||||
void **param, unsigned int *param_len);
|
||||
|
||||
An IPL for each type must be registered using the following macro:
|
||||
|
||||
.. code:: c
|
||||
|
||||
REGISTER_IMG_PARSER_LIB(_type, _name, _init, _check_int, _get_param)
|
||||
|
||||
- ``_type``: one of the types described above.
|
||||
- ``_name``: a string containing the IPL name for debugging purposes.
|
||||
- ``_init``: initialization function pointer.
|
||||
- ``_check_int``: check image integrity function pointer.
|
||||
- ``_get_param``: extract authentication parameter function pointer.
|
||||
|
||||
The ``init()`` function will be used to initialize the IPL.
|
||||
|
||||
The ``check_integrity()`` function is passed a pointer to the memory where the
|
||||
image has been loaded by the IO framework and the image length. It should ensure
|
||||
that the image is in the format corresponding to the parsing method and has not
|
||||
been tampered with. For example, RFC-2459 describes a validation sequence for an
|
||||
X.509 certificate.
|
||||
|
||||
The ``get_auth_param()`` function is passed a parameter descriptor containing
|
||||
information about the parameter (``type_desc`` and ``cookie``) to identify and
|
||||
extract the data corresponding to that parameter from an image. This data will
|
||||
be used to verify either the current or the next image in the CoT sequence.
|
||||
|
||||
Each image in the CoT will specify the parsing method it uses. This information
|
||||
will be used by the IPM to find the right parser descriptor for the image.
|
||||
|
||||
Describing the authentication method(s)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
As part of the CoT, each image has to specify one or more authentication methods
|
||||
which will be used to verify it. As described in the Section "Authentication
|
||||
methods", there are three methods supported by the AM.
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef enum {
|
||||
AUTH_METHOD_NONE,
|
||||
AUTH_METHOD_HASH,
|
||||
AUTH_METHOD_SIG,
|
||||
AUTH_METHOD_NUM
|
||||
} auth_method_type_t;
|
||||
|
||||
The AM defines the type of each parameter used by an authentication method. It
|
||||
uses this information to:
|
||||
|
||||
#. Specify to the ``get_auth_param()`` function exported by the IPM, which
|
||||
parameter should be extracted from an image.
|
||||
|
||||
#. Correctly marshall the parameters while calling the verification function
|
||||
exported by the CM and PP.
|
||||
|
||||
#. Extract authentication parameters from a parent image in order to verify a
|
||||
child image e.g. to verify the certificate image, the public key has to be
|
||||
obtained from the parent image.
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef enum {
|
||||
AUTH_PARAM_NONE,
|
||||
AUTH_PARAM_RAW_DATA, /* Raw image data */
|
||||
AUTH_PARAM_SIG, /* The image signature */
|
||||
AUTH_PARAM_SIG_ALG, /* The image signature algorithm */
|
||||
AUTH_PARAM_HASH, /* A hash (including the algorithm) */
|
||||
AUTH_PARAM_PUB_KEY, /* A public key */
|
||||
} auth_param_type_t;
|
||||
|
||||
The AM defines the following structure to identify an authentication parameter
|
||||
required to verify an image.
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef struct auth_param_type_desc_s {
|
||||
auth_param_type_t type;
|
||||
void *cookie;
|
||||
} auth_param_type_desc_t;
|
||||
|
||||
``cookie`` is used by the platform to specify additional information to the IPM
|
||||
which enables it to uniquely identify the parameter that should be extracted
|
||||
from an image. For example, the hash of a BL3x image in its corresponding
|
||||
content certificate is stored in an X509v3 custom extension field. An extension
|
||||
field can only be identified using an OID. In this case, the ``cookie`` could
|
||||
contain the pointer to the OID defined by the platform for the hash extension
|
||||
field while the ``type`` field could be set to ``AUTH_PARAM_HASH``. A value of 0 for
|
||||
the ``cookie`` field means that it is not used.
|
||||
|
||||
For each method, the AM defines a structure with the parameters required to
|
||||
verify the image.
|
||||
|
||||
.. code:: c
|
||||
|
||||
/*
|
||||
* Parameters for authentication by hash matching
|
||||
*/
|
||||
typedef struct auth_method_param_hash_s {
|
||||
auth_param_type_desc_t *data; /* Data to hash */
|
||||
auth_param_type_desc_t *hash; /* Hash to match with */
|
||||
} auth_method_param_hash_t;
|
||||
|
||||
/*
|
||||
* Parameters for authentication by signature
|
||||
*/
|
||||
typedef struct auth_method_param_sig_s {
|
||||
auth_param_type_desc_t *pk; /* Public key */
|
||||
auth_param_type_desc_t *sig; /* Signature to check */
|
||||
auth_param_type_desc_t *alg; /* Signature algorithm */
|
||||
auth_param_type_desc_t *tbs; /* Data signed */
|
||||
} auth_method_param_sig_t;
|
||||
|
||||
The AM defines the following structure to describe an authentication method for
|
||||
verifying an image
|
||||
|
||||
.. code:: c
|
||||
|
||||
/*
|
||||
* Authentication method descriptor
|
||||
*/
|
||||
typedef struct auth_method_desc_s {
|
||||
auth_method_type_t type;
|
||||
union {
|
||||
auth_method_param_hash_t hash;
|
||||
auth_method_param_sig_t sig;
|
||||
} param;
|
||||
} auth_method_desc_t;
|
||||
|
||||
Using the method type specified in the ``type`` field, the AM finds out what field
|
||||
needs to access within the ``param`` union.
|
||||
|
||||
Storing Authentication parameters
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
A parameter described by ``auth_param_type_desc_t`` to verify an image could be
|
||||
obtained from either the image itself or its parent image. The memory allocated
|
||||
for loading the parent image will be reused for loading the child image. Hence
|
||||
parameters which are obtained from the parent for verifying a child image need
|
||||
to have memory allocated for them separately where they can be stored. This
|
||||
memory must be statically allocated by the platform port.
|
||||
|
||||
The AM defines the following structure to store the data corresponding to an
|
||||
authentication parameter.
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef struct auth_param_data_desc_s {
|
||||
void *auth_param_ptr;
|
||||
unsigned int auth_param_len;
|
||||
} auth_param_data_desc_t;
|
||||
|
||||
The ``auth_param_ptr`` field is initialized by the platform. The ``auth_param_len``
|
||||
field is used to specify the length of the data in the memory.
|
||||
|
||||
For parameters that can be obtained from the child image itself, the IPM is
|
||||
responsible for populating the ``auth_param_ptr`` and ``auth_param_len`` fields
|
||||
while executing the ``img_get_auth_param()`` function.
|
||||
|
||||
The AM defines the following structure to enable an image to describe the
|
||||
parameters that should be extracted from it and used to verify the next image
|
||||
(child) in a CoT.
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef struct auth_param_desc_s {
|
||||
auth_param_type_desc_t type_desc;
|
||||
auth_param_data_desc_t data;
|
||||
} auth_param_desc_t;
|
||||
|
||||
Describing an image in a CoT
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
An image in a CoT is a consolidation of the following aspects of a CoT described
|
||||
above.
|
||||
|
||||
#. A unique identifier specified by the platform which allows the IO framework
|
||||
to locate the image in a FIP and load it in the memory reserved for the data
|
||||
image in the CoT.
|
||||
|
||||
#. A parsing method which is used by the AM to find the appropriate IPM.
|
||||
|
||||
#. Authentication methods and their parameters as described in the previous
|
||||
section. These are used to verify the current image.
|
||||
|
||||
#. Parameters which are used to verify the next image in the current CoT. These
|
||||
parameters are specified only by authentication images and can be extracted
|
||||
from the current image once it has been verified.
|
||||
|
||||
The following data structure describes an image in a CoT.
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef struct auth_img_desc_s {
|
||||
unsigned int img_id;
|
||||
const struct auth_img_desc_s *parent;
|
||||
img_type_t img_type;
|
||||
const auth_method_desc_t *const img_auth_methods;
|
||||
const auth_param_desc_t *const authenticated_data;
|
||||
} auth_img_desc_t;
|
||||
|
||||
A CoT is defined as an array of pointers to ``auth_image_desc_t`` structures
|
||||
linked together by the ``parent`` field. Those nodes with no parent must be
|
||||
authenticated using the ROTPK stored in the platform.
|
||||
|
||||
Implementation example
|
||||
----------------------
|
||||
|
||||
This section is a detailed guide explaining a trusted boot implementation using
|
||||
the authentication framework. This example corresponds to the Applicative
|
||||
Functional Mode (AFM) as specified in the TBBR-Client document. It is
|
||||
recommended to read this guide along with the source code.
|
||||
|
||||
The TBBR CoT
|
||||
~~~~~~~~~~~~
|
||||
|
||||
CoT specific to BL1 and BL2 can be found in ``drivers/auth/tbbr/tbbr_cot_bl1.c``
|
||||
and ``drivers/auth/tbbr/tbbr_cot_bl2.c`` respectively. The common CoT used across
|
||||
BL1 and BL2 can be found in ``drivers/auth/tbbr/tbbr_cot_common.c``.
|
||||
This CoT consists of an array of pointers to image descriptors and it is
|
||||
registered in the framework using the macro ``REGISTER_COT(cot_desc)``, where
|
||||
``cot_desc`` must be the name of the array (passing a pointer or any other
|
||||
type of indirection will cause the registration process to fail).
|
||||
|
||||
The number of images participating in the boot process depends on the CoT.
|
||||
There is, however, a minimum set of images that are mandatory in TF-A and thus
|
||||
all CoTs must present:
|
||||
|
||||
- ``BL2``
|
||||
- ``SCP_BL2`` (platform specific)
|
||||
- ``BL31``
|
||||
- ``BL32`` (optional)
|
||||
- ``BL33``
|
||||
|
||||
The TBBR specifies the additional certificates that must accompany these images
|
||||
for a proper authentication. Details about the TBBR CoT may be found in the
|
||||
:ref:`Trusted Board Boot` document.
|
||||
|
||||
Following the :ref:`Porting Guide`, a platform must provide unique
|
||||
identifiers for all the images and certificates that will be loaded during the
|
||||
boot process. If a platform is using the TBBR as a reference for trusted boot,
|
||||
these identifiers can be obtained from ``include/common/tbbr/tbbr_img_def.h``.
|
||||
Arm platforms include this file in ``include/plat/arm/common/arm_def.h``. Other
|
||||
platforms may also include this file or provide their own identifiers.
|
||||
|
||||
**Important**: the authentication module uses these identifiers to index the
|
||||
CoT array, so the descriptors location in the array must match the identifiers.
|
||||
|
||||
Each image descriptor must specify:
|
||||
|
||||
- ``img_id``: the corresponding image unique identifier defined by the platform.
|
||||
- ``img_type``: the image parser module uses the image type to call the proper
|
||||
parsing library to check the image integrity and extract the required
|
||||
authentication parameters. Three types of images are currently supported:
|
||||
|
||||
- ``IMG_RAW``: image is a raw binary. No parsing functions are available,
|
||||
other than reading the whole image.
|
||||
- ``IMG_PLAT``: image format is platform specific. The platform may use this
|
||||
type for custom images not directly supported by the authentication
|
||||
framework.
|
||||
- ``IMG_CERT``: image is an x509v3 certificate.
|
||||
|
||||
- ``parent``: pointer to the parent image descriptor. The parent will contain
|
||||
the information required to authenticate the current image. If the parent
|
||||
is NULL, the authentication parameters will be obtained from the platform
|
||||
(i.e. the BL2 and Trusted Key certificates are signed with the ROT private
|
||||
key, whose public part is stored in the platform).
|
||||
- ``img_auth_methods``: this points to an array which defines the
|
||||
authentication methods that must be checked to consider an image
|
||||
authenticated. Each method consists of a type and a list of parameter
|
||||
descriptors. A parameter descriptor consists of a type and a cookie which
|
||||
will point to specific information required to extract that parameter from
|
||||
the image (i.e. if the parameter is stored in an x509v3 extension, the
|
||||
cookie will point to the extension OID). Depending on the method type, a
|
||||
different number of parameters must be specified. This pointer should not be
|
||||
NULL.
|
||||
Supported methods are:
|
||||
|
||||
- ``AUTH_METHOD_HASH``: the hash of the image must match the hash extracted
|
||||
from the parent image. The following parameter descriptors must be
|
||||
specified:
|
||||
|
||||
- ``data``: data to be hashed (obtained from current image)
|
||||
- ``hash``: reference hash (obtained from parent image)
|
||||
|
||||
- ``AUTH_METHOD_SIG``: the image (usually a certificate) must be signed with
|
||||
the private key whose public part is extracted from the parent image (or
|
||||
the platform if the parent is NULL). The following parameter descriptors
|
||||
must be specified:
|
||||
|
||||
- ``pk``: the public key (obtained from parent image)
|
||||
- ``sig``: the digital signature (obtained from current image)
|
||||
- ``alg``: the signature algorithm used (obtained from current image)
|
||||
- ``data``: the data to be signed (obtained from current image)
|
||||
|
||||
- ``authenticated_data``: this array pointer indicates what authentication
|
||||
parameters must be extracted from an image once it has been authenticated.
|
||||
Each parameter consists of a parameter descriptor and the buffer
|
||||
address/size to store the parameter. The CoT is responsible for allocating
|
||||
the required memory to store the parameters. This pointer may be NULL.
|
||||
|
||||
In the ``tbbr_cot*.c`` file, a set of buffers are allocated to store the parameters
|
||||
extracted from the certificates. In the case of the TBBR CoT, these parameters
|
||||
are hashes and public keys. In DER format, an RSA-4096 public key requires 550
|
||||
bytes, and a hash requires 51 bytes. Depending on the CoT and the authentication
|
||||
process, some of the buffers may be reused at different stages during the boot.
|
||||
|
||||
Next in that file, the parameter descriptors are defined. These descriptors will
|
||||
be used to extract the parameter data from the corresponding image.
|
||||
|
||||
Example: the BL31 Chain of Trust
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Four image descriptors form the BL31 Chain of Trust:
|
||||
|
||||
.. code:: c
|
||||
|
||||
static const auth_img_desc_t trusted_key_cert = {
|
||||
.img_id = TRUSTED_KEY_CERT_ID,
|
||||
.img_type = IMG_CERT,
|
||||
.parent = NULL,
|
||||
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
|
||||
[0] = {
|
||||
.type = AUTH_METHOD_SIG,
|
||||
.param.sig = {
|
||||
.pk = &subject_pk,
|
||||
.sig = &sig,
|
||||
.alg = &sig_alg,
|
||||
.data = &raw_data
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.type = AUTH_METHOD_NV_CTR,
|
||||
.param.nv_ctr = {
|
||||
.cert_nv_ctr = &trusted_nv_ctr,
|
||||
.plat_nv_ctr = &trusted_nv_ctr
|
||||
}
|
||||
}
|
||||
},
|
||||
.authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
|
||||
[0] = {
|
||||
.type_desc = &trusted_world_pk,
|
||||
.data = {
|
||||
.ptr = (void *)trusted_world_pk_buf,
|
||||
.len = (unsigned int)PK_DER_LEN
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.type_desc = &non_trusted_world_pk,
|
||||
.data = {
|
||||
.ptr = (void *)non_trusted_world_pk_buf,
|
||||
.len = (unsigned int)PK_DER_LEN
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
static const auth_img_desc_t soc_fw_key_cert = {
|
||||
.img_id = SOC_FW_KEY_CERT_ID,
|
||||
.img_type = IMG_CERT,
|
||||
.parent = &trusted_key_cert,
|
||||
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
|
||||
[0] = {
|
||||
.type = AUTH_METHOD_SIG,
|
||||
.param.sig = {
|
||||
.pk = &trusted_world_pk,
|
||||
.sig = &sig,
|
||||
.alg = &sig_alg,
|
||||
.data = &raw_data
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.type = AUTH_METHOD_NV_CTR,
|
||||
.param.nv_ctr = {
|
||||
.cert_nv_ctr = &trusted_nv_ctr,
|
||||
.plat_nv_ctr = &trusted_nv_ctr
|
||||
}
|
||||
}
|
||||
},
|
||||
.authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
|
||||
[0] = {
|
||||
.type_desc = &soc_fw_content_pk,
|
||||
.data = {
|
||||
.ptr = (void *)content_pk_buf,
|
||||
.len = (unsigned int)PK_DER_LEN
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
static const auth_img_desc_t soc_fw_content_cert = {
|
||||
.img_id = SOC_FW_CONTENT_CERT_ID,
|
||||
.img_type = IMG_CERT,
|
||||
.parent = &soc_fw_key_cert,
|
||||
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
|
||||
[0] = {
|
||||
.type = AUTH_METHOD_SIG,
|
||||
.param.sig = {
|
||||
.pk = &soc_fw_content_pk,
|
||||
.sig = &sig,
|
||||
.alg = &sig_alg,
|
||||
.data = &raw_data
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.type = AUTH_METHOD_NV_CTR,
|
||||
.param.nv_ctr = {
|
||||
.cert_nv_ctr = &trusted_nv_ctr,
|
||||
.plat_nv_ctr = &trusted_nv_ctr
|
||||
}
|
||||
}
|
||||
},
|
||||
.authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
|
||||
[0] = {
|
||||
.type_desc = &soc_fw_hash,
|
||||
.data = {
|
||||
.ptr = (void *)soc_fw_hash_buf,
|
||||
.len = (unsigned int)HASH_DER_LEN
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.type_desc = &soc_fw_config_hash,
|
||||
.data = {
|
||||
.ptr = (void *)soc_fw_config_hash_buf,
|
||||
.len = (unsigned int)HASH_DER_LEN
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
static const auth_img_desc_t bl31_image = {
|
||||
.img_id = BL31_IMAGE_ID,
|
||||
.img_type = IMG_RAW,
|
||||
.parent = &soc_fw_content_cert,
|
||||
.img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
|
||||
[0] = {
|
||||
.type = AUTH_METHOD_HASH,
|
||||
.param.hash = {
|
||||
.data = &raw_data,
|
||||
.hash = &soc_fw_hash
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
The **Trusted Key certificate** is signed with the ROT private key and contains
|
||||
the Trusted World public key and the Non-Trusted World public key as x509v3
|
||||
extensions. This must be specified in the image descriptor using the
|
||||
``img_auth_methods`` and ``authenticated_data`` arrays, respectively.
|
||||
|
||||
The Trusted Key certificate is authenticated by checking its digital signature
|
||||
using the ROTPK. Four parameters are required to check a signature: the public
|
||||
key, the algorithm, the signature and the data that has been signed. Therefore,
|
||||
four parameter descriptors must be specified with the authentication method:
|
||||
|
||||
- ``subject_pk``: parameter descriptor of type ``AUTH_PARAM_PUB_KEY``. This type
|
||||
is used to extract a public key from the parent image. If the cookie is an
|
||||
OID, the key is extracted from the corresponding x509v3 extension. If the
|
||||
cookie is NULL, the subject public key is retrieved. In this case, because
|
||||
the parent image is NULL, the public key is obtained from the platform
|
||||
(this key will be the ROTPK).
|
||||
- ``sig``: parameter descriptor of type ``AUTH_PARAM_SIG``. It is used to extract
|
||||
the signature from the certificate.
|
||||
- ``sig_alg``: parameter descriptor of type ``AUTH_PARAM_SIG``. It is used to
|
||||
extract the signature algorithm from the certificate.
|
||||
- ``raw_data``: parameter descriptor of type ``AUTH_PARAM_RAW_DATA``. It is used
|
||||
to extract the data to be signed from the certificate.
|
||||
|
||||
Once the signature has been checked and the certificate authenticated, the
|
||||
Trusted World public key needs to be extracted from the certificate. A new entry
|
||||
is created in the ``authenticated_data`` array for that purpose. In that entry,
|
||||
the corresponding parameter descriptor must be specified along with the buffer
|
||||
address to store the parameter value. In this case, the ``trusted_world_pk``
|
||||
descriptor is used to extract the public key from an x509v3 extension with OID
|
||||
``TRUSTED_WORLD_PK_OID``. The BL31 key certificate will use this descriptor as
|
||||
parameter in the signature authentication method. The key is stored in the
|
||||
``trusted_world_pk_buf`` buffer.
|
||||
|
||||
The **BL31 Key certificate** is authenticated by checking its digital signature
|
||||
using the Trusted World public key obtained previously from the Trusted Key
|
||||
certificate. In the image descriptor, we specify a single authentication method
|
||||
by signature whose public key is the ``trusted_world_pk``. Once this certificate
|
||||
has been authenticated, we have to extract the BL31 public key, stored in the
|
||||
extension specified by ``soc_fw_content_pk``. This key will be copied to the
|
||||
``content_pk_buf`` buffer.
|
||||
|
||||
The **BL31 certificate** is authenticated by checking its digital signature
|
||||
using the BL31 public key obtained previously from the BL31 Key certificate.
|
||||
We specify the authentication method using ``soc_fw_content_pk`` as public key.
|
||||
After authentication, we need to extract the BL31 hash, stored in the extension
|
||||
specified by ``soc_fw_hash``. This hash will be copied to the
|
||||
``soc_fw_hash_buf`` buffer.
|
||||
|
||||
The **BL31 image** is authenticated by calculating its hash and matching it
|
||||
with the hash obtained from the BL31 certificate. The image descriptor contains
|
||||
a single authentication method by hash. The parameters to the hash method are
|
||||
the reference hash, ``soc_fw_hash``, and the data to be hashed. In this case,
|
||||
it is the whole image, so we specify ``raw_data``.
|
||||
|
||||
The image parser library
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The image parser module relies on libraries to check the image integrity and
|
||||
extract the authentication parameters. The number and type of parser libraries
|
||||
depend on the images used in the CoT. Raw images do not need a library, so
|
||||
only an x509v3 library is required for the TBBR CoT.
|
||||
|
||||
Arm platforms will use an x509v3 library based on mbed TLS. This library may be
|
||||
found in ``drivers/auth/mbedtls/mbedtls_x509_parser.c``. It exports three
|
||||
functions:
|
||||
|
||||
.. code:: c
|
||||
|
||||
void init(void);
|
||||
int check_integrity(void *img, unsigned int img_len);
|
||||
int get_auth_param(const auth_param_type_desc_t *type_desc,
|
||||
void *img, unsigned int img_len,
|
||||
void **param, unsigned int *param_len);
|
||||
|
||||
The library is registered in the framework using the macro
|
||||
``REGISTER_IMG_PARSER_LIB()``. Each time the image parser module needs to access
|
||||
an image of type ``IMG_CERT``, it will call the corresponding function exported
|
||||
in this file.
|
||||
|
||||
The build system must be updated to include the corresponding library and
|
||||
mbed TLS sources. Arm platforms use the ``arm_common.mk`` file to pull the
|
||||
sources.
|
||||
|
||||
The cryptographic library
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The cryptographic module relies on a library to perform the required operations,
|
||||
i.e. verify a hash or a digital signature. Arm platforms will use a library
|
||||
based on mbed TLS, which can be found in
|
||||
``drivers/auth/mbedtls/mbedtls_crypto.c``. This library is registered in the
|
||||
authentication framework using the macro ``REGISTER_CRYPTO_LIB()`` and exports
|
||||
four functions:
|
||||
|
||||
.. code:: c
|
||||
|
||||
void init(void);
|
||||
int verify_signature(void *data_ptr, unsigned int data_len,
|
||||
void *sig_ptr, unsigned int sig_len,
|
||||
void *sig_alg, unsigned int sig_alg_len,
|
||||
void *pk_ptr, unsigned int pk_len);
|
||||
int verify_hash(void *data_ptr, unsigned int data_len,
|
||||
void *digest_info_ptr, unsigned int digest_info_len);
|
||||
int auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr,
|
||||
size_t len, const void *key, unsigned int key_len,
|
||||
unsigned int key_flags, const void *iv,
|
||||
unsigned int iv_len, const void *tag,
|
||||
unsigned int tag_len)
|
||||
|
||||
The mbedTLS library algorithm support is configured by both the
|
||||
``TF_MBEDTLS_KEY_ALG`` and ``TF_MBEDTLS_KEY_SIZE`` variables.
|
||||
|
||||
- ``TF_MBEDTLS_KEY_ALG`` can take in 3 values: `rsa`, `ecdsa` or `rsa+ecdsa`.
|
||||
This variable allows the Makefile to include the corresponding sources in
|
||||
the build for the various algorithms. Setting the variable to `rsa+ecdsa`
|
||||
enables support for both rsa and ecdsa algorithms in the mbedTLS library.
|
||||
|
||||
- ``TF_MBEDTLS_KEY_SIZE`` sets the supported RSA key size for TFA. Valid values
|
||||
include 1024, 2048, 3072 and 4096.
|
||||
|
||||
- ``TF_MBEDTLS_USE_AES_GCM`` enables the authenticated decryption support based
|
||||
on AES-GCM algorithm. Valid values are 0 and 1.
|
||||
|
||||
.. note::
|
||||
If code size is a concern, the build option ``MBEDTLS_SHA256_SMALLER`` can
|
||||
be defined in the platform Makefile. It will make mbed TLS use an
|
||||
implementation of SHA-256 with smaller memory footprint (~1.5 KB less) but
|
||||
slower (~30%).
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _TBBR-Client specification: https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
|
||||
800
arm-trusted-firmware/docs/design/cpu-specific-build-macros.rst
Normal file
800
arm-trusted-firmware/docs/design/cpu-specific-build-macros.rst
Normal file
@@ -0,0 +1,800 @@
|
||||
Arm CPU Specific Build Macros
|
||||
=============================
|
||||
|
||||
This document describes the various build options present in the CPU specific
|
||||
operations framework to enable errata workarounds and to enable optimizations
|
||||
for a specific CPU on a platform.
|
||||
|
||||
Security Vulnerability Workarounds
|
||||
----------------------------------
|
||||
|
||||
TF-A exports a series of build flags which control which security
|
||||
vulnerability workarounds should be applied at runtime.
|
||||
|
||||
- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
|
||||
`CVE-2017-5715`_. This flag can be set to 0 by the platform if none
|
||||
of the PEs in the system need the workaround. Setting this flag to 0 provides
|
||||
no performance benefit for non-affected platforms, it just helps to comply
|
||||
with the recommendation in the spec regarding workaround discovery.
|
||||
Defaults to 1.
|
||||
|
||||
- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
|
||||
`CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
|
||||
the default value of 1 even on platforms that are unaffected by
|
||||
CVE-2018-3639, in order to comply with the recommendation in the spec
|
||||
regarding workaround discovery.
|
||||
|
||||
- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
|
||||
`CVE-2018-3639`_. This build option should be set to 1 if the target
|
||||
platform contains at least 1 CPU that requires dynamic mitigation.
|
||||
Defaults to 0.
|
||||
|
||||
- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_.
|
||||
This build option should be set to 1 if the target platform contains at
|
||||
least 1 CPU that requires this mitigation. Defaults to 1.
|
||||
|
||||
.. _arm_cpu_macros_errata_workarounds:
|
||||
|
||||
CPU Errata Workarounds
|
||||
----------------------
|
||||
|
||||
TF-A exports a series of build flags which control the errata workarounds that
|
||||
are applied to each CPU by the reset handler. The errata details can be found
|
||||
in the CPU specific errata documents published by Arm:
|
||||
|
||||
- `Cortex-A53 MPCore Software Developers Errata Notice`_
|
||||
- `Cortex-A57 MPCore Software Developers Errata Notice`_
|
||||
- `Cortex-A72 MPCore Software Developers Errata Notice`_
|
||||
|
||||
The errata workarounds are implemented for a particular revision or a set of
|
||||
processor revisions. This is checked by the reset handler at runtime. Each
|
||||
errata workaround is identified by its ``ID`` as specified in the processor's
|
||||
errata notice document. The format of the define used to enable/disable the
|
||||
errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
|
||||
is for example ``A57`` for the ``Cortex_A57`` CPU.
|
||||
|
||||
Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to
|
||||
write errata workaround functions.
|
||||
|
||||
All workarounds are disabled by default. The platform is responsible for
|
||||
enabling these workarounds according to its requirement by defining the
|
||||
errata workaround build flags in the platform specific makefile. In case
|
||||
these workarounds are enabled for the wrong CPU revision then the errata
|
||||
workaround is not applied. In the DEBUG build, this is indicated by
|
||||
printing a warning to the crash console.
|
||||
|
||||
In the current implementation, a platform which has more than 1 variant
|
||||
with different revisions of a processor has no runtime mechanism available
|
||||
for it to specify which errata workarounds should be enabled or not.
|
||||
|
||||
The value of the build flags is 0 by default, that is, disabled. A value of 1
|
||||
will enable it.
|
||||
|
||||
For Cortex-A9, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
|
||||
CPU. This needs to be enabled for all revisions of the CPU.
|
||||
|
||||
For Cortex-A15, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
|
||||
CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
|
||||
CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
|
||||
|
||||
For Cortex-A17, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
|
||||
CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
|
||||
|
||||
- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
|
||||
CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
|
||||
|
||||
For Cortex-A35, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
|
||||
CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
|
||||
|
||||
For Cortex-A53, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
|
||||
CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
|
||||
|
||||
- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
|
||||
CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
|
||||
|
||||
- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
|
||||
CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
|
||||
|
||||
- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
|
||||
CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
|
||||
|
||||
- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
|
||||
link time to Cortex-A53 CPU. This needs to be enabled for some variants of
|
||||
revision <= r0p4. This workaround can lead the linker to create ``*.stub``
|
||||
sections.
|
||||
|
||||
- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
|
||||
CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
|
||||
r0p4 and onwards, this errata is enabled by default in hardware.
|
||||
|
||||
- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
|
||||
to Cortex-A53 CPU. This needs to be enabled for some variants of revision
|
||||
<= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
|
||||
which are 4kB aligned.
|
||||
|
||||
- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
|
||||
CPUs. Though the erratum is present in every revision of the CPU,
|
||||
this workaround is only applied to CPUs from r0p3 onwards, which feature
|
||||
a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
|
||||
Earlier revisions of the CPU have other errata which require the same
|
||||
workaround in software, so they should be covered anyway.
|
||||
|
||||
- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all
|
||||
revisions of Cortex-A53 CPU.
|
||||
|
||||
For Cortex-A55, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
|
||||
CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
|
||||
CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
|
||||
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all
|
||||
revisions of Cortex-A55 CPU.
|
||||
|
||||
For Cortex-A57, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
|
||||
CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
|
||||
|
||||
- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all
|
||||
revisions of Cortex-A57 CPU.
|
||||
|
||||
For Cortex-A72, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
|
||||
CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
|
||||
|
||||
- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all
|
||||
revisions of Cortex-A72 CPU.
|
||||
|
||||
For Cortex-A73, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
|
||||
CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
|
||||
|
||||
For Cortex-A75, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
|
||||
CPU. This needs to be enabled only for revision r0p0 of the CPU.
|
||||
|
||||
For Cortex-A76, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
|
||||
revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
|
||||
limitation of errata framework this errata is applied to all revisions
|
||||
of Cortex-A76 CPU.
|
||||
|
||||
- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76
|
||||
CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
|
||||
still open.
|
||||
|
||||
For Cortex-A77, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
|
||||
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
|
||||
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
|
||||
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
|
||||
CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
|
||||
|
||||
- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77
|
||||
CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
|
||||
|
||||
- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
|
||||
CPU. This needs to be enabled for revisions <= r1p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77
|
||||
CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
|
||||
|
||||
For Cortex-A78, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
|
||||
CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
|
||||
|
||||
- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
|
||||
|
||||
- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78
|
||||
CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
|
||||
issue but there is no workaround for that revision.
|
||||
|
||||
- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
|
||||
CPU. This needs to be enabled for revisions r0p0 and r1p0.
|
||||
|
||||
- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
|
||||
CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
|
||||
|
||||
- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
|
||||
is still open.
|
||||
|
||||
- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78
|
||||
CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
|
||||
is present in r0p0 but there is no workaround. It is still open.
|
||||
|
||||
- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
|
||||
it is still open.
|
||||
|
||||
- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
|
||||
it is still open.
|
||||
|
||||
For Cortex-A78 AE, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
|
||||
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
|
||||
This erratum is still open.
|
||||
|
||||
- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to
|
||||
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
|
||||
erratum is still open.
|
||||
|
||||
- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to
|
||||
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
|
||||
erratum is still open.
|
||||
|
||||
- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to
|
||||
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
|
||||
erratum is still open.
|
||||
|
||||
- ``ERRATA_A78_AE_2466780`` : This applies errata 2466780 workaround to
|
||||
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
|
||||
This erratum is still open.
|
||||
|
||||
- ``ERRATA_A78_AE_2743093``: This applies errata 2743093 workaround to Cortex-A78 AE
|
||||
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
|
||||
|
||||
- ``ERRATA_A78_AE_2743229`` : This applies errata 2743229 workaround to
|
||||
Cortex-A78 AE CPU. This needs to be enabled for revisions <= r0p2.
|
||||
|
||||
- ``ERRATA_A78_AE_2855379`` : This applies errata 2855379 workaround to
|
||||
Cortex-A78 AE CPU. This needs to be enabled for revisions <= r0p1. This
|
||||
erratum is still open.
|
||||
|
||||
For Cortex-A78C, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to
|
||||
Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
|
||||
it is still open.
|
||||
|
||||
- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to
|
||||
Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
|
||||
it is still open.
|
||||
|
||||
- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to
|
||||
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
|
||||
erratum is still open.
|
||||
|
||||
- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to
|
||||
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
|
||||
erratum is still open.
|
||||
|
||||
- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to
|
||||
Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
|
||||
This erratum is still open.
|
||||
|
||||
- ``ERRATA_A78C_2743228`` : This applies errata 2743228 workaround to
|
||||
Cortex-A78C CPU. This needs to be enabled for revisions <= r0p2.
|
||||
|
||||
- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to
|
||||
Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
|
||||
This erratum is still open.
|
||||
|
||||
- ``ERRATA_A78C_2855381``: This applies errata 2855381 workaround to
|
||||
Cortex-A78C CPU. This needs to be enabled for revision <=r0p1 of the CPU.
|
||||
|
||||
For Cortex-X1 CPU, the following errata build flags are defined:
|
||||
|
||||
- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1
|
||||
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
|
||||
|
||||
- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1
|
||||
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
|
||||
|
||||
- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1
|
||||
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
|
||||
|
||||
For Neoverse N1, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
|
||||
|
||||
- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
|
||||
revisions r0p0, r1p0, and r2p0 there is no workaround.
|
||||
|
||||
- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1
|
||||
CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
|
||||
still open.
|
||||
|
||||
For Neoverse V1, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
|
||||
r1p0.
|
||||
|
||||
- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
|
||||
in r1p1.
|
||||
|
||||
- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
|
||||
in r1p1.
|
||||
|
||||
- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
|
||||
in r1p1.
|
||||
|
||||
- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
|
||||
|
||||
- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
|
||||
CPU.
|
||||
|
||||
- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
|
||||
issue is present in r0p0 as well but there is no workaround for that
|
||||
revision. It is still open.
|
||||
|
||||
- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
|
||||
CPU. It is still open.
|
||||
|
||||
- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
|
||||
It is still open.
|
||||
|
||||
- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
|
||||
issue is present in r0p0 as well but there is no workaround for that
|
||||
revision. It is still open.
|
||||
|
||||
- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
|
||||
|
||||
- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
|
||||
It is still open.
|
||||
|
||||
- ``ERRATA_V2_2394277`` : This applies errata 2394277 workaround to Neoverse-V2
|
||||
CPU. This needs to be enabled for revisions < r0p1.
|
||||
|
||||
- ``ERRATA_V2_2644884`` : This applies errata 2644884 workaround to Neoverse-V2
|
||||
CPU. This needs to be enabled for revisions < r0p2.
|
||||
|
||||
- ``ERRATA_V2_2719105`` : This applies errata 2719105 workaround to Neoverse-V2
|
||||
CPU. This needs to be enabled for revisions < r0p2. Fixed in r0p2.
|
||||
|
||||
- ``ERRATA_V2_2743011`` : This applies errata 2743011 workaround to Neoverse-V2
|
||||
CPU. This needs to be enabled for revisions < r0p2.
|
||||
|
||||
- ``ERRATA_V2_2743088``: This applies errata 2743088 workaround to Neoverse-V2
|
||||
CPU. This needs to be enabled for revision <=r0p1 of the CPU.
|
||||
|
||||
- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2
|
||||
CPU. This needs to be enabled for revision <=r0p2 of the CPU.
|
||||
|
||||
For Cortex-A710, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
|
||||
r2p0 of the CPU. It is still open.
|
||||
|
||||
- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
|
||||
r2p0 of the CPU. It is still open.
|
||||
|
||||
- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
|
||||
and is still open.
|
||||
|
||||
- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
|
||||
is still open.
|
||||
|
||||
- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU
|
||||
and is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
For Neoverse N2, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
|
||||
|
||||
- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
|
||||
r0p1.
|
||||
|
||||
- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
|
||||
r0p1.
|
||||
|
||||
- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
|
||||
r0p1.
|
||||
|
||||
For Cortex-X2, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
|
||||
it is still open.
|
||||
|
||||
- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
|
||||
CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
|
||||
it is still open.
|
||||
|
||||
- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
|
||||
CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
|
||||
|
||||
- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to
|
||||
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
|
||||
r2p0 of the CPU, it is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to
|
||||
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
|
||||
r2p0 of the CPU, it is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to
|
||||
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
|
||||
r2p0 of the CPU, it is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to
|
||||
Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU,
|
||||
it is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to
|
||||
Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
For Cortex-X3, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to
|
||||
Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
|
||||
of the CPU, it is fixed in r1p1.
|
||||
|
||||
For Cortex-A510, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
|
||||
Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is
|
||||
fixed in r0p1.
|
||||
|
||||
- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to
|
||||
Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
|
||||
r0p2, r0p3 and r1p0, it is fixed in r1p1.
|
||||
|
||||
- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to
|
||||
Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
|
||||
r0p2, it is fixed in r0p3.
|
||||
|
||||
- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to
|
||||
Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
|
||||
in r0p3. The issue is also present in r0p0 and r0p1 but there is no
|
||||
workaround for those revisions.
|
||||
|
||||
- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to
|
||||
Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
|
||||
r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
|
||||
ENABLE_MPMM=1.
|
||||
|
||||
- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to
|
||||
Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
|
||||
r0p3 and r1p0, it is fixed in r1p1.
|
||||
|
||||
- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to
|
||||
Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
|
||||
r0p3 and r1p0, it is fixed in r1p1.
|
||||
|
||||
- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to
|
||||
Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
|
||||
r0p3, r1p0 and r1p1. It is fixed in r1p2.
|
||||
|
||||
- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to
|
||||
Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
|
||||
r0p3, r1p0, r1p1, and is fixed in r1p2.
|
||||
|
||||
- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to
|
||||
Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
|
||||
r0p3, r1p0, r1p1. It is fixed in r1p2.
|
||||
|
||||
DSU Errata Workarounds
|
||||
----------------------
|
||||
|
||||
Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
|
||||
Shared Unit) errata. The DSU errata details can be found in the respective Arm
|
||||
documentation:
|
||||
|
||||
- `Arm DSU Software Developers Errata Notice`_.
|
||||
|
||||
Each erratum is identified by an ``ID``, as defined in the DSU errata notice
|
||||
document. Thus, the build flags which enable/disable the errata workarounds
|
||||
have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
|
||||
of DSU errata workarounds are similar to `CPU errata workarounds`_.
|
||||
|
||||
For DSU errata, the following build flags are defined:
|
||||
|
||||
- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
|
||||
affected DSU configurations. This errata applies only for those DSUs that
|
||||
revision is r0p0 (on r0p1 it is fixed). However, please note that this
|
||||
workaround results in increased DSU power consumption on idle.
|
||||
|
||||
- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
|
||||
affected DSU configurations. This errata applies only for those DSUs that
|
||||
contain the ACP interface **and** the DSU revision is older than r2p0 (on
|
||||
r2p0 it is fixed). However, please note that this workaround results in
|
||||
increased DSU power consumption on idle.
|
||||
|
||||
- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the
|
||||
affected DSU configurations. This errata applies for those DSUs with
|
||||
revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However,
|
||||
please note that this workaround results in increased DSU power consumption
|
||||
on idle.
|
||||
|
||||
CPU Specific optimizations
|
||||
--------------------------
|
||||
|
||||
This section describes some of the optimizations allowed by the CPU micro
|
||||
architecture that can be enabled by the platform as desired.
|
||||
|
||||
- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
|
||||
Cortex-A57 cluster power down sequence by not flushing the Level 1 data
|
||||
cache. The L1 data cache and the L2 unified cache are inclusive. A flush
|
||||
of the L2 by set/way flushes any dirty lines from the L1 as well. This
|
||||
is a known safe deviation from the Cortex-A57 TRM defined power down
|
||||
sequence. Each Cortex-A57 based platform must make its own decision on
|
||||
whether to use the optimization.
|
||||
|
||||
- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
|
||||
hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
|
||||
in a way most programmers expect, and will most probably result in a
|
||||
significant speed degradation to any code that employs them. The Armv8-A
|
||||
architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
|
||||
the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
|
||||
flag enforces this behaviour. This needs to be enabled only for revisions
|
||||
<= r0p3 of the CPU and is enabled by default.
|
||||
|
||||
- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
|
||||
``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
|
||||
enabled only for revisions <= r1p2 of the CPU and is enabled by default,
|
||||
as recommended in section "4.7 Non-Temporal Loads/Stores" of the
|
||||
`Cortex-A57 Software Optimization Guide`_.
|
||||
|
||||
- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
|
||||
streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
|
||||
this bit only if their memory system meets the requirement that cache
|
||||
line fill requests from the Cortex-A57 processor are atomic. Each
|
||||
Cortex-A57 based platform must make its own decision on whether to use
|
||||
the optimization. This flag is disabled by default.
|
||||
|
||||
- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
|
||||
level cache(LLC) is present in the system, and that the DataSource field
|
||||
on the master CHI interface indicates when data is returned from the LLC.
|
||||
This is used to control how the LL_CACHE* PMU events count.
|
||||
Default value is 0 (Disabled).
|
||||
|
||||
GIC Errata Workarounds
|
||||
----------------------
|
||||
- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374
|
||||
workaround for the affected GIC600 and GIC600-AE implementations. It applies
|
||||
to implementations of GIC600 and GIC600-AE with revisions less than or equal
|
||||
to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600,
|
||||
then this flag is enabled; otherwise, it is 0 (Disabled).
|
||||
|
||||
- ``GIC600AE_ERRATA_WA_1568841``: This flag applies errata 1568841 workaround
|
||||
for the affected GIC600-AE implementations. It applies to implementations of
|
||||
GIC600-AE with revisions less than or equal to r0p2. If the platform sets
|
||||
GICV3_SUPPORT_GIC600, then this flag is enabled; otherwise, it is 0
|
||||
(Disabled).
|
||||
|
||||
- ''GIC600AE_ERRATA_WA_2079287'': This flag applies errata 2079287 workaround
|
||||
for the affected GIC600-AE implementations. It applies to implementations of
|
||||
GIC600-AE with revisions less than or equal to r0p2. If the platform sets
|
||||
GICV3_SUPPORT_GIC600, then this flag is enabled; otherwise, it is 0
|
||||
(Disabled).
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
|
||||
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
|
||||
.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960
|
||||
.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
|
||||
.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
|
||||
.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
|
||||
.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
|
||||
.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html
|
||||
2766
arm-trusted-firmware/docs/design/firmware-design.rst
Normal file
2766
arm-trusted-firmware/docs/design/firmware-design.rst
Normal file
File diff suppressed because it is too large
Load Diff
20
arm-trusted-firmware/docs/design/index.rst
Normal file
20
arm-trusted-firmware/docs/design/index.rst
Normal file
@@ -0,0 +1,20 @@
|
||||
System Design
|
||||
=============
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Contents
|
||||
|
||||
alt-boot-flows
|
||||
auth-framework
|
||||
cpu-specific-build-macros
|
||||
firmware-design
|
||||
interrupt-framework-design
|
||||
psci-pd-tree
|
||||
reset-design
|
||||
trusted-board-boot
|
||||
trusted-board-boot-build
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019, Arm Limited. All rights reserved.*
|
||||
1021
arm-trusted-firmware/docs/design/interrupt-framework-design.rst
Normal file
1021
arm-trusted-firmware/docs/design/interrupt-framework-design.rst
Normal file
File diff suppressed because it is too large
Load Diff
304
arm-trusted-firmware/docs/design/psci-pd-tree.rst
Normal file
304
arm-trusted-firmware/docs/design/psci-pd-tree.rst
Normal file
@@ -0,0 +1,304 @@
|
||||
PSCI Power Domain Tree Structure
|
||||
================================
|
||||
|
||||
Requirements
|
||||
------------
|
||||
|
||||
#. A platform must export the ``plat_get_aff_count()`` and
|
||||
``plat_get_aff_state()`` APIs to enable the generic PSCI code to
|
||||
populate a tree that describes the hierarchy of power domains in the
|
||||
system. This approach is inflexible because a change to the topology
|
||||
requires a change in the code.
|
||||
|
||||
It would be much simpler for the platform to describe its power domain tree
|
||||
in a data structure.
|
||||
|
||||
#. The generic PSCI code generates MPIDRs in order to populate the power domain
|
||||
tree. It also uses an MPIDR to find a node in the tree. The assumption that
|
||||
a platform will use exactly the same MPIDRs as generated by the generic PSCI
|
||||
code is not scalable. The use of an MPIDR also restricts the number of
|
||||
levels in the power domain tree to four.
|
||||
|
||||
Therefore, there is a need to decouple allocation of MPIDRs from the
|
||||
mechanism used to populate the power domain topology tree.
|
||||
|
||||
#. The current arrangement of the power domain tree requires a binary search
|
||||
over the sibling nodes at a particular level to find a specified power
|
||||
domain node. During a power management operation, the tree is traversed from
|
||||
a 'start' to an 'end' power level. The binary search is required to find the
|
||||
node at each level. The natural way to perform this traversal is to
|
||||
start from a leaf node and follow the parent node pointer to reach the end
|
||||
level.
|
||||
|
||||
Therefore, there is a need to define data structures that implement the tree in
|
||||
a way which facilitates such a traversal.
|
||||
|
||||
#. The attributes of a core power domain differ from the attributes of power
|
||||
domains at higher levels. For example, only a core power domain can be identified
|
||||
using an MPIDR. There is no requirement to perform state coordination while
|
||||
performing a power management operation on the core power domain.
|
||||
|
||||
Therefore, there is a need to implement the tree in a way which facilitates this
|
||||
distinction between a leaf and non-leaf node and any associated
|
||||
optimizations.
|
||||
|
||||
--------------
|
||||
|
||||
Design
|
||||
------
|
||||
|
||||
Describing a power domain tree
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
To fulfill requirement 1., the existing platform APIs
|
||||
``plat_get_aff_count()`` and ``plat_get_aff_state()`` have been
|
||||
removed. A platform must define an array of unsigned chars such that:
|
||||
|
||||
#. The first entry in the array specifies the number of power domains at the
|
||||
highest power level implemented in the platform. This caters for platforms
|
||||
where the power domain tree does not have a single root node, for example,
|
||||
the FVP has two cluster power domains at the highest level (1).
|
||||
|
||||
#. Each subsequent entry corresponds to a power domain and contains the number
|
||||
of power domains that are its direct children.
|
||||
|
||||
#. The size of the array minus the first entry will be equal to the number of
|
||||
non-leaf power domains.
|
||||
|
||||
#. The value in each entry in the array is used to find the number of entries
|
||||
to consider at the next level. The sum of the values (number of children) of
|
||||
all the entries at a level specifies the number of entries in the array for
|
||||
the next level.
|
||||
|
||||
The following example power domain topology tree will be used to describe the
|
||||
above text further. The leaf and non-leaf nodes in this tree have been numbered
|
||||
separately.
|
||||
|
||||
::
|
||||
|
||||
+-+
|
||||
|0|
|
||||
+-+
|
||||
/ \
|
||||
/ \
|
||||
/ \
|
||||
/ \
|
||||
/ \
|
||||
/ \
|
||||
/ \
|
||||
/ \
|
||||
/ \
|
||||
/ \
|
||||
+-+ +-+
|
||||
|1| |2|
|
||||
+-+ +-+
|
||||
/ \ / \
|
||||
/ \ / \
|
||||
/ \ / \
|
||||
/ \ / \
|
||||
+-+ +-+ +-+ +-+
|
||||
|3| |4| |5| |6|
|
||||
+-+ +-+ +-+ +-+
|
||||
+---+-----+ +----+----| +----+----+ +----+-----+-----+
|
||||
| | | | | | | | | | | | |
|
||||
| | | | | | | | | | | | |
|
||||
v v v v v v v v v v v v v
|
||||
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+
|
||||
|0| |1| |2| |3| |4| |5| |6| |7| |8| |9| |10| |11| |12|
|
||||
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+
|
||||
|
||||
This tree is defined by the platform as the array described above as follows:
|
||||
|
||||
.. code:: c
|
||||
|
||||
#define PLAT_NUM_POWER_DOMAINS 20
|
||||
#define PLATFORM_CORE_COUNT 13
|
||||
#define PSCI_NUM_NON_CPU_PWR_DOMAINS \
|
||||
(PLAT_NUM_POWER_DOMAINS - PLATFORM_CORE_COUNT)
|
||||
|
||||
unsigned char plat_power_domain_tree_desc[] = { 1, 2, 2, 2, 3, 3, 3, 4};
|
||||
|
||||
Removing assumptions about MPIDRs used in a platform
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
To fulfill requirement 2., it is assumed that the platform assigns a
|
||||
unique number (core index) between ``0`` and ``PLAT_CORE_COUNT - 1`` to each core
|
||||
power domain. MPIDRs could be allocated in any manner and will not be used to
|
||||
populate the tree.
|
||||
|
||||
``plat_core_pos_by_mpidr(mpidr)`` will return the core index for the core
|
||||
corresponding to the MPIDR. It will return an error (-1) if an MPIDR is passed
|
||||
which is not allocated or corresponds to an absent core. The semantics of this
|
||||
platform API have changed since it is required to validate the passed MPIDR. It
|
||||
has been made a mandatory API as a result.
|
||||
|
||||
Another mandatory API, ``plat_my_core_pos()`` has been added to return the core
|
||||
index for the calling core. This API provides a more lightweight mechanism to get
|
||||
the index since there is no need to validate the MPIDR of the calling core.
|
||||
|
||||
The platform should assign the core indices (as illustrated in the diagram above)
|
||||
such that, if the core nodes are numbered from left to right, then the index
|
||||
for a core domain will be the same as the index returned by
|
||||
``plat_core_pos_by_mpidr()`` or ``plat_my_core_pos()`` for that core. This
|
||||
relationship allows the core nodes to be allocated in a separate array
|
||||
(requirement 4.) during ``psci_setup()`` in such an order that the index of the
|
||||
core in the array is the same as the return value from these APIs.
|
||||
|
||||
Dealing with holes in MPIDR allocation
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
For platforms where the number of allocated MPIDRs is equal to the number of
|
||||
core power domains, for example, Juno and FVPs, the logic to convert an MPIDR to
|
||||
a core index should remain unchanged. Both Juno and FVP use a simple collision
|
||||
proof hash function to do this.
|
||||
|
||||
It is possible that on some platforms, the allocation of MPIDRs is not
|
||||
contiguous or certain cores have been disabled. This essentially means that the
|
||||
MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs
|
||||
used by the platform is not equal to the number of core power domains.
|
||||
|
||||
The platform could adopt one of the following approaches to deal with this
|
||||
scenario:
|
||||
|
||||
#. Implement more complex logic to convert a valid MPIDR to a core index while
|
||||
maintaining the relationship described earlier. This means that the power
|
||||
domain tree descriptor will not describe any core power domains which are
|
||||
disabled or absent. Entries will not be allocated in the tree for these
|
||||
domains.
|
||||
|
||||
#. Treat unallocated MPIDRs and disabled cores as absent but still describe them
|
||||
in the power domain descriptor, that is, the number of core nodes described
|
||||
is equal to the size of the range of MPIDRs allocated. This approach will
|
||||
lead to memory wastage since entries will be allocated in the tree but will
|
||||
allow use of a simpler logic to convert an MPIDR to a core index.
|
||||
|
||||
Traversing through and distinguishing between core and non-core power domains
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
To fulfill requirement 3 and 4, separate data structures have been defined
|
||||
to represent leaf and non-leaf power domain nodes in the tree.
|
||||
|
||||
.. code:: c
|
||||
|
||||
/*******************************************************************************
|
||||
* The following two data structures implement the power domain tree. The tree
|
||||
* is used to track the state of all the nodes i.e. power domain instances
|
||||
* described by the platform. The tree consists of nodes that describe CPU power
|
||||
* domains i.e. leaf nodes and all other power domains which are parents of a
|
||||
* CPU power domain i.e. non-leaf nodes.
|
||||
******************************************************************************/
|
||||
typedef struct non_cpu_pwr_domain_node {
|
||||
/*
|
||||
* Index of the first CPU power domain node level 0 which has this node
|
||||
* as its parent.
|
||||
*/
|
||||
unsigned int cpu_start_idx;
|
||||
|
||||
/*
|
||||
* Number of CPU power domains which are siblings of the domain indexed
|
||||
* by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
|
||||
* -> cpu_start_idx + ncpus' have this node as their parent.
|
||||
*/
|
||||
unsigned int ncpus;
|
||||
|
||||
/* Index of the parent power domain node */
|
||||
unsigned int parent_node;
|
||||
|
||||
-----
|
||||
} non_cpu_pd_node_t;
|
||||
|
||||
typedef struct cpu_pwr_domain_node {
|
||||
u_register_t mpidr;
|
||||
|
||||
/* Index of the parent power domain node */
|
||||
unsigned int parent_node;
|
||||
|
||||
-----
|
||||
} cpu_pd_node_t;
|
||||
|
||||
The power domain tree is implemented as a combination of the following data
|
||||
structures.
|
||||
|
||||
.. code:: c
|
||||
|
||||
non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
|
||||
cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
|
||||
|
||||
Populating the power domain tree
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The ``populate_power_domain_tree()`` function in ``psci_setup.c`` implements the
|
||||
algorithm to parse the power domain descriptor exported by the platform to
|
||||
populate the two arrays. It is essentially a breadth-first-search. The nodes for
|
||||
each level starting from the root are laid out one after another in the
|
||||
``psci_non_cpu_pd_nodes`` and ``psci_cpu_pd_nodes`` arrays as follows:
|
||||
|
||||
::
|
||||
|
||||
psci_non_cpu_pd_nodes -> [[Level 3 nodes][Level 2 nodes][Level 1 nodes]]
|
||||
psci_cpu_pd_nodes -> [Level 0 nodes]
|
||||
|
||||
For the example power domain tree illustrated above, the ``psci_cpu_pd_nodes``
|
||||
will be populated as follows. The value in each entry is the index of the parent
|
||||
node. Other fields have been ignored for simplicity.
|
||||
|
||||
::
|
||||
|
||||
+-------------+ ^
|
||||
CPU0 | 3 | |
|
||||
+-------------+ |
|
||||
CPU1 | 3 | |
|
||||
+-------------+ |
|
||||
CPU2 | 3 | |
|
||||
+-------------+ |
|
||||
CPU3 | 4 | |
|
||||
+-------------+ |
|
||||
CPU4 | 4 | |
|
||||
+-------------+ |
|
||||
CPU5 | 4 | | PLATFORM_CORE_COUNT
|
||||
+-------------+ |
|
||||
CPU6 | 5 | |
|
||||
+-------------+ |
|
||||
CPU7 | 5 | |
|
||||
+-------------+ |
|
||||
CPU8 | 5 | |
|
||||
+-------------+ |
|
||||
CPU9 | 6 | |
|
||||
+-------------+ |
|
||||
CPU10 | 6 | |
|
||||
+-------------+ |
|
||||
CPU11 | 6 | |
|
||||
+-------------+ |
|
||||
CPU12 | 6 | v
|
||||
+-------------+
|
||||
|
||||
The ``psci_non_cpu_pd_nodes`` array will be populated as follows. The value in
|
||||
each entry is the index of the parent node.
|
||||
|
||||
::
|
||||
|
||||
+-------------+ ^
|
||||
PD0 | -1 | |
|
||||
+-------------+ |
|
||||
PD1 | 0 | |
|
||||
+-------------+ |
|
||||
PD2 | 0 | |
|
||||
+-------------+ |
|
||||
PD3 | 1 | | PLAT_NUM_POWER_DOMAINS -
|
||||
+-------------+ | PLATFORM_CORE_COUNT
|
||||
PD4 | 1 | |
|
||||
+-------------+ |
|
||||
PD5 | 2 | |
|
||||
+-------------+ |
|
||||
PD6 | 2 | |
|
||||
+-------------+ v
|
||||
|
||||
Each core can find its node in the ``psci_cpu_pd_nodes`` array using the
|
||||
``plat_my_core_pos()`` function. When a core is turned on, the normal world
|
||||
provides an MPIDR. The ``plat_core_pos_by_mpidr()`` function is used to validate
|
||||
the MPIDR before using it to find the corresponding core node. The non-core power
|
||||
domain nodes do not need to be identified.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.*
|
||||
168
arm-trusted-firmware/docs/design/reset-design.rst
Normal file
168
arm-trusted-firmware/docs/design/reset-design.rst
Normal file
@@ -0,0 +1,168 @@
|
||||
CPU Reset
|
||||
=========
|
||||
|
||||
This document describes the high-level design of the framework to handle CPU
|
||||
resets in Trusted Firmware-A (TF-A). It also describes how the platform
|
||||
integrator can tailor this code to the system configuration to some extent,
|
||||
resulting in a simplified and more optimised boot flow.
|
||||
|
||||
This document should be used in conjunction with the :ref:`Firmware Design`
|
||||
document which provides greater implementation details around the reset code,
|
||||
specifically for the cold boot path.
|
||||
|
||||
General reset code flow
|
||||
-----------------------
|
||||
|
||||
The TF-A reset code is implemented in BL1 by default. The following high-level
|
||||
diagram illustrates this:
|
||||
|
||||
|Default reset code flow|
|
||||
|
||||
This diagram shows the default, unoptimised reset flow. Depending on the system
|
||||
configuration, some of these steps might be unnecessary. The following sections
|
||||
guide the platform integrator by indicating which build options exclude which
|
||||
steps, depending on the capability of the platform.
|
||||
|
||||
.. note::
|
||||
If BL31 is used as the TF-A entry point instead of BL1, the diagram
|
||||
above is still relevant, as all these operations will occur in BL31 in
|
||||
this case. Please refer to section 6 "Using BL31 entrypoint as the reset
|
||||
address" for more information.
|
||||
|
||||
Programmable CPU reset address
|
||||
------------------------------
|
||||
|
||||
By default, TF-A assumes that the CPU reset address is not programmable.
|
||||
Therefore, all CPUs start at the same address (typically address 0) whenever
|
||||
they reset. Further logic is then required to identify whether it is a cold or
|
||||
warm boot to direct CPUs to the right execution path.
|
||||
|
||||
If the reset vector address (reflected in the reset vector base address register
|
||||
``RVBAR_EL3``) is programmable then it is possible to make each CPU start directly
|
||||
at the right address, both on a cold and warm reset. Therefore, the boot type
|
||||
detection can be skipped, resulting in the following boot flow:
|
||||
|
||||
|Reset code flow with programmable reset address|
|
||||
|
||||
To enable this boot flow, compile TF-A with ``PROGRAMMABLE_RESET_ADDRESS=1``.
|
||||
This option only affects the TF-A reset image, which is BL1 by default or BL31 if
|
||||
``RESET_TO_BL31=1``.
|
||||
|
||||
On both the FVP and Juno platforms, the reset vector address is not programmable
|
||||
so both ports use ``PROGRAMMABLE_RESET_ADDRESS=0``.
|
||||
|
||||
Cold boot on a single CPU
|
||||
-------------------------
|
||||
|
||||
By default, TF-A assumes that several CPUs may be released out of reset.
|
||||
Therefore, the cold boot code has to arbitrate access to hardware resources
|
||||
shared amongst CPUs. This is done by nominating one of the CPUs as the primary,
|
||||
which is responsible for initialising shared hardware and coordinating the boot
|
||||
flow with the other CPUs.
|
||||
|
||||
If the platform guarantees that only a single CPU will ever be brought up then
|
||||
no arbitration is required. The notion of primary/secondary CPU itself no longer
|
||||
applies. This results in the following boot flow:
|
||||
|
||||
|Reset code flow with single CPU released out of reset|
|
||||
|
||||
To enable this boot flow, compile TF-A with ``COLD_BOOT_SINGLE_CPU=1``. This
|
||||
option only affects the TF-A reset image, which is BL1 by default or BL31 if
|
||||
``RESET_TO_BL31=1``.
|
||||
|
||||
On both the FVP and Juno platforms, although only one core is powered up by
|
||||
default, there are platform-specific ways to release any number of cores out of
|
||||
reset. Therefore, both platform ports use ``COLD_BOOT_SINGLE_CPU=0``.
|
||||
|
||||
Programmable CPU reset address, Cold boot on a single CPU
|
||||
---------------------------------------------------------
|
||||
|
||||
It is obviously possible to combine both optimisations on platforms that have
|
||||
a programmable CPU reset address and which release a single CPU out of reset.
|
||||
This results in the following boot flow:
|
||||
|
||||
|
||||
|Reset code flow with programmable reset address and single CPU released out of reset|
|
||||
|
||||
To enable this boot flow, compile TF-A with both ``COLD_BOOT_SINGLE_CPU=1``
|
||||
and ``PROGRAMMABLE_RESET_ADDRESS=1``. These options only affect the TF-A reset
|
||||
image, which is BL1 by default or BL31 if ``RESET_TO_BL31=1``.
|
||||
|
||||
Using BL31 entrypoint as the reset address
|
||||
------------------------------------------
|
||||
|
||||
On some platforms the runtime firmware (BL3x images) for the application
|
||||
processors are loaded by some firmware running on a secure system processor
|
||||
on the SoC, rather than by BL1 and BL2 running on the primary application
|
||||
processor. For this type of SoC it is desirable for the application processor
|
||||
to always reset to BL31 which eliminates the need for BL1 and BL2.
|
||||
|
||||
TF-A provides a build-time option ``RESET_TO_BL31`` that includes some additional
|
||||
logic in the BL31 entry point to support this use case.
|
||||
|
||||
In this configuration, the platform's Trusted Boot Firmware must ensure that
|
||||
BL31 is loaded to its runtime address, which must match the CPU's ``RVBAR_EL3``
|
||||
reset vector base address, before the application processor is powered on.
|
||||
Additionally, platform software is responsible for loading the other BL3x images
|
||||
required and providing entry point information for them to BL31. Loading these
|
||||
images might be done by the Trusted Boot Firmware or by platform code in BL31.
|
||||
|
||||
Although the Arm FVP platform does not support programming the reset base
|
||||
address dynamically at run-time, it is possible to set the initial value of the
|
||||
``RVBAR_EL3`` register at start-up. This feature is provided on the Base FVP
|
||||
only.
|
||||
|
||||
It allows the Arm FVP port to support the ``RESET_TO_BL31`` configuration, in
|
||||
which case the ``bl31.bin`` image must be loaded to its run address in Trusted
|
||||
SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
|
||||
address. See the :ref:`Arm Fixed Virtual Platforms (FVP)` for details of running
|
||||
the FVP models in this way.
|
||||
|
||||
Although technically it would be possible to program the reset base address with
|
||||
the right support in the SCP firmware, this is currently not implemented so the
|
||||
Juno port doesn't support the ``RESET_TO_BL31`` configuration.
|
||||
|
||||
The ``RESET_TO_BL31`` configuration requires some additions and changes in the
|
||||
BL31 functionality:
|
||||
|
||||
Determination of boot path
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
In this configuration, BL31 uses the same reset framework and code as the one
|
||||
described for BL1 above. Therefore, it is affected by the
|
||||
``PROGRAMMABLE_RESET_ADDRESS`` and ``COLD_BOOT_SINGLE_CPU`` build options in the
|
||||
same way.
|
||||
|
||||
In the default, unoptimised BL31 reset flow, on a warm boot a CPU is directed
|
||||
to the PSCI implementation via a platform defined mechanism. On a cold boot,
|
||||
the platform must place any secondary CPUs into a safe state while the primary
|
||||
CPU executes a modified BL31 initialization, as described below.
|
||||
|
||||
Platform initialization
|
||||
~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
In this configuration, when the CPU resets to BL31 there should be no parameters
|
||||
that can be passed in registers by previous boot stages. Instead, the platform
|
||||
code in BL31 needs to know, or be able to determine, the location of the BL32
|
||||
(if required) and BL33 images and provide this information in response to the
|
||||
``bl31_plat_get_next_image_ep_info()`` function.
|
||||
|
||||
.. note::
|
||||
Some platforms that configure ``RESET_TO_BL31`` might still be able to
|
||||
receive parameters in registers depending on their actual boot sequence. On
|
||||
those occasions, and in addition to ``RESET_TO_BL31``, these platforms should
|
||||
set ``RESET_TO_BL31_WITH_PARAMS`` to avoid the input registers from being
|
||||
zeroed before entering BL31.
|
||||
|
||||
Additionally, platform software is responsible for carrying out any security
|
||||
initialisation, for example programming a TrustZone address space controller.
|
||||
This might be done by the Trusted Boot Firmware or by platform code in BL31.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. |Default reset code flow| image:: ../resources/diagrams/default_reset_code.png
|
||||
.. |Reset code flow with programmable reset address| image:: ../resources/diagrams/reset_code_no_boot_type_check.png
|
||||
.. |Reset code flow with single CPU released out of reset| image:: ../resources/diagrams/reset_code_no_cpu_check.png
|
||||
.. |Reset code flow with programmable reset address and single CPU released out of reset| image:: ../resources/diagrams/reset_code_no_checks.png
|
||||
122
arm-trusted-firmware/docs/design/trusted-board-boot-build.rst
Normal file
122
arm-trusted-firmware/docs/design/trusted-board-boot-build.rst
Normal file
@@ -0,0 +1,122 @@
|
||||
Building FIP images with support for Trusted Board Boot
|
||||
=======================================================
|
||||
|
||||
Trusted Board Boot primarily consists of the following two features:
|
||||
|
||||
- Image Authentication, described in :ref:`Trusted Board Boot`, and
|
||||
- Firmware Update, described in :ref:`Firmware Update (FWU)`
|
||||
|
||||
The following steps should be followed to build FIP and (optionally) FWU_FIP
|
||||
images with support for these features:
|
||||
|
||||
#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
|
||||
modules by checking out a recent version of the `mbed TLS Repository`_. It
|
||||
is important to use a version that is compatible with TF-A and fixes any
|
||||
known security vulnerabilities. See `mbed TLS Security Center`_ for more
|
||||
information. See the :ref:`Prerequisites` document for the appropriate
|
||||
version of mbed TLS to use.
|
||||
|
||||
The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
|
||||
source files the modules depend upon.
|
||||
``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
|
||||
options required to build the mbed TLS sources.
|
||||
|
||||
Note that the mbed TLS library is licensed under the Apache version 2.0
|
||||
license. Using mbed TLS source code will affect the licensing of TF-A
|
||||
binaries that are built using this library.
|
||||
|
||||
#. To build the FIP image, ensure the following command line variables are set
|
||||
while invoking ``make`` to build TF-A:
|
||||
|
||||
- ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
|
||||
- ``TRUSTED_BOARD_BOOT=1``
|
||||
- ``GENERATE_COT=1``
|
||||
|
||||
By default, this will use the Chain of Trust described in the TBBR-client
|
||||
document. To select a different one, use the ``COT`` build option.
|
||||
|
||||
If using a custom build of OpenSSL, set the ``OPENSSL_DIR`` variable
|
||||
accordingly so it points at the OpenSSL installation path, as explained in
|
||||
:ref:`Build Options`. In addition, set the ``LD_LIBRARY_PATH`` variable
|
||||
when running to point at the custom OpenSSL path, so the OpenSSL libraries
|
||||
are loaded from that path instead of the default OS path. Export this
|
||||
variable if necessary.
|
||||
|
||||
In the case of Arm platforms, the location of the ROTPK hash must also be
|
||||
specified at build time. The following locations are currently supported (see
|
||||
``ARM_ROTPK_LOCATION`` build option):
|
||||
|
||||
- ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
|
||||
root-key storage registers present in the platform. On Juno, these
|
||||
registers are read-only. On FVP Base and Cortex models, the registers
|
||||
are also read-only, but the value can be specified using the command line
|
||||
option ``bp.trusted_key_storage.public_key`` when launching the model.
|
||||
On Juno board, the default value corresponds to an ECDSA-SECP256R1 public
|
||||
key hash, whose private part is not currently available.
|
||||
|
||||
- ``ARM_ROTPK_LOCATION=devel_rsa``: use the default hash located in
|
||||
``plat/arm/board/common/rotpk/arm_rotpk_rsa_sha256.bin``. Enforce
|
||||
generation of the new hash if ``ROT_KEY`` is specified.
|
||||
|
||||
- ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the default hash located in
|
||||
``plat/arm/board/common/rotpk/arm_rotpk_ecdsa_sha256.bin``. Enforce
|
||||
generation of the new hash if ``ROT_KEY`` is specified.
|
||||
|
||||
Example of command line using RSA development keys:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
|
||||
make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
|
||||
ARM_ROTPK_LOCATION=devel_rsa \
|
||||
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
|
||||
BL33=<path-to>/<bl33_image> OPENSSL_DIR=<path-to>/<openssl> \
|
||||
all fip
|
||||
|
||||
The result of this build will be the bl1.bin and the fip.bin binaries. This
|
||||
FIP will include the certificates corresponding to the selected Chain of
|
||||
Trust. These certificates can also be found in the output build directory.
|
||||
|
||||
#. The optional FWU_FIP contains any additional images to be loaded from
|
||||
Non-Volatile storage during the :ref:`Firmware Update (FWU)` process. To build the
|
||||
FWU_FIP, any FWU images required by the platform must be specified on the
|
||||
command line. On Arm development platforms like Juno, these are:
|
||||
|
||||
- NS_BL2U. The AP non-secure Firmware Updater image.
|
||||
- SCP_BL2U. The SCP Firmware Update Configuration image.
|
||||
|
||||
Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
|
||||
targets using RSA development:
|
||||
|
||||
::
|
||||
|
||||
MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
|
||||
make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
|
||||
ARM_ROTPK_LOCATION=devel_rsa \
|
||||
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
|
||||
BL33=<path-to>/<bl33_image> OPENSSL_DIR=<path-to>/<openssl> \
|
||||
SCP_BL2=<path-to>/<scp_bl2_image> \
|
||||
SCP_BL2U=<path-to>/<scp_bl2u_image> \
|
||||
NS_BL2U=<path-to>/<ns_bl2u_image> \
|
||||
all fip fwu_fip
|
||||
|
||||
.. note::
|
||||
The BL2U image will be built by default and added to the FWU_FIP.
|
||||
The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
|
||||
to the command line above.
|
||||
|
||||
.. note::
|
||||
Building and installing the non-secure and SCP FWU images (NS_BL1U,
|
||||
NS_BL2U and SCP_BL2U) is outside the scope of this document.
|
||||
|
||||
The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
|
||||
Both the FIP and FWU_FIP will include the certificates corresponding to the
|
||||
selected Chain of Trust. These certificates can also be found in the output
|
||||
build directory.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
|
||||
|
||||
.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
|
||||
.. _mbed TLS Security Center: https://tls.mbed.org/security
|
||||
263
arm-trusted-firmware/docs/design/trusted-board-boot.rst
Normal file
263
arm-trusted-firmware/docs/design/trusted-board-boot.rst
Normal file
@@ -0,0 +1,263 @@
|
||||
Trusted Board Boot
|
||||
==================
|
||||
|
||||
The Trusted Board Boot (TBB) feature prevents malicious firmware from running on
|
||||
the platform by authenticating all firmware images up to and including the
|
||||
normal world bootloader. It does this by establishing a Chain of Trust using
|
||||
Public-Key-Cryptography Standards (PKCS).
|
||||
|
||||
This document describes the design of Trusted Firmware-A (TF-A) TBB, which is an
|
||||
implementation of the `Trusted Board Boot Requirements (TBBR)`_ specification,
|
||||
Arm DEN0006D. It should be used in conjunction with the
|
||||
:ref:`Firmware Update (FWU)` design document, which implements a specific aspect
|
||||
of the TBBR.
|
||||
|
||||
Chain of Trust
|
||||
--------------
|
||||
|
||||
A Chain of Trust (CoT) starts with a set of implicitly trusted components. On
|
||||
the Arm development platforms, these components are:
|
||||
|
||||
- A SHA-256 hash of the Root of Trust Public Key (ROTPK). It is stored in the
|
||||
trusted root-key storage registers. Alternatively, a development ROTPK might
|
||||
be used and its hash embedded into the BL1 and BL2 images (only for
|
||||
development purposes).
|
||||
|
||||
- The BL1 image, on the assumption that it resides in ROM so cannot be
|
||||
tampered with.
|
||||
|
||||
The remaining components in the CoT are either certificates or boot loader
|
||||
images. The certificates follow the `X.509 v3`_ standard. This standard
|
||||
enables adding custom extensions to the certificates, which are used to store
|
||||
essential information to establish the CoT.
|
||||
|
||||
In the TBB CoT all certificates are self-signed. There is no need for a
|
||||
Certificate Authority (CA) because the CoT is not established by verifying the
|
||||
validity of a certificate's issuer but by the content of the certificate
|
||||
extensions. To sign the certificates, different signature schemes are available,
|
||||
please refer to the :ref:`Build Options` for more details.
|
||||
|
||||
The certificates are categorised as "Key" and "Content" certificates. Key
|
||||
certificates are used to verify public keys which have been used to sign content
|
||||
certificates. Content certificates are used to store the hash of a boot loader
|
||||
image. An image can be authenticated by calculating its hash and matching it
|
||||
with the hash extracted from the content certificate. Various hash algorithms
|
||||
are supported to calculate all hashes, please refer to the :ref:`Build Options`
|
||||
for more details.. The public keys and hashes are included as non-standard
|
||||
extension fields in the `X.509 v3`_ certificates.
|
||||
|
||||
The keys used to establish the CoT are:
|
||||
|
||||
- **Root of trust key**
|
||||
|
||||
The private part of this key is used to sign the BL2 content certificate and
|
||||
the trusted key certificate. The public part is the ROTPK.
|
||||
|
||||
- **Trusted world key**
|
||||
|
||||
The private part is used to sign the key certificates corresponding to the
|
||||
secure world images (SCP_BL2, BL31 and BL32). The public part is stored in
|
||||
one of the extension fields in the trusted world certificate.
|
||||
|
||||
- **Non-trusted world key**
|
||||
|
||||
The private part is used to sign the key certificate corresponding to the
|
||||
non secure world image (BL33). The public part is stored in one of the
|
||||
extension fields in the trusted world certificate.
|
||||
|
||||
- **BL3X keys**
|
||||
|
||||
For each of SCP_BL2, BL31, BL32 and BL33, the private part is used to
|
||||
sign the content certificate for the BL3X image. The public part is stored
|
||||
in one of the extension fields in the corresponding key certificate.
|
||||
|
||||
The following images are included in the CoT:
|
||||
|
||||
- BL1
|
||||
- BL2
|
||||
- SCP_BL2 (optional)
|
||||
- BL31
|
||||
- BL33
|
||||
- BL32 (optional)
|
||||
|
||||
The following certificates are used to authenticate the images.
|
||||
|
||||
- **BL2 content certificate**
|
||||
|
||||
It is self-signed with the private part of the ROT key. It contains a hash
|
||||
of the BL2 image.
|
||||
|
||||
- **Trusted key certificate**
|
||||
|
||||
It is self-signed with the private part of the ROT key. It contains the
|
||||
public part of the trusted world key and the public part of the non-trusted
|
||||
world key.
|
||||
|
||||
- **SCP_BL2 key certificate**
|
||||
|
||||
It is self-signed with the trusted world key. It contains the public part of
|
||||
the SCP_BL2 key.
|
||||
|
||||
- **SCP_BL2 content certificate**
|
||||
|
||||
It is self-signed with the SCP_BL2 key. It contains a hash of the SCP_BL2
|
||||
image.
|
||||
|
||||
- **BL31 key certificate**
|
||||
|
||||
It is self-signed with the trusted world key. It contains the public part of
|
||||
the BL31 key.
|
||||
|
||||
- **BL31 content certificate**
|
||||
|
||||
It is self-signed with the BL31 key. It contains a hash of the BL31 image.
|
||||
|
||||
- **BL32 key certificate**
|
||||
|
||||
It is self-signed with the trusted world key. It contains the public part of
|
||||
the BL32 key.
|
||||
|
||||
- **BL32 content certificate**
|
||||
|
||||
It is self-signed with the BL32 key. It contains a hash of the BL32 image.
|
||||
|
||||
- **BL33 key certificate**
|
||||
|
||||
It is self-signed with the non-trusted world key. It contains the public
|
||||
part of the BL33 key.
|
||||
|
||||
- **BL33 content certificate**
|
||||
|
||||
It is self-signed with the BL33 key. It contains a hash of the BL33 image.
|
||||
|
||||
The SCP_BL2 and BL32 certificates are optional, but they must be present if the
|
||||
corresponding SCP_BL2 or BL32 images are present.
|
||||
|
||||
Trusted Board Boot Sequence
|
||||
---------------------------
|
||||
|
||||
The CoT is verified through the following sequence of steps. The system panics
|
||||
if any of the steps fail.
|
||||
|
||||
- BL1 loads and verifies the BL2 content certificate. The issuer public key is
|
||||
read from the verified certificate. A hash of that key is calculated and
|
||||
compared with the hash of the ROTPK read from the trusted root-key storage
|
||||
registers. If they match, the BL2 hash is read from the certificate.
|
||||
|
||||
.. note::
|
||||
The matching operation is platform specific and is currently
|
||||
unimplemented on the Arm development platforms.
|
||||
|
||||
- BL1 loads the BL2 image. Its hash is calculated and compared with the hash
|
||||
read from the certificate. Control is transferred to the BL2 image if all
|
||||
the comparisons succeed.
|
||||
|
||||
- BL2 loads and verifies the trusted key certificate. The issuer public key is
|
||||
read from the verified certificate. A hash of that key is calculated and
|
||||
compared with the hash of the ROTPK read from the trusted root-key storage
|
||||
registers. If the comparison succeeds, BL2 reads and saves the trusted and
|
||||
non-trusted world public keys from the verified certificate.
|
||||
|
||||
The next two steps are executed for each of the SCP_BL2, BL31 & BL32 images.
|
||||
The steps for the optional SCP_BL2 and BL32 images are skipped if these images
|
||||
are not present.
|
||||
|
||||
- BL2 loads and verifies the BL3x key certificate. The certificate signature
|
||||
is verified using the trusted world public key. If the signature
|
||||
verification succeeds, BL2 reads and saves the BL3x public key from the
|
||||
certificate.
|
||||
|
||||
- BL2 loads and verifies the BL3x content certificate. The signature is
|
||||
verified using the BL3x public key. If the signature verification succeeds,
|
||||
BL2 reads and saves the BL3x image hash from the certificate.
|
||||
|
||||
The next two steps are executed only for the BL33 image.
|
||||
|
||||
- BL2 loads and verifies the BL33 key certificate. If the signature
|
||||
verification succeeds, BL2 reads and saves the BL33 public key from the
|
||||
certificate.
|
||||
|
||||
- BL2 loads and verifies the BL33 content certificate. If the signature
|
||||
verification succeeds, BL2 reads and saves the BL33 image hash from the
|
||||
certificate.
|
||||
|
||||
The next step is executed for all the boot loader images.
|
||||
|
||||
- BL2 calculates the hash of each image. It compares it with the hash obtained
|
||||
from the corresponding content certificate. The image authentication succeeds
|
||||
if the hashes match.
|
||||
|
||||
The Trusted Board Boot implementation spans both generic and platform-specific
|
||||
BL1 and BL2 code, and in tool code on the host build machine. The feature is
|
||||
enabled through use of specific build flags as described in
|
||||
:ref:`Build Options`.
|
||||
|
||||
On the host machine, a tool generates the certificates, which are included in
|
||||
the FIP along with the boot loader images. These certificates are loaded in
|
||||
Trusted SRAM using the IO storage framework. They are then verified by an
|
||||
Authentication module included in TF-A.
|
||||
|
||||
The mechanism used for generating the FIP and the Authentication module are
|
||||
described in the following sections.
|
||||
|
||||
Authentication Framework
|
||||
------------------------
|
||||
|
||||
The authentication framework included in TF-A provides support to implement
|
||||
the desired trusted boot sequence. Arm platforms use this framework to
|
||||
implement the boot requirements specified in the
|
||||
`Trusted Board Boot Requirements (TBBR)`_ document.
|
||||
|
||||
More information about the authentication framework can be found in the
|
||||
:ref:`Authentication Framework & Chain of Trust` document.
|
||||
|
||||
Certificate Generation Tool
|
||||
---------------------------
|
||||
|
||||
The ``cert_create`` tool is built and runs on the host machine as part of the
|
||||
TF-A build process when ``GENERATE_COT=1``. It takes the boot loader images
|
||||
and keys as inputs (keys must be in PEM format) and generates the
|
||||
certificates (in DER format) required to establish the CoT. New keys can be
|
||||
generated by the tool in case they are not provided. The certificates are then
|
||||
passed as inputs to the ``fiptool`` utility for creating the FIP.
|
||||
|
||||
The certificates are also stored individually in the output build directory.
|
||||
|
||||
The tool resides in the ``tools/cert_create`` directory. It uses the OpenSSL SSL
|
||||
library version to generate the X.509 certificates. The specific version of the
|
||||
library that is required is given in the :ref:`Prerequisites` document.
|
||||
|
||||
Instructions for building and using the tool can be found at
|
||||
:ref:`tools_build_cert_create`.
|
||||
|
||||
Authenticated Encryption Framework
|
||||
----------------------------------
|
||||
|
||||
The authenticated encryption framework included in TF-A provides support to
|
||||
implement the optional firmware encryption feature. This feature can be
|
||||
optionally enabled on platforms to implement the optional requirement:
|
||||
R060_TBBR_FUNCTION as specified in the `Trusted Board Boot Requirements (TBBR)`_
|
||||
document.
|
||||
|
||||
Firmware Encryption Tool
|
||||
------------------------
|
||||
|
||||
The ``encrypt_fw`` tool is built and runs on the host machine as part of the
|
||||
TF-A build process when ``DECRYPTION_SUPPORT != none``. It takes the plain
|
||||
firmware image as input and generates the encrypted firmware image which can
|
||||
then be passed as input to the ``fiptool`` utility for creating the FIP.
|
||||
|
||||
The encrypted firmwares are also stored individually in the output build
|
||||
directory.
|
||||
|
||||
The tool resides in the ``tools/encrypt_fw`` directory. It uses OpenSSL SSL
|
||||
library version 1.0.1 or later to do authenticated encryption operation.
|
||||
Instructions for building and using the tool can be found in the
|
||||
:ref:`tools_build_enctool`.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _X.509 v3: https://tools.ietf.org/rfc/rfc5280.txt
|
||||
.. _Trusted Board Boot Requirements (TBBR): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
|
||||
165
arm-trusted-firmware/docs/design_documents/cmake_framework.rst
Normal file
165
arm-trusted-firmware/docs/design_documents/cmake_framework.rst
Normal file
@@ -0,0 +1,165 @@
|
||||
TF-A CMake buildsystem
|
||||
======================
|
||||
|
||||
:Author: Balint Dobszay
|
||||
:Organization: Arm Limited
|
||||
:Contact: Balint Dobszay <balint.dobszay@arm.com>
|
||||
:Status: Accepted
|
||||
|
||||
.. contents:: Table of Contents
|
||||
|
||||
Abstract
|
||||
--------
|
||||
This document presents a proposal for a new buildsystem for TF-A using CMake,
|
||||
and as part of this a reusable CMake framework for embedded projects. For a
|
||||
summary about the proposal, please see the `Phabricator wiki page
|
||||
<https://developer.trustedfirmware.org/w/tf_a/cmake-buildsystem-proposal/>`_. As
|
||||
mentioned there, the proposal consists of two phases. The subject of this
|
||||
document is the first phase only.
|
||||
|
||||
Introduction
|
||||
------------
|
||||
The current Makefile based buildsystem of TF-A has become complicated and hard
|
||||
to maintain, there is a need for a new, more flexible solution. The proposal is
|
||||
to use CMake language for the new buildsystem. The main reasons of this decision
|
||||
are the following:
|
||||
|
||||
* It is a well-established, mature tool, widely accepted by open-source
|
||||
projects.
|
||||
* TF-M is already using CMake, reducing fragmentation for tf.org projects can be
|
||||
beneficial.
|
||||
* CMake has various advantages over Make, e.g.:
|
||||
|
||||
* Host and target system agnostic project.
|
||||
* CMake project is scalable, supports project modularization.
|
||||
* Supports software integration.
|
||||
* Out-of-the-box support for integration with several tools (e.g. project
|
||||
generation for various IDEs, integration with cppcheck, etc).
|
||||
|
||||
Of course there are drawbacks too:
|
||||
|
||||
* Language is problematic (e.g. variable scope).
|
||||
* Not embedded approach.
|
||||
|
||||
To overcome these and other problems, we need to create workarounds for some
|
||||
tasks, wrap CMake functions, etc. Since this functionality can be useful in
|
||||
other embedded projects too, it is beneficial to collect the new code into a
|
||||
reusable framework and store this in a separate repository. The following
|
||||
diagram provides an overview of the framework structure:
|
||||
|
||||
|Framework structure|
|
||||
|
||||
Main features
|
||||
-------------
|
||||
|
||||
Structured configuration description
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
In the current Makefile system the build configuration description, validation,
|
||||
processing, and the target creation, source file description are mixed and
|
||||
spread across several files. One of the goals of the framework is to organize
|
||||
this.
|
||||
|
||||
The framework provides a solution to describe the input build parameters, flags,
|
||||
macros, etc. in a structured way. It contains two utilities for this purpose:
|
||||
|
||||
* Map: simple key-value pair implementation.
|
||||
* Group: collection of related maps.
|
||||
|
||||
The related parameters shall be packed into a group (or "setting group"). The
|
||||
setting groups shall be defined and filled with content in config files.
|
||||
Currently the config files are created and edited manually, but later a
|
||||
configuration management tool (e.g. Kconfig) shall be used to generate these
|
||||
files. Therefore, the framework does not contain parameter validation and
|
||||
conflict checking, these shall be handled by the configuration tool.
|
||||
|
||||
Target description
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
The framework provides an API called STGT ('simple target') to describe the
|
||||
targets, i.e. what is the build output, what source files are used, what
|
||||
libraries are linked, etc. The API wraps the CMake target functions, and also
|
||||
extends the built-in functionality, it can use the setting groups described in
|
||||
the previous section. A group can be applied onto a target, i.e. a collection of
|
||||
macros, flags, etc. can be applied onto the given output executable/library.
|
||||
This provides a more granular way than the current Makefile system where most of
|
||||
these are global and applied onto each target.
|
||||
|
||||
Compiler abstraction
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
Apart from the built-in CMake usage of the compiler, there are some common tasks
|
||||
that CMake does not solve (e.g. preprocessing a file). For these tasks the
|
||||
framework uses wrapper functions instead of direct calls to the compiler. This
|
||||
way it is not tied to one specific compiler.
|
||||
|
||||
External tools
|
||||
^^^^^^^^^^^^^^
|
||||
In the TF-A buildsystem some external tools are used, e.g. fiptool for image
|
||||
generation or dtc for device tree compilation. These tools have to be found
|
||||
and/or built by the framework. For this, the CMake find_package functionality is
|
||||
used, any other necessary tools can be added later.
|
||||
|
||||
Workflow
|
||||
--------
|
||||
The following diagram demonstrates the development workflow using the framework:
|
||||
|
||||
|Framework workflow|
|
||||
|
||||
The process can be split into two main phases:
|
||||
|
||||
In the provisioning phase, first we have to obtain the necessary resources, i.e.
|
||||
clone the code repository and other dependencies. Next we have to do the
|
||||
configuration, preferably using a config tool like KConfig.
|
||||
|
||||
In the development phase first we run CMake, which will generate the buildsystem
|
||||
using the selected generator backend (currently only the Makefile generator is
|
||||
supported). After this we run the selected build tool which in turn calls the
|
||||
compiler, linker, packaging tool, etc. Finally we can run and debug the output
|
||||
executables.
|
||||
|
||||
Usually during development only the steps in this second phase have to be
|
||||
repeated, while the provisioning phase needs to be done only once (or rarely).
|
||||
|
||||
Example
|
||||
-------
|
||||
This is a short example for the basic framework usage.
|
||||
|
||||
First, we create a setting group called *mem_conf* and fill it with several
|
||||
parameters. It is worth noting the difference between *CONFIG* and *DEFINE*
|
||||
types: the former is only a CMake domain option, the latter is only a C language
|
||||
macro.
|
||||
|
||||
Next, we create a target called *fw1* and add the *mem_conf* setting group to
|
||||
it. This means that all source and header files used by the target will have all
|
||||
the parameters declared in the setting group. Then we set the target type to
|
||||
executable, and add some source files. Since the target has the parameters from
|
||||
the settings group, we can use it for conditionally adding source files. E.g.
|
||||
*dram_controller.c* will only be added if MEM_TYPE equals dram.
|
||||
|
||||
.. code-block:: cmake
|
||||
|
||||
group_new(NAME mem_conf)
|
||||
group_add(NAME mem_conf TYPE DEFINE KEY MEM_SIZE VAL 1024)
|
||||
group_add(NAME mem_conf TYPE CONFIG DEFINE KEY MEM_TYPE VAL dram)
|
||||
group_add(NAME mem_conf TYPE CFLAG KEY -Os)
|
||||
|
||||
stgt_create(NAME fw1)
|
||||
stgt_add_setting(NAME fw1 GROUPS mem_conf)
|
||||
stgt_set_target(NAME fw1 TYPE exe)
|
||||
|
||||
stgt_add_src(NAME fw1 SRC
|
||||
${CMAKE_SOURCE_DIR}/main.c
|
||||
)
|
||||
|
||||
stgt_add_src_cond(NAME fw1 KEY MEM_TYPE VAL dram SRC
|
||||
${CMAKE_SOURCE_DIR}/dram_controller.c
|
||||
)
|
||||
|
||||
.. |Framework structure| image::
|
||||
../resources/diagrams/cmake_framework_structure.png
|
||||
:width: 75 %
|
||||
|
||||
.. |Framework workflow| image::
|
||||
../resources/diagrams/cmake_framework_workflow.png
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
|
||||
@@ -0,0 +1,197 @@
|
||||
Enhance Context Management library for EL3 firmware
|
||||
===================================================
|
||||
|
||||
:Authors: Soby Mathew & Zelalem Aweke
|
||||
:Organization: Arm Limited
|
||||
:Contact: Soby Mathew <soby.mathew@arm.com> & Zelalem Aweke <zelalem.aweke@arm.com>
|
||||
:Status: RFC
|
||||
|
||||
.. contents:: Table of Contents
|
||||
|
||||
Introduction
|
||||
------------
|
||||
The context management library in TF-A provides the basic CPU context
|
||||
initialization and management routines for use by different components
|
||||
in EL3 firmware. The original design of the library was done keeping in
|
||||
mind the 2 world switch and hence this design pattern has been extended to
|
||||
keep up with growing requirements of EL3 firmware. With the introduction
|
||||
of a new Realm world and a separate Root world for EL3 firmware, it is clear
|
||||
that this library needs to be refactored to cater for future enhancements and
|
||||
reduce chances of introducing error in code. This also aligns with the overall
|
||||
goal of reducing EL3 firmware complexity and footprint.
|
||||
|
||||
It is expected that the suggestions below could have legacy implications and
|
||||
hence we are mainly targeting SPM/RMM based systems. It is expected that these
|
||||
legacy issues will need to be sorted out as part of implementation on a case
|
||||
by case basis.
|
||||
|
||||
Design Principles
|
||||
-----------------
|
||||
The below section lays down the design principles for re-factoring the context
|
||||
management library :
|
||||
|
||||
(1) **Decentralized model for context mgmt**
|
||||
|
||||
Both the Secure and Realm worlds have associated dispatcher component in
|
||||
EL3 firmware to allow management of their respective worlds. Allowing the
|
||||
dispatcher to own the context for their respective world and moving away
|
||||
from a centralized policy management by context management library will
|
||||
remove the world differentiation code in the library. This also means that
|
||||
the library will not be responsible for CPU feature enablement for
|
||||
Secure and Realm worlds. See point 3 and 4 for more details.
|
||||
|
||||
The Non Secure world does not have a dispatcher component and hence EL3
|
||||
firmware (BL31)/context management library needs to have routines to help
|
||||
initialize the Non Secure world context.
|
||||
|
||||
(2) **EL3 should only initialize immediate used lower EL**
|
||||
|
||||
Due to the way TF-A evolved, from EL3 interacting with an S-EL1 payload to
|
||||
SPM in S-EL2, there is some code initializing S-EL1 registers which is
|
||||
probably redundant when SPM is present in S-EL2. As a principle, EL3
|
||||
firmware should only initialize the next immediate lower EL in use.
|
||||
If EL2 needs to be skipped and is not to be used at runtime, then
|
||||
EL3 can do the bare minimal EL2 init and init EL1 to prepare for EL3 exit.
|
||||
It is expected that this skip EL2 configuration is only needed for NS
|
||||
world to support legacy Android deployments. It is worth removing this
|
||||
`skip EL2 for Non Secure` config support if this is no longer used.
|
||||
|
||||
(3) **Maintain EL3 sysregs which affect lower EL within CPU context**
|
||||
|
||||
The CPU context contains some EL3 sysregs and gets applied on a per-world
|
||||
basis (eg: cptr_el3, scr_el3, zcr_el3 is part of the context
|
||||
because different settings need to be applied between each world).
|
||||
But this design pattern is not enforced in TF-A. It is possible to directly
|
||||
modify EL3 sysreg dynamically during the transition between NS and Secure
|
||||
worlds. Having multiple ways of manipulating EL3 sysregs for different
|
||||
values between the worlds is flaky and error prone. The proposal is to
|
||||
enforce the rule that any EL3 sysreg which can be different between worlds
|
||||
is maintained in the CPU Context. Once the context is initialized the
|
||||
EL3 sysreg values corresponding to the world being entered will be restored.
|
||||
|
||||
(4) **Allow more flexibility for Dispatchers to select feature set to save and restore**
|
||||
|
||||
The current functions for EL2 CPU context save and restore is a single
|
||||
function which takes care of saving and restoring all the registers for
|
||||
EL2. This method is inflexible and it does not allow to dynamically detect
|
||||
CPU features to select registers to save and restore. It also assumes that
|
||||
both Realm and Secure world will have the same feature set enabled from
|
||||
EL3 at runtime and makes it hard to enable different features for each
|
||||
world. The framework should cater for selective save and restore of CPU
|
||||
registers which can be controlled by the dispatcher.
|
||||
|
||||
For the implementation, this could mean that there is a separate assembly
|
||||
save and restore routine corresponding to Arch feature. The memory allocation
|
||||
within the CPU Context for each set of registers will be controlled by a
|
||||
FEAT_xxx build option. It is a valid configuration to have
|
||||
context memory allocated but not used at runtime based on feature detection
|
||||
at runtime or the platform owner has decided not to enable the feature
|
||||
for the particular world.
|
||||
|
||||
Context Allocation and Initialization
|
||||
-------------------------------------
|
||||
|
||||
|context_mgmt_abs|
|
||||
|
||||
.. |context_mgmt_abs| image::
|
||||
../resources/diagrams/context_management_abs.png
|
||||
|
||||
The above figure shows how the CPU context is allocated within TF-A. The
|
||||
allocation for Secure and Realm world is by the respective dispatcher. In the case
|
||||
of NS world, the context is allocated by the PSCI lib. This scheme allows TF-A
|
||||
to be built in various configurations (with or without Secure/Realm worlds) and
|
||||
will result in optimal memory footprint. The Secure and Realm world contexts are
|
||||
initialized by invoking context management library APIs which then initialize
|
||||
each world based on conditional evaluation of the security state of the
|
||||
context. The proposal here is to move the conditional initialization
|
||||
of context for Secure and Realm worlds to their respective dispatchers and
|
||||
have the library do only the common init needed. The library can export
|
||||
helpers to initialize registers corresponding to certain features but
|
||||
should not try to do different initialization between the worlds. The library
|
||||
can also export helpers for initialization of NS CPU Context since there is no
|
||||
dispatcher for that world.
|
||||
|
||||
This implies that any world specific code in context mgmt lib should now be
|
||||
migrated to the respective "owners". To maintain compatibility with legacy, the
|
||||
current functions can be retained in the lib and perhaps define new ones for
|
||||
use by SPMD and RMMD. The details of this can be worked out during
|
||||
implementation.
|
||||
|
||||
Introducing Root Context
|
||||
------------------------
|
||||
Till now, we have been ignoring the fact that Root world (or EL3) itself could
|
||||
have some settings which are distinct from NS/S/Realm worlds. In this case,
|
||||
Root world itself would need to maintain some sysregs settings for its own
|
||||
execution and would need to use sysregs of lower EL (eg: PAuth, pmcr) to enable
|
||||
some functionalities in EL3. The current sequence for context save and restore
|
||||
in TF-A is as given below:
|
||||
|
||||
|context_mgmt_existing|
|
||||
|
||||
.. |context_mgmt_existing| image::
|
||||
../resources/diagrams/context_mgmt_existing.png
|
||||
|
||||
Note1: The EL3 CPU context is not a homogenous collection of EL3 sysregs but
|
||||
a collection of EL3 and some other lower EL registers. The save and restore
|
||||
is also not done homogenously but based on the objective of using the
|
||||
particular register.
|
||||
|
||||
Note2: The EL1 context save and restore can possibly be removed when switching
|
||||
to S-EL2 as SPM can take care of saving the incoming NS EL1 context.
|
||||
|
||||
It can be seen that the EL3 sysreg values applied while the execution is in Root
|
||||
world corresponds to the world it came from (eg: if entering EL3 from NS world,
|
||||
the sysregs correspond to the values in NS context). There is a case that EL3
|
||||
itself may have some settings to apply for various reasons. A good example for
|
||||
this is the cptr_el3 regsiter. Although FPU traps need to be disabled for
|
||||
Non Secure, Secure and Realm worlds, the EL3 execution itself may keep the trap
|
||||
enabled for the sake of robustness. Another example is, if the MTE feature
|
||||
is enabled for a particular world, this feature will be enabled for Root world
|
||||
as well when entering EL3 from that world. The firmware at EL3 may not
|
||||
be expecting this feature to be enabled and may cause unwanted side-effects
|
||||
which could be problematic. Thus it would be more robust if Root world is not
|
||||
subject to EL3 sysreg values from other worlds but maintains its own values
|
||||
which is stable and predictable throughout root world execution.
|
||||
|
||||
There is also the case that when EL3 would like to make use of some
|
||||
Architectural feature(s) or do some security hardening, it might need
|
||||
programming of some lower EL sysregs. For example, if EL3 needs to make
|
||||
use of Pointer Authentication (PAuth) feature, it needs to program
|
||||
its own PAuth Keys during execution at EL3. Hence EL3 needs its
|
||||
own copy of PAuth registers which needs to be restored on every
|
||||
entry to EL3. A similar case can be made for DIT bit in PSTATE,
|
||||
or use of SP_EL0 for C Runtime Stack at EL3.
|
||||
|
||||
The proposal here is to maintain a separate root world CPU context
|
||||
which gets applied for Root world execution. This is not the full
|
||||
CPU_Context, but subset of EL3 sysregs (`el3_sysreg`) and lower EL
|
||||
sysregs (`root_exc_context`) used by EL3. The save and restore
|
||||
sequence for this Root context would need to be done in
|
||||
an optimal way. The `el3_sysreg` does not need to be saved
|
||||
on EL3 Exit and possibly only some registers in `root_exc_context`
|
||||
of Root world context would need to be saved on EL3 exit (eg: SP_EL0).
|
||||
|
||||
The new sequence for world switch including Root world context would
|
||||
be as given below :
|
||||
|
||||
|context_mgmt_proposed|
|
||||
|
||||
.. |context_mgmt_proposed| image::
|
||||
../resources/diagrams/context_mgmt_proposed.png
|
||||
|
||||
Having this framework in place will allow Root world to make use of lower EL
|
||||
registers easily for its own purposes and also have a fixed EL3 sysreg setting
|
||||
which is not affected by the settings of other worlds. This will unify the
|
||||
Root world register usage pattern for its own execution and remove some
|
||||
of the adhoc usages in code.
|
||||
|
||||
Conclusion
|
||||
----------
|
||||
Of all the proposals, the introduction of Root world context would likely need
|
||||
further prototyping to confirm the design and we will need to measure the
|
||||
performance and memory impact of this change. Other changes are incremental
|
||||
improvements which are thought to have negligible impact on EL3 performance.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.*
|
||||
132
arm-trusted-firmware/docs/design_documents/drtm_poc.rst
Normal file
132
arm-trusted-firmware/docs/design_documents/drtm_poc.rst
Normal file
@@ -0,0 +1,132 @@
|
||||
DRTM Proof of Concept
|
||||
=====================
|
||||
|
||||
Dynamic Root of Trust for Measurement (DRTM) begins a new trust environment
|
||||
by measuring and executing a protected payload.
|
||||
|
||||
Static Root of Trust for Measurement (SRTM)/Measured Boot implementation,
|
||||
currently used by TF-A covers all firmwares, from the boot ROM to the normal
|
||||
world bootloader. As a whole, they make up the system's TCB. These boot
|
||||
measurements allow attesting to what software is running on the system and
|
||||
enable enforcing security policies.
|
||||
|
||||
As the boot chain grows or firmware becomes dynamically extensible,
|
||||
establishing an attestable TCB becomes more challenging. DRTM provides a
|
||||
solution to this problem by allowing measurement chains to be started at
|
||||
any time. As these measurements are stored separately from the boot-time
|
||||
measurements, they reduce the size of the TCB, which helps reduce the attack
|
||||
surface and the risk of untrusted code executing, which could compromise
|
||||
the security of the system.
|
||||
|
||||
Components
|
||||
~~~~~~~~~~
|
||||
|
||||
- **DCE-Preamble**: The DCE Preamble prepares the platform for DRTM by
|
||||
doing any needed configuration, loading the target payload image(DLME),
|
||||
and preparing input parameters needed by DRTM. Finally, it invokes the
|
||||
DL Event to start the dynamic launch.
|
||||
|
||||
- **D-CRTM**: The D-CRTM is the trust anchor (or root of trust) for the
|
||||
DRTM boot sequence and is where the dynamic launch starts. The D-CRTM
|
||||
must be implemented as a trusted agent in the system. The D-CRTM
|
||||
initializes the TPM for DRTM and prepares the environment for the next
|
||||
stage of DRTM, the DCE. The D-CRTM measures the DCE, verifies its
|
||||
signature, and transfers control to it.
|
||||
|
||||
- **DCE**: The DCE executes on an application core. The DCE verifies the
|
||||
system’s state, measures security-critical attributes of the system,
|
||||
prepares the memory region for the target payload, measures the payload,
|
||||
and finally transfers control to the payload.
|
||||
|
||||
- **DLME**: The protected payload is referred to as the Dynamically Launched
|
||||
Measured Environment, or DLME. The DLME begins execution in a safe state,
|
||||
with a single thread of execution, DMA protections, and interrupts
|
||||
disabled. The DCE provides data to the DLME that it can use to verify the
|
||||
configuration of the system.
|
||||
|
||||
In this proof of concept, DCE and D-CRTM are implemented in BL31 and
|
||||
DCE-Preamble and DLME are implemented in UEFI application. A DL Event is
|
||||
triggered as a SMC by DCE-Preamble and handled by D-CRTM, which launches the
|
||||
DLME via DCE.
|
||||
|
||||
This manual provides instructions to build TF-A code with pre-buit EDK2
|
||||
and DRTM UEFI application.
|
||||
|
||||
Building the PoC for the Arm FVP platform
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
(1) Use the below command to clone TF-A source code -
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
|
||||
|
||||
(2) There are prebuilt binaries required to execute the DRTM implementation
|
||||
in the `prebuilts-drtm-bins`_.
|
||||
Download EDK2 *FVP_AARCH64_EFI.fd* and UEFI DRTM application *test-disk.img*
|
||||
binary from `prebuilts-drtm-bins`_.
|
||||
|
||||
(3) Build the TF-A code using below command
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$ make CROSS_COMPILE=aarch64-none-elf- ARM_ROTPK_LOCATION=devel_rsa
|
||||
DEBUG=1 V=1 BL33=</path/to/FVP_AARCH64_EFI.fd> DRTM_SUPPORT=1
|
||||
MBEDTLS_DIR=</path/to/mbedTLS-source> USE_ROMLIB=1 all fip
|
||||
|
||||
Running DRTM UEFI application on the Armv8-A AEM FVP
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
To run the DRTM test application along with DRTM implementation in BL31,
|
||||
you need an FVP model. Please use the version of FVP_Base_RevC-2xAEMvA model
|
||||
advertised in the TF-A documentation.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
FVP_Base_RevC-2xAEMvA \
|
||||
--data cluster0.cpu0=</path/to/romlib.bin>@0x03ff2000 \
|
||||
--stat \
|
||||
-C bp.flashloader0.fname=<path/to/fip.bin> \
|
||||
-C bp.secureflashloader.fname=<path/to/bl1.bin> \
|
||||
-C bp.ve_sysregs.exit_on_shutdown=1 \
|
||||
-C bp.virtioblockdevice.image_path=<path/to/test-disk.img> \
|
||||
-C cache_state_modelled=1 \
|
||||
-C cluster0.check_memory_attributes=0 \
|
||||
-C cluster0.cpu0.etm-present=0 \
|
||||
-C cluster0.cpu1.etm-present=0 \
|
||||
-C cluster0.cpu2.etm-present=0 \
|
||||
-C cluster0.cpu3.etm-present=0 \
|
||||
-C cluster0.stage12_tlb_size=1024 \
|
||||
-C cluster1.check_memory_attributes=0 \
|
||||
-C cluster1.cpu0.etm-present=0 \
|
||||
-C cluster1.cpu1.etm-present=0 \
|
||||
-C cluster1.cpu2.etm-present=0 \
|
||||
-C cluster1.cpu3.etm-present=0 \
|
||||
-C cluster1.stage12_tlb_size=1024 \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-Q 1000 \
|
||||
"$@"
|
||||
|
||||
The bottom of the output from *uart1* should look something like the
|
||||
following to indicate that the last SMC to unprotect memory has been fired
|
||||
successfully.
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
...
|
||||
|
||||
INFO: DRTM service handler: version
|
||||
INFO: ++ DRTM service handler: TPM features
|
||||
INFO: ++ DRTM service handler: Min. mem. requirement features
|
||||
INFO: ++ DRTM service handler: DMA protection features
|
||||
INFO: ++ DRTM service handler: Boot PE ID features
|
||||
INFO: ++ DRTM service handler: TCB-hashes features
|
||||
INFO: DRTM service handler: dynamic launch
|
||||
WARNING: DRTM service handler: close locality is not supported
|
||||
INFO: DRTM service handler: unprotect mem
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2022, Arm Limited. All rights reserved.*
|
||||
|
||||
.. _prebuilts-drtm-bins: https://downloads.trustedfirmware.org/tf-a/drtm
|
||||
.. _DRTM-specification: https://developer.arm.com/documentation/den0113/a
|
||||
15
arm-trusted-firmware/docs/design_documents/index.rst
Normal file
15
arm-trusted-firmware/docs/design_documents/index.rst
Normal file
@@ -0,0 +1,15 @@
|
||||
Design Documents
|
||||
================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Contents
|
||||
|
||||
cmake_framework
|
||||
context_mgmt_rework
|
||||
measured_boot_poc
|
||||
drtm_poc
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.*
|
||||
507
arm-trusted-firmware/docs/design_documents/measured_boot_poc.rst
Normal file
507
arm-trusted-firmware/docs/design_documents/measured_boot_poc.rst
Normal file
@@ -0,0 +1,507 @@
|
||||
Interaction between Measured Boot and an fTPM (PoC)
|
||||
===================================================
|
||||
|
||||
Measured Boot is the process of cryptographically measuring the code and
|
||||
critical data used at boot time, for example using a TPM, so that the
|
||||
security state can be attested later.
|
||||
|
||||
The current implementation of the driver included in Trusted Firmware-A
|
||||
(TF-A) stores the measurements into a `TGC event log`_ in secure
|
||||
memory. No other means of recording measurements (such as a discrete TPM) is
|
||||
supported right now.
|
||||
|
||||
The driver also provides mechanisms to pass the Event Log to normal world if
|
||||
needed.
|
||||
|
||||
This manual provides instructions to build a proof of concept (PoC) with the
|
||||
sole intention of showing how Measured Boot can be used in conjunction with
|
||||
a firmware TPM (fTPM) service implemented on top of OP-TEE.
|
||||
|
||||
.. note::
|
||||
The instructions given in this document are meant to be used to build
|
||||
a PoC to show how Measured Boot on TF-A can interact with a third
|
||||
party (f)TPM service and they try to be as general as possible. Different
|
||||
platforms might have different needs and configurations (e.g. different
|
||||
SHA algorithms) and they might also use different types of TPM services
|
||||
(or even a different type of service to provide the attestation)
|
||||
and therefore the instuctions given here might not apply in such scenarios.
|
||||
|
||||
Components
|
||||
~~~~~~~~~~
|
||||
|
||||
The PoC is built on top of the `OP-TEE Toolkit`_, which has support to build
|
||||
TF-A with support for Measured Boot enabled (and run it on a Foundation Model)
|
||||
since commit cf56848.
|
||||
|
||||
The aforementioned toolkit builds a set of images that contain all the components
|
||||
needed to test that the Event Log was properly created. One of these images will
|
||||
contain a third party fTPM service which in turn will be used to process the
|
||||
Event Log.
|
||||
|
||||
The reason to choose OP-TEE Toolkit to build our PoC around it is mostly
|
||||
for convenience. As the fTPM service used is an OP-TEE TA, it was easy to add
|
||||
build support for it to the toolkit and then build the PoC around it.
|
||||
|
||||
The most relevant components installed in the image that are closely related to
|
||||
Measured Boot/fTPM functionality are:
|
||||
|
||||
- **OP-TEE**: As stated earlier, the fTPM service used in this PoC is built as an
|
||||
OP-TEE TA and therefore we need to include the OP-TEE OS image.
|
||||
Support to interfacing with Measured Boot was added to version 3.9.0 of
|
||||
OP-TEE by implementing the ``PTA_SYSTEM_GET_TPM_EVENT_LOG`` syscall, which
|
||||
allows the former to pass a copy of the Event Log to any TA requesting it.
|
||||
OP-TEE knows the location of the Event Log by reading the DTB bindings
|
||||
received from TF-A. Visit :ref:`DTB binding for Event Log properties`
|
||||
for more details on this.
|
||||
|
||||
- **fTPM Service**: We use a third party fTPM service in order to validate
|
||||
the Measured Boot functionality. The chosen fTPM service is a sample
|
||||
implementation for Aarch32 architecture included on the `ms-tpm-20-ref`_
|
||||
reference implementation from Microsoft. The service was updated in order
|
||||
to extend the Measured Boot Event Log at boot up and it uses the
|
||||
aforementioned ``PTA_SYSTEM_GET_TPM_EVENT_LOG`` call to retrieve a copy
|
||||
of the former.
|
||||
|
||||
.. note::
|
||||
Arm does not provide an fTPM implementation. The fTPM service used here
|
||||
is a third party one which has been updated to support Measured Boot
|
||||
service as provided by TF-A. As such, it is beyond the scope of this
|
||||
manual to test and verify the correctness of the output generated by the
|
||||
fTPM service.
|
||||
|
||||
- **TPM Kernel module**: In order to interact with the fTPM service, we need
|
||||
a kernel module to forward the request from user space to the secure world.
|
||||
|
||||
- `tpm2-tools`_: This is a set of tools that allow to interact with the
|
||||
fTPM service. We use this in order to read the PCRs with the measurements.
|
||||
|
||||
Building the PoC for the Arm FVP platform
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
As mentioned before, this PoC is based on the OP-TEE Toolkit with some
|
||||
extensions to enable Measured Boot and an fTPM service. Therefore, we can rely
|
||||
on the instructions to build the original OP-TEE Toolkit. As a general rule,
|
||||
the following steps should suffice:
|
||||
|
||||
(1) Start by following the `Get and build the solution`_ instructions to build
|
||||
the OP-TEE toolkit. On step 3, you need to get the manifest for FVP
|
||||
platform from the main branch:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$ repo init -u https://github.com/OP-TEE/manifest.git -m fvp.xml
|
||||
|
||||
Then proceed synching the repos as stated in step 3. Continue following
|
||||
the instructions and stop before step 5.
|
||||
|
||||
(2) Next you should obtain the `Armv8-A Foundation Platform (For Linux Hosts Only)`_.
|
||||
The binary should be untar'ed to the root of the repo tree, i.e., like
|
||||
this: ``<fvp-project>/Foundation_Platformpkg``. In the end, after cloning
|
||||
all source code, getting the toolchains and "installing"
|
||||
Foundation_Platformpkg, you should have a folder structure that looks like
|
||||
this:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$ ls -la
|
||||
total 80
|
||||
drwxrwxr-x 20 tf-a_user tf-a_user 4096 Jul 1 12:16 .
|
||||
drwxr-xr-x 23 tf-a_user tf-a_user 4096 Jul 1 10:40 ..
|
||||
drwxrwxr-x 12 tf-a_user tf-a_user 4096 Jul 1 10:45 build
|
||||
drwxrwxr-x 16 tf-a_user tf-a_user 4096 Jul 1 12:16 buildroot
|
||||
drwxrwxr-x 51 tf-a_user tf-a_user 4096 Jul 1 10:45 edk2
|
||||
drwxrwxr-x 6 tf-a_user tf-a_user 4096 Jul 1 12:14 edk2-platforms
|
||||
drwxr-xr-x 7 tf-a_user tf-a_user 4096 Jul 1 10:52 Foundation_Platformpkg
|
||||
drwxrwxr-x 17 tf-a_user tf-a_user 4096 Jul 2 10:40 grub
|
||||
drwxrwxr-x 25 tf-a_user tf-a_user 4096 Jul 2 10:39 linux
|
||||
drwxrwxr-x 15 tf-a_user tf-a_user 4096 Jul 1 10:45 mbedtls
|
||||
drwxrwxr-x 6 tf-a_user tf-a_user 4096 Jul 1 10:45 ms-tpm-20-ref
|
||||
drwxrwxr-x 8 tf-a_user tf-a_user 4096 Jul 1 10:45 optee_client
|
||||
drwxrwxr-x 10 tf-a_user tf-a_user 4096 Jul 1 10:45 optee_examples
|
||||
drwxrwxr-x 12 tf-a_user tf-a_user 4096 Jul 1 12:13 optee_os
|
||||
drwxrwxr-x 8 tf-a_user tf-a_user 4096 Jul 1 10:45 optee_test
|
||||
drwxrwxr-x 7 tf-a_user tf-a_user 4096 Jul 1 10:45 .repo
|
||||
drwxrwxr-x 4 tf-a_user tf-a_user 4096 Jul 1 12:12 toolchains
|
||||
drwxrwxr-x 21 tf-a_user tf-a_user 4096 Jul 1 12:15 trusted-firmware-a
|
||||
|
||||
(3) Now enter into ``ms-tpm-20-ref`` and get its dependencies:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$ cd ms-tpm-20-ref
|
||||
$ git submodule init
|
||||
$ git submodule update
|
||||
Submodule path 'external/wolfssl': checked out '9c87f979a7f1d3a6d786b260653d566c1d31a1c4'
|
||||
|
||||
(4) Now, you should be able to continue with step 5 in "`Get and build the solution`_"
|
||||
instructions. In order to enable support for Measured Boot, you need to
|
||||
set the ``MEASURED_BOOT`` build option:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$ MEASURED_BOOT=y make -j `nproc`
|
||||
|
||||
.. note::
|
||||
The build process will likely take a long time. It is strongly recommended to
|
||||
pass the ``-j`` option to make to run the process faster.
|
||||
|
||||
After this step, you should be ready to run the image.
|
||||
|
||||
Running and using the PoC on the Armv8-A Foundation AEM FVP
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
With everything built, you can now run the image:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$ make run-only
|
||||
|
||||
.. note::
|
||||
Using ``make run`` will build and run the image and it can be used instead
|
||||
of simply ``make``. However, once the image is built, it is recommended to
|
||||
use ``make run-only`` to avoid re-running all the building rules, which
|
||||
would take time.
|
||||
|
||||
When FVP is launched, two terminal windows will appear. ``FVP terminal_0``
|
||||
is the userspace terminal whereas ``FVP terminal_1`` is the counterpart for
|
||||
the secure world (where TAs will print their logs, for instance).
|
||||
|
||||
Log into the image shell with user ``root``, no password will be required.
|
||||
Then we can issue the ``ftpm`` command, which is an alias that
|
||||
|
||||
(1) loads the ftpm kernel module and
|
||||
|
||||
(2) calls ``tpm2_pcrread``, which will access the fTPM service to read the
|
||||
PCRs.
|
||||
|
||||
When loading the ftpm kernel module, the fTPM TA is loaded into the secure
|
||||
world. This TA then requests a copy of the Event Log generated during the
|
||||
booting process so it can retrieve all the entries on the log and record them
|
||||
first thing.
|
||||
|
||||
.. note::
|
||||
For this PoC, nothing loaded after BL33 and NT_FW_CONFIG is recorded
|
||||
in the Event Log.
|
||||
|
||||
The secure world terminal should show the debug logs for the fTPM service,
|
||||
including all the measurements available in the Event Log as they are being
|
||||
processed:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
M/TA: Preparing to extend the following TPM Event Log:
|
||||
M/TA: TCG_EfiSpecIDEvent:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 3
|
||||
M/TA: Digest : 00
|
||||
M/TA: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
M/TA: : 00 00 00
|
||||
M/TA: EventSize : 33
|
||||
M/TA: Signature : Spec ID Event03
|
||||
M/TA: PlatformClass : 0
|
||||
M/TA: SpecVersion : 2.0.2
|
||||
M/TA: UintnSize : 1
|
||||
M/TA: NumberOfAlgorithms : 1
|
||||
M/TA: DigestSizes :
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: DigestSize : 32
|
||||
M/TA: VendorInfoSize : 0
|
||||
M/TA: PCR_Event2:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 3
|
||||
M/TA: Digests Count : 1
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: Digest : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
M/TA: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
M/TA: EventSize : 17
|
||||
M/TA: Signature : StartupLocality
|
||||
M/TA: StartupLocality : 0
|
||||
M/TA: PCR_Event2:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 1
|
||||
M/TA: Digests Count : 1
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: Digest : 58 26 32 6e 64 45 64 da 45 de 35 db 96 fd ed 63
|
||||
M/TA: : 2a 6a d4 0d aa 94 b0 b1 55 e4 72 e7 1f 0a e0 d5
|
||||
M/TA: EventSize : 5
|
||||
M/TA: Event : BL_2
|
||||
M/TA: PCR_Event2:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 1
|
||||
M/TA: Digests Count : 1
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: Digest : cf f9 7d a3 5c 73 ac cb 7b a0 25 80 6a 6e 50 a5
|
||||
M/TA: : 6b 2e d2 8c c9 36 92 7d 46 c5 b9 c3 a4 6c 51 7c
|
||||
M/TA: EventSize : 6
|
||||
M/TA: Event : BL_31
|
||||
M/TA: PCR_Event2:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 1
|
||||
M/TA: Digests Count : 1
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: Digest : 23 b0 a3 5d 54 d9 43 1a 5c b9 89 63 1c da 06 c2
|
||||
M/TA: : e5 de e7 7e 99 17 52 12 7d f7 45 ca 4f 4a 39 c0
|
||||
M/TA: EventSize : 10
|
||||
M/TA: Event : HW_CONFIG
|
||||
M/TA: PCR_Event2:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 1
|
||||
M/TA: Digests Count : 1
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: Digest : 4e e4 8e 5a e6 50 ed e0 b5 a3 54 8a 1f d6 0e 8a
|
||||
M/TA: : ea 0e 71 75 0e a4 3f 82 76 ce af cd 7c b0 91 e0
|
||||
M/TA: EventSize : 14
|
||||
M/TA: Event : SOC_FW_CONFIG
|
||||
M/TA: PCR_Event2:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 1
|
||||
M/TA: Digests Count : 1
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: Digest : 01 b0 80 47 a1 ce 86 cd df 89 d2 1f 2e fc 6c 22
|
||||
M/TA: : f8 19 ec 6e 1e ec 73 ba 5a be d0 96 e3 5f 6d 75
|
||||
M/TA: EventSize : 6
|
||||
M/TA: Event : BL_32
|
||||
M/TA: PCR_Event2:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 1
|
||||
M/TA: Digests Count : 1
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: Digest : 5d c6 ef 35 5a 90 81 b4 37 e6 3b 52 da 92 ab 8e
|
||||
M/TA: : d9 6e 93 98 2d 40 87 96 1b 5a a7 ee f1 f4 40 63
|
||||
M/TA: EventSize : 18
|
||||
M/TA: Event : BL32_EXTRA1_IMAGE
|
||||
M/TA: PCR_Event2:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 1
|
||||
M/TA: Digests Count : 1
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: Digest : 39 b7 13 b9 93 db 32 2f 1b 48 30 eb 2c f2 5c 25
|
||||
M/TA: : 00 0f 38 dc 8e c8 02 cd 79 f2 48 d2 2c 25 ab e2
|
||||
M/TA: EventSize : 6
|
||||
M/TA: Event : BL_33
|
||||
M/TA: PCR_Event2:
|
||||
M/TA: PCRIndex : 0
|
||||
M/TA: EventType : 1
|
||||
M/TA: Digests Count : 1
|
||||
M/TA: #0 AlgorithmId : SHA256
|
||||
M/TA: Digest : 25 10 60 5d d4 bc 9d 82 7a 16 9f 8a cc 47 95 a6
|
||||
M/TA: : fd ca a0 c1 2b c9 99 8f 51 20 ff c6 ed 74 68 5a
|
||||
M/TA: EventSize : 13
|
||||
M/TA: Event : NT_FW_CONFIG
|
||||
|
||||
These logs correspond to the measurements stored by TF-A during the measured
|
||||
boot process and therefore, they should match the logs dumped by the former
|
||||
during the boot up process. These can be seen on the terminal_0:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
NOTICE: Booting Trusted Firmware
|
||||
NOTICE: BL1: v2.5(release):v2.5
|
||||
NOTICE: BL1: Built : 10:41:20, Jul 2 2021
|
||||
NOTICE: BL1: Booting BL2
|
||||
NOTICE: BL2: v2.5(release):v2.5
|
||||
NOTICE: BL2: Built : 10:41:20, Jul 2 2021
|
||||
NOTICE: TCG_EfiSpecIDEvent:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 3
|
||||
NOTICE: Digest : 00
|
||||
NOTICE: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
NOTICE: : 00 00 00
|
||||
NOTICE: EventSize : 33
|
||||
NOTICE: Signature : Spec ID Event03
|
||||
NOTICE: PlatformClass : 0
|
||||
NOTICE: SpecVersion : 2.0.2
|
||||
NOTICE: UintnSize : 1
|
||||
NOTICE: NumberOfAlgorithms : 1
|
||||
NOTICE: DigestSizes :
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: DigestSize : 32
|
||||
NOTICE: VendorInfoSize : 0
|
||||
NOTICE: PCR_Event2:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 3
|
||||
NOTICE: Digests Count : 1
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: Digest : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
NOTICE: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
NOTICE: EventSize : 17
|
||||
NOTICE: Signature : StartupLocality
|
||||
NOTICE: StartupLocality : 0
|
||||
NOTICE: PCR_Event2:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 1
|
||||
NOTICE: Digests Count : 1
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: Digest : 58 26 32 6e 64 45 64 da 45 de 35 db 96 fd ed 63
|
||||
NOTICE: : 2a 6a d4 0d aa 94 b0 b1 55 e4 72 e7 1f 0a e0 d5
|
||||
NOTICE: EventSize : 5
|
||||
NOTICE: Event : BL_2
|
||||
NOTICE: PCR_Event2:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 1
|
||||
NOTICE: Digests Count : 1
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: Digest : cf f9 7d a3 5c 73 ac cb 7b a0 25 80 6a 6e 50 a5
|
||||
NOTICE: : 6b 2e d2 8c c9 36 92 7d 46 c5 b9 c3 a4 6c 51 7c
|
||||
NOTICE: EventSize : 6
|
||||
NOTICE: Event : BL_31
|
||||
NOTICE: PCR_Event2:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 1
|
||||
NOTICE: Digests Count : 1
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: Digest : 23 b0 a3 5d 54 d9 43 1a 5c b9 89 63 1c da 06 c2
|
||||
NOTICE: : e5 de e7 7e 99 17 52 12 7d f7 45 ca 4f 4a 39 c0
|
||||
NOTICE: EventSize : 10
|
||||
NOTICE: Event : HW_CONFIG
|
||||
NOTICE: PCR_Event2:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 1
|
||||
NOTICE: Digests Count : 1
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: Digest : 4e e4 8e 5a e6 50 ed e0 b5 a3 54 8a 1f d6 0e 8a
|
||||
NOTICE: : ea 0e 71 75 0e a4 3f 82 76 ce af cd 7c b0 91 e0
|
||||
NOTICE: EventSize : 14
|
||||
NOTICE: Event : SOC_FW_CONFIG
|
||||
NOTICE: PCR_Event2:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 1
|
||||
NOTICE: Digests Count : 1
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: Digest : 01 b0 80 47 a1 ce 86 cd df 89 d2 1f 2e fc 6c 22
|
||||
NOTICE: : f8 19 ec 6e 1e ec 73 ba 5a be d0 96 e3 5f 6d 75
|
||||
NOTICE: EventSize : 6
|
||||
NOTICE: Event : BL_32
|
||||
NOTICE: PCR_Event2:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 1
|
||||
NOTICE: Digests Count : 1
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: Digest : 5d c6 ef 35 5a 90 81 b4 37 e6 3b 52 da 92 ab 8e
|
||||
NOTICE: : d9 6e 93 98 2d 40 87 96 1b 5a a7 ee f1 f4 40 63
|
||||
NOTICE: EventSize : 18
|
||||
NOTICE: Event : BL32_EXTRA1_IMAGE
|
||||
NOTICE: PCR_Event2:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 1
|
||||
NOTICE: Digests Count : 1
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: Digest : 39 b7 13 b9 93 db 32 2f 1b 48 30 eb 2c f2 5c 25
|
||||
NOTICE: : 00 0f 38 dc 8e c8 02 cd 79 f2 48 d2 2c 25 ab e2
|
||||
NOTICE: EventSize : 6
|
||||
NOTICE: Event : BL_33
|
||||
NOTICE: PCR_Event2:
|
||||
NOTICE: PCRIndex : 0
|
||||
NOTICE: EventType : 1
|
||||
NOTICE: Digests Count : 1
|
||||
NOTICE: #0 AlgorithmId : SHA256
|
||||
NOTICE: Digest : 25 10 60 5d d4 bc 9d 82 7a 16 9f 8a cc 47 95 a6
|
||||
NOTICE: : fd ca a0 c1 2b c9 99 8f 51 20 ff c6 ed 74 68 5a
|
||||
NOTICE: EventSize : 13
|
||||
NOTICE: Event : NT_FW_CONFIG
|
||||
NOTICE: BL1: Booting BL31
|
||||
NOTICE: BL31: v2.5(release):v2.5
|
||||
NOTICE: BL31: Built : 10:41:20, Jul 2 2021
|
||||
|
||||
Following up with the fTPM startup process, we can see that all the
|
||||
measurements in the Event Log are extended and recorded in the appropriate PCR:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
M/TA: TPM2_PCR_EXTEND_COMMAND returned value:
|
||||
M/TA: ret_tag = 0x8002, size = 0x00000013, rc = 0x00000000
|
||||
M/TA: TPM2_PCR_EXTEND_COMMAND returned value:
|
||||
M/TA: ret_tag = 0x8002, size = 0x00000013, rc = 0x00000000
|
||||
M/TA: TPM2_PCR_EXTEND_COMMAND returned value:
|
||||
M/TA: ret_tag = 0x8002, size = 0x00000013, rc = 0x00000000
|
||||
M/TA: TPM2_PCR_EXTEND_COMMAND returned value:
|
||||
M/TA: ret_tag = 0x8002, size = 0x00000013, rc = 0x00000000
|
||||
M/TA: TPM2_PCR_EXTEND_COMMAND returned value:
|
||||
M/TA: ret_tag = 0x8002, size = 0x00000013, rc = 0x00000000
|
||||
M/TA: TPM2_PCR_EXTEND_COMMAND returned value:
|
||||
M/TA: ret_tag = 0x8002, size = 0x00000013, rc = 0x00000000
|
||||
M/TA: TPM2_PCR_EXTEND_COMMAND returned value:
|
||||
M/TA: ret_tag = 0x8002, size = 0x00000013, rc = 0x00000000
|
||||
M/TA: TPM2_PCR_EXTEND_COMMAND returned value:
|
||||
M/TA: ret_tag = 0x8002, size = 0x00000013, rc = 0x00000000
|
||||
M/TA: TPM2_PCR_EXTEND_COMMAND returned value:
|
||||
M/TA: ret_tag = 0x8002, size = 0x00000013, rc = 0x00000000
|
||||
M/TA: 9 Event logs processed
|
||||
|
||||
After the fTPM TA is loaded, the call to ``insmod`` issued by the ``ftpm``
|
||||
alias to load the ftpm kernel module returns, and then the TPM PCRs are read
|
||||
by means of ``tpm_pcrread`` command. Note that we are only interested in the
|
||||
SHA256 logs here, as this is the algorithm we used on TF-A for the measurements
|
||||
(see the field ``AlgorithmId`` on the logs above):
|
||||
|
||||
.. code:: shell
|
||||
|
||||
sha256:
|
||||
0 : 0xA6EB3A7417B8CFA9EBA2E7C22AD5A4C03CDB8F3FBDD7667F9C3EF2EA285A8C9F
|
||||
1 : 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
2 : 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
3 : 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
4 : 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
5 : 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
6 : 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
7 : 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
8 : 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
9 : 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
10: 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
11: 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
12: 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
13: 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
14: 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
15: 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
16: 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
17: 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
||||
18: 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
||||
19: 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
||||
20: 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
||||
21: 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
||||
22: 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
||||
23: 0x0000000000000000000000000000000000000000000000000000000000000000
|
||||
|
||||
In this PoC we are only interested in PCR0, which must be non-null. This is
|
||||
because the boot process records all the images in this PCR (see field ``PCRIndex``
|
||||
on the Event Log above). The rest of the records must be 0 at this point.
|
||||
|
||||
.. note::
|
||||
The fTPM service used has support only for 16 PCRs, therefore the content
|
||||
of PCRs above 15 can be ignored.
|
||||
|
||||
.. note::
|
||||
As stated earlier, Arm does not provide an fTPM implementation and therefore
|
||||
we do not validate here if the content of PCR0 is correct or not. For this
|
||||
PoC, we are only focused on the fact that the event log could be passed to a third
|
||||
party fTPM and its records were properly extended.
|
||||
|
||||
Fine-tuning the fTPM TA
|
||||
~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
As stated earlier, the OP-TEE Toolkit includes support to build a third party fTPM
|
||||
service. The build options for this service are tailored for the PoC and defined in
|
||||
the build environment variable ``FTPM_FLAGS`` (see ``<toolkit_home>/build/common.mk``)
|
||||
but they can be modified if needed to better adapt it to a specific scenario.
|
||||
|
||||
The most relevant options for Measured Boot support are:
|
||||
|
||||
- **CFG_TA_DEBUG**: Enables debug logs in the Terminal_1 console.
|
||||
- **CFG_TEE_TA_LOG_LEVEL**: Defines the log level used for the debug messages.
|
||||
- **CFG_TA_MEASURED_BOOT**: Enables support for measured boot on the fTPM.
|
||||
- **CFG_TA_EVENT_LOG_SIZE**: Defines the size, in bytes, of the larger event log that
|
||||
the fTPM is able to store, as this buffer is allocated at build time. This must be at
|
||||
least the same as the size of the event log generated by TF-A. If this build option
|
||||
is not defined, the fTPM falls back to a default value of 1024 bytes, which is enough
|
||||
for this PoC, so this variable is not defined in FTPM_FLAGS.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2021, Arm Limited. All rights reserved.*
|
||||
|
||||
.. _OP-TEE Toolkit: https://github.com/OP-TEE/build
|
||||
.. _ms-tpm-20-ref: https://github.com/microsoft/ms-tpm-20-ref
|
||||
.. _Get and build the solution: https://optee.readthedocs.io/en/latest/building/gits/build.html#get-and-build-the-solution
|
||||
.. _Armv8-A Foundation Platform (For Linux Hosts Only): https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models
|
||||
.. _tpm2-tools: https://github.com/tpm2-software/tpm2-tools
|
||||
.. _TGC event log: https://trustedcomputinggroup.org/resource/tcg-efi-platform-specification/
|
||||
1168
arm-trusted-firmware/docs/getting_started/build-options.rst
Normal file
1168
arm-trusted-firmware/docs/getting_started/build-options.rst
Normal file
File diff suppressed because it is too large
Load Diff
112
arm-trusted-firmware/docs/getting_started/docs-build.rst
Normal file
112
arm-trusted-firmware/docs/getting_started/docs-build.rst
Normal file
@@ -0,0 +1,112 @@
|
||||
Building Documentation
|
||||
======================
|
||||
|
||||
To create a rendered copy of this documentation locally you can use the
|
||||
`Sphinx`_ tool to build and package the plain-text documents into HTML-formatted
|
||||
pages.
|
||||
|
||||
If you are building the documentation for the first time then you will need to
|
||||
check that you have the required software packages, as described in the
|
||||
*Prerequisites* section that follows.
|
||||
|
||||
.. note::
|
||||
An online copy of the documentation is available at
|
||||
https://www.trustedfirmware.org/docs/tf-a, if you want to view a rendered
|
||||
copy without doing a local build.
|
||||
|
||||
Prerequisites
|
||||
-------------
|
||||
|
||||
For building a local copy of the |TF-A| documentation you will need:
|
||||
|
||||
- Python 3 (3.5 or later)
|
||||
- PlantUML (1.2017.15 or later)
|
||||
- Python modules specified in ``docs/requirements.txt``
|
||||
|
||||
You can install these with ``pip3`` (the Python Package Installer) by
|
||||
passing it the requirements file above (with ``-r``). An optional ``--user``
|
||||
argument will install them locally, but you have to add their location to
|
||||
$PATH (pip will emit a warning). Alternatively, they can be installed
|
||||
globally (but will probably require root privileges).
|
||||
|
||||
.. note::
|
||||
Although not necessary, it is recommended you use a virtual environment.
|
||||
More advanced usage instructions for *pip* are beyond the scope of this
|
||||
document but you can refer to the `pip homepage`_ for detailed guides.
|
||||
|
||||
- Optionally, the `Dia`_ application can be installed if you need to edit
|
||||
existing ``.dia`` diagram files, or create new ones.
|
||||
|
||||
An example set of installation commands for Ubuntu follows, assuming that the
|
||||
working directory is ``docs``:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
sudo apt install python3 python3-pip plantuml [dia]
|
||||
pip3 install [--user] -r requirements.txt
|
||||
|
||||
.. note::
|
||||
Several other modules will be installed as dependencies. Please review
|
||||
the list to ensure that there will be no conflicts with other modules already
|
||||
installed in your environment.
|
||||
|
||||
Building rendered documentation
|
||||
-------------------------------
|
||||
|
||||
Documents can be built into HTML-formatted pages from project root directory by
|
||||
running the following command.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make doc
|
||||
|
||||
Output from the build process will be placed in:
|
||||
|
||||
::
|
||||
|
||||
docs/build/html
|
||||
|
||||
We also support building documentation in other formats. From the ``docs``
|
||||
directory of the project, run the following command to see the supported
|
||||
formats. It is important to note that you will not get the correct result if
|
||||
the command is run from the project root directory, as that would invoke the
|
||||
top-level Makefile for |TF-A| itself.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make help
|
||||
|
||||
Building rendered documentation from a container
|
||||
------------------------------------------------
|
||||
|
||||
There may be cases where you can not either install or upgrade required
|
||||
dependencies to generate the documents, so in this case, one way to
|
||||
create the documentation is through a docker container. The first step is
|
||||
to check if `docker`_ is installed in your host, otherwise check main docker
|
||||
page for installation instructions. Once installed, run the following script
|
||||
from project root directory
|
||||
|
||||
.. code:: shell
|
||||
|
||||
docker run --rm -v $PWD:/TF sphinxdoc/sphinx \
|
||||
bash -c 'cd /TF && \
|
||||
pip3 install plantuml -r ./docs/requirements.txt && make doc'
|
||||
|
||||
The above command fetches the ``sphinxdoc/sphinx`` container from `docker
|
||||
hub`_, launches the container, installs documentation requirements and finally
|
||||
creates the documentation. Once done, exit the container and output from the
|
||||
build process will be placed in:
|
||||
|
||||
::
|
||||
|
||||
docs/build/html
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019, Arm Limited. All rights reserved.*
|
||||
|
||||
.. _Sphinx: http://www.sphinx-doc.org/en/master/
|
||||
.. _pip homepage: https://pip.pypa.io/en/stable/
|
||||
.. _Dia: https://wiki.gnome.org/Apps/Dia
|
||||
.. _docker: https://www.docker.com/
|
||||
.. _docker hub: https://hub.docker.com/repository/docker/sphinxdoc/sphinx
|
||||
192
arm-trusted-firmware/docs/getting_started/image-terminology.rst
Normal file
192
arm-trusted-firmware/docs/getting_started/image-terminology.rst
Normal file
@@ -0,0 +1,192 @@
|
||||
Image Terminology
|
||||
=================
|
||||
|
||||
This page contains the current name, abbreviated name and purpose of the various
|
||||
images referred to in the Trusted Firmware project.
|
||||
|
||||
Common Image Features
|
||||
---------------------
|
||||
|
||||
- Some of the names and abbreviated names have changed to accommodate new
|
||||
requirements. The changed names are as backward compatible as possible to
|
||||
minimize confusion. Where applicable, the previous names are indicated. Some
|
||||
code, documentation and build artefacts may still refer to the previous names;
|
||||
these will inevitably take time to catch up.
|
||||
|
||||
- The main name change is to prefix each image with the processor it corresponds
|
||||
to (for example ``AP_``, ``SCP_``, ...). In situations where there is no
|
||||
ambiguity (for example, within AP specific code/documentation), it is
|
||||
permitted to omit the processor prefix (for example, just BL1 instead of
|
||||
``AP_BL1``).
|
||||
|
||||
- Previously, the format for 3rd level images had 2 forms; ``BL3`` was either
|
||||
suffixed with a dash ("-") followed by a number (for example, ``BL3-1``) or a
|
||||
subscript number, depending on whether rich text formatting was available.
|
||||
This was confusing and often the dash gets omitted in practice. Therefore the
|
||||
new form is to just omit the dash and not use subscript formatting.
|
||||
|
||||
- The names no longer contain dash ("-") characters at all. In some places (for
|
||||
example, function names) it's not possible to use this character. All dashes
|
||||
are either removed or replaced by underscores ("_").
|
||||
|
||||
- The abbreviation BL stands for BootLoader. This is a historical anomaly.
|
||||
Clearly, many of these images are not BootLoaders, they are simply firmware
|
||||
images. However, the BL abbreviation is now widely used and is retained for
|
||||
backwards compatibility.
|
||||
|
||||
- The image names are not case sensitive. For example, ``bl1`` is
|
||||
interchangeable with ``BL1``, although mixed case should be avoided.
|
||||
|
||||
Trusted Firmware Images
|
||||
-----------------------
|
||||
|
||||
Firmware Image Package: ``FIP``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This is a packaging format used by TF-A to package firmware images in a single
|
||||
binary. The number and type of images that should be packed in a FIP is
|
||||
platform-specific and may include TF-A images and other firmware images
|
||||
required by the platform. For example, most platforms require a BL33 image
|
||||
which corresponds to the normal world bootloader (e.g. UEFI or U-Boot).
|
||||
|
||||
AP Boot ROM: ``AP_BL1``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Typically, this is the first code to execute on the AP and cannot be modified.
|
||||
Its primary purpose is to perform the minimum initialization necessary to load
|
||||
and authenticate an updateable AP firmware image into an executable RAM
|
||||
location, then hand-off control to that image.
|
||||
|
||||
AP RAM Firmware: ``AP_BL2``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This is the 2nd stage AP firmware. It is currently also known as the "Trusted
|
||||
Boot Firmware". Its primary purpose is to perform any additional initialization
|
||||
required to load and authenticate all 3rd level firmware images into their
|
||||
executable RAM locations, then hand-off control to the EL3 Runtime Firmware.
|
||||
|
||||
EL3 Runtime Firmware: ``AP_BL31``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Also known as "SoC AP firmware" or "EL3 monitor firmware". Its primary purpose
|
||||
is to handle transitions between the normal and secure world.
|
||||
|
||||
Secure-EL1 Payload (SP): ``AP_BL32``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Typically this is a TEE or Trusted OS, providing runtime secure services to the
|
||||
normal world. However, it may refer to a more abstract Secure-EL1 Payload (SP).
|
||||
Note that this abbreviation should only be used in systems where there is a
|
||||
single or primary image executing at Secure-EL1. In systems where there are
|
||||
potentially multiple SPs and there is no concept of a primary SP, this
|
||||
abbreviation should be avoided; use the recommended **Other AP 3rd level
|
||||
images** abbreviation instead.
|
||||
|
||||
AP Normal World Firmware: ``AP_BL33``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
For example, UEFI or uboot. Its primary purpose is to boot a normal world OS.
|
||||
|
||||
Other AP 3rd level images: ``AP_BL3_XXX``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The abbreviated names of the existing 3rd level images imply a load/execution
|
||||
ordering (for example, ``AP_BL31 -> AP_BL32 -> AP_BL33``). Some systems may
|
||||
have additional images and/or a different load/execution ordering. The
|
||||
abbreviated names of the existing images are retained for backward compatibility
|
||||
but new 3rd level images should be suffixed with an underscore followed by text
|
||||
identifier, not a number.
|
||||
|
||||
In systems where 3rd level images are provided by different vendors, the
|
||||
abbreviated name should identify the vendor as well as the image
|
||||
function. For example, ``AP_BL3_ARM_RAS``.
|
||||
|
||||
Realm Monitor Management Firmware: ``RMM``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This is the Realm-EL2 firmware. It is required if
|
||||
:ref:`Realm Management Extension (RME)` feature is enabled. If a path to RMM
|
||||
image is not provided, TF-A builds Test Realm Payload (TRP) image by default
|
||||
and uses it as the RMM image.
|
||||
|
||||
SCP Boot ROM: ``SCP_BL1`` (previously ``BL0``)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Typically, this is the first code to execute on the SCP and cannot be modified.
|
||||
Its primary purpose is to perform the minimum initialization necessary to load
|
||||
and authenticate an updateable SCP firmware image into an executable RAM
|
||||
location, then hand-off control to that image. This may be performed in
|
||||
conjunction with other processor firmware (for example, ``AP_BL1`` and
|
||||
``AP_BL2``).
|
||||
|
||||
This image was previously abbreviated as ``BL0`` but in some systems, the SCP
|
||||
may directly load/authenticate its own firmware. In these systems, it doesn't
|
||||
make sense to interleave the image terminology for AP and SCP; both AP and SCP
|
||||
Boot ROMs are ``BL1`` from their own point of view.
|
||||
|
||||
SCP RAM Firmware: ``SCP_BL2`` (previously ``BL3-0``)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This is the 2nd stage SCP firmware. It is currently also known as the "SCP
|
||||
runtime firmware" but it could potentially be an intermediate firmware if the
|
||||
SCP needs to load/authenticate multiple 3rd level images in future.
|
||||
|
||||
This image was previously abbreviated as BL3-0 but from the SCP's point of view,
|
||||
this has always been the 2nd stage firmware. The previous name is too
|
||||
AP-centric.
|
||||
|
||||
Firmware Update (FWU) Images
|
||||
----------------------------
|
||||
|
||||
The terminology for these images has not been widely adopted yet but they have
|
||||
to be considered in a production Trusted Board Boot solution.
|
||||
|
||||
AP Firmware Update Boot ROM: ``AP_NS_BL1U``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Typically, this is the first normal world code to execute on the AP during a
|
||||
firmware update operation, and cannot be modified. Its primary purpose is to
|
||||
load subsequent firmware update images from an external interface and communicate
|
||||
with ``AP_BL1`` to authenticate those images.
|
||||
|
||||
During firmware update, there are (potentially) multiple transitions between the
|
||||
secure and normal world. The "level" of the BL image is relative to the world
|
||||
it's in so it makes sense to encode "NS" in the normal world images. The absence
|
||||
of "NS" implies a secure world image.
|
||||
|
||||
AP Firmware Update Config: ``AP_BL2U``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This image does the minimum necessary AP secure world configuration required to
|
||||
complete the firmware update operation. It is potentially a subset of ``AP_BL2``
|
||||
functionality.
|
||||
|
||||
SCP Firmware Update Config: ``SCP_BL2U`` (previously ``BL2-U0``)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This image does the minimum necessary SCP secure world configuration required to
|
||||
complete the firmware update operation. It is potentially a subset of
|
||||
``SCP_BL2`` functionality.
|
||||
|
||||
AP Firmware Updater: ``AP_NS_BL2U`` (previously ``BL3-U``)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This is the 2nd stage AP normal world firmware updater. Its primary purpose is
|
||||
to load a new set of firmware images from an external interface and write them
|
||||
into non-volatile storage.
|
||||
|
||||
Other Processor Firmware Images
|
||||
-------------------------------
|
||||
|
||||
Some systems may have additional processors to the AP and SCP. For example, a
|
||||
Management Control Processor (MCP). Images for these processors should follow
|
||||
the same terminology, with the processor abbreviation prefix, followed by
|
||||
underscore and the level of the firmware image.
|
||||
|
||||
For example,
|
||||
|
||||
MCP Boot ROM: ``MCP_BL1``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
MCP RAM Firmware: ``MCP_BL2``
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
20
arm-trusted-firmware/docs/getting_started/index.rst
Normal file
20
arm-trusted-firmware/docs/getting_started/index.rst
Normal file
@@ -0,0 +1,20 @@
|
||||
Getting Started
|
||||
===============
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Contents
|
||||
|
||||
prerequisites
|
||||
docs-build
|
||||
initial-build
|
||||
tools-build
|
||||
build-options
|
||||
image-terminology
|
||||
porting-guide
|
||||
psci-lib-integration-guide
|
||||
rt-svc-writers-guide
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019, Arm Limited. All rights reserved.*
|
||||
118
arm-trusted-firmware/docs/getting_started/initial-build.rst
Normal file
118
arm-trusted-firmware/docs/getting_started/initial-build.rst
Normal file
@@ -0,0 +1,118 @@
|
||||
Performing an Initial Build
|
||||
===========================
|
||||
|
||||
- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
|
||||
to your cross compiler.
|
||||
|
||||
For AArch64:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
|
||||
|
||||
For AArch32:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-none-eabi-
|
||||
|
||||
It is possible to build TF-A using Clang or Arm Compiler 6. To do so
|
||||
``CC`` needs to point to the clang or armclang binary, which will
|
||||
also select the clang or armclang assembler. Arm Compiler 6 will be selected
|
||||
when the base name of the path assigned to ``CC`` matches the string
|
||||
'armclang'. GNU binutils are required since the TF-A build system doesn't
|
||||
currently support Arm Scatter files. Meaning the GNU linker is used by
|
||||
default for Arm Compiler 6. Because of this dependency, ``CROSS_COMPILE``
|
||||
should be set as described above.
|
||||
|
||||
For AArch64 using Arm Compiler 6:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
|
||||
make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
|
||||
|
||||
On the other hand, Clang uses LLVM linker (LLD) and other LLVM binutils by
|
||||
default instead of GNU utilities (LLVM linker (LLD) 14.0.0 is known to
|
||||
work with TF-A). ``CROSS_COMPILE`` need not be set for Clang. Please note,
|
||||
that the default linker may be manually overridden using the ``LD`` variable.
|
||||
|
||||
Clang will be selected when the base name of the path assigned to ``CC``
|
||||
contains the string 'clang'. This is to allow both clang and clang-X.Y
|
||||
to work.
|
||||
|
||||
For AArch64 using clang:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make CC=<path-to-clang>/bin/clang PLAT=<platform> all
|
||||
|
||||
- Change to the root directory of the TF-A source tree and build.
|
||||
|
||||
For AArch64:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=<platform> all
|
||||
|
||||
For AArch32:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
|
||||
|
||||
Notes:
|
||||
|
||||
- If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
|
||||
:ref:`Build Options` document for more information on available build
|
||||
options.
|
||||
|
||||
- (AArch32 only) Currently only ``PLAT=fvp`` is supported.
|
||||
|
||||
- (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
|
||||
corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
|
||||
provided by TF-A to demonstrate how PSCI Library can be integrated with
|
||||
an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
|
||||
include other runtime services, for example Trusted OS services. A guide
|
||||
to integrate PSCI library with AArch32 EL3 Runtime Software can be found
|
||||
at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
|
||||
|
||||
- (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
|
||||
image, is not compiled in by default. Refer to the
|
||||
:ref:`Test Secure Payload (TSP) and Dispatcher (TSPD)` document for
|
||||
details on building the TSP.
|
||||
|
||||
- By default this produces a release version of the build. To produce a
|
||||
debug version instead, refer to the "Debugging options" section below.
|
||||
|
||||
- The build process creates products in a ``build`` directory tree, building
|
||||
the objects and binaries for each boot loader stage in separate
|
||||
sub-directories. The following boot loader binary files are created
|
||||
from the corresponding ELF files:
|
||||
|
||||
- ``build/<platform>/<build-type>/bl1.bin``
|
||||
- ``build/<platform>/<build-type>/bl2.bin``
|
||||
- ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
|
||||
- ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
|
||||
|
||||
where ``<platform>`` is the name of the chosen platform and ``<build-type>``
|
||||
is either ``debug`` or ``release``. The actual number of images might differ
|
||||
depending on the platform.
|
||||
|
||||
- Build products for a specific build variant can be removed using:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make DEBUG=<D> PLAT=<platform> clean
|
||||
|
||||
... where ``<D>`` is ``0`` or ``1``, as specified when building.
|
||||
|
||||
The build tree can be removed completely using:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make realclean
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2020-2022, Arm Limited. All rights reserved.*
|
||||
3580
arm-trusted-firmware/docs/getting_started/porting-guide.rst
Normal file
3580
arm-trusted-firmware/docs/getting_started/porting-guide.rst
Normal file
File diff suppressed because it is too large
Load Diff
181
arm-trusted-firmware/docs/getting_started/prerequisites.rst
Normal file
181
arm-trusted-firmware/docs/getting_started/prerequisites.rst
Normal file
@@ -0,0 +1,181 @@
|
||||
Prerequisites
|
||||
=============
|
||||
|
||||
This document describes the software requirements for building |TF-A| for
|
||||
AArch32 and AArch64 target platforms.
|
||||
|
||||
It may possible to build |TF-A| with combinations of software packages that are
|
||||
different from those listed below, however only the software described in this
|
||||
document can be officially supported.
|
||||
|
||||
Build Host
|
||||
----------
|
||||
|
||||
|TF-A| can be built using either a Linux or a Windows machine as the build host.
|
||||
|
||||
A relatively recent Linux distribution is recommended for building |TF-A|. We
|
||||
have performed tests using Ubuntu 20.04 LTS (64-bit) but other distributions
|
||||
should also work fine as a base, provided that the necessary tools and libraries
|
||||
can be installed.
|
||||
|
||||
.. _prerequisites_toolchain:
|
||||
|
||||
Toolchain
|
||||
---------
|
||||
|
||||
|TF-A| can be built with any of the following *cross-compiler* toolchains that
|
||||
target the Armv7-A or Armv8-A architectures:
|
||||
|
||||
- GCC >= 11.3.Rel1 (from the `Arm Developer website`_)
|
||||
|
||||
You will need the targets ``arm-none-eabi`` and ``aarch64-none-elf`` for
|
||||
AArch32 and AArch64 builds respectively.
|
||||
|
||||
- Clang >= 14.0.0
|
||||
- Arm Compiler >= 6.18
|
||||
|
||||
In addition, a native compiler is required to build the supporting tools.
|
||||
|
||||
.. note::
|
||||
The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
|
||||
Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
|
||||
|
||||
.. note::
|
||||
For instructions on how to select the cross compiler refer to
|
||||
:ref:`Performing an Initial Build`.
|
||||
|
||||
.. _prerequisites_software_and_libraries:
|
||||
|
||||
Software and Libraries
|
||||
----------------------
|
||||
|
||||
The following tools are required to obtain and build |TF-A|:
|
||||
|
||||
- An appropriate toolchain (see :ref:`prerequisites_toolchain`)
|
||||
- GNU Make
|
||||
- Git
|
||||
|
||||
The following libraries must be available to build one or more components or
|
||||
supporting tools:
|
||||
|
||||
- OpenSSL >= 1.1.1 (v3.0.0 to v3.0.6 highly discouraged due to security issues)
|
||||
|
||||
Required to build the cert_create, encrypt_fw, and fiptool tools.
|
||||
|
||||
.. note::
|
||||
|
||||
If using OpenSSL 3, older Linux versions may require it to be built from
|
||||
source code, as it may not be available in the default package repositories.
|
||||
Please refer to the OpenSSL project documentation for more information.
|
||||
|
||||
The following libraries are required for Trusted Board Boot and Measured Boot
|
||||
support:
|
||||
|
||||
- mbed TLS == 2.28.1 (tag: ``mbedtls-2.28.1``)
|
||||
|
||||
These tools are optional:
|
||||
|
||||
- Device Tree Compiler (DTC) >= 1.4.6
|
||||
|
||||
Needed if you want to rebuild the provided Flattened Device Tree (FDT)
|
||||
source files (``.dts`` files). DTC is available for Linux through the package
|
||||
repositories of most distributions.
|
||||
|
||||
- Arm `Development Studio (Arm-DS)`_
|
||||
|
||||
The standard software package used for debugging software on Arm development
|
||||
platforms and |FVP| models.
|
||||
|
||||
- Node.js >= 16
|
||||
|
||||
Highly recommended, and necessary in order to install and use the packaged
|
||||
Git hooks and helper tools. Without these tools you will need to rely on the
|
||||
CI for feedback on commit message conformance.
|
||||
|
||||
Package Installation (Linux)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
If you are using the recommended Ubuntu distribution then you can install the
|
||||
required packages with the following command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
sudo apt install build-essential git
|
||||
|
||||
The optional packages can be installed using:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
sudo apt install device-tree-compiler
|
||||
|
||||
Additionally, to install a version of Node.js compatible with TF-A's repository
|
||||
scripts, you can use the `Node Version Manager`_. To install both NVM and an
|
||||
appropriate version of Node.js, run the following **from the root directory of
|
||||
the repository**:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
curl -o- https://raw.githubusercontent.com/nvm-sh/nvm/v0.39.1/install.sh | bash
|
||||
exec "$SHELL" -ic "nvm install; exec $SHELL"
|
||||
|
||||
.. _Node Version Manager: https://github.com/nvm-sh/nvm#install--update-script
|
||||
|
||||
Supporting Files
|
||||
----------------
|
||||
|
||||
TF-A has been tested with pre-built binaries and file systems from `Linaro
|
||||
Release 20.01`_. Alternatively, you can build the binaries from source using
|
||||
instructions in :ref:`Performing an Initial Build`.
|
||||
|
||||
.. _prerequisites_get_source:
|
||||
|
||||
Getting the TF-A Source
|
||||
-----------------------
|
||||
|
||||
Source code for |TF-A| is maintained in a Git repository hosted on
|
||||
TrustedFirmware.org. To clone this repository from the server, run the following
|
||||
in your shell:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
|
||||
|
||||
Additional Steps for Contributors
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
If you are planning on contributing back to TF-A, there are some things you'll
|
||||
want to know.
|
||||
|
||||
TF-A is hosted by a `Gerrit Code Review`_ server. Gerrit requires that all
|
||||
commits include a ``Change-Id`` footer, and this footer is typically
|
||||
automatically generated by a Git hook installed by you, the developer.
|
||||
|
||||
If you have Node.js installed already, you can automatically install this hook,
|
||||
along with any additional hooks and Javascript-based tooling that we use, by
|
||||
running from within your newly-cloned repository:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
npm install --no-save
|
||||
|
||||
If you have opted **not** to install Node.js, you can install the Gerrit hook
|
||||
manually by running:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
curl -Lo $(git rev-parse --git-dir)/hooks/commit-msg https://review.trustedfirmware.org/tools/hooks/commit-msg
|
||||
chmod +x $(git rev-parse --git-dir)/hooks/commit-msg
|
||||
|
||||
You can read more about Git hooks in the *githooks* page of the Git
|
||||
documentation, available `here <https://git-scm.com/docs/githooks>`_.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2021-2022, Arm Limited. All rights reserved.*
|
||||
|
||||
.. _Arm Developer website: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
|
||||
.. _Gerrit Code Review: https://www.gerritcodereview.com/
|
||||
.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
|
||||
.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
|
||||
.. _Development Studio (Arm-DS): https://developer.arm.com/Tools%20and%20Software/Arm%20Development%20Studio
|
||||
.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
|
||||
@@ -0,0 +1,536 @@
|
||||
PSCI Library Integration guide for Armv8-A AArch32 systems
|
||||
==========================================================
|
||||
|
||||
This document describes the PSCI library interface with a focus on how to
|
||||
integrate with a suitable Trusted OS for an Armv8-A AArch32 system. The PSCI
|
||||
Library implements the PSCI Standard as described in `PSCI spec`_ and is meant
|
||||
to be integrated with EL3 Runtime Software which invokes the PSCI Library
|
||||
interface appropriately. **EL3 Runtime Software** refers to software executing
|
||||
at the highest secure privileged mode, which is EL3 in AArch64 or Secure SVC/
|
||||
Monitor mode in AArch32, and provides runtime services to the non-secure world.
|
||||
The runtime service request is made via SMC (Secure Monitor Call) and the call
|
||||
must adhere to `SMCCC`_. In AArch32, EL3 Runtime Software may additionally
|
||||
include Trusted OS functionality. A minimal AArch32 Secure Payload, SP-MIN, is
|
||||
provided in Trusted Firmware-A (TF-A) to illustrate the usage and integration
|
||||
of the PSCI library. The description of PSCI library interface and its
|
||||
integration with EL3 Runtime Software in this document is targeted towards
|
||||
AArch32 systems.
|
||||
|
||||
Generic call sequence for PSCI Library interface (AArch32)
|
||||
----------------------------------------------------------
|
||||
|
||||
The generic call sequence of PSCI Library interfaces (see
|
||||
`PSCI Library Interface`_) during cold boot in AArch32
|
||||
system is described below:
|
||||
|
||||
#. After cold reset, the EL3 Runtime Software performs its cold boot
|
||||
initialization including the PSCI library pre-requisites mentioned in
|
||||
`PSCI Library Interface`_, and also the necessary platform
|
||||
setup.
|
||||
|
||||
#. Call ``psci_setup()`` in Monitor mode.
|
||||
|
||||
#. Optionally call ``psci_register_spd_pm_hook()`` to register callbacks to
|
||||
do bookkeeping for the EL3 Runtime Software during power management.
|
||||
|
||||
#. Call ``psci_prepare_next_non_secure_ctx()`` to initialize the non-secure CPU
|
||||
context.
|
||||
|
||||
#. Get the non-secure ``cpu_context_t`` for the current CPU by calling
|
||||
``cm_get_context()`` , then programming the registers in the non-secure
|
||||
context and exiting to non-secure world. If the EL3 Runtime Software needs
|
||||
additional configuration to be set for non-secure context, like routing
|
||||
FIQs to the secure world, the values of the registers can be modified prior
|
||||
to programming. See `PSCI CPU context management`_ for more
|
||||
details on CPU context management.
|
||||
|
||||
The generic call sequence of PSCI library interfaces during warm boot in
|
||||
AArch32 systems is described below:
|
||||
|
||||
#. After warm reset, the EL3 Runtime Software performs the necessary warm
|
||||
boot initialization including the PSCI library pre-requisites mentioned in
|
||||
`PSCI Library Interface`_ (Note that the Data cache
|
||||
**must not** be enabled).
|
||||
|
||||
#. Call ``psci_warmboot_entrypoint()`` in Monitor mode. This interface
|
||||
initializes/restores the non-secure CPU context as well.
|
||||
|
||||
#. Do step 5 of the cold boot call sequence described above.
|
||||
|
||||
The generic call sequence of PSCI library interfaces on receipt of a PSCI SMC
|
||||
on an AArch32 system is described below:
|
||||
|
||||
#. On receipt of an SMC, save the register context as per `SMCCC`_.
|
||||
|
||||
#. If the SMC function identifier corresponds to a SMC32 PSCI API, construct
|
||||
the appropriate arguments and call the ``psci_smc_handler()`` interface.
|
||||
The invocation may or may not return back to the caller depending on
|
||||
whether the PSCI API resulted in power down of the CPU.
|
||||
|
||||
#. If ``psci_smc_handler()`` returns, populate the return value in R0 (AArch32)/
|
||||
X0 (AArch64) and restore other registers as per `SMCCC`_.
|
||||
|
||||
PSCI CPU context management
|
||||
---------------------------
|
||||
|
||||
PSCI library is in charge of initializing/restoring the non-secure CPU system
|
||||
registers according to `PSCI specification`_ during cold/warm boot.
|
||||
This is referred to as ``PSCI CPU Context Management``. Registers that need to
|
||||
be preserved across CPU power down/power up cycles are maintained in
|
||||
``cpu_context_t`` data structure. The initialization of other non-secure CPU
|
||||
system registers which do not require coordination with the EL3 Runtime
|
||||
Software is done directly by the PSCI library (see ``cm_prepare_el3_exit()``).
|
||||
|
||||
The EL3 Runtime Software is responsible for managing register context
|
||||
during switch between Normal and Secure worlds. The register context to be
|
||||
saved and restored depends on the mechanism used to trigger the world switch.
|
||||
For example, if the world switch was triggered by an SMC call, then the
|
||||
registers need to be saved and restored according to `SMCCC`_. In AArch64,
|
||||
due to the tight integration with BL31, both BL31 and PSCI library
|
||||
use the same ``cpu_context_t`` data structure for PSCI CPU context management
|
||||
and register context management during world switch. This cannot be assumed
|
||||
for AArch32 EL3 Runtime Software since most AArch32 Trusted OSes already implement
|
||||
a mechanism for register context management during world switch. Hence, when
|
||||
the PSCI library is integrated with a AArch32 EL3 Runtime Software, the
|
||||
``cpu_context_t`` is stripped down for just PSCI CPU context management.
|
||||
|
||||
During cold/warm boot, after invoking appropriate PSCI library interfaces, it
|
||||
is expected that the EL3 Runtime Software will query the ``cpu_context_t`` and
|
||||
write appropriate values to the corresponding system registers. This mechanism
|
||||
resolves 2 additional problems for AArch32 EL3 Runtime Software:
|
||||
|
||||
#. Values for certain system registers like SCR and SCTLR cannot be
|
||||
unilaterally determined by PSCI library and need inputs from the EL3
|
||||
Runtime Software. Using ``cpu_context_t`` as an intermediary data store
|
||||
allows EL3 Runtime Software to modify the register values appropriately
|
||||
before programming them.
|
||||
|
||||
#. The PSCI library provides appropriate LR and SPSR values (entrypoint
|
||||
information) for exit into non-secure world. Using ``cpu_context_t`` as an
|
||||
intermediary data store allows the EL3 Runtime Software to store these
|
||||
values safely until it is ready for exit to non-secure world.
|
||||
|
||||
Currently the ``cpu_context_t`` data structure for AArch32 stores the following
|
||||
registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
|
||||
|
||||
The EL3 Runtime Software must implement accessors to get/set pointers
|
||||
to CPU context ``cpu_context_t`` data and these are described in
|
||||
`CPU Context management API`_.
|
||||
|
||||
PSCI Library Interface
|
||||
----------------------
|
||||
|
||||
The PSCI library implements the `PSCI Specification`_. The interfaces
|
||||
to this library are declared in ``psci_lib.h`` and are as listed below:
|
||||
|
||||
.. code:: c
|
||||
|
||||
u_register_t psci_smc_handler(uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3,
|
||||
u_register_t x4, void *cookie,
|
||||
void *handle, u_register_t flags);
|
||||
int psci_setup(const psci_lib_args_t *lib_args);
|
||||
void psci_warmboot_entrypoint(void);
|
||||
void psci_register_spd_pm_hook(const spd_pm_ops_t *pm);
|
||||
void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info);
|
||||
|
||||
The CPU context data 'cpu_context_t' is programmed to the registers differently
|
||||
when PSCI is integrated with an AArch32 EL3 Runtime Software compared to
|
||||
when the PSCI is integrated with an AArch64 EL3 Runtime Software (BL31). For
|
||||
example, in the case of AArch64, there is no need to retrieve ``cpu_context_t``
|
||||
data and program the registers as it will done implicitly as part of
|
||||
``el3_exit``. The description below of the PSCI interfaces is targeted at
|
||||
integration with an AArch32 EL3 Runtime Software.
|
||||
|
||||
The PSCI library is responsible for initializing/restoring the non-secure world
|
||||
to an appropriate state after boot and may choose to directly program the
|
||||
non-secure system registers. The PSCI generic code takes care not to directly
|
||||
modify any of the system registers affecting the secure world and instead
|
||||
returns the values to be programmed to these registers via ``cpu_context_t``.
|
||||
The EL3 Runtime Software is responsible for programming those registers and
|
||||
can use the proposed values provided in the ``cpu_context_t``, modifying the
|
||||
values if required.
|
||||
|
||||
PSCI library needs the flexibility to access both secure and non-secure
|
||||
copies of banked registers. Hence it needs to be invoked in Monitor mode
|
||||
for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR_EL3
|
||||
(in AArch64) must be set to 0. Additional requirements for the PSCI library
|
||||
interfaces are:
|
||||
|
||||
- Instruction cache must be enabled
|
||||
- Both IRQ and FIQ must be masked for the current CPU
|
||||
- The page tables must be setup and the MMU enabled
|
||||
- The C runtime environment must be setup and stack initialized
|
||||
- The Data cache must be enabled prior to invoking any of the PSCI library
|
||||
interfaces except for ``psci_warmboot_entrypoint()``. For
|
||||
``psci_warmboot_entrypoint()``, if the build option ``HW_ASSISTED_COHERENCY``
|
||||
is enabled however, data caches are expected to be enabled.
|
||||
|
||||
Further requirements for each interface can be found in the interface
|
||||
description.
|
||||
|
||||
Interface : psci_setup()
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : const psci_lib_args_t *lib_args
|
||||
Return : void
|
||||
|
||||
This function is to be called by the primary CPU during cold boot before
|
||||
any other interface to the PSCI library. It takes ``lib_args``, a const pointer
|
||||
to ``psci_lib_args_t``, as the argument. The ``psci_lib_args_t`` is a versioned
|
||||
structure and is declared in ``psci_lib.h`` header as follows:
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef struct psci_lib_args {
|
||||
/* The version information of PSCI Library Interface */
|
||||
param_header_t h;
|
||||
/* The warm boot entrypoint function */
|
||||
mailbox_entrypoint_t mailbox_ep;
|
||||
} psci_lib_args_t;
|
||||
|
||||
The first field ``h``, of ``param_header_t`` type, provides the version
|
||||
information. The second field ``mailbox_ep`` is the warm boot entrypoint address
|
||||
and is used to configure the platform mailbox. Helper macros are provided in
|
||||
``psci_lib.h`` to construct the ``lib_args`` argument statically or during
|
||||
runtime. Prior to calling the ``psci_setup()`` interface, the platform setup for
|
||||
cold boot must have completed. Major actions performed by this interface are:
|
||||
|
||||
- Initializes architecture.
|
||||
- Initializes PSCI power domain and state coordination data structures.
|
||||
- Calls ``plat_setup_psci_ops()`` with warm boot entrypoint ``mailbox_ep`` as
|
||||
argument.
|
||||
- Calls ``cm_set_context_by_index()`` (see
|
||||
`CPU Context management API`_) for all the CPUs in the
|
||||
platform
|
||||
|
||||
Interface : psci_prepare_next_non_secure_ctx()
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : entry_point_info_t *next_image_info
|
||||
Return : void
|
||||
|
||||
After ``psci_setup()`` and prior to exit to the non-secure world, this function
|
||||
must be called by the EL3 Runtime Software to initialize the non-secure world
|
||||
context. The non-secure world entrypoint information ``next_image_info`` (first
|
||||
argument) will be used to determine the non-secure context. After this function
|
||||
returns, the EL3 Runtime Software must retrieve the ``cpu_context_t`` (using
|
||||
cm_get_context()) for the current CPU and program the registers prior to exit
|
||||
to the non-secure world.
|
||||
|
||||
Interface : psci_register_spd_pm_hook()
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : const spd_pm_ops_t *
|
||||
Return : void
|
||||
|
||||
As explained in `Secure payload power management callback`_,
|
||||
the EL3 Runtime Software may want to perform some bookkeeping during power
|
||||
management operations. This function is used to register the ``spd_pm_ops_t``
|
||||
(first argument) callbacks with the PSCI library which will be called
|
||||
appropriately during power management. Calling this function is optional and
|
||||
need to be called by the primary CPU during the cold boot sequence after
|
||||
``psci_setup()`` has completed.
|
||||
|
||||
Interface : psci_smc_handler()
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : uint32_t smc_fid, u_register_t x1,
|
||||
u_register_t x2, u_register_t x3,
|
||||
u_register_t x4, void *cookie,
|
||||
void *handle, u_register_t flags
|
||||
Return : u_register_t
|
||||
|
||||
This function is the top level handler for SMCs which fall within the
|
||||
PSCI service range specified in `SMCCC`_. The function ID ``smc_fid`` (first
|
||||
argument) determines the PSCI API to be called. The ``x1`` to ``x4`` (2nd to 5th
|
||||
arguments), are the values of the registers r1 - r4 (in AArch32) or x1 - x4
|
||||
(in AArch64) when the SMC is received. These are the arguments to PSCI API as
|
||||
described in `PSCI spec`_. The 'flags' (8th argument) is a bit field parameter
|
||||
and is detailed in 'smccc.h' header. It includes whether the call is from the
|
||||
secure or non-secure world. The ``cookie`` (6th argument) and the ``handle``
|
||||
(7th argument) are not used and are reserved for future use.
|
||||
|
||||
The return value from this interface is the return value from the underlying
|
||||
PSCI API corresponding to ``smc_fid``. This function may not return back to the
|
||||
caller if PSCI API causes power down of the CPU. In this case, when the CPU
|
||||
wakes up, it will start execution from the warm reset address.
|
||||
|
||||
Interface : psci_warmboot_entrypoint()
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
Argument : void
|
||||
Return : void
|
||||
|
||||
This function performs the warm boot initialization/restoration as mandated by
|
||||
`PSCI spec`_. For AArch32, on wakeup from power down the CPU resets to secure SVC
|
||||
mode and the EL3 Runtime Software must perform the prerequisite initializations
|
||||
mentioned at top of this section. This function must be called with Data cache
|
||||
disabled (unless build option ``HW_ASSISTED_COHERENCY`` is enabled) but with MMU
|
||||
initialized and enabled. The major actions performed by this function are:
|
||||
|
||||
- Invalidates the stack and enables the data cache.
|
||||
- Initializes architecture and PSCI state coordination.
|
||||
- Restores/Initializes the peripheral drivers to the required state via
|
||||
appropriate ``plat_psci_ops_t`` hooks
|
||||
- Restores the EL3 Runtime Software context via appropriate ``spd_pm_ops_t``
|
||||
callbacks.
|
||||
- Restores/Initializes the non-secure context and populates the
|
||||
``cpu_context_t`` for the current CPU.
|
||||
|
||||
Upon the return of this function, the EL3 Runtime Software must retrieve the
|
||||
non-secure ``cpu_context_t`` using ``cm_get_context()`` and program the registers
|
||||
prior to exit to the non-secure world.
|
||||
|
||||
EL3 Runtime Software dependencies
|
||||
---------------------------------
|
||||
|
||||
The PSCI Library includes supporting frameworks like context management,
|
||||
cpu operations (cpu_ops) and per-cpu data framework. Other helper library
|
||||
functions like bakery locks and spin locks are also included in the library.
|
||||
The dependencies which must be fulfilled by the EL3 Runtime Software
|
||||
for integration with PSCI library are described below.
|
||||
|
||||
General dependencies
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The PSCI library being a Multiprocessor (MP) implementation, EL3 Runtime
|
||||
Software must provide an SMC handling framework capable of MP adhering to
|
||||
`SMCCC`_ specification.
|
||||
|
||||
The EL3 Runtime Software must also export cache maintenance primitives
|
||||
and some helper utilities for assert, print and memory operations as listed
|
||||
below. The TF-A source tree provides implementations for all
|
||||
these functions but the EL3 Runtime Software may use its own implementation.
|
||||
|
||||
**Functions : assert(), memcpy(), memset(), printf()**
|
||||
|
||||
These must be implemented as described in ISO C Standard.
|
||||
|
||||
**Function : flush_dcache_range()**
|
||||
|
||||
::
|
||||
|
||||
Argument : uintptr_t addr, size_t size
|
||||
Return : void
|
||||
|
||||
This function cleans and invalidates (flushes) the data cache for memory
|
||||
at address ``addr`` (first argument) address and of size ``size`` (second argument).
|
||||
|
||||
**Function : inv_dcache_range()**
|
||||
|
||||
::
|
||||
|
||||
Argument : uintptr_t addr, size_t size
|
||||
Return : void
|
||||
|
||||
This function invalidates (flushes) the data cache for memory at address
|
||||
``addr`` (first argument) address and of size ``size`` (second argument).
|
||||
|
||||
CPU Context management API
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The CPU context management data memory is statically allocated by PSCI library
|
||||
in BSS section. The PSCI library requires the EL3 Runtime Software to implement
|
||||
APIs to store and retrieve pointers to this CPU context data. SP-MIN
|
||||
demonstrates how these APIs can be implemented but the EL3 Runtime Software can
|
||||
choose a more optimal implementation (like dedicating the secure TPIDRPRW
|
||||
system register (in AArch32) for storing these pointers).
|
||||
|
||||
**Function : cm_set_context_by_index()**
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int cpu_idx, void *context, unsigned int security_state
|
||||
Return : void
|
||||
|
||||
This function is called during cold boot when the ``psci_setup()`` PSCI library
|
||||
interface is called.
|
||||
|
||||
This function must store the pointer to the CPU context data, ``context`` (2nd
|
||||
argument), for the specified ``security_state`` (3rd argument) and CPU identified
|
||||
by ``cpu_idx`` (first argument). The ``security_state`` will always be non-secure
|
||||
when called by PSCI library and this argument is retained for compatibility
|
||||
with BL31. The ``cpu_idx`` will correspond to the index returned by the
|
||||
``plat_core_pos_by_mpidr()`` for ``mpidr`` of the CPU.
|
||||
|
||||
The actual method of storing the ``context`` pointers is implementation specific.
|
||||
For example, SP-MIN stores the pointers in the array ``sp_min_cpu_ctx_ptr``
|
||||
declared in ``sp_min_main.c``.
|
||||
|
||||
**Function : cm_get_context()**
|
||||
|
||||
::
|
||||
|
||||
Argument : uint32_t security_state
|
||||
Return : void *
|
||||
|
||||
This function must return the pointer to the ``cpu_context_t`` structure for
|
||||
the specified ``security_state`` (first argument) for the current CPU. The caller
|
||||
must ensure that ``cm_set_context_by_index`` is called first and the appropriate
|
||||
context pointers are stored prior to invoking this API. The ``security_state``
|
||||
will always be non-secure when called by PSCI library and this argument
|
||||
is retained for compatibility with BL31.
|
||||
|
||||
**Function : cm_get_context_by_index()**
|
||||
|
||||
::
|
||||
|
||||
Argument : unsigned int cpu_idx, unsigned int security_state
|
||||
Return : void *
|
||||
|
||||
This function must return the pointer to the ``cpu_context_t`` structure for
|
||||
the specified ``security_state`` (second argument) for the CPU identified by
|
||||
``cpu_idx`` (first argument). The caller must ensure that
|
||||
``cm_set_context_by_index`` is called first and the appropriate context
|
||||
pointers are stored prior to invoking this API. The ``security_state`` will
|
||||
always be non-secure when called by PSCI library and this argument is
|
||||
retained for compatibility with BL31. The ``cpu_idx`` will correspond to the
|
||||
index returned by the ``plat_core_pos_by_mpidr()`` for ``mpidr`` of the CPU.
|
||||
|
||||
Platform API
|
||||
~~~~~~~~~~~~
|
||||
|
||||
The platform layer abstracts the platform-specific details from the generic
|
||||
PSCI library. The following platform APIs/macros must be defined by the EL3
|
||||
Runtime Software for integration with the PSCI library.
|
||||
|
||||
The mandatory platform APIs are:
|
||||
|
||||
- plat_my_core_pos
|
||||
- plat_core_pos_by_mpidr
|
||||
- plat_get_syscnt_freq2
|
||||
- plat_get_power_domain_tree_desc
|
||||
- plat_setup_psci_ops
|
||||
- plat_reset_handler
|
||||
- plat_panic_handler
|
||||
- plat_get_my_stack
|
||||
|
||||
The mandatory platform macros are:
|
||||
|
||||
- PLATFORM_CORE_COUNT
|
||||
- PLAT_MAX_PWR_LVL
|
||||
- PLAT_NUM_PWR_DOMAINS
|
||||
- CACHE_WRITEBACK_GRANULE
|
||||
- PLAT_MAX_OFF_STATE
|
||||
- PLAT_MAX_RET_STATE
|
||||
- PLAT_MAX_PWR_LVL_STATES (optional)
|
||||
- PLAT_PCPU_DATA_SIZE (optional)
|
||||
|
||||
The details of these APIs/macros can be found in the :ref:`Porting Guide`.
|
||||
|
||||
All platform specific operations for power management are done via
|
||||
``plat_psci_ops_t`` callbacks registered by the platform when
|
||||
``plat_setup_psci_ops()`` API is called. The description of each of
|
||||
the callbacks in ``plat_psci_ops_t`` can be found in PSCI section of the
|
||||
:ref:`Porting Guide`. If any these callbacks are not registered, then the
|
||||
PSCI API associated with that callback will not be supported by PSCI
|
||||
library.
|
||||
|
||||
Secure payload power management callback
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
During PSCI power management operations, the EL3 Runtime Software may
|
||||
need to perform some bookkeeping, and PSCI library provides
|
||||
``spd_pm_ops_t`` callbacks for this purpose. These hooks must be
|
||||
populated and registered by using ``psci_register_spd_pm_hook()`` PSCI
|
||||
library interface.
|
||||
|
||||
Typical bookkeeping during PSCI power management calls include save/restore
|
||||
of the EL3 Runtime Software context. Also if the EL3 Runtime Software makes
|
||||
use of secure interrupts, then these interrupts must also be managed
|
||||
appropriately during CPU power down/power up. Any secure interrupt targeted
|
||||
to the current CPU must be disabled or re-targeted to other running CPU prior
|
||||
to power down of the current CPU. During power up, these interrupt can be
|
||||
enabled/re-targeted back to the current CPU.
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef struct spd_pm_ops {
|
||||
void (*svc_on)(u_register_t target_cpu);
|
||||
int32_t (*svc_off)(u_register_t __unused);
|
||||
void (*svc_suspend)(u_register_t max_off_pwrlvl);
|
||||
void (*svc_on_finish)(u_register_t __unused);
|
||||
void (*svc_suspend_finish)(u_register_t max_off_pwrlvl);
|
||||
int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu);
|
||||
int32_t (*svc_migrate_info)(u_register_t *resident_cpu);
|
||||
void (*svc_system_off)(void);
|
||||
void (*svc_system_reset)(void);
|
||||
} spd_pm_ops_t;
|
||||
|
||||
A brief description of each callback is given below:
|
||||
|
||||
- svc_on, svc_off, svc_on_finish
|
||||
|
||||
The ``svc_on``, ``svc_off`` callbacks are called during PSCI_CPU_ON,
|
||||
PSCI_CPU_OFF APIs respectively. The ``svc_on_finish`` is called when the
|
||||
target CPU of PSCI_CPU_ON API powers up and executes the
|
||||
``psci_warmboot_entrypoint()`` PSCI library interface.
|
||||
|
||||
- svc_suspend, svc_suspend_finish
|
||||
|
||||
The ``svc_suspend`` callback is called during power down bu either
|
||||
PSCI_SUSPEND or PSCI_SYSTEM_SUSPEND APIs. The ``svc_suspend_finish`` is
|
||||
called when the CPU wakes up from suspend and executes the
|
||||
``psci_warmboot_entrypoint()`` PSCI library interface. The ``max_off_pwrlvl``
|
||||
(first parameter) denotes the highest power domain level being powered down
|
||||
to or woken up from suspend.
|
||||
|
||||
- svc_system_off, svc_system_reset
|
||||
|
||||
These callbacks are called during PSCI_SYSTEM_OFF and PSCI_SYSTEM_RESET
|
||||
PSCI APIs respectively.
|
||||
|
||||
- svc_migrate_info
|
||||
|
||||
This callback is called in response to PSCI_MIGRATE_INFO_TYPE or
|
||||
PSCI_MIGRATE_INFO_UP_CPU APIs. The return value of this callback must
|
||||
correspond to the return value of PSCI_MIGRATE_INFO_TYPE API as described
|
||||
in `PSCI spec`_. If the secure payload is a Uniprocessor (UP)
|
||||
implementation, then it must update the mpidr of the CPU it is resident in
|
||||
via ``resident_cpu`` (first argument). The updates to ``resident_cpu`` is
|
||||
ignored if the secure payload is a multiprocessor (MP) implementation.
|
||||
|
||||
- svc_migrate
|
||||
|
||||
This callback is only relevant if the secure payload in EL3 Runtime
|
||||
Software is a Uniprocessor (UP) implementation and supports migration from
|
||||
the current CPU ``from_cpu`` (first argument) to another CPU ``to_cpu``
|
||||
(second argument). This callback is called in response to PSCI_MIGRATE
|
||||
API. This callback is never called if the secure payload is a
|
||||
Multiprocessor (MP) implementation.
|
||||
|
||||
CPU operations
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
The CPU operations (cpu_ops) framework implement power down sequence specific
|
||||
to the CPU and the details of which can be found at
|
||||
:ref:`firmware_design_cpu_ops_fwk`. The TF-A tree implements the ``cpu_ops``
|
||||
for various supported CPUs and the EL3 Runtime Software needs to include the
|
||||
required ``cpu_ops`` in its build. The start and end of the ``cpu_ops``
|
||||
descriptors must be exported by the EL3 Runtime Software via the
|
||||
``__CPU_OPS_START__`` and ``__CPU_OPS_END__`` linker symbols.
|
||||
|
||||
The ``cpu_ops`` descriptors also include reset sequences and may include errata
|
||||
workarounds for the CPU. The EL3 Runtime Software can choose to call this
|
||||
during cold/warm reset if it does not implement its own reset sequence/errata
|
||||
workarounds.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _PSCI spec: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
|
||||
.. _SMCCC: https://developer.arm.com/docs/den0028/latest
|
||||
.. _PSCI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
|
||||
.. _PSCI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
|
||||
@@ -0,0 +1,320 @@
|
||||
EL3 Runtime Service Writer's Guide
|
||||
=====================================================
|
||||
|
||||
Introduction
|
||||
------------
|
||||
|
||||
This document describes how to add a runtime service to the EL3 Runtime
|
||||
Firmware component of Trusted Firmware-A (TF-A), BL31.
|
||||
|
||||
Software executing in the normal world and in the trusted world at exception
|
||||
levels lower than EL3 will request runtime services using the Secure Monitor
|
||||
Call (SMC) instruction. These requests will follow the convention described in
|
||||
the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
|
||||
identifiers to each SMC request and describes how arguments are passed and
|
||||
results are returned.
|
||||
|
||||
SMC Functions are grouped together based on the implementor of the service, for
|
||||
example a subset of the Function IDs are designated as "OEM Calls" (see `SMCCC`_
|
||||
for full details). The EL3 runtime services framework in BL31 enables the
|
||||
independent implementation of services for each group, which are then compiled
|
||||
into the BL31 image. This simplifies the integration of common software from
|
||||
Arm to support `PSCI`_, Secure Monitor for a Trusted OS and SoC specific
|
||||
software. The common runtime services framework ensures that SMC Functions are
|
||||
dispatched to their respective service implementation - the
|
||||
:ref:`Firmware Design` document provides details of how this is achieved.
|
||||
|
||||
The interface and operation of the runtime services depends heavily on the
|
||||
concepts and definitions described in the `SMCCC`_, in particular SMC Function
|
||||
IDs, Owning Entity Numbers (OEN), Fast and Standard calls, and the SMC32 and
|
||||
SMC64 calling conventions. Please refer to that document for a full explanation
|
||||
of these terms.
|
||||
|
||||
Owning Entities, Call Types and Function IDs
|
||||
--------------------------------------------
|
||||
|
||||
The SMC Function Identifier includes a OEN field. These values and their
|
||||
meaning are described in `SMCCC`_ and summarized in table 1 below. Some entities
|
||||
are allocated a range of of OENs. The OEN must be interpreted in conjunction
|
||||
with the SMC call type, which is either *Fast* or *Yielding*. Fast calls are
|
||||
uninterruptible whereas Yielding calls can be pre-empted. The majority of
|
||||
Owning Entities only have allocated ranges for Fast calls: Yielding calls are
|
||||
reserved exclusively for Trusted OS providers or for interoperability with
|
||||
legacy 32-bit software that predates the `SMCCC`_.
|
||||
|
||||
::
|
||||
|
||||
Type OEN Service
|
||||
Fast 0 Arm Architecture calls
|
||||
Fast 1 CPU Service calls
|
||||
Fast 2 SiP Service calls
|
||||
Fast 3 OEM Service calls
|
||||
Fast 4 Standard Service calls
|
||||
Fast 5-47 Reserved for future use
|
||||
Fast 48-49 Trusted Application calls
|
||||
Fast 50-63 Trusted OS calls
|
||||
|
||||
Yielding 0- 1 Reserved for existing Armv7-A calls
|
||||
Yielding 2-63 Trusted OS Standard Calls
|
||||
|
||||
*Table 1: Service types and their corresponding Owning Entity Numbers*
|
||||
|
||||
Each individual entity can allocate the valid identifiers within the entity
|
||||
range as they need - it is not necessary to coordinate with other entities of
|
||||
the same type. For example, two SoC providers can use the same Function ID
|
||||
within the SiP Service calls OEN range to mean different things - as these
|
||||
calls should be specific to the SoC. The Standard Runtime Calls OEN is used for
|
||||
services defined by Arm standards, such as `PSCI`_.
|
||||
|
||||
The SMC Function ID also indicates whether the call has followed the SMC32
|
||||
calling convention, where all parameters are 32-bit, or the SMC64 calling
|
||||
convention, where the parameters are 64-bit. The framework identifies and
|
||||
rejects invalid calls that use the SMC64 calling convention but that originate
|
||||
from an AArch32 caller.
|
||||
|
||||
The EL3 runtime services framework uses the call type and OEN to identify a
|
||||
specific handler for each SMC call, but it is expected that an individual
|
||||
handler will be responsible for all SMC Functions within a given service type.
|
||||
|
||||
Getting started
|
||||
---------------
|
||||
|
||||
TF-A has a ``services`` directory in the source tree under which
|
||||
each owning entity can place the implementation of its runtime service. The
|
||||
`PSCI`_ implementation is located here in the ``lib/psci`` directory.
|
||||
|
||||
Runtime service sources will need to include the ``runtime_svc.h`` header file.
|
||||
|
||||
Registering a runtime service
|
||||
-----------------------------
|
||||
|
||||
A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
|
||||
the name of the service, the range of OENs covered, the type of service and
|
||||
initialization and call handler functions.
|
||||
|
||||
.. code:: c
|
||||
|
||||
#define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch)
|
||||
|
||||
- ``_name`` is used to identify the data structure declared by this macro, and
|
||||
is also used for diagnostic purposes
|
||||
|
||||
- ``_start`` and ``_end`` values must be based on the ``OEN_*`` values defined in
|
||||
``smccc.h``
|
||||
|
||||
- ``_type`` must be one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD``
|
||||
|
||||
- ``_setup`` is the initialization function with the ``rt_svc_init`` signature:
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef int32_t (*rt_svc_init)(void);
|
||||
|
||||
- ``_smch`` is the SMC handler function with the ``rt_svc_handle`` signature:
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid,
|
||||
u_register_t x1, u_register_t x2,
|
||||
u_register_t x3, u_register_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
u_register_t flags);
|
||||
|
||||
Details of the requirements and behavior of the two callbacks is provided in
|
||||
the following sections.
|
||||
|
||||
During initialization the services framework validates each declared service
|
||||
to ensure that the following conditions are met:
|
||||
|
||||
#. The ``_start`` OEN is not greater than the ``_end`` OEN
|
||||
#. The ``_end`` OEN does not exceed the maximum OEN value (63)
|
||||
#. The ``_type`` is one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD``
|
||||
#. ``_setup`` and ``_smch`` routines have been specified
|
||||
|
||||
``std_svc_setup.c`` provides an example of registering a runtime service:
|
||||
|
||||
.. code:: c
|
||||
|
||||
/* Register Standard Service Calls as runtime service */
|
||||
DECLARE_RT_SVC(
|
||||
std_svc,
|
||||
OEN_STD_START,
|
||||
OEN_STD_END,
|
||||
SMC_TYPE_FAST,
|
||||
std_svc_setup,
|
||||
std_svc_smc_handler
|
||||
);
|
||||
|
||||
Initializing a runtime service
|
||||
------------------------------
|
||||
|
||||
Runtime services are initialized once, during cold boot, by the primary CPU
|
||||
after platform and architectural initialization is complete. The framework
|
||||
performs basic validation of the declared service before calling
|
||||
the service initialization function (``_setup`` in the declaration). This
|
||||
function must carry out any essential EL3 initialization prior to receiving a
|
||||
SMC Function call via the handler function.
|
||||
|
||||
On success, the initialization function must return ``0``. Any other return value
|
||||
will cause the framework to issue a diagnostic:
|
||||
|
||||
::
|
||||
|
||||
Error initializing runtime service <name of the service>
|
||||
|
||||
and then ignore the service - the system will continue to boot but SMC calls
|
||||
will not be passed to the service handler and instead return the *Unknown SMC
|
||||
Function ID* result ``0xFFFFFFFF``.
|
||||
|
||||
If the system must not be allowed to proceed without the service, the
|
||||
initialization function must itself cause the firmware boot to be halted.
|
||||
|
||||
If the service uses per-CPU data this must either be initialized for all CPUs
|
||||
during this call, or be done lazily when a CPU first issues an SMC call to that
|
||||
service.
|
||||
|
||||
Handling runtime service requests
|
||||
---------------------------------
|
||||
|
||||
SMC calls for a service are forwarded by the framework to the service's SMC
|
||||
handler function (``_smch`` in the service declaration). This function must have
|
||||
the following signature:
|
||||
|
||||
.. code:: c
|
||||
|
||||
typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid,
|
||||
u_register_t x1, u_register_t x2,
|
||||
u_register_t x3, u_register_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
u_register_t flags);
|
||||
|
||||
The handler is responsible for:
|
||||
|
||||
#. Determining that ``smc_fid`` is a valid and supported SMC Function ID,
|
||||
otherwise completing the request with the *Unknown SMC Function ID*:
|
||||
|
||||
.. code:: c
|
||||
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
#. Determining if the requested function is valid for the calling security
|
||||
state. SMC Calls can be made from Non-secure, Secure or Realm worlds and
|
||||
the framework will forward all calls to the service handler.
|
||||
|
||||
The ``flags`` parameter to this function indicates the caller security state
|
||||
in bits 0 and 5. The ``is_caller_secure(flags)``, ``is_caller_non_secure(flags)``
|
||||
and ``is_caller_realm(flags)`` helper functions can be used to determine whether
|
||||
the caller's security state is Secure, Non-secure or Realm respectively.
|
||||
|
||||
If invalid, the request should be completed with:
|
||||
|
||||
.. code:: c
|
||||
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
#. Truncating parameters for calls made using the SMC32 calling convention.
|
||||
Such calls can be determined by checking the CC field in bit[30] of the
|
||||
``smc_fid`` parameter, for example by using:
|
||||
|
||||
::
|
||||
|
||||
if (GET_SMC_CC(smc_fid) == SMC_32) ...
|
||||
|
||||
For such calls, the upper bits of the parameters x1-x4 and the saved
|
||||
parameters X5-X7 are UNDEFINED and must be explicitly ignored by the
|
||||
handler. This can be done by truncating the values to a suitable 32-bit
|
||||
integer type before use, for example by ensuring that functions defined
|
||||
to handle individual SMC Functions use appropriate 32-bit parameters.
|
||||
|
||||
#. Providing the service requested by the SMC Function, utilizing the
|
||||
immediate parameters x1-x4 and/or the additional saved parameters X5-X7.
|
||||
The latter can be retrieved using the ``SMC_GET_GP(handle, ref)`` function,
|
||||
supplying the appropriate ``CTX_GPREG_Xn`` reference, e.g.
|
||||
|
||||
.. code:: c
|
||||
|
||||
uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
|
||||
|
||||
#. Implementing the standard SMC32 Functions that provide information about
|
||||
the implementation of the service. These are the Call Count, Implementor
|
||||
UID and Revision Details for each service documented in section 6 of the
|
||||
`SMCCC`_.
|
||||
|
||||
TF-A expects owning entities to follow this recommendation.
|
||||
|
||||
#. Returning the result to the caller. Based on `SMCCC`_ spec, results are
|
||||
returned in W0-W7(X0-X7) registers for SMC32(SMC64) calls from AArch64
|
||||
state. Results are returned in R0-R7 registers for SMC32 calls from AArch32
|
||||
state. The framework provides a family of macros to set the multi-register
|
||||
return value and complete the handler:
|
||||
|
||||
.. code:: c
|
||||
|
||||
AArch64 state:
|
||||
|
||||
SMC_RET1(handle, x0);
|
||||
SMC_RET2(handle, x0, x1);
|
||||
SMC_RET3(handle, x0, x1, x2);
|
||||
SMC_RET4(handle, x0, x1, x2, x3);
|
||||
SMC_RET5(handle, x0, x1, x2, x3, x4);
|
||||
SMC_RET6(handle, x0, x1, x2, x3, x4, x5);
|
||||
SMC_RET7(handle, x0, x1, x2, x3, x4, x5, x6);
|
||||
SMC_RET8(handle, x0, x1, x2, x3, x4, x5, x6, x7);
|
||||
|
||||
AArch32 state:
|
||||
|
||||
SMC_RET1(handle, r0);
|
||||
SMC_RET2(handle, r0, r1);
|
||||
SMC_RET3(handle, r0, r1, r2);
|
||||
SMC_RET4(handle, r0, r1, r2, r3);
|
||||
SMC_RET5(handle, r0, r1, r2, r3, r4);
|
||||
SMC_RET6(handle, r0, r1, r2, r3, r4, r5);
|
||||
SMC_RET7(handle, r0, r1, r2, r3, r4, r5, r6);
|
||||
SMC_RET8(handle, r0, r1, r2, r3, r4, r5, r6, r7);
|
||||
|
||||
The ``cookie`` parameter to the handler is reserved for future use and can be
|
||||
ignored. The ``handle`` is returned by the SMC handler - completion of the
|
||||
handler function must always be via one of the ``SMC_RETn()`` macros.
|
||||
|
||||
.. note::
|
||||
The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow
|
||||
all of the above requirements yet.
|
||||
|
||||
Services that contain multiple sub-services
|
||||
-------------------------------------------
|
||||
|
||||
It is possible that a single owning entity implements multiple sub-services. For
|
||||
example, the Standard calls service handles ``0x84000000``-``0x8400FFFF`` and
|
||||
``0xC4000000``-``0xC400FFFF`` functions. Within that range, the `PSCI`_ service
|
||||
handles the ``0x84000000``-``0x8400001F`` and ``0xC4000000``-``0xC400001F`` functions.
|
||||
In that respect, `PSCI`_ is a 'sub-service' of the Standard calls service. In
|
||||
future, there could be additional such sub-services in the Standard calls
|
||||
service which perform independent functions.
|
||||
|
||||
In this situation it may be valuable to introduce a second level framework to
|
||||
enable independent implementation of sub-services. Such a framework might look
|
||||
very similar to the current runtime services framework, but using a different
|
||||
part of the SMC Function ID to identify the sub-service. TF-A does not provide
|
||||
such a framework at present.
|
||||
|
||||
Secure-EL1 Payload Dispatcher service (SPD)
|
||||
-------------------------------------------
|
||||
|
||||
Services that handle SMC Functions targeting a Trusted OS, Trusted Application,
|
||||
or other Secure-EL1 Payload are special. These services need to manage the
|
||||
Secure-EL1 context, provide the *Secure Monitor* functionality of switching
|
||||
between the normal and secure worlds, deliver SMC Calls through to Secure-EL1
|
||||
and generally manage the Secure-EL1 Payload through CPU power-state transitions.
|
||||
|
||||
TODO: Provide details of the additional work required to implement a SPD and
|
||||
the BL31 support for these services. Or a reference to the document that will
|
||||
provide this information....
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _SMCCC: https://developer.arm.com/docs/den0028/latest
|
||||
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
|
||||
179
arm-trusted-firmware/docs/getting_started/tools-build.rst
Normal file
179
arm-trusted-firmware/docs/getting_started/tools-build.rst
Normal file
@@ -0,0 +1,179 @@
|
||||
Building Supporting Tools
|
||||
=========================
|
||||
|
||||
.. note::
|
||||
|
||||
OpenSSL 3.0 is needed in order to build the tools. A custom installation
|
||||
can be used if not updating the OpenSSL version on the OS. In order to do
|
||||
this, use the ``OPENSSL_DIR`` variable after the ``make`` command to
|
||||
indicate the location of the custom OpenSSL build. Then, to run the tools,
|
||||
use the ``LD_LIBRARY_PATH`` to indicate the location of the built
|
||||
libraries. More info about ``OPENSSL_DIR`` can be found at
|
||||
:ref:`Build Options`.
|
||||
|
||||
Building and using the FIP tool
|
||||
-------------------------------
|
||||
|
||||
The following snippets build a :ref:`FIP<Image Terminology>` for the FVP
|
||||
platform. While it is not an intrinsic part of the FIP format, a BL33 image is
|
||||
required for these examples. For the purposes of experimentation, `Trusted
|
||||
Firmware-A Tests`_ (`tftf.bin``) may be used. Refer to to the `TFTF
|
||||
documentation`_ for instructions on building a TFTF binary.
|
||||
|
||||
The TF-A build system provides the make target ``fip`` to create a FIP file
|
||||
for the specified platform using the FIP creation tool included in the TF-A
|
||||
project. Examples below show how to build a FIP file for FVP, packaging TF-A
|
||||
and BL33 images.
|
||||
|
||||
For AArch64:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=fvp BL33=<path-to>/bl33.bin fip
|
||||
|
||||
For AArch32:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
|
||||
|
||||
The resulting FIP may be found in:
|
||||
|
||||
::
|
||||
|
||||
build/fvp/<build-type>/fip.bin
|
||||
|
||||
For advanced operations on FIP files, it is also possible to independently build
|
||||
the tool and create or modify FIPs using this tool. To do this, follow these
|
||||
steps:
|
||||
|
||||
It is recommended to remove old artifacts before building the tool:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make -C tools/fiptool clean
|
||||
|
||||
Build the tool:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make [DEBUG=1] [V=1] fiptool
|
||||
|
||||
The tool binary can be located in:
|
||||
|
||||
::
|
||||
|
||||
./tools/fiptool/fiptool
|
||||
|
||||
Invoking the tool with ``help`` will print a help message with all available
|
||||
options.
|
||||
|
||||
Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
./tools/fiptool/fiptool create \
|
||||
--tb-fw build/<platform>/<build-type>/bl2.bin \
|
||||
--soc-fw build/<platform>/<build-type>/bl31.bin \
|
||||
fip.bin
|
||||
|
||||
Example 2: view the contents of an existing Firmware package:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
./tools/fiptool/fiptool info <path-to>/fip.bin
|
||||
|
||||
Example 3: update the entries of an existing Firmware package:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
# Change the BL2 from Debug to Release version
|
||||
./tools/fiptool/fiptool update \
|
||||
--tb-fw build/<platform>/release/bl2.bin \
|
||||
build/<platform>/debug/fip.bin
|
||||
|
||||
Example 4: unpack all entries from an existing Firmware package:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
# Images will be unpacked to the working directory
|
||||
./tools/fiptool/fiptool unpack <path-to>/fip.bin
|
||||
|
||||
Example 5: remove an entry from an existing Firmware package:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
./tools/fiptool/fiptool remove \
|
||||
--tb-fw build/<platform>/debug/fip.bin
|
||||
|
||||
Note that if the destination FIP file exists, the create, update and
|
||||
remove operations will automatically overwrite it.
|
||||
|
||||
The unpack operation will fail if the images already exist at the
|
||||
destination. In that case, use -f or --force to continue.
|
||||
|
||||
More information about FIP can be found in the :ref:`Firmware Design` document.
|
||||
|
||||
.. _tools_build_cert_create:
|
||||
|
||||
Building the Certificate Generation Tool
|
||||
----------------------------------------
|
||||
|
||||
The ``cert_create`` tool is built as part of the TF-A build process when the
|
||||
``fip`` make target is specified and TBB is enabled (as described in the
|
||||
previous section), but it can also be built separately with the following
|
||||
command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=<platform> [DEBUG=1] [V=1] certtool
|
||||
|
||||
For platforms that require their own IDs in certificate files, the generic
|
||||
'cert_create' tool can be built with the following command. Note that the target
|
||||
platform must define its IDs within a ``platform_oid.h`` header file for the
|
||||
build to succeed.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
|
||||
|
||||
``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
|
||||
verbose. The following command should be used to obtain help about the tool:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
./tools/cert_create/cert_create -h
|
||||
|
||||
.. _tools_build_enctool:
|
||||
|
||||
Building the Firmware Encryption Tool
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The ``encrypt_fw`` tool is built as part of the TF-A build process when the
|
||||
``fip`` make target is specified, DECRYPTION_SUPPORT and TBB are enabled, but
|
||||
it can also be built separately with the following command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=<platform> [DEBUG=1] [V=1] enctool
|
||||
|
||||
``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
|
||||
verbose. The following command should be used to obtain help about the tool:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
./tools/encrypt_fw/encrypt_fw -h
|
||||
|
||||
Note that the enctool in its current implementation only supports encryption
|
||||
key to be provided in plain format. A typical implementation can very well
|
||||
extend this tool to support custom techniques to protect encryption key.
|
||||
|
||||
Also, a user may choose to provide encryption key or nonce as an input file
|
||||
via using ``cat <filename>`` instead of a hex string.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
|
||||
|
||||
.. _Trusted Firmware-A Tests: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/
|
||||
.. _TFTF documentation: https://trustedfirmware-a-tests.readthedocs.io/en/latest/
|
||||
68
arm-trusted-firmware/docs/global_substitutions.txt
Normal file
68
arm-trusted-firmware/docs/global_substitutions.txt
Normal file
@@ -0,0 +1,68 @@
|
||||
.. |AArch32| replace:: :term:`AArch32`
|
||||
.. |AArch64| replace:: :term:`AArch64`
|
||||
.. |AMU| replace:: :term:`AMU`
|
||||
.. |AMUs| replace:: :term:`AMUs <AMU>`
|
||||
.. |API| replace:: :term:`API`
|
||||
.. |BTI| replace:: :term:`BTI`
|
||||
.. |CoT| replace:: :term:`CoT`
|
||||
.. |COT| replace:: :term:`COT`
|
||||
.. |CSS| replace:: :term:`CSS`
|
||||
.. |CVE| replace:: :term:`CVE`
|
||||
.. |DTB| replace:: :term:`DTB`
|
||||
.. |DS-5| replace:: :term:`DS-5`
|
||||
.. |DSU| replace:: :term:`DSU`
|
||||
.. |DT| replace:: :term:`DT`
|
||||
.. |EL| replace:: :term:`EL`
|
||||
.. |EHF| replace:: :term:`EHF`
|
||||
.. |FCONF| replace:: :term:`FCONF`
|
||||
.. |FDT| replace:: :term:`FDT`
|
||||
.. |FF-A| replace:: :term:`FF-A`
|
||||
.. |FIP| replace:: :term:`FIP`
|
||||
.. |FVP| replace:: :term:`FVP`
|
||||
.. |FWU| replace:: :term:`FWU`
|
||||
.. |GIC| replace:: :term:`GIC`
|
||||
.. |ISA| replace:: :term:`ISA`
|
||||
.. |Linaro| replace:: :term:`Linaro`
|
||||
.. |MMU| replace:: :term:`MMU`
|
||||
.. |MPAM| replace:: :term:`MPAM`
|
||||
.. |MPMM| replace:: :term:`MPMM`
|
||||
.. |MPIDR| replace:: :term:`MPIDR`
|
||||
.. |MTE| replace:: :term:`MTE`
|
||||
.. |OEN| replace:: :term:`OEN`
|
||||
.. |OP-TEE| replace:: :term:`OP-TEE`
|
||||
.. |OTE| replace:: :term:`OTE`
|
||||
.. |PDD| replace:: :term:`PDD`
|
||||
.. |PAUTH| replace:: :term:`PAUTH`
|
||||
.. |PMF| replace:: :term:`PMF`
|
||||
.. |PSCI| replace:: :term:`PSCI`
|
||||
.. |RAS| replace:: :term:`RAS`
|
||||
.. |ROT| replace:: :term:`ROT`
|
||||
.. |SCMI| replace:: :term:`SCMI`
|
||||
.. |SCP| replace:: :term:`SCP`
|
||||
.. |SDEI| replace:: :term:`SDEI`
|
||||
.. |SDS| replace:: :term:`SDS`
|
||||
.. |SEA| replace:: :term:`SEA`
|
||||
.. |SiP| replace:: :term:`SiP`
|
||||
.. |SIP| replace:: :term:`SIP`
|
||||
.. |SMC| replace:: :term:`SMC`
|
||||
.. |SMCCC| replace:: :term:`SMCCC`
|
||||
.. |SoC| replace:: :term:`SoC`
|
||||
.. |SP| replace:: :term:`SP`
|
||||
.. |SPD| replace:: :term:`SPD`
|
||||
.. |SPM| replace:: :term:`SPM`
|
||||
.. |SSBS| replace:: :term:`SSBS`
|
||||
.. |SVE| replace:: :term:`SVE`
|
||||
.. |TBB| replace:: :term:`TBB`
|
||||
.. |TBBR| replace:: :term:`TBBR`
|
||||
.. |TEE| replace:: :term:`TEE`
|
||||
.. |TF-A| replace:: :term:`TF-A`
|
||||
.. |TF-M| replace:: :term:`TF-M`
|
||||
.. |TLB| replace:: :term:`TLB`
|
||||
.. |TLK| replace:: :term:`TLK`
|
||||
.. |TRNG| replace:: :term:`TRNG`
|
||||
.. |TSP| replace:: :term:`TSP`
|
||||
.. |TZC| replace:: :term:`TZC`
|
||||
.. |UBSAN| replace:: :term:`UBSAN`
|
||||
.. |UEFI| replace:: :term:`UEFI`
|
||||
.. |WDOG| replace:: :term:`WDOG`
|
||||
.. |XLAT| replace:: :term:`XLAT`
|
||||
243
arm-trusted-firmware/docs/glossary.rst
Normal file
243
arm-trusted-firmware/docs/glossary.rst
Normal file
@@ -0,0 +1,243 @@
|
||||
Glossary
|
||||
========
|
||||
|
||||
This glossary provides definitions for terms and abbreviations used in the TF-A
|
||||
documentation.
|
||||
|
||||
You can find additional definitions in the `Arm Glossary`_.
|
||||
|
||||
.. glossary::
|
||||
:sorted:
|
||||
|
||||
AArch32
|
||||
32-bit execution state of the ARMv8 ISA
|
||||
|
||||
AArch64
|
||||
64-bit execution state of the ARMv8 ISA
|
||||
|
||||
AMU
|
||||
Activity Monitor Unit, a hardware monitoring unit introduced by FEAT_AMUv1
|
||||
that exposes CPU core runtime metrics as a set of counter registers.
|
||||
|
||||
API
|
||||
Application Programming Interface
|
||||
|
||||
AT
|
||||
Address Translation
|
||||
|
||||
BTI
|
||||
Branch Target Identification. An Armv8.5 extension providing additional
|
||||
control flow integrity around indirect branches and their targets.
|
||||
|
||||
CoT
|
||||
COT
|
||||
Chain of Trust
|
||||
|
||||
CSS
|
||||
Compute Sub-System
|
||||
|
||||
CVE
|
||||
Common Vulnerabilities and Exposures. A CVE document is commonly used to
|
||||
describe a publicly-known security vulnerability.
|
||||
|
||||
DCE
|
||||
DRTM Configuration Environment
|
||||
|
||||
D-CRTM
|
||||
Dynamic Code Root of Trust for Measurement
|
||||
|
||||
DLME
|
||||
Dynamically Launched Measured Environment
|
||||
|
||||
DRTM
|
||||
Dynamic Root of Trust for Measurement
|
||||
|
||||
DS-5
|
||||
Arm Development Studio 5
|
||||
|
||||
DSU
|
||||
DynamIQ Shared Unit
|
||||
|
||||
DT
|
||||
Device Tree
|
||||
|
||||
DTB
|
||||
Device Tree Blob
|
||||
|
||||
EL
|
||||
Exception Level
|
||||
|
||||
EHF
|
||||
Exception Handling Framework
|
||||
|
||||
FCONF
|
||||
Firmware Configuration Framework
|
||||
|
||||
FDT
|
||||
Flattened Device Tree
|
||||
|
||||
FF-A
|
||||
Firmware Framework for Arm A-profile
|
||||
|
||||
FIP
|
||||
Firmware Image Package
|
||||
|
||||
FVP
|
||||
Fixed Virtual Platform
|
||||
|
||||
FWU
|
||||
FirmWare Update
|
||||
|
||||
GIC
|
||||
Generic Interrupt Controller
|
||||
|
||||
ISA
|
||||
Instruction Set Architecture
|
||||
|
||||
Linaro
|
||||
A collaborative engineering organization consolidating
|
||||
and optimizing open source software and tools for the Arm architecture.
|
||||
|
||||
LSP
|
||||
A logical secure partition managed by SPM
|
||||
|
||||
MMU
|
||||
Memory Management Unit
|
||||
|
||||
MPAM
|
||||
Memory Partitioning And Monitoring. An optional Armv8.4 extension.
|
||||
|
||||
MPMM
|
||||
Maximum Power Mitigation Mechanism, an optional power management mechanism
|
||||
supported by some Arm Armv9-A cores.
|
||||
|
||||
MPIDR
|
||||
Multiprocessor Affinity Register
|
||||
|
||||
MTE
|
||||
Memory Tagging Extension. An optional Armv8.5 extension that enables
|
||||
hardware-assisted memory tagging.
|
||||
|
||||
OEN
|
||||
Owning Entity Number
|
||||
|
||||
OP-TEE
|
||||
Open Portable Trusted Execution Environment. An example of a :term:`TEE`
|
||||
|
||||
OTE
|
||||
Open-source Trusted Execution Environment
|
||||
|
||||
PDD
|
||||
Platform Design Document
|
||||
|
||||
PAUTH
|
||||
Pointer Authentication. An optional extension introduced in Armv8.3.
|
||||
|
||||
PMF
|
||||
Performance Measurement Framework
|
||||
|
||||
PSA
|
||||
Platform Security Architecture
|
||||
|
||||
PSCI
|
||||
Power State Coordination Interface
|
||||
|
||||
RAS
|
||||
Reliability, Availability, and Serviceability extensions. A mandatory
|
||||
extension for the Armv8.2 architecture and later. An optional extension to
|
||||
the base Armv8 architecture.
|
||||
|
||||
ROT
|
||||
Root of Trust
|
||||
|
||||
SCMI
|
||||
System Control and Management Interface
|
||||
|
||||
SCP
|
||||
System Control Processor
|
||||
|
||||
SDEI
|
||||
Software Delegated Exception Interface
|
||||
|
||||
SDS
|
||||
Shared Data Storage
|
||||
|
||||
SEA
|
||||
Synchronous External Abort
|
||||
|
||||
SiP
|
||||
SIP
|
||||
Silicon Provider
|
||||
|
||||
SMC
|
||||
Secure Monitor Call
|
||||
|
||||
SMCCC
|
||||
:term:`SMC` Calling Convention
|
||||
|
||||
SoC
|
||||
System on Chip
|
||||
|
||||
SP
|
||||
Secure Partition
|
||||
|
||||
SPD
|
||||
Secure Payload Dispatcher
|
||||
|
||||
SPM
|
||||
Secure Partition Manager
|
||||
|
||||
SSBS
|
||||
Speculative Store Bypass Safe. Introduced in Armv8.5, this configuration
|
||||
bit can be set by software to allow or prevent the hardware from
|
||||
performing speculative operations.
|
||||
|
||||
SVE
|
||||
Scalable Vector Extension
|
||||
|
||||
TBB
|
||||
Trusted Board Boot
|
||||
|
||||
TBBR
|
||||
Trusted Board Boot Requirements
|
||||
|
||||
TCB
|
||||
Trusted Compute Base
|
||||
|
||||
TEE
|
||||
Trusted Execution Environment
|
||||
|
||||
TF-A
|
||||
Trusted Firmware-A
|
||||
|
||||
TF-M
|
||||
Trusted Firmware-M
|
||||
|
||||
TLB
|
||||
Translation Lookaside Buffer
|
||||
|
||||
TLK
|
||||
Trusted Little Kernel. A Trusted OS from NVIDIA.
|
||||
|
||||
TRNG
|
||||
True Randon Number Generator (hardware based)
|
||||
|
||||
TSP
|
||||
Test Secure Payload
|
||||
|
||||
TZC
|
||||
TrustZone Controller
|
||||
|
||||
UBSAN
|
||||
Undefined Behavior Sanitizer
|
||||
|
||||
UEFI
|
||||
Unified Extensible Firmware Interface
|
||||
|
||||
WDOG
|
||||
Watchdog
|
||||
|
||||
XLAT
|
||||
Translation (abbr.). For example, "XLAT table".
|
||||
|
||||
.. _`Arm Glossary`: https://developer.arm.com/support/arm-glossary
|
||||
96
arm-trusted-firmware/docs/index.rst
Normal file
96
arm-trusted-firmware/docs/index.rst
Normal file
@@ -0,0 +1,96 @@
|
||||
Trusted Firmware-A Documentation
|
||||
================================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:numbered:
|
||||
|
||||
Home<self>
|
||||
about/index
|
||||
getting_started/index
|
||||
process/index
|
||||
components/index
|
||||
design/index
|
||||
plat/index
|
||||
perf/index
|
||||
security_advisories/index
|
||||
design_documents/index
|
||||
threat_model/index
|
||||
change-log
|
||||
glossary
|
||||
license
|
||||
|
||||
Trusted Firmware-A (TF-A) provides a reference implementation of secure world
|
||||
software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
|
||||
at Exception Level 3 (EL3). It implements various Arm interface standards,
|
||||
such as:
|
||||
|
||||
- The `Power State Coordination Interface (PSCI)`_
|
||||
- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_
|
||||
- `SMC Calling Convention`_
|
||||
- `System Control and Management Interface (SCMI)`_
|
||||
- `Software Delegated Exception Interface (SDEI)`_
|
||||
- `PSA FW update specification`_
|
||||
|
||||
Where possible, the code is designed for reuse or porting to other Armv7-A and
|
||||
Armv8-A model and hardware platforms.
|
||||
|
||||
This release provides a suitable starting point for productization of secure
|
||||
world boot and runtime firmware, in either the AArch32 or AArch64 execution
|
||||
states.
|
||||
|
||||
Users are encouraged to do their own security validation, including penetration
|
||||
testing, on any secure world code derived from TF-A.
|
||||
|
||||
In collaboration with interested parties, we will continue to enhance |TF-A|
|
||||
with reference implementations of Arm standards to benefit developers working
|
||||
with Armv7-A and Armv8-A TrustZone technology.
|
||||
|
||||
Getting Started
|
||||
---------------
|
||||
|
||||
The |TF-A| documentation contains guidance for obtaining and building the
|
||||
software for existing, supported platforms, as well as supporting information
|
||||
for porting the software to a new platform.
|
||||
|
||||
The **About** chapter gives a high-level overview of |TF-A| features as well as
|
||||
some information on the project and how it is organized.
|
||||
|
||||
Refer to the documents in the **Getting Started** chapter for information about
|
||||
the prerequisites and requirements for building |TF-A|.
|
||||
|
||||
The **Processes & Policies** chapter explains the project's release schedule
|
||||
and process, how security disclosures are handled, and the guidelines for
|
||||
contributing to the project (including the coding style).
|
||||
|
||||
The **Components** chapter holds documents that explain specific components
|
||||
that make up the |TF-A| software, the :ref:`Exception Handling Framework`, for
|
||||
example.
|
||||
|
||||
In the **System Design** chapter you will find documents that explain the
|
||||
design of portions of the software that involve more than one component, such
|
||||
as the :ref:`Trusted Board Boot` process.
|
||||
|
||||
**Platform Ports** provides a list of the supported hardware and software-model
|
||||
platforms that are supported upstream in |TF-A|. Most of these platforms also
|
||||
have additional documentation that has been provided by the maintainers of the
|
||||
platform.
|
||||
|
||||
The results of any performance evaluations are added to the
|
||||
**Performance & Testing** chapter.
|
||||
|
||||
**Security Advisories** holds a list of documents relating to |CVE| entries that
|
||||
have previously been raised against the software.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
|
||||
.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
|
||||
.. _Power State Coordination Interface (PSCI): http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
|
||||
.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
|
||||
.. _System Control and Management Interface (SCMI): http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
|
||||
.. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
|
||||
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
|
||||
.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
|
||||
90
arm-trusted-firmware/docs/license.rst
Normal file
90
arm-trusted-firmware/docs/license.rst
Normal file
@@ -0,0 +1,90 @@
|
||||
License
|
||||
=======
|
||||
|
||||
The software is provided under a BSD-3-Clause license (below). Contributions to
|
||||
this project are accepted under the same license with developer sign-off as
|
||||
described in the :ref:`Contributor's Guide`.
|
||||
|
||||
::
|
||||
|
||||
Copyright (c) [XXXX-]YYYY, <OWNER>. All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
- Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
- Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
- Neither the name of Arm nor the names of its contributors may be used to
|
||||
endorse or promote products derived from this software without specific
|
||||
prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
SPDX Identifiers
|
||||
----------------
|
||||
|
||||
Individual files contain the following tag instead of the full license text.
|
||||
|
||||
::
|
||||
|
||||
SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
This enables machine processing of license information based on the SPDX
|
||||
License Identifiers that are here available: http://spdx.org/licenses/
|
||||
|
||||
|
||||
Other Projects
|
||||
--------------
|
||||
|
||||
This project contains code from other projects as listed below. The original
|
||||
license text is included in those source files.
|
||||
|
||||
- The libc source code is derived from `FreeBSD`_ and `SCC`_. FreeBSD uses
|
||||
various BSD licenses, including BSD-3-Clause and BSD-2-Clause. The SCC code
|
||||
is used under the BSD-3-Clause license with the author's permission.
|
||||
|
||||
- The libfdt source code is disjunctively dual licensed
|
||||
(GPL-2.0+ OR BSD-2-Clause). It is used by this project under the terms of
|
||||
the BSD-2-Clause license. Any contributions to this code must be made under
|
||||
the terms of both licenses.
|
||||
|
||||
- The LLVM compiler-rt source code is disjunctively dual licensed
|
||||
(NCSA OR MIT). It is used by this project under the terms of the NCSA
|
||||
license (also known as the University of Illinois/NCSA Open Source License),
|
||||
which is a permissive license compatible with BSD-3-Clause. Any
|
||||
contributions to this code must be made under the terms of both licenses.
|
||||
|
||||
- The zlib source code is licensed under the Zlib license, which is a
|
||||
permissive license compatible with BSD-3-Clause.
|
||||
|
||||
- Some STMicroelectronics platform source code is disjunctively dual licensed
|
||||
(GPL-2.0+ OR BSD-3-Clause). It is used by this project under the terms of the
|
||||
BSD-3-Clause license. Any contributions to this code must be made under the
|
||||
terms of both licenses.
|
||||
|
||||
- Some source files originating from the Linux source tree, which are
|
||||
disjunctively dual licensed (GPL-2.0 OR MIT), are redistributed under the
|
||||
terms of the MIT license. These files are:
|
||||
|
||||
- ``include/dt-bindings/interrupt-controller/arm-gic.h``
|
||||
- ``include/dt-bindings/interrupt-controller/irq.h``
|
||||
|
||||
See the original `Linux MIT license`_.
|
||||
|
||||
.. _FreeBSD: http://www.freebsd.org
|
||||
.. _Linux MIT license: https://raw.githubusercontent.com/torvalds/linux/master/LICENSES/preferred/MIT
|
||||
.. _SCC: http://www.simple-cc.org/
|
||||
14
arm-trusted-firmware/docs/perf/index.rst
Normal file
14
arm-trusted-firmware/docs/perf/index.rst
Normal file
@@ -0,0 +1,14 @@
|
||||
Performance & Testing
|
||||
=====================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Contents
|
||||
|
||||
psci-performance-juno
|
||||
tsp
|
||||
performance-monitoring-unit
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
|
||||
158
arm-trusted-firmware/docs/perf/performance-monitoring-unit.rst
Normal file
158
arm-trusted-firmware/docs/perf/performance-monitoring-unit.rst
Normal file
@@ -0,0 +1,158 @@
|
||||
Performance Monitoring Unit
|
||||
===========================
|
||||
|
||||
The Performance Monitoring Unit (PMU) allows recording of architectural and
|
||||
microarchitectural events for profiling purposes.
|
||||
|
||||
This document gives an overview of the PMU counter configuration to assist with
|
||||
implementation and to complement the PMU security guidelines given in the
|
||||
:ref:`Secure Development Guidelines` document.
|
||||
|
||||
.. note::
|
||||
This section applies to Armv8-A implementations which have version 3
|
||||
of the Performance Monitors Extension (PMUv3).
|
||||
|
||||
PMU Counters
|
||||
------------
|
||||
|
||||
The PMU makes 32 counters available at all privilege levels:
|
||||
|
||||
- 31 programmable event counters: ``PMEVCNTR<n>``, where ``n`` is ``0`` to
|
||||
``30``.
|
||||
- A dedicated cycle counter: ``PMCCNTR``.
|
||||
|
||||
Architectural mappings
|
||||
~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
+--------------+---------+----------------------------+
|
||||
| Counters | State | System Register Name |
|
||||
+==============+=========+============================+
|
||||
| | AArch64 | ``PMEVCNTR<n>_EL0[63*:0]`` |
|
||||
| Programmable +---------+----------------------------+
|
||||
| | AArch32 | ``PMEVCNTR<n>[31:0]`` |
|
||||
+--------------+---------+----------------------------+
|
||||
| | AArch64 | ``PMCCNTR_EL0[63:0]`` |
|
||||
| Cycle +---------+----------------------------+
|
||||
| | AArch32 | ``PMCCNTR[63:0]`` |
|
||||
+--------------+---------+----------------------------+
|
||||
|
||||
.. note::
|
||||
Bits [63:32] are only available if ARMv8.5-PMU is implemented. Refer to the
|
||||
`Arm ARM`_ for a detailed description of ARMv8.5-PMU features.
|
||||
|
||||
Configuring the PMU for counting events
|
||||
---------------------------------------
|
||||
|
||||
Each programmable counter has an associated register, ``PMEVTYPER<n>`` which
|
||||
configures it. The cycle counter has the ``PMCCFILTR_EL0`` register, which has
|
||||
an identical function and bit field layout as ``PMEVTYPER<n>``. In addition,
|
||||
the counters are enabled (permitted to increment) via the ``PMCNTENSET`` and
|
||||
``PMCR`` registers. These can be accessed at all privilege levels.
|
||||
|
||||
Architectural mappings
|
||||
~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
+-----------------------------+------------------------+
|
||||
| AArch64 | AArch32 |
|
||||
+=============================+========================+
|
||||
| ``PMEVTYPER<n>_EL0[63*:0]`` | ``PMEVTYPER<n>[31:0]`` |
|
||||
+-----------------------------+------------------------+
|
||||
| ``PMCCFILTR_EL0[63*:0]`` | ``PMCCFILTR[31:0]`` |
|
||||
+-----------------------------+------------------------+
|
||||
| ``PMCNTENSET_EL0[63*:0]`` | ``PMCNTENSET[31:0]`` |
|
||||
+-----------------------------+------------------------+
|
||||
| ``PMCR_EL0[63*:0]`` | ``PMCR[31:0]`` |
|
||||
+-----------------------------+------------------------+
|
||||
|
||||
.. note::
|
||||
Bits [63:32] are reserved.
|
||||
|
||||
Relevant register fields
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
For ``PMEVTYPER<n>_EL0``/``PMEVTYPER<n>`` and ``PMCCFILTR_EL0/PMCCFILTR``, the
|
||||
most important fields are:
|
||||
|
||||
- ``P``:
|
||||
|
||||
- Bit 31.
|
||||
- If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
|
||||
|
||||
- ``NSK``:
|
||||
|
||||
- Bit 29.
|
||||
- If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
|
||||
Non-secure EL1.
|
||||
- Reserved if EL3 not implemented.
|
||||
|
||||
- ``NSH``:
|
||||
|
||||
- Bit 27.
|
||||
- If set to ``1``, will increment the associated ``PMEVCNTR<n>`` at EL2.
|
||||
- Reserved if EL2 not implemented.
|
||||
|
||||
- ``SH``:
|
||||
|
||||
- Bit 24.
|
||||
- If different to the ``NSH`` bit it enables the associated ``PMEVCNTR<n>``
|
||||
at Secure EL2.
|
||||
- Reserved if Secure EL2 not implemented.
|
||||
|
||||
- ``M``:
|
||||
|
||||
- Bit 26.
|
||||
- If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
|
||||
EL3.
|
||||
|
||||
- ``evtCount[15:10]``:
|
||||
|
||||
- Extension to ``evtCount[9:0]``. Reserved unless ARMv8.1-PMU implemented.
|
||||
|
||||
- ``evtCount[9:0]``:
|
||||
|
||||
- The event number that the associated ``PMEVCNTR<n>`` will count.
|
||||
|
||||
For ``PMCNTENSET_EL0``/``PMCNTENSET``, the most important fields are:
|
||||
|
||||
- ``P[30:0]``:
|
||||
|
||||
- Setting bit ``P[n]`` to ``1`` enables counter ``PMEVCNTR<n>``.
|
||||
- The effects of ``PMEVTYPER<n>`` are applied on top of this.
|
||||
In other words, the counter will not increment at any privilege level or
|
||||
security state unless it is enabled here.
|
||||
|
||||
- ``C``:
|
||||
|
||||
- Bit 31.
|
||||
- If set to ``1`` enables the cycle counter ``PMCCNTR``.
|
||||
|
||||
For ``PMCR``/``PMCR_EL0``, the most important fields are:
|
||||
|
||||
- ``DP``:
|
||||
|
||||
- Bit 5.
|
||||
- If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
|
||||
counting (by ``PMEVCNTR<n>``) is prohibited (e.g. EL2 and the Secure
|
||||
world).
|
||||
- If set to ``0``, ``PMCCNTR`` will not be affected by this bit and
|
||||
therefore will be able to count where the programmable counters are
|
||||
prohibited.
|
||||
|
||||
- ``E``:
|
||||
|
||||
- Bit 0.
|
||||
- Enables/disables counting altogether.
|
||||
- The effects of ``PMCNTENSET`` and ``PMCR.DP`` are applied on top of this.
|
||||
In other words, if this bit is ``0`` then no counters will increment
|
||||
regardless of how the other PMU system registers or bit fields are
|
||||
configured.
|
||||
|
||||
.. rubric:: References
|
||||
|
||||
- `Arm ARM`_
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
|
||||
292
arm-trusted-firmware/docs/perf/psci-performance-juno.rst
Normal file
292
arm-trusted-firmware/docs/perf/psci-performance-juno.rst
Normal file
@@ -0,0 +1,292 @@
|
||||
PSCI Performance Measurements on Arm Juno Development Platform
|
||||
==============================================================
|
||||
|
||||
This document summarises the findings of performance measurements of key
|
||||
operations in the Trusted Firmware-A Power State Coordination Interface (PSCI)
|
||||
implementation, using the in-built Performance Measurement Framework (PMF) and
|
||||
runtime instrumentation timestamps.
|
||||
|
||||
Method
|
||||
------
|
||||
|
||||
We used the `Juno R1 platform`_ for these tests, which has 4 x Cortex-A53 and 2
|
||||
x Cortex-A57 clusters running at the following frequencies:
|
||||
|
||||
+-----------------+--------------------+
|
||||
| Domain | Frequency (MHz) |
|
||||
+=================+====================+
|
||||
| Cortex-A57 | 900 (nominal) |
|
||||
+-----------------+--------------------+
|
||||
| Cortex-A53 | 650 (underdrive) |
|
||||
+-----------------+--------------------+
|
||||
| AXI subsystem | 533 |
|
||||
+-----------------+--------------------+
|
||||
|
||||
Juno supports CPU, cluster and system power down states, corresponding to power
|
||||
levels 0, 1 and 2 respectively. It does not support any retention states.
|
||||
|
||||
We used the upstream `TF master as of 31/01/2017`_, building the platform using
|
||||
the ``ENABLE_RUNTIME_INSTRUMENTATION`` option:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=juno ENABLE_RUNTIME_INSTRUMENTATION=1 \
|
||||
SCP_BL2=<path/to/scp-fw.bin> \
|
||||
BL33=<path/to/test-fw.bin> \
|
||||
all fip
|
||||
|
||||
When using the debug build of TF, there was no noticeable difference in the
|
||||
results.
|
||||
|
||||
The tests are based on an ARM-internal test framework. The release build of this
|
||||
framework was used because the results in the debug build became skewed; the
|
||||
console output prevented some of the tests from executing in parallel.
|
||||
|
||||
The tests consist of both parallel and sequential tests, which are broadly
|
||||
described as follows:
|
||||
|
||||
- **Parallel Tests** This type of test powers on all the non-lead CPUs and
|
||||
brings them and the lead CPU to a common synchronization point. The lead CPU
|
||||
then initiates the test on all CPUs in parallel.
|
||||
|
||||
- **Sequential Tests** This type of test powers on each non-lead CPU in
|
||||
sequence. The lead CPU initiates the test on a non-lead CPU then waits for the
|
||||
test to complete before proceeding to the next non-lead CPU. The lead CPU then
|
||||
executes the test on itself.
|
||||
|
||||
In the results below, CPUs 0-3 refer to CPUs in the little cluster (A53) and
|
||||
CPUs 4-5 refer to CPUs in the big cluster (A57). In all cases CPU 4 is the lead
|
||||
CPU.
|
||||
|
||||
``PSCI_ENTRY`` refers to the time taken from entering the TF PSCI implementation
|
||||
to the point the hardware enters the low power state (WFI). Referring to the TF
|
||||
runtime instrumentation points, this corresponds to:
|
||||
``(RT_INSTR_ENTER_HW_LOW_PWR - RT_INSTR_ENTER_PSCI)``.
|
||||
|
||||
``PSCI_EXIT`` refers to the time taken from the point the hardware exits the low
|
||||
power state to exiting the TF PSCI implementation. This corresponds to:
|
||||
``(RT_INSTR_EXIT_PSCI - RT_INSTR_EXIT_HW_LOW_PWR)``.
|
||||
|
||||
``CFLUSH_OVERHEAD`` refers to the part of ``PSCI_ENTRY`` taken to flush the
|
||||
caches. This corresponds to: ``(RT_INSTR_EXIT_CFLUSH - RT_INSTR_ENTER_CFLUSH)``.
|
||||
|
||||
Note there is very little variance observed in the values given (~1us), although
|
||||
the values for each CPU are sometimes interchanged, depending on the order in
|
||||
which locks are acquired. Also, there is very little variance observed between
|
||||
executing the tests sequentially in a single boot or rebooting between tests.
|
||||
|
||||
Given that runtime instrumentation using PMF is invasive, there is a small
|
||||
(unquantified) overhead on the results. PMF uses the generic counter for
|
||||
timestamps, which runs at 50MHz on Juno.
|
||||
|
||||
Results and Commentary
|
||||
----------------------
|
||||
|
||||
``CPU_SUSPEND`` to deepest power level on all CPUs in parallel
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| CPU | ``PSCI_ENTRY`` (us) | ``PSCI_EXIT`` (us) | ``CFLUSH_OVERHEAD`` (us) |
|
||||
+=======+=====================+====================+==========================+
|
||||
| 0 | 27 | 20 | 5 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 1 | 114 | 86 | 5 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 2 | 202 | 58 | 5 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 3 | 375 | 29 | 94 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 4 | 20 | 22 | 6 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 5 | 290 | 18 | 206 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
|
||||
A large variance in ``PSCI_ENTRY`` and ``PSCI_EXIT`` times across CPUs is
|
||||
observed due to TF PSCI lock contention. In the worst case, CPU 3 has to wait
|
||||
for the 3 other CPUs in the cluster (0-2) to complete ``PSCI_ENTRY`` and release
|
||||
the lock before proceeding.
|
||||
|
||||
The ``CFLUSH_OVERHEAD`` times for CPUs 3 and 5 are higher because they are the
|
||||
last CPUs in their respective clusters to power down, therefore both the L1 and
|
||||
L2 caches are flushed.
|
||||
|
||||
The ``CFLUSH_OVERHEAD`` time for CPU 5 is a lot larger than that for CPU 3
|
||||
because the L2 cache size for the big cluster is lot larger (2MB) compared to
|
||||
the little cluster (1MB).
|
||||
|
||||
``CPU_SUSPEND`` to power level 0 on all CPUs in parallel
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| CPU | ``PSCI_ENTRY`` (us) | ``PSCI_EXIT`` (us) | ``CFLUSH_OVERHEAD`` (us) |
|
||||
+=======+=====================+====================+==========================+
|
||||
| 0 | 116 | 14 | 8 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 1 | 204 | 14 | 8 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 2 | 287 | 13 | 8 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 3 | 376 | 13 | 9 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 4 | 29 | 15 | 7 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 5 | 21 | 15 | 8 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
|
||||
There is no lock contention in TF generic code at power level 0 but the large
|
||||
variance in ``PSCI_ENTRY`` times across CPUs is due to lock contention in Juno
|
||||
platform code. The platform lock is used to mediate access to a single SCP
|
||||
communication channel. This is compounded by the SCP firmware waiting for each
|
||||
AP CPU to enter WFI before making the channel available to other CPUs, which
|
||||
effectively serializes the SCP power down commands from all CPUs.
|
||||
|
||||
On platforms with a more efficient CPU power down mechanism, it should be
|
||||
possible to make the ``PSCI_ENTRY`` times smaller and consistent.
|
||||
|
||||
The ``PSCI_EXIT`` times are consistent across all CPUs because TF does not
|
||||
require locks at power level 0.
|
||||
|
||||
The ``CFLUSH_OVERHEAD`` times for all CPUs are small and consistent since only
|
||||
the cache associated with power level 0 is flushed (L1).
|
||||
|
||||
``CPU_SUSPEND`` to deepest power level on all CPUs in sequence
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| CPU | ``PSCI_ENTRY`` (us) | ``PSCI_EXIT`` (us) | ``CFLUSH_OVERHEAD`` (us) |
|
||||
+=======+=====================+====================+==========================+
|
||||
| 0 | 114 | 20 | 94 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 1 | 114 | 20 | 94 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 2 | 114 | 20 | 94 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 3 | 114 | 20 | 94 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 4 | 195 | 22 | 180 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 5 | 21 | 17 | 6 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
|
||||
The ``CFLUSH_OVERHEAD`` times for lead CPU 4 and all CPUs in the non-lead cluster
|
||||
are large because all other CPUs in the cluster are powered down during the
|
||||
test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a
|
||||
flush of both L1 and L2 caches.
|
||||
|
||||
The ``CFLUSH_OVERHEAD`` time for CPU 4 is a lot larger than those for the little
|
||||
CPUs because the L2 cache size for the big cluster is lot larger (2MB) compared
|
||||
to the little cluster (1MB).
|
||||
|
||||
The ``PSCI_ENTRY`` and ``CFLUSH_OVERHEAD`` times for CPU 5 are low because lead
|
||||
CPU 4 continues to run while CPU 5 is suspended. Hence CPU 5 only powers down to
|
||||
level 0, which only requires L1 cache flush.
|
||||
|
||||
``CPU_SUSPEND`` to power level 0 on all CPUs in sequence
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| CPU | ``PSCI_ENTRY`` (us) | ``PSCI_EXIT`` (us) | ``CFLUSH_OVERHEAD`` (us) |
|
||||
+=======+=====================+====================+==========================+
|
||||
| 0 | 22 | 14 | 5 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 1 | 22 | 14 | 5 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 2 | 21 | 14 | 5 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 3 | 22 | 14 | 5 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 4 | 17 | 14 | 6 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 5 | 18 | 15 | 6 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
|
||||
Here the times are small and consistent since there is no contention and it is
|
||||
only necessary to flush the cache to power level 0 (L1). This is the best case
|
||||
scenario.
|
||||
|
||||
The ``PSCI_ENTRY`` times for CPUs in the big cluster are slightly smaller than
|
||||
for the CPUs in little cluster due to greater CPU performance.
|
||||
|
||||
The ``PSCI_EXIT`` times are generally lower than in the last test because the
|
||||
cluster remains powered on throughout the test and there is less code to execute
|
||||
on power on (for example, no need to enter CCI coherency)
|
||||
|
||||
``CPU_OFF`` on all non-lead CPUs in sequence then ``CPU_SUSPEND`` on lead CPU to deepest power level
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The test sequence here is as follows:
|
||||
|
||||
1. Call ``CPU_ON`` and ``CPU_OFF`` on each non-lead CPU in sequence.
|
||||
|
||||
2. Program wake up timer and suspend the lead CPU to the deepest power level.
|
||||
|
||||
3. Call ``CPU_ON`` on non-lead CPU to get the timestamps from each CPU.
|
||||
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| CPU | ``PSCI_ENTRY`` (us) | ``PSCI_EXIT`` (us) | ``CFLUSH_OVERHEAD`` (us) |
|
||||
+=======+=====================+====================+==========================+
|
||||
| 0 | 110 | 28 | 93 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 1 | 110 | 28 | 93 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 2 | 110 | 28 | 93 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 3 | 111 | 28 | 93 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 4 | 195 | 22 | 181 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
| 5 | 20 | 23 | 6 |
|
||||
+-------+---------------------+--------------------+--------------------------+
|
||||
|
||||
The ``CFLUSH_OVERHEAD`` times for all little CPUs are large because all other
|
||||
CPUs in that cluster are powerered down during the test. The ``CPU_OFF`` call
|
||||
powers down to the cluster level, requiring a flush of both L1 and L2 caches.
|
||||
|
||||
The ``PSCI_ENTRY`` and ``CFLUSH_OVERHEAD`` times for CPU 5 are small because
|
||||
lead CPU 4 is running and CPU 5 only powers down to level 0, which only requires
|
||||
an L1 cache flush.
|
||||
|
||||
The ``CFLUSH_OVERHEAD`` time for CPU 4 is a lot larger than those for the little
|
||||
CPUs because the L2 cache size for the big cluster is lot larger (2MB) compared
|
||||
to the little cluster (1MB).
|
||||
|
||||
The ``PSCI_EXIT`` times for CPUs in the big cluster are slightly smaller than
|
||||
for CPUs in the little cluster due to greater CPU performance. These times
|
||||
generally are greater than the ``PSCI_EXIT`` times in the ``CPU_SUSPEND`` tests
|
||||
because there is more code to execute in the "on finisher" compared to the
|
||||
"suspend finisher" (for example, GIC redistributor register programming).
|
||||
|
||||
``PSCI_VERSION`` on all CPUs in parallel
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Since very little code is associated with ``PSCI_VERSION``, this test
|
||||
approximates the round trip latency for handling a fast SMC at EL3 in TF.
|
||||
|
||||
+-------+-------------------+
|
||||
| CPU | TOTAL TIME (ns) |
|
||||
+=======+===================+
|
||||
| 0 | 3020 |
|
||||
+-------+-------------------+
|
||||
| 1 | 2940 |
|
||||
+-------+-------------------+
|
||||
| 2 | 2980 |
|
||||
+-------+-------------------+
|
||||
| 3 | 3060 |
|
||||
+-------+-------------------+
|
||||
| 4 | 520 |
|
||||
+-------+-------------------+
|
||||
| 5 | 720 |
|
||||
+-------+-------------------+
|
||||
|
||||
The times for the big CPUs are less than the little CPUs due to greater CPU
|
||||
performance.
|
||||
|
||||
We suspect the time for lead CPU 4 is shorter than CPU 5 due to subtle cache
|
||||
effects, given that these measurements are at the nano-second level.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
|
||||
|
||||
.. _Juno R1 platform: https://static.docs.arm.com/100122/0100/arm_versatile_express_juno_r1_development_platform_(v2m_juno_r1)_technical_reference_manual_100122_0100_05_en.pdf
|
||||
.. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
|
||||
27
arm-trusted-firmware/docs/perf/tsp.rst
Normal file
27
arm-trusted-firmware/docs/perf/tsp.rst
Normal file
@@ -0,0 +1,27 @@
|
||||
Test Secure Payload (TSP) and Dispatcher (TSPD)
|
||||
===============================================
|
||||
|
||||
Building the Test Secure Payload
|
||||
--------------------------------
|
||||
|
||||
The TSP is coupled with a companion runtime service in the BL31 firmware,
|
||||
called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
|
||||
must be recompiled as well. For more information on SPs and SPDs, see the
|
||||
:ref:`firmware_design_sel1_spd` section in the :ref:`Firmware Design`.
|
||||
|
||||
First clean the TF-A build directory to get rid of any previous BL31 binary.
|
||||
Then to build the TSP image use:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=<platform> SPD=tspd all
|
||||
|
||||
An additional boot loader binary file is created in the ``build`` directory:
|
||||
|
||||
::
|
||||
|
||||
build/<platform>/<build-type>/bl32.bin
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019, Arm Limited. All rights reserved.*
|
||||
142
arm-trusted-firmware/docs/plat/allwinner.rst
Normal file
142
arm-trusted-firmware/docs/plat/allwinner.rst
Normal file
@@ -0,0 +1,142 @@
|
||||
Allwinner ARMv8 SoCs
|
||||
====================
|
||||
|
||||
Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Allwinner
|
||||
SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and
|
||||
PSCI runtime services.
|
||||
|
||||
Building TF-A
|
||||
-------------
|
||||
|
||||
There is one build target per supported SoC:
|
||||
|
||||
+------+-------------------+
|
||||
| SoC | TF-A build target |
|
||||
+======+===================+
|
||||
| A64 | sun50i_a64 |
|
||||
+------+-------------------+
|
||||
| H5 | sun50i_a64 |
|
||||
+------+-------------------+
|
||||
| H6 | sun50i_h6 |
|
||||
+------+-------------------+
|
||||
| H616 | sun50i_h616 |
|
||||
+------+-------------------+
|
||||
| H313 | sun50i_h616 |
|
||||
+------+-------------------+
|
||||
| R329 | sun50i_r329 |
|
||||
+------+-------------------+
|
||||
|
||||
To build with the default settings for a particular SoC:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=<build target> DEBUG=1
|
||||
|
||||
So for instance to build for a board with the Allwinner A64 SoC::
|
||||
|
||||
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1
|
||||
|
||||
Platform-specific build options
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The default build options should generate a working firmware image. There are
|
||||
some build options that allow to fine-tune the firmware, or to disable support
|
||||
for optional features.
|
||||
|
||||
- ``SUNXI_PSCI_USE_NATIVE`` : Support direct control of the CPU cores powerdown
|
||||
and powerup sequence by BL31. This requires either support for a code snippet
|
||||
to be loaded into the ARISC SCP (A64, H5), or the power sequence control
|
||||
registers to be programmed directly (H6, H616). This supports only basic
|
||||
control, like core on/off and system off/reset.
|
||||
This option defaults to 1. If an active SCP supporting the SCPI protocol
|
||||
is detected at runtime, this control scheme will be ignored, and SCPI
|
||||
will be used instead, unless support has been explicitly disabled.
|
||||
|
||||
- ``SUNXI_PSCI_USE_SCPI`` : Support control of the CPU cores powerdown and
|
||||
powerup sequence by talking to the SCP processor via the SCPI protocol.
|
||||
This allows more advanced power saving techniques, like suspend to RAM.
|
||||
This option defaults to 1 on SoCs that feature an SCP. If no SCP firmware
|
||||
using the SCPI protocol is detected, the native sequence will be used
|
||||
instead. If both native and SCPI methods are included, SCPI will be favoured
|
||||
if SCP support is detected.
|
||||
|
||||
- ``SUNXI_SETUP_REGULATORS`` : On SoCs that typically ship with a PMIC
|
||||
power management controller, BL31 tries to set up all needed power rails,
|
||||
programming them to their respective voltages. That allows bootloader
|
||||
software like U-Boot to ignore power control via the PMIC.
|
||||
This setting defaults to 1. In some situations that enables too many
|
||||
regulators, or some regulators need to be enabled in a very specific
|
||||
sequence. To avoid problems with those boards, ``SUNXI_SETUP_REGULATORS``
|
||||
can bet set to ``0`` on the build command line, to skip the PMIC setup
|
||||
entirely. Any bootloader or OS would need to setup the PMIC on its own then.
|
||||
|
||||
Installation
|
||||
------------
|
||||
|
||||
U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot).
|
||||
Loading is done from SD card, eMMC or SPI flash, also via an USB debug
|
||||
interface (FEL).
|
||||
|
||||
After building bl31.bin, the binary must be fed to the U-Boot build system
|
||||
to include it in the FIT image that the SPL loader will process.
|
||||
bl31.bin can be either copied (or sym-linked) into U-Boot's root directory,
|
||||
or the environment variable BL31 must contain the binary's path.
|
||||
See the respective `U-Boot documentation`_ for more details.
|
||||
|
||||
.. _U-Boot documentation: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/sunxi/README.sunxi64
|
||||
|
||||
Memory layout
|
||||
-------------
|
||||
|
||||
A64, H5 and H6 SoCs
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
BL31 lives in SRAM A2, which is documented to be accessible from secure
|
||||
world only. Since this SRAM region is very limited (48 KB), we take
|
||||
several measures to reduce memory consumption. One of them is to confine
|
||||
BL31 to only 28 bits of virtual address space, which reduces the number
|
||||
of required page tables (each occupying 4KB of memory).
|
||||
The mapping we use on those SoCs is as follows:
|
||||
|
||||
::
|
||||
|
||||
0 64K 16M 1GB 1G+160M physical address
|
||||
+-+------+-+---+------+--...---+-------+----+------+----------
|
||||
|B| |S|///| |//...///| |////| |
|
||||
|R| SRAM |C|///| dev |//...///| (sec) |////| BL33 | DRAM ...
|
||||
|O| |P|///| MMIO |//...///| DRAM |////| |
|
||||
|M| | |///| |//...///| (32M) |////| |
|
||||
+-+------+-+---+------+--...---+-------+----+------+----------
|
||||
| | | | | | / / / /
|
||||
| | | | | | / / / /
|
||||
| | | | | | / / / /
|
||||
| | | | | | / // /
|
||||
| | | | | | / / /
|
||||
+-+------+-+---+------+--+-------+------+
|
||||
|B| |S|///| |//| | |
|
||||
|R| SRAM |C|///| dev |//| sec | BL33 |
|
||||
|O| |P|///| MMIO |//| DRAM | |
|
||||
|M| | |///| |//| | |
|
||||
+-+------+-+---+------+--+-------+------+
|
||||
0 64K 16M 160M 192M 256M virtual address
|
||||
|
||||
|
||||
H616 SoC
|
||||
~~~~~~~~
|
||||
|
||||
The H616 lacks the secure SRAM region present on the other SoCs, also
|
||||
lacks the "ARISC" management processor (SCP) we use. BL31 thus needs to
|
||||
run from DRAM, which prevents our compressed virtual memory map described
|
||||
above. Since running in DRAM also lifts the restriction of the limited
|
||||
SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual
|
||||
address space. So the virtual addresses used in BL31 match the physical
|
||||
addresses as presented above.
|
||||
|
||||
Trusted OS dispatcher
|
||||
---------------------
|
||||
|
||||
One can boot Trusted OS(OP-TEE OS, bl32 image) along side bl31 image on Allwinner A64.
|
||||
|
||||
In order to include the 'opteed' dispatcher in the image, pass 'SPD=opteed' on the command line
|
||||
while compiling the bl31 image and make sure the loader (SPL) loads the Trusted OS binary to
|
||||
the beginning of DRAM (0x40000000).
|
||||
164
arm-trusted-firmware/docs/plat/arm/arm-build-options.rst
Normal file
164
arm-trusted-firmware/docs/plat/arm/arm-build-options.rst
Normal file
@@ -0,0 +1,164 @@
|
||||
Arm Development Platform Build Options
|
||||
======================================
|
||||
|
||||
Arm Platform Build Options
|
||||
--------------------------
|
||||
|
||||
- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
|
||||
DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
|
||||
BL31 in TZC secured DRAM. If TSP is present, then setting this option also
|
||||
sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
|
||||
flag.
|
||||
|
||||
- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
|
||||
frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
|
||||
frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which
|
||||
should match the frame used by the Non-Secure image (normally the Linux
|
||||
kernel). Default is true (access to the frame is allowed).
|
||||
|
||||
- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
|
||||
By default, Arm platforms use a watchdog to trigger a system reset in case
|
||||
an error is encountered during the boot process (for example, when an image
|
||||
could not be loaded or authenticated). The watchdog is enabled in the early
|
||||
platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
|
||||
Trusted Watchdog may be disabled at build time for testing or development
|
||||
purposes.
|
||||
|
||||
- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
|
||||
have specific values at boot. This boolean option allows the Trusted Firmware
|
||||
to have a Linux kernel image as BL33 by preparing the registers to these
|
||||
values before jumping to BL33. This option defaults to 0 (disabled). For
|
||||
AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
|
||||
using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
|
||||
to the location of a device tree blob (DTB) already loaded in memory. The
|
||||
Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
|
||||
option.
|
||||
|
||||
- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
|
||||
cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
|
||||
is set, the functions which deal with MPIDR assume that the ``MT`` bit in
|
||||
MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
|
||||
this flag is 0. Note that this option is not used on FVP platforms.
|
||||
|
||||
- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
|
||||
for the construction of composite state-ID in the power-state parameter.
|
||||
The existing PSCI clients currently do not support this encoding of
|
||||
State-ID yet. Hence this flag is used to configure whether to use the
|
||||
recommended State-ID encoding or not. The default value of this flag is 0,
|
||||
in which case the platform is configured to expect NULL in the State-ID
|
||||
field of power-state parameter.
|
||||
|
||||
- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
|
||||
location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
|
||||
for Arm platforms. Depending on the selected option, the proper private key
|
||||
must be specified using the ``ROT_KEY`` option when building the Trusted
|
||||
Firmware. This private key will be used by the certificate generation tool
|
||||
to sign the BL2 and Trusted Key certificates. Available options for
|
||||
``ARM_ROTPK_LOCATION`` are:
|
||||
|
||||
- ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
|
||||
registers.
|
||||
- ``devel_rsa`` : return a development public key hash embedded in the BL1
|
||||
and BL2 binaries. This hash has been obtained from the RSA public key
|
||||
``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
|
||||
this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY``
|
||||
when creating the certificates.
|
||||
- ``devel_ecdsa`` : return a development public key hash embedded in the BL1
|
||||
and BL2 binaries. This hash has been obtained from the ECDSA public key
|
||||
``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To
|
||||
use this option, ``arm_rotprivk_ecdsa.pem`` must be specified as
|
||||
``ROT_KEY`` when creating the certificates.
|
||||
|
||||
- ``ARM_ROTPK_HASH``: used when ``ARM_ROTPK_LOCATION=devel_*``. Specifies the
|
||||
location of the ROTPK hash. Not expected to be a build option. This defaults to
|
||||
``plat/arm/board/common/rotpk/*_sha256.bin`` depending on the specified algorithm.
|
||||
Providing ``ROT_KEY`` enforces generation of the hash from the ``ROT_KEY`` and
|
||||
overwrites the default hash file.
|
||||
|
||||
- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
|
||||
|
||||
- ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
|
||||
- ``tdram`` : Trusted DRAM (if available)
|
||||
- ``dram`` : Secure region in DRAM (default option when TBB is enabled,
|
||||
configured by the TrustZone controller)
|
||||
|
||||
- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
|
||||
of the translation tables library instead of version 2. It is set to 0 by
|
||||
default, which selects version 2.
|
||||
|
||||
- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
|
||||
TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
|
||||
platforms. If this option is specified, then the path to the CryptoCell
|
||||
SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
|
||||
|
||||
- ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
|
||||
configure an Arm® Ethos™-N NPU. To use this service the target platform's
|
||||
``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
|
||||
the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
|
||||
only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
|
||||
|
||||
- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the
|
||||
SPMC Core manifest. Valid when ``SPD=spmd`` is selected.
|
||||
|
||||
- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded
|
||||
SP nodes in tb_fw_config.
|
||||
|
||||
- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in tb_fw_config
|
||||
device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest
|
||||
file name contains pattern optee_sp.
|
||||
|
||||
- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and
|
||||
internal-trusted-storage) as SP in tb_fw_config device tree.
|
||||
|
||||
- ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of
|
||||
the various partitions present in the GPT image. This support is available
|
||||
only for the BL2 component, and it is disabled by default.
|
||||
The following diagram shows the view of the FIP partition inside the GPT
|
||||
image:
|
||||
|
||||
|FIP in a GPT image|
|
||||
|
||||
For a better understanding of these options, the Arm development platform memory
|
||||
map is explained in the :ref:`Firmware Design`.
|
||||
|
||||
.. _build_options_arm_css_platform:
|
||||
|
||||
Arm CSS Platform-Specific Build Options
|
||||
---------------------------------------
|
||||
|
||||
- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
|
||||
incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
|
||||
compatible change to the MTL protocol, used for AP/SCP communication.
|
||||
TF-A no longer supports earlier SCP versions. If this option is set to 1
|
||||
then TF-A will detect if an earlier version is in use. Default is 1.
|
||||
|
||||
- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
|
||||
SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
|
||||
during boot. Default is 1.
|
||||
|
||||
- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
|
||||
instead of SCPI/BOM driver for communicating with the SCP during power
|
||||
management operations and for SCP RAM Firmware transfer. If this option
|
||||
is set to 1, then SCMI/SDS drivers will be used. Default is 0.
|
||||
|
||||
- ``CSS_SGI_CHIP_COUNT``: Configures the number of chips on a SGI/RD platform
|
||||
which supports multi-chip operation. If ``CSS_SGI_CHIP_COUNT`` is set to any
|
||||
valid value greater than 1, the platform code performs required configuration
|
||||
to support multi-chip operation.
|
||||
|
||||
- ``CSS_SGI_PLATFORM_VARIANT``: Selects the variant of a SGI/RD platform. A
|
||||
particular SGI/RD platform may have multiple variants which may differ in
|
||||
core count, cluster count or other peripherals. This build option is used
|
||||
to select the appropriate platform variant for the build. The range of
|
||||
valid values is platform specific.
|
||||
|
||||
- ``CSS_SYSTEM_GRACEFUL_RESET``: Build option to enable graceful powerdown of
|
||||
CPU core on reset. This build option can be used on CSS platforms that
|
||||
require all the CPUs to execute the CPU specific power down sequence to
|
||||
complete a warm reboot sequence in which only the CPUs are power cycled.
|
||||
|
||||
--------------
|
||||
|
||||
.. |FIP in a GPT image| image:: ../../resources/diagrams/FIP_in_a_GPT_image.png
|
||||
|
||||
*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
|
||||
97
arm-trusted-firmware/docs/plat/arm/arm_fpga/index.rst
Normal file
97
arm-trusted-firmware/docs/plat/arm/arm_fpga/index.rst
Normal file
@@ -0,0 +1,97 @@
|
||||
Arm FPGA Platform
|
||||
=================
|
||||
|
||||
This platform supports FPGA images used internally in Arm Ltd., for
|
||||
testing and bringup of new cores. With that focus, peripheral support is
|
||||
minimal: there is no mass storage or display output, for instance. Also
|
||||
this port ignores any power management features of the platform.
|
||||
Some interconnect setup is done internally by the platform, so the TF-A code
|
||||
just needs to setup UART and GIC.
|
||||
|
||||
The FPGA platform requires to pass on a DTB for the non-secure payload
|
||||
(mostly Linux), so we let TF-A use information from the DTB for dynamic
|
||||
configuration: the UART and GIC base addresses are read from there.
|
||||
|
||||
As a result this port is a fairly generic BL31-only port, which can serve
|
||||
as a template for a minimal new (and possibly DT-based) platform port.
|
||||
|
||||
The aim of this port is to support as many FPGA images as possible with
|
||||
a single build. Image specific data must be described in the DTB or should
|
||||
be auto-detected at runtime.
|
||||
|
||||
As the number and topology layout of the CPU cores differs significantly
|
||||
across the various images, this is detected at runtime by BL31.
|
||||
The /cpus node in the DT will be added and filled accordingly, as long as
|
||||
it does not exist already.
|
||||
|
||||
Platform-specific build options
|
||||
-------------------------------
|
||||
|
||||
- ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers.
|
||||
Normally TF-A panics if it encounters a MPID value not matched to its
|
||||
internal list, but for new or experimental cores this creates a lot of
|
||||
churn. With this option, the code will fall back to some basic CPU support
|
||||
code (only architectural system registers, and no errata).
|
||||
Default value of this flag is 1.
|
||||
|
||||
- ``PRELOADED_BL33_BASE`` : Physical address of the BL33 non-secure payload.
|
||||
It must have been loaded into DRAM already, typically this is done by
|
||||
the script that also loads BL31 and the DTB.
|
||||
It defaults to 0x80080000, which is the traditional load address for an
|
||||
arm64 Linux kernel.
|
||||
|
||||
- ``FPGA_PRELOADED_DTB_BASE`` : Physical address of the flattened device
|
||||
tree blob (DTB). This DT will be used by TF-A for dynamic configuration,
|
||||
so it must describe at least the UART and a GICv3 interrupt controller.
|
||||
The DT gets amended by the code, to potentially add a command line and
|
||||
fill the CPU topology nodes. It will also be passed on to BL33, by
|
||||
putting its address into the x0 register before jumping to the entry
|
||||
point (following the Linux kernel boot protocol).
|
||||
It defaults to 0x80070000, which is 64KB before the BL33 load address.
|
||||
|
||||
- ``FPGA_PRELOADED_CMD_LINE`` : Physical address of the command line to
|
||||
put into the devicetree blob. Due to the lack of a proper bootloader,
|
||||
a command line can be put somewhere into memory, so that BL31 will
|
||||
detect it and copy it into the DTB passed on to BL33.
|
||||
To avoid random garbage, there needs to be a "CMD:" signature before the
|
||||
actual command line.
|
||||
Defaults to 0x1000, which is normally in the "ROM" space of the typical
|
||||
FPGA image (which can be written by the FPGA payload uploader, but is
|
||||
read-only to the CPU). The FPGA payload tool should be given a text file
|
||||
containing the desired command line, prefixed by the "CMD:" signature.
|
||||
|
||||
Building the TF-A image
|
||||
-----------------------
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=arm_fgpa DEBUG=1
|
||||
|
||||
This will use the default load addresses as described above. When those
|
||||
addresses need to differ for a certain setup, they can be passed on the
|
||||
make command line:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=arm_fgpa DEBUG=1 PRELOADED_BL33_BASE=0x80200000 FPGA_PRELOADED_DTB_BASE=0x80180000 bl31
|
||||
|
||||
Running the TF-A image
|
||||
----------------------
|
||||
|
||||
After building TF-A, the actual TF-A code will be located in ``bl31.bin`` in
|
||||
the build directory.
|
||||
Additionally there is a ``bl31.axf`` ELF file, which contains BL31, as well
|
||||
as some simple ROM trampoline code (required by the Arm FPGA boot flow) and
|
||||
a generic DTB to support most of the FPGA images. This can be simply handed
|
||||
over to the FPGA payload uploader, which will take care of loading the
|
||||
components at their respective load addresses. In addition to this file
|
||||
you need at least a BL33 payload (typically a Linux kernel image), optionally
|
||||
a Linux initrd image file and possibly a command line:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
fpga-run ... -m bl31.axf -l auto -m Image -l 0x80080000 -m initrd.gz -l 0x84000000 -m cmdline.txt -l 0x1000
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2020, Arm Limited. All rights reserved.*
|
||||
61
arm-trusted-firmware/docs/plat/arm/corstone1000/index.rst
Normal file
61
arm-trusted-firmware/docs/plat/arm/corstone1000/index.rst
Normal file
@@ -0,0 +1,61 @@
|
||||
Corstone1000 Platform
|
||||
==========================
|
||||
|
||||
Some of the features of the Corstone1000 platform referenced in TF-A include:
|
||||
|
||||
- Cortex-A35 application processor (64-bit mode)
|
||||
- Secure Enclave
|
||||
- GIC-400
|
||||
- Trusted Board Boot
|
||||
|
||||
Boot Sequence
|
||||
-------------
|
||||
|
||||
The board boot relies on CoT (chain of trust). The trusted-firmware-a
|
||||
BL2 is extracted from the FIP and verified by the Secure Enclave
|
||||
processor. BL2 verification relies on the signature area at the
|
||||
beginning of the BL2 image. This area is needed by the SecureEnclave
|
||||
bootloader.
|
||||
|
||||
Then, the application processor is released from reset and starts by
|
||||
executing BL2.
|
||||
|
||||
BL2 performs the actions described in the trusted-firmware-a TBB design
|
||||
document.
|
||||
|
||||
Build Procedure (TF-A only)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
- Obtain AArch64 ELF bare-metal target `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
|
||||
Set the CROSS_COMPILE environment variable to point to the toolchain folder.
|
||||
|
||||
- Build TF-A:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make LD=aarch64-none-elf-ld \
|
||||
CC=aarch64-none-elf-gcc \
|
||||
V=1 \
|
||||
BUILD_BASE=<path to the build folder> \
|
||||
PLAT=corstone1000 \
|
||||
SPD=spmd \
|
||||
SPMD_SPM_AT_SEL2=0 \
|
||||
DEBUG=1 \
|
||||
MBEDTLS_DIR=mbedtls \
|
||||
OPENSSL_DIR=<path to openssl usr folder> \
|
||||
RUNTIME_SYSROOT=<path to the sysroot> \
|
||||
ARCH=aarch64 \
|
||||
TARGET_PLATFORM=<fpga or fvp> \
|
||||
ENABLE_PIE=1 \
|
||||
BL2_AT_EL3=1 \
|
||||
CREATE_KEYS=1 \
|
||||
GENERATE_COT=1 \
|
||||
TRUSTED_BOARD_BOOT=1 \
|
||||
COT=tbbr \
|
||||
ARM_ROTPK_LOCATION=devel_rsa \
|
||||
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
|
||||
BL32=<path to optee binary> \
|
||||
BL33=<path to u-boot binary> \
|
||||
bl2
|
||||
|
||||
*Copyright (c) 2021, Arm Limited. All rights reserved.*
|
||||
84
arm-trusted-firmware/docs/plat/arm/fvp-ve/index.rst
Normal file
84
arm-trusted-firmware/docs/plat/arm/fvp-ve/index.rst
Normal file
@@ -0,0 +1,84 @@
|
||||
Arm Versatile Express
|
||||
=====================
|
||||
|
||||
Versatile Express (VE) family development platform provides an ultra fast
|
||||
environment for prototyping Armv7 System-on-Chip designs. VE Fixed Virtual
|
||||
Platforms (FVP) are simulations of Versatile Express boards. The platform in
|
||||
Trusted Firmware-A has been verified with Arm Cortex-A5 and Cortex-A7 VE FVP's.
|
||||
This platform is tested on and only expected to work with single core models.
|
||||
|
||||
Boot Sequence
|
||||
-------------
|
||||
|
||||
BL1 --> BL2 --> BL32(sp_min) --> BL33(u-boot) --> Linux kernel
|
||||
|
||||
How to build
|
||||
------------
|
||||
|
||||
Code Locations
|
||||
~~~~~~~~~~~~~~
|
||||
- `U-boot <https://git.linaro.org/landing-teams/working/arm/u-boot.git>`__
|
||||
|
||||
- `Trusted Firmware-A <https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git>`__
|
||||
|
||||
Build Procedure
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
- Obtain arm toolchain. The software stack has been verified with linaro 6.2
|
||||
`arm-linux-gnueabihf <https://releases.linaro.org/components/toolchain/binaries/6.2-2016.11/arm-linux-gnueabihf/>`__.
|
||||
Set the CROSS_COMPILE environment variable to point to the toolchain folder.
|
||||
|
||||
- Fetch and build u-boot.
|
||||
Make the .config file using the command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make ARCH=arm vexpress_aemv8a_aarch32_config
|
||||
|
||||
Make the u-boot binary for Cortex-A5 using the command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make ARCH=arm SUPPORT_ARCH_TIMER=no
|
||||
|
||||
Make the u-boot binary for Cortex-A7 using the command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make ARCH=arm
|
||||
|
||||
|
||||
- Build TF-A:
|
||||
|
||||
The make command for Cortex-A5 is:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=fvp_ve ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A5=yes \
|
||||
AARCH32_SP=sp_min FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A5x1.dts \
|
||||
ARM_XLAT_TABLES_LIB_V1=1 BL33=<path_to_u-boot.bin> all fip
|
||||
|
||||
The make command for Cortex-A7 is:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=fvp_ve ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes \
|
||||
AARCH32_SP=sp_min FVP_HW_CONFIG_DTS=fdts/fvp-ve-Cortex-A7x1.dts \
|
||||
BL33=<path_to_u-boot.bin> all fip
|
||||
|
||||
Run Procedure
|
||||
~~~~~~~~~~~~~
|
||||
|
||||
The following model parameters should be used to boot Linux using the build of
|
||||
Trusted Firmware-A made using the above make commands:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
./<path_to_model> <path_to_bl1.elf> \
|
||||
-C motherboard.flashloader1.fname=<path_to_fip.bin> \
|
||||
--data cluster.cpu0=<path_to_zImage>@0x80080000 \
|
||||
--data cluster.cpu0=<path_to_ramdisk>@0x84000000
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019, Arm Limited. All rights reserved.*
|
||||
640
arm-trusted-firmware/docs/plat/arm/fvp/index.rst
Normal file
640
arm-trusted-firmware/docs/plat/arm/fvp/index.rst
Normal file
@@ -0,0 +1,640 @@
|
||||
Arm Fixed Virtual Platforms (FVP)
|
||||
=================================
|
||||
|
||||
Fixed Virtual Platform (FVP) Support
|
||||
------------------------------------
|
||||
|
||||
This section lists the supported Arm |FVP| platforms. Please refer to the FVP
|
||||
documentation for a detailed description of the model parameter options.
|
||||
|
||||
The latest version of the AArch64 build of TF-A has been tested on the following
|
||||
Arm FVPs without shifted affinities, and that do not support threaded CPU cores
|
||||
(64-bit host machine only).
|
||||
|
||||
.. note::
|
||||
The FVP models used are Version 11.19 Build 14, unless otherwise stated.
|
||||
|
||||
- ``Foundation_Platform``
|
||||
- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21)
|
||||
- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21)
|
||||
- ``FVP_Base_AEMvA``
|
||||
- ``FVP_Base_AEMvA-AEMvA``
|
||||
- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38)
|
||||
- ``FVP_Base_Cortex-A35x4``
|
||||
- ``FVP_Base_Cortex-A53x4``
|
||||
- ``FVP_Base_Cortex-A55``
|
||||
- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
|
||||
- ``FVP_Base_Cortex-A55x4+Cortex-A76x2``
|
||||
- ``FVP_Base_Cortex-A57x1-A53x1``
|
||||
- ``FVP_Base_Cortex-A57x2-A53x4``
|
||||
- ``FVP_Base_Cortex-A57x4``
|
||||
- ``FVP_Base_Cortex-A57x4-A53x4``
|
||||
- ``FVP_Base_Cortex-A65``
|
||||
- ``FVP_Base_Cortex-A65AE``
|
||||
- ``FVP_Base_Cortex-A710x4`` (Version 11.17/21)
|
||||
- ``FVP_Base_Cortex-A72x4``
|
||||
- ``FVP_Base_Cortex-A72x4-A53x4``
|
||||
- ``FVP_Base_Cortex-A73x4``
|
||||
- ``FVP_Base_Cortex-A73x4-A53x4``
|
||||
- ``FVP_Base_Cortex-A75``
|
||||
- ``FVP_Base_Cortex-A76``
|
||||
- ``FVP_Base_Cortex-A76AE``
|
||||
- ``FVP_Base_Cortex-A77``
|
||||
- ``FVP_Base_Cortex-A78``
|
||||
- ``FVP_Base_Cortex-A78C``
|
||||
- ``FVP_Base_Cortex-X2x4`` (Version 11.17/21)
|
||||
- ``FVP_Base_Neoverse-E1``
|
||||
- ``FVP_Base_Neoverse-N1``
|
||||
- ``FVP_Base_Neoverse-N2x4`` (Version 11.16/16)
|
||||
- ``FVP_Base_Neoverse-V1``
|
||||
- ``FVP_Base_RevC-2xAEMvA``
|
||||
- ``FVP_Morello`` (Version 0.11/33)
|
||||
- ``FVP_RD_E1_edge`` (Version 11.17/29)
|
||||
- ``FVP_RD_V1`` (Version 11.17/29)
|
||||
- ``FVP_TC0`` (Version 11.17/18)
|
||||
- ``FVP_TC1`` (Version 11.17/33)
|
||||
- ``FVP_TC2`` (Version 11.18/28)
|
||||
|
||||
The latest version of the AArch32 build of TF-A has been tested on the
|
||||
following Arm FVPs without shifted affinities, and that do not support threaded
|
||||
CPU cores (64-bit host machine only).
|
||||
|
||||
- ``FVP_Base_AEMvA``
|
||||
- ``FVP_Base_AEMvA-AEMvA``
|
||||
- ``FVP_Base_Cortex-A32x4``
|
||||
|
||||
.. note::
|
||||
The ``FVP_Base_RevC-2xAEMvA`` FVP only supports shifted affinities, which
|
||||
is not compatible with legacy GIC configurations. Therefore this FVP does not
|
||||
support these legacy GIC configurations.
|
||||
|
||||
The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
|
||||
FVP website`_. The Cortex-A models listed above are also available to download
|
||||
from `Arm's website`_.
|
||||
|
||||
.. note::
|
||||
The build numbers quoted above are those reported by launching the FVP
|
||||
with the ``--version`` parameter.
|
||||
|
||||
.. note::
|
||||
Linaro provides a ramdisk image in prebuilt FVP configurations and full
|
||||
file systems that can be downloaded separately. To run an FVP with a virtio
|
||||
file system image an additional FVP configuration option
|
||||
``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
|
||||
used.
|
||||
|
||||
.. note::
|
||||
The software will not work on Version 1.0 of the Foundation FVP.
|
||||
The commands below would report an ``unhandled argument`` error in this case.
|
||||
|
||||
.. note::
|
||||
FVPs can be launched with ``--cadi-server`` option such that a
|
||||
CADI-compliant debugger (for example, Arm DS-5) can connect to and control
|
||||
its execution.
|
||||
|
||||
.. warning::
|
||||
Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
|
||||
the internal synchronisation timings changed compared to older versions of
|
||||
the models. The models can be launched with ``-Q 100`` option if they are
|
||||
required to match the run time characteristics of the older versions.
|
||||
|
||||
All the above platforms have been tested with `Linaro Release 20.01`_.
|
||||
|
||||
.. _build_options_arm_fvp_platform:
|
||||
|
||||
Arm FVP Platform Specific Build Options
|
||||
---------------------------------------
|
||||
|
||||
- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
|
||||
build the topology tree within TF-A. By default TF-A is configured for dual
|
||||
cluster topology and this option can be used to override the default value.
|
||||
|
||||
- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
|
||||
default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
|
||||
explained in the options below:
|
||||
|
||||
- ``FVP_CCI`` : The CCI driver is selected. This is the default
|
||||
if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
|
||||
- ``FVP_CCN`` : The CCN driver is selected. This is the default
|
||||
if ``FVP_CLUSTER_COUNT`` > 2.
|
||||
|
||||
- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
|
||||
a single cluster. This option defaults to 4.
|
||||
|
||||
- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
|
||||
in the system. This option defaults to 1. Note that the build option
|
||||
``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
|
||||
|
||||
- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
|
||||
|
||||
- ``FVP_GICV2`` : The GICv2 only driver is selected
|
||||
- ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
|
||||
|
||||
- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
|
||||
to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
|
||||
details on HW_CONFIG. By default, this is initialized to a sensible DTS
|
||||
file in ``fdts/`` folder depending on other build options. But some cases,
|
||||
like shifted affinity format for MPIDR, cannot be detected at build time
|
||||
and this option is needed to specify the appropriate DTS file.
|
||||
|
||||
- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
|
||||
FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is
|
||||
similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
|
||||
HW_CONFIG blob instead of the DTS file. This option is useful to override
|
||||
the default HW_CONFIG selected by the build system.
|
||||
|
||||
- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
|
||||
inactive/fused CPU cores as read-only. The default value of this option
|
||||
is ``0``, which means the redistributor pages of all CPU cores are marked
|
||||
as read and write.
|
||||
|
||||
Booting Firmware Update images
|
||||
------------------------------
|
||||
|
||||
When Firmware Update (FWU) is enabled there are at least 2 new images
|
||||
that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
|
||||
FWU FIP.
|
||||
|
||||
The additional fip images must be loaded with:
|
||||
|
||||
::
|
||||
|
||||
--data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
|
||||
--data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
|
||||
|
||||
The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
|
||||
In the same way, the address ns_bl2u_base_address is the value of
|
||||
NS_BL2U_BASE.
|
||||
|
||||
Booting an EL3 payload
|
||||
----------------------
|
||||
|
||||
The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
|
||||
the secondary CPUs holding pen to work properly. Unfortunately, its reset value
|
||||
is undefined on the FVP platform and the FVP platform code doesn't clear it.
|
||||
Therefore, one must modify the way the model is normally invoked in order to
|
||||
clear the mailbox at start-up.
|
||||
|
||||
One way to do that is to create an 8-byte file containing all zero bytes using
|
||||
the following command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
dd if=/dev/zero of=mailbox.dat bs=1 count=8
|
||||
|
||||
and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
|
||||
using the following model parameters:
|
||||
|
||||
::
|
||||
|
||||
--data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
|
||||
--data=mailbox.dat@0x04000000 [Foundation FVP]
|
||||
|
||||
To provide the model with the EL3 payload image, the following methods may be
|
||||
used:
|
||||
|
||||
#. If the EL3 payload is able to execute in place, it may be programmed into
|
||||
flash memory. On Base Cortex and AEM FVPs, the following model parameter
|
||||
loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
|
||||
used for the FIP):
|
||||
|
||||
::
|
||||
|
||||
-C bp.flashloader1.fname="<path-to>/<el3-payload>"
|
||||
|
||||
On Foundation FVP, there is no flash loader component and the EL3 payload
|
||||
may be programmed anywhere in flash using method 3 below.
|
||||
|
||||
#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
|
||||
command may be used to load the EL3 payload ELF image over JTAG:
|
||||
|
||||
::
|
||||
|
||||
load <path-to>/el3-payload.elf
|
||||
|
||||
#. The EL3 payload may be pre-loaded in volatile memory using the following
|
||||
model parameters:
|
||||
|
||||
::
|
||||
|
||||
--data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
|
||||
--data="<path-to>/<el3-payload>"@address [Foundation FVP]
|
||||
|
||||
The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
|
||||
used when building TF-A.
|
||||
|
||||
Booting a preloaded kernel image (Base FVP)
|
||||
-------------------------------------------
|
||||
|
||||
The following example uses a simplified boot flow by directly jumping from the
|
||||
TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
|
||||
useful if both the kernel and the device tree blob (DTB) are already present in
|
||||
memory (like in FVP).
|
||||
|
||||
For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
|
||||
address ``0x82000000``, the firmware can be built like this:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
CROSS_COMPILE=aarch64-none-elf- \
|
||||
make PLAT=fvp DEBUG=1 \
|
||||
RESET_TO_BL31=1 \
|
||||
ARM_LINUX_KERNEL_AS_BL33=1 \
|
||||
PRELOADED_BL33_BASE=0x80080000 \
|
||||
ARM_PRELOADED_DTB_BASE=0x82000000 \
|
||||
all fip
|
||||
|
||||
Now, it is needed to modify the DTB so that the kernel knows the address of the
|
||||
ramdisk. The following script generates a patched DTB from the provided one,
|
||||
assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
|
||||
script assumes that the user is using a ramdisk image prepared for U-Boot, like
|
||||
the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
|
||||
offset in ``INITRD_START`` has to be removed.
|
||||
|
||||
.. code:: bash
|
||||
|
||||
#!/bin/bash
|
||||
|
||||
# Path to the input DTB
|
||||
KERNEL_DTB=<path-to>/<fdt>
|
||||
# Path to the output DTB
|
||||
PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
|
||||
# Base address of the ramdisk
|
||||
INITRD_BASE=0x84000000
|
||||
# Path to the ramdisk
|
||||
INITRD=<path-to>/<ramdisk.img>
|
||||
|
||||
# Skip uboot header (64 bytes)
|
||||
INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
|
||||
INITRD_SIZE=$(stat -Lc %s ${INITRD})
|
||||
INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
|
||||
|
||||
CHOSEN_NODE=$(echo \
|
||||
"/ { \
|
||||
chosen { \
|
||||
linux,initrd-start = <${INITRD_START}>; \
|
||||
linux,initrd-end = <${INITRD_END}>; \
|
||||
}; \
|
||||
};")
|
||||
|
||||
echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
|
||||
dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
|
||||
|
||||
And the FVP binary can be run with the following command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/FVP_Base_AEMv8A-AEMv8A \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C cluster0.NUM_CORES=4 \
|
||||
-C cluster1.NUM_CORES=4 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C cluster0.cpu0.RVBAR=0x04001000 \
|
||||
-C cluster0.cpu1.RVBAR=0x04001000 \
|
||||
-C cluster0.cpu2.RVBAR=0x04001000 \
|
||||
-C cluster0.cpu3.RVBAR=0x04001000 \
|
||||
-C cluster1.cpu0.RVBAR=0x04001000 \
|
||||
-C cluster1.cpu1.RVBAR=0x04001000 \
|
||||
-C cluster1.cpu2.RVBAR=0x04001000 \
|
||||
-C cluster1.cpu3.RVBAR=0x04001000 \
|
||||
--data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \
|
||||
--data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
|
||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
|
||||
|
||||
Obtaining the Flattened Device Trees
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Depending on the FVP configuration and Linux configuration used, different
|
||||
FDT files are required. FDT source files for the Foundation and Base FVPs can
|
||||
be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
|
||||
a subset of the Base FVP components. For example, the Foundation FVP lacks
|
||||
CLCD and MMC support, and has only one CPU cluster.
|
||||
|
||||
.. note::
|
||||
It is not recommended to use the FDTs built along the kernel because not
|
||||
all FDTs are available from there.
|
||||
|
||||
The dynamic configuration capability is enabled in the firmware for FVPs.
|
||||
This means that the firmware can authenticate and load the FDT if present in
|
||||
FIP. A default FDT is packaged into FIP during the build based on
|
||||
the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
|
||||
or ``FVP_HW_CONFIG_DTS`` build options (refer to
|
||||
:ref:`build_options_arm_fvp_platform` for details on the options).
|
||||
|
||||
- ``fvp-base-gicv2-psci.dts``
|
||||
|
||||
For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
|
||||
without shifted affinities and with Base memory map configuration.
|
||||
|
||||
- ``fvp-base-gicv3-psci.dts``
|
||||
|
||||
For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
|
||||
without shifted affinities and with Base memory map configuration and
|
||||
Linux GICv3 support.
|
||||
|
||||
- ``fvp-base-gicv3-psci-1t.dts``
|
||||
|
||||
For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
|
||||
single threaded CPUs, Base memory map configuration and Linux GICv3 support.
|
||||
|
||||
- ``fvp-base-gicv3-psci-dynamiq.dts``
|
||||
|
||||
For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
|
||||
single cluster, single threaded CPUs, Base memory map configuration and Linux
|
||||
GICv3 support.
|
||||
|
||||
- ``fvp-foundation-gicv2-psci.dts``
|
||||
|
||||
For use with Foundation FVP with Base memory map configuration.
|
||||
|
||||
- ``fvp-foundation-gicv3-psci.dts``
|
||||
|
||||
(Default) For use with Foundation FVP with Base memory map configuration
|
||||
and Linux GICv3 support.
|
||||
|
||||
|
||||
Running on the Foundation FVP with reset to BL1 entrypoint
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following ``Foundation_Platform`` parameters should be used to boot Linux with
|
||||
4 CPUs using the AArch64 build of TF-A.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/Foundation_Platform \
|
||||
--cores=4 \
|
||||
--arm-v8.0 \
|
||||
--secure-memory \
|
||||
--visualization \
|
||||
--gicv3 \
|
||||
--data="<path-to>/<bl1-binary>"@0x0 \
|
||||
--data="<path-to>/<FIP-binary>"@0x08000000 \
|
||||
--data="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data="<path-to>/<ramdisk-binary>"@0x84000000
|
||||
|
||||
Notes:
|
||||
|
||||
- BL1 is loaded at the start of the Trusted ROM.
|
||||
- The Firmware Image Package is loaded at the start of NOR FLASH0.
|
||||
- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
|
||||
is specified via the ``load-address`` property in the ``hw-config`` node of
|
||||
`FW_CONFIG for FVP`_.
|
||||
- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
|
||||
and enable the GICv3 device in the model. Note that without this option,
|
||||
the Foundation FVP defaults to legacy (Versatile Express) memory map which
|
||||
is not supported by TF-A.
|
||||
- In order for TF-A to run correctly on the Foundation FVP, the architecture
|
||||
versions must match. The Foundation FVP defaults to the highest v8.x
|
||||
version it supports but the default build for TF-A is for v8.0. To avoid
|
||||
issues either start the Foundation FVP to use v8.0 architecture using the
|
||||
``--arm-v8.0`` option, or build TF-A with an appropriate value for
|
||||
``ARM_ARCH_MINOR``.
|
||||
|
||||
Running on the AEMv8 Base FVP with reset to BL1 entrypoint
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
|
||||
with 8 CPUs using the AArch64 build of TF-A.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/FVP_Base_RevC-2xAEMv8A \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C bp.tzc_400.diagnostics=1 \
|
||||
-C cluster0.NUM_CORES=4 \
|
||||
-C cluster1.NUM_CORES=4 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
|
||||
-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
|
||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
.. note::
|
||||
The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
|
||||
a specific DTS for all the CPUs to be loaded.
|
||||
|
||||
Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
|
||||
with 8 CPUs using the AArch32 build of TF-A.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/FVP_Base_AEMv8A-AEMv8A \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C bp.tzc_400.diagnostics=1 \
|
||||
-C cluster0.NUM_CORES=4 \
|
||||
-C cluster1.NUM_CORES=4 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C cluster0.cpu0.CONFIG64=0 \
|
||||
-C cluster0.cpu1.CONFIG64=0 \
|
||||
-C cluster0.cpu2.CONFIG64=0 \
|
||||
-C cluster0.cpu3.CONFIG64=0 \
|
||||
-C cluster1.cpu0.CONFIG64=0 \
|
||||
-C cluster1.cpu1.CONFIG64=0 \
|
||||
-C cluster1.cpu2.CONFIG64=0 \
|
||||
-C cluster1.cpu3.CONFIG64=0 \
|
||||
-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
|
||||
-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
|
||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
|
||||
boot Linux with 8 CPUs using the AArch64 build of TF-A.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C bp.tzc_400.diagnostics=1 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
|
||||
-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
|
||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
|
||||
boot Linux with 4 CPUs using the AArch32 build of TF-A.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/FVP_Base_Cortex-A32x4 \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C bp.tzc_400.diagnostics=1 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
|
||||
-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
|
||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
|
||||
Running on the AEMv8 Base FVP with reset to BL31 entrypoint
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
|
||||
with 8 CPUs using the AArch64 build of TF-A.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/FVP_Base_RevC-2xAEMv8A \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C bp.tzc_400.diagnostics=1 \
|
||||
-C cluster0.NUM_CORES=4 \
|
||||
-C cluster1.NUM_CORES=4 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C cluster0.cpu0.RVBAR=0x04010000 \
|
||||
-C cluster0.cpu1.RVBAR=0x04010000 \
|
||||
-C cluster0.cpu2.RVBAR=0x04010000 \
|
||||
-C cluster0.cpu3.RVBAR=0x04010000 \
|
||||
-C cluster1.cpu0.RVBAR=0x04010000 \
|
||||
-C cluster1.cpu1.RVBAR=0x04010000 \
|
||||
-C cluster1.cpu2.RVBAR=0x04010000 \
|
||||
-C cluster1.cpu3.RVBAR=0x04010000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
|
||||
--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
|
||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
Notes:
|
||||
|
||||
- Position Independent Executable (PIE) support is enabled in this
|
||||
config allowing BL31 to be loaded at any valid address for execution.
|
||||
|
||||
- Since a FIP is not loaded when using BL31 as reset entrypoint, the
|
||||
``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
|
||||
parameter is needed to load the individual bootloader images in memory.
|
||||
BL32 image is only needed if BL31 has been built to expect a Secure-EL1
|
||||
Payload. For the same reason, the FDT needs to be compiled from the DT source
|
||||
and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
|
||||
parameter.
|
||||
|
||||
- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
|
||||
specific DTS for all the CPUs to be loaded.
|
||||
|
||||
- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
|
||||
X and Y are the cluster and CPU numbers respectively, is used to set the
|
||||
reset vector for each core.
|
||||
|
||||
- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
|
||||
changing the value of
|
||||
``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
|
||||
``BL32_BASE``.
|
||||
|
||||
|
||||
Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
|
||||
with 8 CPUs using the AArch32 build of TF-A.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/FVP_Base_AEMv8A-AEMv8A \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C bp.tzc_400.diagnostics=1 \
|
||||
-C cluster0.NUM_CORES=4 \
|
||||
-C cluster1.NUM_CORES=4 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C cluster0.cpu0.CONFIG64=0 \
|
||||
-C cluster0.cpu1.CONFIG64=0 \
|
||||
-C cluster0.cpu2.CONFIG64=0 \
|
||||
-C cluster0.cpu3.CONFIG64=0 \
|
||||
-C cluster1.cpu0.CONFIG64=0 \
|
||||
-C cluster1.cpu1.CONFIG64=0 \
|
||||
-C cluster1.cpu2.CONFIG64=0 \
|
||||
-C cluster1.cpu3.CONFIG64=0 \
|
||||
-C cluster0.cpu0.RVBAR=0x04002000 \
|
||||
-C cluster0.cpu1.RVBAR=0x04002000 \
|
||||
-C cluster0.cpu2.RVBAR=0x04002000 \
|
||||
-C cluster0.cpu3.RVBAR=0x04002000 \
|
||||
-C cluster1.cpu0.RVBAR=0x04002000 \
|
||||
-C cluster1.cpu1.RVBAR=0x04002000 \
|
||||
-C cluster1.cpu2.RVBAR=0x04002000 \
|
||||
-C cluster1.cpu3.RVBAR=0x04002000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
|
||||
--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
|
||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
.. note::
|
||||
Position Independent Executable (PIE) support is enabled in this
|
||||
config allowing SP_MIN to be loaded at any valid address for execution.
|
||||
|
||||
Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
|
||||
boot Linux with 8 CPUs using the AArch64 build of TF-A.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C bp.tzc_400.diagnostics=1 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C cluster0.cpu0.RVBARADDR=0x04010000 \
|
||||
-C cluster0.cpu1.RVBARADDR=0x04010000 \
|
||||
-C cluster0.cpu2.RVBARADDR=0x04010000 \
|
||||
-C cluster0.cpu3.RVBARADDR=0x04010000 \
|
||||
-C cluster1.cpu0.RVBARADDR=0x04010000 \
|
||||
-C cluster1.cpu1.RVBARADDR=0x04010000 \
|
||||
-C cluster1.cpu2.RVBARADDR=0x04010000 \
|
||||
-C cluster1.cpu3.RVBARADDR=0x04010000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
|
||||
--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
|
||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
|
||||
boot Linux with 4 CPUs using the AArch32 build of TF-A.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
<path-to>/FVP_Base_Cortex-A32x4 \
|
||||
-C pctl.startup=0.0.0.0 \
|
||||
-C bp.secure_memory=1 \
|
||||
-C bp.tzc_400.diagnostics=1 \
|
||||
-C cache_state_modelled=1 \
|
||||
-C cluster0.cpu0.RVBARADDR=0x04002000 \
|
||||
-C cluster0.cpu1.RVBARADDR=0x04002000 \
|
||||
-C cluster0.cpu2.RVBARADDR=0x04002000 \
|
||||
-C cluster0.cpu3.RVBARADDR=0x04002000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
|
||||
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
|
||||
--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
|
||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
|
||||
|
||||
.. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts
|
||||
.. _Arm's website: `FVP models`_
|
||||
.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
|
||||
.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
|
||||
.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
|
||||
46
arm-trusted-firmware/docs/plat/arm/fvp_r/index.rst
Normal file
46
arm-trusted-firmware/docs/plat/arm/fvp_r/index.rst
Normal file
@@ -0,0 +1,46 @@
|
||||
ARM V8-R64 Fixed Virtual Platform (FVP)
|
||||
=======================================
|
||||
|
||||
Some of the features of Armv8-R AArch64 FVP platform referenced in Trusted
|
||||
Boot R-class include:
|
||||
|
||||
- Secure World Support Only
|
||||
- EL2 as Maximum EL support (No EL3)
|
||||
- MPU Support only at EL2
|
||||
- MPU or MMU Support at EL0/EL1
|
||||
- AArch64 Support Only
|
||||
- Trusted Board Boot
|
||||
|
||||
Further information on v8-R64 FVP is available at `info <https://developer.arm.com/documentation/ddi0600/latest/>`_
|
||||
|
||||
Boot Sequence
|
||||
-------------
|
||||
|
||||
BL1 –> BL33
|
||||
|
||||
The execution begins from BL1 which loads the BL33 image, a boot-wrapped (bootloader + Operating System)
|
||||
Operating System, from FIP to DRAM.
|
||||
|
||||
Build Procedure
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
- Obtain arm `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
|
||||
Set the CROSS_COMPILE environment variable to point to the toolchain folder.
|
||||
|
||||
- Build TF-A:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=fvp_r BL33=<path_to_os.bin> all fip
|
||||
|
||||
Enable TBBR by adding the following options to the make command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
MBEDTLS_DIR=<path_to_mbedtls_directory> \
|
||||
TRUSTED_BOARD_BOOT=1 \
|
||||
GENERATE_COT=1 \
|
||||
ARM_ROTPK_LOCATION=devel_rsa \
|
||||
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
|
||||
|
||||
*Copyright (c) 2021, Arm Limited. All rights reserved.*
|
||||
24
arm-trusted-firmware/docs/plat/arm/index.rst
Normal file
24
arm-trusted-firmware/docs/plat/arm/index.rst
Normal file
@@ -0,0 +1,24 @@
|
||||
Arm Development Platforms
|
||||
=========================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Contents
|
||||
|
||||
juno/index
|
||||
fvp/index
|
||||
fvp_r/index
|
||||
fvp-ve/index
|
||||
tc/index
|
||||
arm_fpga/index
|
||||
arm-build-options
|
||||
morello/index
|
||||
corstone1000/index
|
||||
|
||||
This chapter holds documentation related to Arm's development platforms,
|
||||
including both software models (FVPs) and hardware development boards
|
||||
such as Juno.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
|
||||
253
arm-trusted-firmware/docs/plat/arm/juno/index.rst
Normal file
253
arm-trusted-firmware/docs/plat/arm/juno/index.rst
Normal file
@@ -0,0 +1,253 @@
|
||||
Arm Juno Development Platform
|
||||
=============================
|
||||
|
||||
Platform-specific build options
|
||||
-------------------------------
|
||||
|
||||
- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
|
||||
Media Protection (TZ-MP1). Default value of this flag is 0.
|
||||
|
||||
Running software on Juno
|
||||
------------------------
|
||||
|
||||
This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
|
||||
|
||||
To run TF-A on Juno, you need to first prepare an SD card with Juno software
|
||||
stack that includes TF-A. This version of TF-A is tested with pre-built
|
||||
`Linaro release software stack`_ version 20.01. You can alternatively
|
||||
build the software stack yourself by following the
|
||||
`Juno platform software user guide`_. Once you prepare the software stack
|
||||
on an SD card, you can replace the ``bl1.bin`` and ``fip.bin``
|
||||
binaries in the ``SOFTWARE/`` directory with custom built TF-A binaries.
|
||||
|
||||
Preparing TF-A images
|
||||
---------------------
|
||||
|
||||
This section provides Juno and FVP specific instructions to build Trusted
|
||||
Firmware, obtain the additional required firmware, and pack it all together in
|
||||
a single FIP binary. It assumes that a Linaro release software stack has been
|
||||
installed.
|
||||
|
||||
.. note::
|
||||
Pre-built binaries for AArch32 are available from Linaro Release 16.12
|
||||
onwards. Before that release, pre-built binaries are only available for
|
||||
AArch64.
|
||||
|
||||
.. warning::
|
||||
Follow the full instructions for one platform before switching to a
|
||||
different one. Mixing instructions for different platforms may result in
|
||||
corrupted binaries.
|
||||
|
||||
.. warning::
|
||||
The uboot image downloaded by the Linaro workspace script does not always
|
||||
match the uboot image packaged as BL33 in the corresponding fip file. It is
|
||||
recommended to use the version that is packaged in the fip file using the
|
||||
instructions below.
|
||||
|
||||
.. note::
|
||||
For the FVP, the kernel FDT is packaged in FIP during build and loaded
|
||||
by the firmware at runtime.
|
||||
|
||||
#. Clean the working directory
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make realclean
|
||||
|
||||
#. Obtain SCP binaries (Juno)
|
||||
|
||||
This version of TF-A is tested with SCP version 2.8.0 on Juno. You can
|
||||
download pre-built SCP binaries (``scp_bl1.bin`` and ``scp_bl2.bin``)
|
||||
from `TF-A downloads page`_. Alternatively, you can `build
|
||||
the binaries from source`_.
|
||||
|
||||
#. Obtain BL33 (all platforms)
|
||||
|
||||
Use the fiptool to extract the BL33 image from the FIP
|
||||
package included in the Linaro release:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
# Build the fiptool
|
||||
make [DEBUG=1] [V=1] fiptool
|
||||
|
||||
# Unpack firmware images from Linaro FIP
|
||||
./tools/fiptool/fiptool unpack <path-to-linaro-release>/[SOFTWARE]/fip.bin
|
||||
|
||||
The unpack operation will result in a set of binary images extracted to the
|
||||
current working directory. BL33 corresponds to ``nt-fw.bin``.
|
||||
|
||||
.. note::
|
||||
The fiptool will complain if the images to be unpacked already
|
||||
exist in the current directory. If that is the case, either delete those
|
||||
files or use the ``--force`` option to overwrite.
|
||||
|
||||
.. note::
|
||||
For AArch32, the instructions below assume that nt-fw.bin is a
|
||||
normal world boot loader that supports AArch32.
|
||||
|
||||
#. Build TF-A images and create a new FIP for FVP
|
||||
|
||||
.. code:: shell
|
||||
|
||||
# AArch64
|
||||
make PLAT=fvp BL33=nt-fw.bin all fip
|
||||
|
||||
# AArch32
|
||||
make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
|
||||
|
||||
#. Build TF-A images and create a new FIP for Juno
|
||||
|
||||
For AArch64:
|
||||
|
||||
Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
|
||||
as a build parameter.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp_bl2.bin all fip
|
||||
|
||||
For AArch32:
|
||||
|
||||
Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
|
||||
therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
|
||||
separately for AArch32.
|
||||
|
||||
- Before building BL32, the environment variable ``CROSS_COMPILE`` must point
|
||||
to the AArch32 Linaro cross compiler.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
|
||||
|
||||
- Build BL32 in AArch32.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
|
||||
RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
|
||||
|
||||
- Save ``bl32.bin`` to a temporary location and clean the build products.
|
||||
|
||||
::
|
||||
|
||||
cp <path-to-build>/bl32.bin <path-to-temporary>
|
||||
make realclean
|
||||
|
||||
- Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
|
||||
must point to the AArch64 Linaro cross compiler.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
|
||||
|
||||
- The following parameters should be used to build BL1 and BL2 in AArch64
|
||||
and point to the BL32 file.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
|
||||
BL33=nt-fw.bin SCP_BL2=scp_bl2.bin \
|
||||
BL32=<path-to-temporary>/bl32.bin all fip
|
||||
|
||||
The resulting BL1 and FIP images may be found in:
|
||||
|
||||
::
|
||||
|
||||
# Juno
|
||||
./build/juno/release/bl1.bin
|
||||
./build/juno/release/fip.bin
|
||||
|
||||
# FVP
|
||||
./build/fvp/release/bl1.bin
|
||||
./build/fvp/release/fip.bin
|
||||
|
||||
After building TF-A, the files ``bl1.bin``, ``fip.bin`` and ``scp_bl1.bin``
|
||||
need to be copied to the ``SOFTWARE/`` directory on the Juno SD card.
|
||||
|
||||
Booting Firmware Update images
|
||||
------------------------------
|
||||
|
||||
The new images must be programmed in flash memory by adding
|
||||
an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
|
||||
on the Juno SD card (where ``x`` depends on the revision of the Juno board).
|
||||
Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
|
||||
programming" for more information. User should ensure these do not
|
||||
overlap with any other entries in the file.
|
||||
|
||||
::
|
||||
|
||||
NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
|
||||
NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
|
||||
NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
|
||||
NOR10LOAD: 00000000 ;Image Load Address
|
||||
NOR10ENTRY: 00000000 ;Image Entry Point
|
||||
|
||||
NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
|
||||
NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
|
||||
NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
|
||||
NOR11LOAD: 00000000 ;Image Load Address
|
||||
|
||||
The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
|
||||
In the same way, the address ns_bl2u_base_address is the value of
|
||||
NS_BL2U_BASE - 0x8000000.
|
||||
|
||||
.. _plat_juno_booting_el3_payload:
|
||||
|
||||
Booting an EL3 payload
|
||||
----------------------
|
||||
|
||||
If the EL3 payload is able to execute in place, it may be programmed in flash
|
||||
memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
|
||||
on the Juno SD card (where ``x`` depends on the revision of the Juno board).
|
||||
Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
|
||||
programming" for more information.
|
||||
|
||||
Alternatively, the same DS-5 command mentioned in the FVP section above can
|
||||
be used to load the EL3 payload's ELF file over JTAG on Juno.
|
||||
|
||||
For more information on EL3 payloads in general, see
|
||||
:ref:`alt_boot_flows_el3_payload`.
|
||||
|
||||
Booting a preloaded kernel image
|
||||
--------------------------------
|
||||
|
||||
The Trusted Firmware must be compiled in a similar way as for FVP explained
|
||||
above. The process to load binaries to memory is the one explained in
|
||||
`plat_juno_booting_el3_payload`_.
|
||||
|
||||
Testing System Suspend
|
||||
----------------------
|
||||
|
||||
The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
|
||||
to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
|
||||
on Juno, at the linux shell prompt, issue the following command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
echo +10 > /sys/class/rtc/rtc0/wakealarm
|
||||
echo -n mem > /sys/power/state
|
||||
|
||||
The Juno board should suspend to RAM and then wakeup after 10 seconds due to
|
||||
wakeup interrupt from RTC.
|
||||
|
||||
Additional Resources
|
||||
--------------------
|
||||
|
||||
Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
|
||||
software information. Please also refer to the `Juno Getting Started Guide`_ to
|
||||
get more detailed information about the Juno Arm development platform and how to
|
||||
configure it.
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
|
||||
|
||||
.. _Linaro release software stack: http://releases.linaro.org/members/arm/platforms/
|
||||
.. _Juno platform software user guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/juno/user-guide.rst
|
||||
.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.8.0/juno/
|
||||
.. _build the binaries from source: https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md#scp-firmware-user-guide
|
||||
.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
|
||||
.. _Juno Getting Started Guide: https://developer.arm.com/documentation/den0928/f/?lang=en
|
||||
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
|
||||
.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
|
||||
33
arm-trusted-firmware/docs/plat/arm/morello/index.rst
Normal file
33
arm-trusted-firmware/docs/plat/arm/morello/index.rst
Normal file
@@ -0,0 +1,33 @@
|
||||
Morello Platform
|
||||
================
|
||||
|
||||
Morello is an ARMv8-A platform that implements the capability architecture extension.
|
||||
The platform port present at `site <https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git>`_
|
||||
provides ARMv8-A architecture enablement.
|
||||
|
||||
Capability architecture specific changes will be added `here <https://git.morello-project.org/morello>`_
|
||||
|
||||
Further information on Morello Platform is available at `info <https://developer.arm.com/architectures/cpu-architecture/a-profile/morello>`_
|
||||
|
||||
Boot Sequence
|
||||
-------------
|
||||
|
||||
The execution begins from SCP_BL1 which loads the SCP_BL2 and starts its
|
||||
execution. SCP_BL2 powers up the AP which starts execution at AP_BL31. The AP
|
||||
then continues executing and hands off execution to Non-secure world (UEFI).
|
||||
|
||||
Build Procedure (TF-A only)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
- Obtain arm `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
|
||||
Set the CROSS_COMPILE environment variable to point to the toolchain folder.
|
||||
|
||||
- Build TF-A:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
|
||||
|
||||
make PLAT=morello all
|
||||
|
||||
*Copyright (c) 2020, Arm Limited. All rights reserved.*
|
||||
63
arm-trusted-firmware/docs/plat/arm/tc/index.rst
Normal file
63
arm-trusted-firmware/docs/plat/arm/tc/index.rst
Normal file
@@ -0,0 +1,63 @@
|
||||
TC Total Compute Platform
|
||||
==========================
|
||||
|
||||
Some of the features of TC platform referenced in TF-A include:
|
||||
|
||||
- A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_
|
||||
to abstract power and system management tasks away from application
|
||||
processors. The RAM firmware for SCP is included in the TF-A FIP and is
|
||||
loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access
|
||||
to AP SRAM).
|
||||
- GICv4
|
||||
- Trusted Board Boot
|
||||
- SCMI
|
||||
- MHUv2
|
||||
|
||||
Currently, the main difference between TC0 (TARGET_PLATFORM=0), TC1
|
||||
(TARGET_PLATFORM=1), TC2 (TARGET_PLATFORM=2) platforms w.r.t to TF-A
|
||||
is the CPUs supported as below:
|
||||
|
||||
- TC0 has support for Cortex A510, Cortex A710 and Cortex X2.
|
||||
- TC1 has support for Cortex A510, Cortex Makalu and Cortex X3.
|
||||
- TC2 has support for Hayes and Hunter Arm CPUs.
|
||||
|
||||
|
||||
Boot Sequence
|
||||
-------------
|
||||
|
||||
The execution begins from SCP_BL1. SCP_BL1 powers up the AP which starts
|
||||
executing AP_BL1 and then executes AP_BL2 which loads the SCP_BL2 from
|
||||
FIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2
|
||||
is communicated to SCP using SDS. SCP copies SCP_BL2 from SRAM to its own
|
||||
RAM and starts executing it. The AP then continues executing the rest of TF-A
|
||||
stages including BL31 runtime stage and hands off executing to
|
||||
Non-secure world (u-boot).
|
||||
|
||||
Build Procedure (TF-A only)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
- Obtain `Arm toolchain`_ and set the CROSS_COMPILE environment variable to
|
||||
point to the toolchain folder.
|
||||
|
||||
- Build TF-A:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=tc BL33=<path_to_uboot.bin> \
|
||||
SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={0,1,2} all fip
|
||||
|
||||
Enable TBBR by adding the following options to the make command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
MBEDTLS_DIR=<path_to_mbedtls_directory> \
|
||||
TRUSTED_BOARD_BOOT=1 \
|
||||
GENERATE_COT=1 \
|
||||
ARM_ROTPK_LOCATION=devel_rsa \
|
||||
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2020-2022, Arm Limited. All rights reserved.*
|
||||
|
||||
.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
|
||||
43
arm-trusted-firmware/docs/plat/brcm-stingray.rst
Normal file
43
arm-trusted-firmware/docs/plat/brcm-stingray.rst
Normal file
@@ -0,0 +1,43 @@
|
||||
Broadcom Stingray
|
||||
=================
|
||||
|
||||
Description
|
||||
-----------
|
||||
Broadcom's Stingray(BCM958742t) is a multi-core processor with 8 Cortex-A72 cores.
|
||||
Trusted Firmware-A (TF-A) is used to implement secure world firmware, supporting
|
||||
BL2 and BL31 for Broadcom Stingray SoCs.
|
||||
|
||||
On Poweron, Boot ROM will load bl2 image and Bl2 will initialize the hardware,
|
||||
then loads bl31 and bl33 into DDR and boots to bl33.
|
||||
|
||||
Boot Sequence
|
||||
-------------
|
||||
|
||||
Bootrom --> TF-A BL2 --> TF-A BL31 --> BL33(u-boot)
|
||||
|
||||
Code Locations
|
||||
~~~~~~~~~~~~~~
|
||||
- Trusted Firmware-A:
|
||||
`link <https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/>`__
|
||||
|
||||
How to build
|
||||
------------
|
||||
|
||||
Build Procedure
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
- Prepare AARCH64 toolchain.
|
||||
|
||||
- Build u-boot first, and get the binary image: u-boot.bin,
|
||||
|
||||
- Build TF-A
|
||||
|
||||
Build fip:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=stingray BOARD_CFG=bcm958742t all fip BL33=u-boot.bin
|
||||
|
||||
Deploy TF-A Images
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
The u-boot will be upstreamed soon, this doc will be updated once they are ready, and the link will be posted.
|
||||
155
arm-trusted-firmware/docs/plat/hikey.rst
Normal file
155
arm-trusted-firmware/docs/plat/hikey.rst
Normal file
@@ -0,0 +1,155 @@
|
||||
HiKey
|
||||
=====
|
||||
|
||||
HiKey is one of 96boards. Hisilicon Kirin6220 processor is installed on HiKey.
|
||||
|
||||
More information are listed in `link`_.
|
||||
|
||||
How to build
|
||||
------------
|
||||
|
||||
Code Locations
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
- Trusted Firmware-A:
|
||||
`link <https://github.com/ARM-software/arm-trusted-firmware>`__
|
||||
|
||||
- OP-TEE
|
||||
`link <https://github.com/OP-TEE/optee_os>`__
|
||||
|
||||
- edk2:
|
||||
`link <https://github.com/96boards-hikey/edk2/tree/testing/hikey960_v2.5>`__
|
||||
|
||||
- OpenPlatformPkg:
|
||||
`link <https://github.com/96boards-hikey/OpenPlatformPkg/tree/testing/hikey960_v1.3.4>`__
|
||||
|
||||
- l-loader:
|
||||
`link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__
|
||||
|
||||
- atf-fastboot:
|
||||
`link <https://github.com/96boards-hikey/atf-fastboot/tree/master>`__
|
||||
|
||||
Build Procedure
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
- Fetch all the above repositories into local host.
|
||||
Make all the repositories in the same ${BUILD\_PATH}.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
git clone https://github.com/ARM-software/arm-trusted-firmware -b integration
|
||||
git clone https://github.com/OP-TEE/optee_os
|
||||
git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
|
||||
git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
|
||||
git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
|
||||
git clone https://github.com/96boards-hikey/atf-fastboot
|
||||
|
||||
- Create the symbol link to OpenPlatformPkg in edk2.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$cd ${BUILD_PATH}/edk2
|
||||
$ln -sf ../OpenPlatformPkg
|
||||
|
||||
- Prepare AARCH64 && AARCH32 toolchain. Prepare python.
|
||||
|
||||
- If your hikey hardware is built by CircuitCo, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dsc* first. *(optional)*
|
||||
console on hikey.**
|
||||
|
||||
.. code:: shell
|
||||
|
||||
DEFINE SERIAL_BASE=0xF8015000
|
||||
|
||||
If your hikey hardware is built by LeMaker, nothing to do.
|
||||
|
||||
- Build it as debug mode. Create your own build script file or you could refer to **build\_uefi.sh** in l-loader git repository.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
cd {BUILD_PATH}/arm-trusted-firmware
|
||||
sh ../l-loader/build_uefi.sh hikey
|
||||
|
||||
- Generate l-loader.bin and partition table for aosp. The eMMC capacity is either 8GB or 4GB. Just change "aosp-8g" to "linux-8g" for debian.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
cd ${BUILD_PATH}/l-loader
|
||||
ln -sf ${EDK2_OUTPUT_DIR}/FV/bl1.bin
|
||||
ln -sf ${EDK2_OUTPUT_DIR}/FV/bl2.bin
|
||||
ln -sf ${BUILD_PATH}/atf-fastboot/build/hikey/${FASTBOOT_BUILD_OPTION}/bl1.bin fastboot.bin
|
||||
make hikey PTABLE_LST=aosp-8g
|
||||
|
||||
Setup Console
|
||||
-------------
|
||||
|
||||
- Install ser2net. Use telnet as the console since UEFI fails to display Boot Manager GUI in minicom. **If you don't need Boot Manager GUI, just ignore this section.**
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo apt-get install ser2net
|
||||
|
||||
- Configure ser2net.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo vi /etc/ser2net.conf
|
||||
|
||||
Append one line for serial-over-USB in below.
|
||||
*#ser2net.conf*
|
||||
|
||||
.. code:: shell
|
||||
|
||||
2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
|
||||
|
||||
- Start ser2net
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo killall ser2net
|
||||
$sudo ser2net -u
|
||||
|
||||
- Open the console.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$telnet localhost 2004
|
||||
|
||||
And you could open the console remotely, too.
|
||||
|
||||
Flash images in recovery mode
|
||||
-----------------------------
|
||||
|
||||
- Make sure Pin3-Pin4 on J15 are connected for recovery mode. Then power on HiKey.
|
||||
|
||||
- Remove the modemmanager package. This package may cause the idt tool failure.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo apt-get purge modemmanager
|
||||
|
||||
- Run the command to download recovery.bin into HiKey.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo python hisi-idt.py -d /dev/ttyUSB1 --img1 recovery.bin
|
||||
|
||||
- Update images. All aosp or debian images could be fetched from `link <http://releases.linaro.org/96boards/>`__.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo fastboot flash ptable prm_ptable.img
|
||||
$sudo fastboot flash loader l-loader.bin
|
||||
$sudo fastboot flash fastboot fip.bin
|
||||
$sudo fastboot flash boot boot.img
|
||||
$sudo fastboot flash cache cache.img
|
||||
$sudo fastboot flash system system.img
|
||||
$sudo fastboot flash userdata userdata.img
|
||||
|
||||
Boot UEFI in normal mode
|
||||
------------------------
|
||||
|
||||
- Make sure Pin3-Pin4 on J15 are open for normal boot mode. Then power on HiKey.
|
||||
|
||||
- Reference `link <https://github.com/96boards-hikey/tools-images-hikey960/blob/master/build-from-source/README-ATF-UEFI-build-from-source.md>`__
|
||||
|
||||
.. _link: https://www.96boards.org/documentation/consumer/hikey/
|
||||
180
arm-trusted-firmware/docs/plat/hikey960.rst
Normal file
180
arm-trusted-firmware/docs/plat/hikey960.rst
Normal file
@@ -0,0 +1,180 @@
|
||||
HiKey960
|
||||
========
|
||||
|
||||
HiKey960 is one of 96boards. Hisilicon Hi3660 processor is installed on HiKey960.
|
||||
|
||||
More information are listed in `link`_.
|
||||
|
||||
How to build
|
||||
------------
|
||||
|
||||
Code Locations
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
- Trusted Firmware-A:
|
||||
`link <https://github.com/ARM-software/arm-trusted-firmware>`__
|
||||
|
||||
- OP-TEE:
|
||||
`link <https://github.com/OP-TEE/optee_os>`__
|
||||
|
||||
- edk2:
|
||||
`link <https://github.com/96boards-hikey/edk2/tree/testing/hikey960_v2.5>`__
|
||||
|
||||
- OpenPlatformPkg:
|
||||
`link <https://github.com/96boards-hikey/OpenPlatformPkg/tree/testing/hikey960_v1.3.4>`__
|
||||
|
||||
- l-loader:
|
||||
`link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__
|
||||
|
||||
Build Procedure
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
- Fetch all the above 5 repositories into local host.
|
||||
Make all the repositories in the same ${BUILD\_PATH}.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
git clone https://github.com/ARM-software/arm-trusted-firmware -b integration
|
||||
git clone https://github.com/OP-TEE/optee_os
|
||||
git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
|
||||
git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
|
||||
git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
|
||||
|
||||
- Create the symbol link to OpenPlatformPkg in edk2.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$cd ${BUILD_PATH}/edk2
|
||||
$ln -sf ../OpenPlatformPkg
|
||||
|
||||
- Prepare AARCH64 toolchain.
|
||||
|
||||
- If your hikey960 hardware is v1, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.dsc* first. *(optional)*
|
||||
|
||||
.. code:: shell
|
||||
|
||||
DEFINE SERIAL_BASE=0xFDF05000
|
||||
|
||||
If your hikey960 hardware is v2 or newer, nothing to do.
|
||||
|
||||
- Build it as debug mode. Create script file for build.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
cd {BUILD_PATH}/arm-trusted-firmware
|
||||
sh ../l-loader/build_uefi.sh hikey960
|
||||
|
||||
- Generate l-loader.bin and partition table.
|
||||
*Make sure that you're using the sgdisk in the l-loader directory.*
|
||||
|
||||
.. code:: shell
|
||||
|
||||
cd ${BUILD_PATH}/l-loader
|
||||
ln -sf ${EDK2_OUTPUT_DIR}/FV/bl1.bin
|
||||
ln -sf ${EDK2_OUTPUT_DIR}/FV/bl2.bin
|
||||
ln -sf ${EDK2_OUTPUT_DIR}/FV/fip.bin
|
||||
ln -sf ${EDK2_OUTPUT_DIR}/FV/BL33_AP_UEFI.fd
|
||||
make hikey960
|
||||
|
||||
Setup Console
|
||||
-------------
|
||||
|
||||
- Install ser2net. Use telnet as the console since UEFI will output window
|
||||
that fails to display in minicom.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo apt-get install ser2net
|
||||
|
||||
- Configure ser2net.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo vi /etc/ser2net.conf
|
||||
|
||||
Append one line for serial-over-USB in *#ser2net.conf*
|
||||
|
||||
::
|
||||
|
||||
2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
|
||||
|
||||
- Start ser2net
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo killall ser2net
|
||||
$sudo ser2net -u
|
||||
|
||||
- Open the console.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$telnet localhost 2004
|
||||
|
||||
And you could open the console remotely, too.
|
||||
|
||||
Boot UEFI in recovery mode
|
||||
--------------------------
|
||||
|
||||
- Fetch that are used in recovery mode. The code location is in below.
|
||||
`link <https://github.com/96boards-hikey/tools-images-hikey960>`__
|
||||
|
||||
- Prepare recovery binary.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$cd tools-images-hikey960
|
||||
$ln -sf ${BUILD_PATH}/l-loader/l-loader.bin
|
||||
$ln -sf ${BUILD_PATH}/l-loader/fip.bin
|
||||
$ln -sf ${BUILD_PATH}/l-loader/recovery.bin
|
||||
|
||||
- Prepare config file.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$vi config
|
||||
# The content of config file
|
||||
./sec_usb_xloader.img 0x00020000
|
||||
./sec_uce_boot.img 0x6A908000
|
||||
./recovery.bin 0x1AC00000
|
||||
|
||||
- Remove the modemmanager package. This package may causes hikey\_idt tool failure.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo apt-get purge modemmanager
|
||||
|
||||
- Run the command to download recovery.bin into HiKey960.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo ./hikey_idt -c config -p /dev/ttyUSB1
|
||||
|
||||
- UEFI running in recovery mode.
|
||||
When prompt '.' is displayed on console, press hotkey 'f' in keyboard. Then Android fastboot app is running.
|
||||
The timeout of prompt '.' is 10 seconds.
|
||||
|
||||
- Update images.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
$sudo fastboot flash ptable prm_ptable.img
|
||||
$sudo fastboot flash xloader sec_xloader.img
|
||||
$sudo fastboot flash fastboot l-loader.bin
|
||||
$sudo fastboot flash fip fip.bin
|
||||
$sudo fastboot flash boot boot.img
|
||||
$sudo fastboot flash cache cache.img
|
||||
$sudo fastboot flash system system.img
|
||||
$sudo fastboot flash userdata userdata.img
|
||||
|
||||
- Notice: UEFI could also boot kernel in recovery mode, but BL31 isn't loaded in
|
||||
recovery mode.
|
||||
|
||||
Boot UEFI in normal mode
|
||||
------------------------
|
||||
|
||||
- Make sure "Boot Mode" switch is OFF for normal boot mode. Then power on HiKey960.
|
||||
|
||||
- Reference `link <https://github.com/96boards-hikey/tools-images-hikey960/blob/master/build-from-source/README-ATF-UEFI-build-from-source.md>`__
|
||||
|
||||
.. _link: https://www.96boards.org/documentation/consumer/hikey/hikey960
|
||||
58
arm-trusted-firmware/docs/plat/imx8.rst
Normal file
58
arm-trusted-firmware/docs/plat/imx8.rst
Normal file
@@ -0,0 +1,58 @@
|
||||
NXP i.MX 8 Series
|
||||
=================
|
||||
|
||||
The i.MX 8 series of applications processors is a feature- and
|
||||
performance-scalable multi-core platform that includes single-,
|
||||
dual-, and quad-core families based on the Arm® Cortex®
|
||||
architecture—including combined Cortex-A72 + Cortex-A53,
|
||||
Cortex-A35, and Cortex-M4 based solutions for advanced graphics,
|
||||
imaging, machine vision, audio, voice, video, and safety-critical
|
||||
applications.
|
||||
|
||||
The i.MX8QM is with 2 Cortex-A72 ARM core, 4 Cortex-A53 ARM core
|
||||
and 1 Cortex-M4 system controller.
|
||||
|
||||
The i.MX8QX is with 4 Cortex-A35 ARM core and 1 Cortex-M4 system
|
||||
controller.
|
||||
|
||||
The System Controller (SC) represents the evolution of centralized
|
||||
control for system-level resources on i.MX8. The heart of the system
|
||||
controller is a Cortex-M4 that executes system controller firmware.
|
||||
|
||||
Boot Sequence
|
||||
-------------
|
||||
|
||||
Bootrom --> BL31 --> BL33(u-boot) --> Linux kernel
|
||||
|
||||
How to build
|
||||
------------
|
||||
|
||||
Build Procedure
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
- Prepare AARCH64 toolchain.
|
||||
|
||||
- Build System Controller Firmware and u-boot firstly, and get binary images: scfw_tcm.bin and u-boot.bin
|
||||
|
||||
- Build TF-A
|
||||
|
||||
Build bl31:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
CROSS_COMPILE=aarch64-linux-gnu- make PLAT=<Target_SoC> bl31
|
||||
|
||||
Target_SoC should be "imx8qm" for i.MX8QM SoC.
|
||||
Target_SoC should be "imx8qx" for i.MX8QX SoC.
|
||||
|
||||
Deploy TF-A Images
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
TF-A binary(bl31.bin), scfw_tcm.bin and u-boot.bin are combined together
|
||||
to generate a binary file called flash.bin, the imx-mkimage tool is used
|
||||
to generate flash.bin, and flash.bin needs to be flashed into SD card
|
||||
with certain offset for BOOT ROM. The system controller firmware,
|
||||
u-boot and imx-mkimage will be upstreamed soon, this doc will be updated
|
||||
once they are ready, and the link will be posted.
|
||||
|
||||
.. _i.MX8: https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8-family-arm-cortex-a53-cortex-a72-virtualization-vision-3d-graphics-4k-video:i.MX8
|
||||
113
arm-trusted-firmware/docs/plat/imx8m.rst
Normal file
113
arm-trusted-firmware/docs/plat/imx8m.rst
Normal file
@@ -0,0 +1,113 @@
|
||||
NXP i.MX 8M Series
|
||||
==================
|
||||
|
||||
The i.MX 8M family of applications processors based on Arm Corte-A53 and Cortex-M4
|
||||
cores provide high-performance computing, power efficiency, enhanced system
|
||||
reliability and embedded security needed to drive the growth of fast-growing
|
||||
edge node computing, streaming multimedia, and machine learning applications.
|
||||
|
||||
imx8mq is dropped in TF-A CI build due to the small OCRAM size, but still actively
|
||||
maintained in NXP official release.
|
||||
|
||||
Boot Sequence
|
||||
-------------
|
||||
|
||||
Bootrom --> SPL --> BL31 --> BL33(u-boot) --> Linux kernel
|
||||
|
||||
How to build
|
||||
------------
|
||||
|
||||
Build Procedure
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
- Prepare AARCH64 toolchain.
|
||||
|
||||
- Build spl and u-boot firstly, and get binary images: u-boot-spl.bin,
|
||||
u-boot-nodtb.bin and dtb for the target board.
|
||||
|
||||
- Build TF-A
|
||||
|
||||
Build bl31:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
CROSS_COMPILE=aarch64-linux-gnu- make PLAT=<Target_SoC> bl31
|
||||
|
||||
Target_SoC should be "imx8mq" for i.MX8MQ SoC.
|
||||
Target_SoC should be "imx8mm" for i.MX8MM SoC.
|
||||
Target_SoC should be "imx8mn" for i.MX8MN SoC.
|
||||
Target_SoC should be "imx8mp" for i.MX8MP SoC.
|
||||
|
||||
Deploy TF-A Images
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
TF-A binary(bl31.bin), u-boot-spl.bin u-boot-nodtb.bin and dtb are combined
|
||||
together to generate a binary file called flash.bin, the imx-mkimage tool is
|
||||
used to generate flash.bin, and flash.bin needs to be flashed into SD card
|
||||
with certain offset for BOOT ROM. the u-boot and imx-mkimage will be upstreamed
|
||||
soon, this doc will be updated once they are ready, and the link will be posted.
|
||||
|
||||
TBBR Boot Sequence
|
||||
------------------
|
||||
|
||||
When setting NEED_BL2=1 on imx8mm. We support an alternative way of
|
||||
boot sequence to support TBBR.
|
||||
|
||||
Bootrom --> SPL --> BL2 --> BL31 --> BL33(u-boot with UEFI) --> grub
|
||||
|
||||
This helps us to fulfill the SystemReady EBBR standard.
|
||||
BL2 will be in the FIT image and SPL will verify it.
|
||||
All of the BL3x will be put in the FIP image. BL2 will verify them.
|
||||
In U-boot we turn on the UEFI secure boot features so it can verify
|
||||
grub. And we use grub to verify linux kernel.
|
||||
|
||||
Measured Boot
|
||||
-------------
|
||||
|
||||
When setting MEASURED_BOOT=1 on imx8mm we can let TF-A generate event logs
|
||||
with a DTB overlay. The overlay will be put at PLAT_IMX8M_DTO_BASE with
|
||||
maximum size PLAT_IMX8M_DTO_MAX_SIZE. Then in U-boot we can apply the DTB
|
||||
overlay and let U-boot to parse the event log and update the PCRs.
|
||||
|
||||
High Assurance Boot (HABv4)
|
||||
---------------------------
|
||||
|
||||
All actively maintained platforms have a support for High Assurance
|
||||
Boot (HABv4), which is implemented via ROM Vector Table (RVT) API to
|
||||
extend the Root-of-Trust beyond the SPL. Those calls are done via SMC
|
||||
and are executed in EL3, with results returned back to original caller.
|
||||
|
||||
Note on DRAM Memory Mapping
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
There is a special case of mapping the DRAM: entire DRAM available on the
|
||||
platform is mapped into the EL3 with MT_RW attributes.
|
||||
|
||||
Mapping the entire DRAM allows the usage of 2MB block mapping in Level-2
|
||||
Translation Table entries, which use less Page Table Entries (PTEs). If
|
||||
Level-3 PTE mapping is used instead then additional PTEs would be required,
|
||||
which leads to the increase of translation table size.
|
||||
|
||||
Due to the fact that the size of SRAM is limited on some platforms in the
|
||||
family it should rather be avoided creating additional Level-3 mapping and
|
||||
introduce more PTEs, hence the implementation uses Level-2 mapping which
|
||||
maps entire DRAM space.
|
||||
|
||||
The reason for the MT_RW attribute mapping scheme is the fact that the SMC
|
||||
API to get the status and events is called from NS world passing destination
|
||||
pointers which are located in DRAM. Mapping DRAM without MT_RW permissions
|
||||
causes those locations not to be filled, which in turn causing EL1&0 software
|
||||
not to receive replies.
|
||||
|
||||
Therefore, DRAM mapping is done with MT_RW attributes, as it is required for
|
||||
data exchange between EL3 and EL1&0 software.
|
||||
|
||||
Reference Documentation
|
||||
~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Details on HABv4 usage and implementation could be found in following documents:
|
||||
|
||||
- AN4581: "i.MX Secure Boot on HABv4 Supported Devices", Rev. 4 - June 2020
|
||||
- AN12263: "HABv4 RVT Guidelines and Recommendations", Rev. 1 - 06/2020
|
||||
- "HABv4 API Reference Manual". This document in the part of NXP Code Signing Tool (CST) distribution.
|
||||
|
||||
82
arm-trusted-firmware/docs/plat/index.rst
Normal file
82
arm-trusted-firmware/docs/plat/index.rst
Normal file
@@ -0,0 +1,82 @@
|
||||
Platform Ports
|
||||
==============
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Contents
|
||||
:hidden:
|
||||
|
||||
allwinner
|
||||
arm/index
|
||||
meson-axg
|
||||
meson-gxbb
|
||||
meson-gxl
|
||||
meson-g12a
|
||||
hikey
|
||||
hikey960
|
||||
intel-agilex
|
||||
intel-stratix10
|
||||
marvell/index
|
||||
mt8183
|
||||
mt8186
|
||||
mt8188
|
||||
mt8192
|
||||
mt8195
|
||||
nvidia-tegra
|
||||
warp7
|
||||
imx8
|
||||
imx8m
|
||||
nxp/index
|
||||
poplar
|
||||
qemu
|
||||
qemu-sbsa
|
||||
qti
|
||||
qti-msm8916
|
||||
rpi3
|
||||
rpi4
|
||||
rcar-gen3
|
||||
rz-g2
|
||||
rockchip
|
||||
socionext-uniphier
|
||||
synquacer
|
||||
stm32mp1
|
||||
ti-k3
|
||||
xilinx-versal-net
|
||||
xilinx-versal
|
||||
xilinx-zynqmp
|
||||
brcm-stingray
|
||||
|
||||
This section provides a list of supported upstream *platform ports* and the
|
||||
documentation associated with them.
|
||||
|
||||
.. note::
|
||||
In addition to the platforms ports listed within the table of contents, there
|
||||
are several additional platforms that are supported upstream but which do not
|
||||
currently have associated documentation:
|
||||
|
||||
- Arm Neoverse N1 System Development Platform (N1SDP)
|
||||
- Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
|
||||
- Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
|
||||
- Arm SGI-575
|
||||
- MediaTek MT8173 SoCs
|
||||
|
||||
Deprecated platforms
|
||||
--------------------
|
||||
|
||||
+----------------+----------------+--------------------+--------------------+
|
||||
| Platform | Vendor | Deprecated version | Deleted version |
|
||||
+================+================+====================+====================+
|
||||
| sgm775 | Arm | 2.5 | 2.7 |
|
||||
+----------------+----------------+--------------------+--------------------+
|
||||
| mt6795 | MTK | 2.5 | 2.7 |
|
||||
+----------------+----------------+--------------------+--------------------+
|
||||
| sgi575 | Arm | 2.8 | 3.0 |
|
||||
+----------------+----------------+--------------------+--------------------+
|
||||
| rdn1edge | Arm | 2.8 | 3.0 |
|
||||
+----------------+----------------+--------------------+--------------------+
|
||||
| tc0 | Arm | 2.8 | 3.0 |
|
||||
+----------------+----------------+--------------------+--------------------+
|
||||
|
||||
--------------
|
||||
|
||||
*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
|
||||
86
arm-trusted-firmware/docs/plat/intel-agilex.rst
Normal file
86
arm-trusted-firmware/docs/plat/intel-agilex.rst
Normal file
@@ -0,0 +1,86 @@
|
||||
Intel Agilex SoCFPGA
|
||||
========================
|
||||
|
||||
Agilex SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A53 processor.
|
||||
|
||||
Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes
|
||||
the hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33.
|
||||
|
||||
::
|
||||
|
||||
Boot ROM --> Trusted Firmware-A --> UEFI
|
||||
|
||||
How to build
|
||||
------------
|
||||
|
||||
Code Locations
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
- Trusted Firmware-A:
|
||||
`link <https://github.com/ARM-software/arm-trusted-firmware>`__
|
||||
|
||||
- UEFI (to be updated with new upstreamed UEFI):
|
||||
`link <https://github.com/altera-opensource/uefi-socfpga>`__
|
||||
|
||||
Build Procedure
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
- Fetch all the above 2 repositories into local host.
|
||||
Make all the repositories in the same ${BUILD\_PATH}.
|
||||
|
||||
- Prepare the AARCH64 toolchain.
|
||||
|
||||
- Build UEFI using Agilex platform as configuration
|
||||
This will be updated to use an updated UEFI using the latest EDK2 source
|
||||
|
||||
.. code:: bash
|
||||
|
||||
make CROSS_COMPILE=aarch64-linux-gnu- device=agx
|
||||
|
||||
- Build atf providing the previously generated UEFI as the BL33 image
|
||||
|
||||
.. code:: bash
|
||||
|
||||
make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=agilex
|
||||
BL33=PEI.ROM
|
||||
|
||||
Install Procedure
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
- dd fip.bin to a A2 partition on the MMC drive to be booted in Agilex
|
||||
board.
|
||||
|
||||
- Generate a SOF containing bl2
|
||||
|
||||
.. code:: bash
|
||||
|
||||
aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
|
||||
quartus_cpf --bootloader bl2.hex <quartus_generated_sof> <output_sof_with_bl2>
|
||||
|
||||
- Configure SOF to board
|
||||
|
||||
.. code:: bash
|
||||
|
||||
nios2-configure-sof <output_sof_with_bl2>
|
||||
|
||||
Boot trace
|
||||
----------
|
||||
|
||||
::
|
||||
|
||||
INFO: DDR: DRAM calibration success.
|
||||
INFO: ECC is disabled.
|
||||
NOTICE: BL2: v2.1(debug)
|
||||
NOTICE: BL2: Built
|
||||
INFO: BL2: Doing platform setup
|
||||
NOTICE: BL2: Booting BL31
|
||||
INFO: Entry point address = 0xffe1c000
|
||||
INFO: SPSR = 0x3cd
|
||||
NOTICE: BL31: v2.1(debug)
|
||||
NOTICE: BL31: Built
|
||||
INFO: ARM GICv2 driver initialized
|
||||
INFO: BL31: Initializing runtime services
|
||||
WARNING: BL31: cortex_a53
|
||||
INFO: BL31: Preparing for EL3 exit to normal world
|
||||
INFO: Entry point address = 0x50000
|
||||
INFO: SPSR = 0x3c9
|
||||
94
arm-trusted-firmware/docs/plat/intel-stratix10.rst
Normal file
94
arm-trusted-firmware/docs/plat/intel-stratix10.rst
Normal file
@@ -0,0 +1,94 @@
|
||||
Intel Stratix 10 SoCFPGA
|
||||
========================
|
||||
|
||||
Stratix 10 SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A53 processor.
|
||||
|
||||
Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes
|
||||
the hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33.
|
||||
|
||||
::
|
||||
|
||||
Boot ROM --> Trusted Firmware-A --> UEFI
|
||||
|
||||
How to build
|
||||
------------
|
||||
|
||||
Code Locations
|
||||
~~~~~~~~~~~~~~
|
||||
|
||||
- Trusted Firmware-A:
|
||||
`link <https://github.com/ARM-software/arm-trusted-firmware>`__
|
||||
|
||||
- UEFI (to be updated with new upstreamed UEFI):
|
||||
`link <https://github.com/altera-opensource/uefi-socfpga>`__
|
||||
|
||||
Build Procedure
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
- Fetch all the above 2 repositories into local host.
|
||||
Make all the repositories in the same ${BUILD\_PATH}.
|
||||
|
||||
- Prepare the AARCH64 toolchain.
|
||||
|
||||
- Build UEFI using Stratix 10 platform as configuration
|
||||
This will be updated to use an updated UEFI using the latest EDK2 source
|
||||
|
||||
.. code:: bash
|
||||
|
||||
make CROSS_COMPILE=aarch64-linux-gnu- device=s10
|
||||
|
||||
- Build atf providing the previously generated UEFI as the BL33 image
|
||||
|
||||
.. code:: bash
|
||||
|
||||
make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=stratix10
|
||||
BL33=PEI.ROM
|
||||
|
||||
Install Procedure
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
- dd fip.bin to a A2 partition on the MMC drive to be booted in Stratix 10
|
||||
board.
|
||||
|
||||
- Generate a SOF containing bl2
|
||||
|
||||
.. code:: bash
|
||||
|
||||
aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
|
||||
quartus_cpf --bootloader bl2.hex <quartus_generated_sof> <output_sof_with_bl2>
|
||||
|
||||
- Configure SOF to board
|
||||
|
||||
.. code:: bash
|
||||
|
||||
nios2-configure-sof <output_sof_with_bl2>
|
||||
|
||||
Boot trace
|
||||
----------
|
||||
|
||||
::
|
||||
|
||||
INFO: DDR: DRAM calibration success.
|
||||
INFO: ECC is disabled.
|
||||
INFO: Init HPS NOC's DDR Scheduler.
|
||||
NOTICE: BL2: v2.0(debug):v2.0-809-g7f8474a-dirty
|
||||
NOTICE: BL2: Built : 17:38:19, Feb 18 2019
|
||||
INFO: BL2: Doing platform setup
|
||||
INFO: BL2: Loading image id 3
|
||||
INFO: Loading image id=3 at address 0xffe1c000
|
||||
INFO: Image id=3 loaded: 0xffe1c000 - 0xffe24034
|
||||
INFO: BL2: Loading image id 5
|
||||
INFO: Loading image id=5 at address 0x50000
|
||||
INFO: Image id=5 loaded: 0x50000 - 0x550000
|
||||
NOTICE: BL2: Booting BL31
|
||||
INFO: Entry point address = 0xffe1c000
|
||||
INFO: SPSR = 0x3cd
|
||||
NOTICE: BL31: v2.0(debug):v2.0-810-g788c436-dirty
|
||||
NOTICE: BL31: Built : 15:17:16, Feb 20 2019
|
||||
INFO: ARM GICv2 driver initialized
|
||||
INFO: BL31: Initializing runtime services
|
||||
WARNING: BL31: cortex_a53: CPU workaround for 855873 was missing!
|
||||
INFO: BL31: Preparing for EL3 exit to normal world
|
||||
INFO: Entry point address = 0x50000
|
||||
INFO: SPSR = 0x3c9
|
||||
UEFI firmware (version 1.0 built at 11:26:18 on Nov 7 2018)
|
||||
476
arm-trusted-firmware/docs/plat/marvell/armada/build.rst
Normal file
476
arm-trusted-firmware/docs/plat/marvell/armada/build.rst
Normal file
@@ -0,0 +1,476 @@
|
||||
TF-A Build Instructions for Marvell Platforms
|
||||
=============================================
|
||||
|
||||
This section describes how to compile the Trusted Firmware-A (TF-A) project for Marvell's platforms.
|
||||
|
||||
Build Instructions
|
||||
------------------
|
||||
(1) Set the cross compiler
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> export CROSS_COMPILE=/path/to/toolchain/aarch64-linux-gnu-
|
||||
|
||||
(2) Set path for FIP images:
|
||||
|
||||
Set U-Boot image path (relatively to TF-A root or absolute path)
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> export BL33=path/to/u-boot.bin
|
||||
|
||||
For example: if U-Boot project (and its images) is located at ``~/project/u-boot``,
|
||||
BL33 should be ``~/project/u-boot/u-boot.bin``
|
||||
|
||||
.. note::
|
||||
|
||||
*u-boot.bin* should be used and not *u-boot-spl.bin*
|
||||
|
||||
Set MSS/SCP image path (mandatory only for A7K/A8K/CN913x when MSS_SUPPORT=1)
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> export SCP_BL2=path/to/mrvl_scp_bl2*.img
|
||||
|
||||
(3) Armada-37x0 build requires WTP tools installation.
|
||||
|
||||
See below in the section "Tools and external components installation".
|
||||
Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> sudo apt-get install gcc-arm-linux-gnueabi
|
||||
|
||||
(4) Clean previous build residuals (if any)
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> make distclean
|
||||
|
||||
(5) Build TF-A
|
||||
|
||||
There are several build options:
|
||||
|
||||
- PLAT
|
||||
|
||||
Supported Marvell platforms are:
|
||||
|
||||
- a3700 - A3720 DB, EspressoBin and Turris MOX
|
||||
- a70x0
|
||||
- a70x0_amc - AMC board
|
||||
- a70x0_mochabin - Globalscale MOCHAbin
|
||||
- a80x0
|
||||
- a80x0_mcbin - MacchiatoBin
|
||||
- a80x0_puzzle - IEI Puzzle-M801
|
||||
- t9130 - CN913x
|
||||
- t9130_cex7_eval - CN913x CEx7 Evaluation Board
|
||||
|
||||
- DEBUG
|
||||
|
||||
Default is without debug information (=0). in order to enable it use ``DEBUG=1``.
|
||||
Can be enabled also when building UART recovery images, there is no issue with it.
|
||||
|
||||
Production TF-A images should be built without this debug option!
|
||||
|
||||
- LOG_LEVEL
|
||||
|
||||
Defines the level of logging which will be purged to the default output port.
|
||||
|
||||
- 0 - LOG_LEVEL_NONE
|
||||
- 10 - LOG_LEVEL_ERROR
|
||||
- 20 - LOG_LEVEL_NOTICE (default for DEBUG=0)
|
||||
- 30 - LOG_LEVEL_WARNING
|
||||
- 40 - LOG_LEVEL_INFO (default for DEBUG=1)
|
||||
- 50 - LOG_LEVEL_VERBOSE
|
||||
|
||||
- USE_COHERENT_MEM
|
||||
|
||||
This flag determines whether to include the coherent memory region in the
|
||||
BL memory map or not. Enabled by default.
|
||||
|
||||
- LLC_ENABLE
|
||||
|
||||
Flag defining the LLC (L3) cache state. The cache is enabled by default (``LLC_ENABLE=1``).
|
||||
|
||||
- LLC_SRAM
|
||||
|
||||
Flag enabling the LLC (L3) cache SRAM support. The LLC SRAM is activated and used
|
||||
by Trusted OS (OP-TEE OS, BL32). The TF-A only prepares CCU address translation windows
|
||||
for SRAM address range at BL31 execution stage with window target set to DRAM-0.
|
||||
When Trusted OS activates LLC SRAM, the CCU window target is changed to SRAM.
|
||||
There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n.
|
||||
Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y.
|
||||
|
||||
- MARVELL_SECURE_BOOT
|
||||
|
||||
Build trusted(=1)/non trusted(=0) image, default is non trusted.
|
||||
This parameter is used only for ``mrvl_flash`` and ``mrvl_uart`` targets.
|
||||
|
||||
- MV_DDR_PATH
|
||||
|
||||
This parameter is required for ``mrvl_flash`` and ``mrvl_uart`` targets.
|
||||
For A7K/A8K/CN913x it is used for BLE build and for Armada37x0 it used
|
||||
for ddr_tool build.
|
||||
|
||||
Specify path to the full checkout of Marvell mv-ddr-marvell git
|
||||
repository. Checkout must contain also .git subdirectory because
|
||||
mv-ddr build process calls git commands.
|
||||
|
||||
Do not remove any parts of git checkout becuase build process and other
|
||||
applications need them for correct building and version determination.
|
||||
|
||||
|
||||
CN913x specific build options:
|
||||
|
||||
- CP_NUM
|
||||
|
||||
Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted,
|
||||
the build uses the default number of CPs, which is a number of embedded CPs inside the
|
||||
package: 1 or 2 depending on the SoC used. The parameter is valid for OcteonTX2 CN913x SoC
|
||||
family (PLAT=t9130), which can have external CPs connected to the MCI ports. Valid
|
||||
values with CP_NUM are in a range of 1 to 3.
|
||||
|
||||
|
||||
A7K/A8K/CN913x specific build options:
|
||||
|
||||
- BLE_PATH
|
||||
|
||||
Points to BLE (Binary ROM extension) sources folder.
|
||||
The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``
|
||||
which uses TF-A in-tree BLE implementation.
|
||||
|
||||
- MSS_SUPPORT
|
||||
|
||||
When ``MSS_SUPPORT=1``, then TF-A includes support for Management SubSystem (MSS).
|
||||
When enabled it is required to specify path to the MSS firmware image via ``SCP_BL2``
|
||||
option.
|
||||
|
||||
This option is by default enabled.
|
||||
|
||||
- SCP_BL2
|
||||
|
||||
Specify path to the MSS fimware image binary which will run on Cortex-M3 coprocessor.
|
||||
It is available in Marvell binaries-marvell git repository. Required when ``MSS_SUPPORT=1``.
|
||||
|
||||
Globalscale MOCHAbin specific build options:
|
||||
|
||||
- DDR_TOPOLOGY
|
||||
|
||||
The DDR topology map index/name, default is 0.
|
||||
|
||||
Supported Options:
|
||||
- 0 - DDR4 1CS 2GB
|
||||
- 1 - DDR4 1CS 4GB
|
||||
- 2 - DDR4 2CS 8GB
|
||||
|
||||
Armada37x0 specific build options:
|
||||
|
||||
- HANDLE_EA_EL3_FIRST_NS
|
||||
|
||||
When ``HANDLE_EA_EL3_FIRST_NS=1``, External Aborts and SError Interrupts, resulting from errors
|
||||
in NS world, will be always trapped in TF-A. TF-A in this case enables dirty hack / workaround for
|
||||
a bug found in U-Boot and Linux kernel PCIe controller driver pci-aardvark.c, traps and then masks
|
||||
SError interrupt caused by AXI SLVERR on external access (syndrome 0xbf000002).
|
||||
|
||||
Otherwise when ``HANDLE_EA_EL3_FIRST_NS=0``, these exceptions will be trapped in the current
|
||||
exception level (or in EL1 if the current exception level is EL0). So exceptions caused by
|
||||
U-Boot will be trapped in U-Boot, exceptions caused by Linux kernel (or user applications)
|
||||
will be trapped in Linux kernel.
|
||||
|
||||
Mentioned bug in pci-aardvark.c driver is fixed in U-Boot version v2021.07 and Linux kernel
|
||||
version v5.13 (workarounded since Linux kernel version 5.9) and also backported in Linux
|
||||
kernel stable releases since versions v5.12.13, v5.10.46, v5.4.128, v4.19.198, v4.14.240.
|
||||
|
||||
If target system has already patched version of U-Boot and Linux kernel then it is strongly
|
||||
recommended to not enable this workaround as it disallows propagating of all External Aborts
|
||||
to running Linux kernel and makes correctable errors as fatal aborts.
|
||||
|
||||
This option is now disabled by default. In past this option has different name "HANDLE_EA_EL3_FIRST" and
|
||||
was enabled by default in TF-A versions v2.2, v2.3, v2.4 and v2.5.
|
||||
|
||||
- CM3_SYSTEM_RESET
|
||||
|
||||
When ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will be used for system reset.
|
||||
|
||||
TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the
|
||||
Cortex-M3 secure coprocessor.
|
||||
The firmware running in the coprocessor must either implement this functionality or
|
||||
ignore the 0x0009 command (which is true for the firmware from A3700-utils-marvell
|
||||
repository). If this option is enabled but the firmware does not support this command,
|
||||
an error message will be printed prior trying to reboot via the usual way.
|
||||
|
||||
This option is needed on Turris MOX as a workaround to a HW bug which causes reset to
|
||||
sometime hang the board.
|
||||
|
||||
- A3720_DB_PM_WAKEUP_SRC
|
||||
|
||||
For Armada 3720 Development Board only, when ``A3720_DB_PM_WAKEUP_SRC=1``,
|
||||
TF-A will setup PM wake up src configuration. This option is disabled by default.
|
||||
|
||||
|
||||
Armada37x0 specific build options for ``mrvl_flash`` and ``mrvl_uart`` targets:
|
||||
|
||||
- DDR_TOPOLOGY
|
||||
|
||||
The DDR topology map index/name, default is 0.
|
||||
|
||||
Supported Options:
|
||||
- 0 - DDR3 1CS 512MB (DB-88F3720-DDR3-Modular, EspressoBin V3-V5)
|
||||
- 1 - DDR4 1CS 512MB (DB-88F3720-DDR4-Modular)
|
||||
- 2 - DDR3 2CS 1GB (EspressoBin V3-V5)
|
||||
- 3 - DDR4 2CS 4GB (DB-88F3720-DDR4-Modular)
|
||||
- 4 - DDR3 1CS 1GB (DB-88F3720-DDR3-Modular, EspressoBin V3-V5)
|
||||
- 5 - DDR4 1CS 1GB (EspressoBin V7, EspressoBin-Ultra)
|
||||
- 6 - DDR4 2CS 2GB (EspressoBin V7)
|
||||
- 7 - DDR3 2CS 2GB (EspressoBin V3-V5)
|
||||
- CUST - CUSTOMER BOARD (Customer board settings)
|
||||
|
||||
- CLOCKSPRESET
|
||||
|
||||
The clock tree configuration preset including CPU and DDR frequency,
|
||||
default is CPU_800_DDR_800.
|
||||
|
||||
- CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
|
||||
- CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
|
||||
- CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
|
||||
- CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
|
||||
|
||||
Look at Armada37x0 chip package marking on board to identify correct CPU frequency.
|
||||
The last line on package marking (next line after the 88F37x0 line) should contain:
|
||||
|
||||
- C080 or I080 - chip with 800 MHz CPU - use ``CLOCKSPRESET=CPU_800_DDR_800``
|
||||
- C100 or I100 - chip with 1000 MHz CPU - use ``CLOCKSPRESET=CPU_1000_DDR_800``
|
||||
- C120 - chip with 1200 MHz CPU - use ``CLOCKSPRESET=CPU_1200_DDR_750``
|
||||
|
||||
- BOOTDEV
|
||||
|
||||
The flash boot device, default is ``SPINOR``.
|
||||
|
||||
Currently, Armada37x0 only supports ``SPINOR``, ``SPINAND``, ``EMMCNORM`` and ``SATA``:
|
||||
|
||||
- SPINOR - SPI NOR flash boot
|
||||
- SPINAND - SPI NAND flash boot
|
||||
- EMMCNORM - eMMC Download Mode
|
||||
|
||||
Download boot loader or program code from eMMC flash into CM3 or CA53
|
||||
Requires full initialization and command sequence
|
||||
|
||||
- SATA - SATA device boot
|
||||
|
||||
Image needs to be stored at disk LBA 0 or at disk partition with
|
||||
MBR type 0x4d (ASCII 'M' as in Marvell) or at disk partition with
|
||||
GPT partition type GUID ``6828311A-BA55-42A4-BCDE-A89BB5EDECAE``.
|
||||
|
||||
- PARTNUM
|
||||
|
||||
The boot partition number, default is 0.
|
||||
|
||||
To boot from eMMC, the value should be aligned with the parameter in
|
||||
U-Boot with name of ``CONFIG_SYS_MMC_ENV_PART``, whose value by default is
|
||||
1. For details about CONFIG_SYS_MMC_ENV_PART, please refer to the U-Boot
|
||||
build instructions.
|
||||
|
||||
- WTMI_IMG
|
||||
|
||||
The path of the binary can point to an image which
|
||||
does nothing, an image which supports EFUSE or a customized CM3 firmware
|
||||
binary. The default image is ``fuse.bin`` that built from sources in WTP
|
||||
folder, which is the next option. If the default image is OK, then this
|
||||
option should be skipped.
|
||||
|
||||
Please note that this is not a full WTMI image, just a main loop without
|
||||
hardware initialization code. Final WTMI image is built from this WTMI_IMG
|
||||
binary and sys-init code from the WTP directory which sets DDR and CPU
|
||||
clocks according to DDR_TOPOLOGY and CLOCKSPRESET options.
|
||||
|
||||
CZ.NIC as part of Turris project released free and open source WTMI
|
||||
application firmware ``wtmi_app.bin`` for all Armada 3720 devices.
|
||||
This firmware includes additional features like access to Hardware
|
||||
Random Number Generator of Armada 3720 SoC which original Marvell's
|
||||
``fuse.bin`` image does not have.
|
||||
|
||||
CZ.NIC's Armada 3720 Secure Firmware is available at website:
|
||||
|
||||
https://gitlab.nic.cz/turris/mox-boot-builder/
|
||||
|
||||
- WTP
|
||||
|
||||
Specify path to the full checkout of Marvell A3700-utils-marvell git
|
||||
repository. Checkout must contain also .git subdirectory because WTP
|
||||
build process calls git commands.
|
||||
|
||||
WTP build process uses also Marvell mv-ddr-marvell git repository
|
||||
specified in MV_DDR_PATH option.
|
||||
|
||||
Do not remove any parts of git checkout becuase build process and other
|
||||
applications need them for correct building and version determination.
|
||||
|
||||
- CRYPTOPP_PATH
|
||||
|
||||
Use this parameter to point to Crypto++ source code
|
||||
directory. If this option is specified then Crypto++ source code in
|
||||
CRYPTOPP_PATH directory will be automatically compiled. Crypto++ library
|
||||
is required for building WTP image tool. Either CRYPTOPP_PATH or
|
||||
CRYPTOPP_LIBDIR with CRYPTOPP_INCDIR needs to be specified for Armada37x0.
|
||||
|
||||
- CRYPTOPP_LIBDIR
|
||||
|
||||
Use this parameter to point to the directory with
|
||||
compiled Crypto++ library. By default it points to the CRYPTOPP_PATH.
|
||||
|
||||
On Debian systems it is possible to install system-wide Crypto++ library
|
||||
via command ``apt install libcrypto++-dev`` and specify CRYPTOPP_LIBDIR
|
||||
to ``/usr/lib/``.
|
||||
|
||||
- CRYPTOPP_INCDIR
|
||||
|
||||
Use this parameter to point to the directory with
|
||||
header files of Crypto++ library. By default it points to the CRYPTOPP_PATH.
|
||||
|
||||
On Debian systems it is possible to install system-wide Crypto++ library
|
||||
via command ``apt install libcrypto++-dev`` and specify CRYPTOPP_INCDIR
|
||||
to ``/usr/include/crypto++/``.
|
||||
|
||||
|
||||
For example, in order to build the image in debug mode with log level up to 'notice' level run
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> mrvl_flash
|
||||
|
||||
And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level,
|
||||
the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
|
||||
the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command
|
||||
line is as following
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \
|
||||
MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \
|
||||
MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \
|
||||
CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \
|
||||
all fip mrvl_bootimage mrvl_flash mrvl_uart
|
||||
|
||||
To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run following command:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> make USE_COHERENT_MEM=0 PLAT=a3700 CM3_SYSTEM_RESET=1 BL33=/path/to/u-boot.bin \
|
||||
CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
|
||||
|
||||
Here is full example how to build production release of Marvell firmware image (concatenated
|
||||
binary of Marvell's A3720 sys-init, CZ.NIC's Armada 3720 Secure Firmware, TF-A and U-Boot) for
|
||||
EspressoBin board (PLAT=a3700) with 1GHz CPU (CLOCKSPRESET=CPU_1000_DDR_800) and
|
||||
1GB DDR4 RAM (DDR_TOPOLOGY=5):
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
|
||||
> git clone https://source.denx.de/u-boot/u-boot.git
|
||||
> git clone https://github.com/weidai11/cryptopp.git
|
||||
> git clone https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
|
||||
> git clone https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
|
||||
> git clone https://gitlab.nic.cz/turris/mox-boot-builder.git
|
||||
> make -C u-boot CROSS_COMPILE=aarch64-linux-gnu- mvebu_espressobin-88f3720_defconfig u-boot.bin
|
||||
> make -C mox-boot-builder CROSS_CM3=arm-linux-gnueabi- wtmi_app.bin
|
||||
> make -C trusted-firmware-a CROSS_COMPILE=aarch64-linux-gnu- CROSS_CM3=arm-linux-gnueabi- \
|
||||
USE_COHERENT_MEM=0 PLAT=a3700 CLOCKSPRESET=CPU_1000_DDR_800 DDR_TOPOLOGY=5 \
|
||||
MV_DDR_PATH=$PWD/mv-ddr-marvell/ WTP=$PWD/A3700-utils-marvell/ \
|
||||
CRYPTOPP_PATH=$PWD/cryptopp/ BL33=$PWD/u-boot/u-boot.bin \
|
||||
WTMI_IMG=$PWD/mox-boot-builder/wtmi_app.bin FIP_ALIGN=0x100 mrvl_flash
|
||||
|
||||
Produced Marvell firmware flash image: ``trusted-firmware-a/build/a3700/release/flash-image.bin``
|
||||
|
||||
Special Build Flags
|
||||
--------------------
|
||||
|
||||
- PLAT_RECOVERY_IMAGE_ENABLE
|
||||
When set this option to enable secondary recovery function when build atf.
|
||||
In order to build UART recovery image this operation should be disabled for
|
||||
A7K/A8K/CN913x because of hardware limitation (boot from secondary image
|
||||
can interrupt UART recovery process). This MACRO definition is set in
|
||||
``plat/marvell/armada/a8k/common/include/platform_def.h`` file.
|
||||
|
||||
- DDR32
|
||||
In order to work in 32bit DDR, instead of the default 64bit ECC DDR,
|
||||
this flag should be set to 1.
|
||||
|
||||
For more information about build options, please refer to the
|
||||
:ref:`Build Options` document.
|
||||
|
||||
|
||||
Build output
|
||||
------------
|
||||
Marvell's TF-A compilation generates 8 files:
|
||||
|
||||
- ble.bin - BLe image (not available for Armada37x0)
|
||||
- bl1.bin - BL1 image
|
||||
- bl2.bin - BL2 image
|
||||
- bl31.bin - BL31 image
|
||||
- fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images)
|
||||
- boot-image.bin - TF-A image (contains BL1 and FIP images)
|
||||
- flash-image.bin - Flashable Marvell firmware image. For Armada37x0 it
|
||||
contains TIM, WTMI and boot-image.bin images. For other platforms it contains
|
||||
BLe and boot-image.bin images. Should be placed on the boot flash/device.
|
||||
- uart-images.tgz.bin - GZIPed TAR archive which contains Armada37x0 images
|
||||
for booting via UART. Could be loaded via Marvell's WtpDownload tool from
|
||||
A3700-utils-marvell repository.
|
||||
|
||||
Additional make target ``mrvl_bootimage`` produce ``boot-image.bin`` file. Target
|
||||
``mrvl_flash`` produce final ``flash-image.bin`` file and target ``mrvl_uart``
|
||||
produce ``uart-images.tgz.bin`` file.
|
||||
|
||||
|
||||
Tools and external components installation
|
||||
------------------------------------------
|
||||
|
||||
Armada37x0 Builds require installation of additional components
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
(1) ARM cross compiler capable of building images for the service CPU (CM3).
|
||||
This component is usually included in the Linux host packages.
|
||||
On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed
|
||||
using the following command
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> sudo apt-get install gcc-arm-linux-gnueabi
|
||||
|
||||
Only if required, the default tool chain prefix ``arm-linux-gnueabi-`` can be
|
||||
overwritten using the environment variable ``CROSS_CM3``.
|
||||
Example for BASH shell
|
||||
|
||||
.. code:: shell
|
||||
|
||||
> export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi
|
||||
|
||||
(2) DDR initialization library sources (mv_ddr) available at the following repository
|
||||
(use the "master" branch):
|
||||
|
||||
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
|
||||
|
||||
(3) Armada3700 tools available at the following repository
|
||||
(use the "master" branch):
|
||||
|
||||
https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
|
||||
|
||||
(4) Crypto++ library available at the following repository:
|
||||
|
||||
https://github.com/weidai11/cryptopp.git
|
||||
|
||||
(5) Optional CZ.NIC's Armada 3720 Secure Firmware:
|
||||
|
||||
https://gitlab.nic.cz/turris/mox-boot-builder.git
|
||||
|
||||
Armada70x0, Armada80x0 and CN913x Builds require installation of additional components
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
(1) DDR initialization library sources (mv_ddr) available at the following repository
|
||||
(use the "master" branch):
|
||||
|
||||
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
|
||||
|
||||
(2) MSS Management SubSystem Firmware available at the following repository
|
||||
(use the "binaries-marvell-armada-SDK10.0.1.0" branch):
|
||||
|
||||
https://github.com/MarvellEmbeddedProcessors/binaries-marvell.git
|
||||
@@ -0,0 +1,49 @@
|
||||
Address decoding flow and address translation units of Marvell Armada 8K SoC family
|
||||
===================================================================================
|
||||
|
||||
::
|
||||
|
||||
+--------------------------------------------------------------------------------------------------+
|
||||
| +-------------+ +--------------+ |
|
||||
| | Memory +----- DRAM CS | |
|
||||
|+------------+ +-----------+ +-----------+ | Controller | +--------------+ |
|
||||
|| AP DMA | | | | | +-------------+ |
|
||||
|| SD/eMMC | | CA72 CPUs | | AP MSS | +-------------+ |
|
||||
|| MCI-0/1 | | | | | | Memory | |
|
||||
|+------+-----+ +--+--------+ +--------+--+ +------------+ | Controller | +-------------+ |
|
||||
| | | | | +----- Translaton | |AP | |
|
||||
| | | | | | +-------------+ |Configuration| |
|
||||
| | | +-----+ +-------------------------Space | |
|
||||
| | | +-------------+ | CCU | +-------------+ |
|
||||
| | | | MMU +---------+ Windows | +-----------+ +-------------+ |
|
||||
| | +-| translation | | Lookup +---- +--------- AP SPI | |
|
||||
| | +-------------+ | | | | +-------------+ |
|
||||
| | +-------------+ | | | IO | +-------------+ |
|
||||
| +------------| SMMU +---------+ | | Windows +--------- AP MCI0/1 | |
|
||||
| | translation | +------------+ | Lookup | +-------------+ |
|
||||
| +---------+---+ | | +-------------+ |
|
||||
| - | | +--------- AP STM | |
|
||||
| +----------------- | | +-------------+ |
|
||||
| AP | | +-+---------+ |
|
||||
+---------------------------------------------------------------|----------------------------------+
|
||||
+-------------|-------------------------------------------------|----------------------------------+
|
||||
| CP | +-------------+ +------+-----+ +-------------------+ |
|
||||
| | | | | +------- SB CFG Space | |
|
||||
| | | DIOB | | | +-------------------+ |
|
||||
| | | Windows ----------------- IOB | +-------------------+ |
|
||||
| | | Control | | Windows +------| SB PCIe-0 - PCIe2 | |
|
||||
| | | | | Lookup | +-------------------+ |
|
||||
| | +------+------+ | | +-------------------+ |
|
||||
| | | | +------+ SB NAND | |
|
||||
| | | +------+-----+ +-------------------+ |
|
||||
| | | | |
|
||||
| | | | |
|
||||
| +------------------+ +------------+ +------+-----+ +-------------------+ |
|
||||
| | Network Engine | | | | +------- SB SPI-0/SPI-1 | |
|
||||
| | Security Engine | | PCIe, MSS | | RUNIT | +-------------------+ |
|
||||
| | SATA, USB | | DMA | | Windows | +-------------------+ |
|
||||
| | SD/eMMC | | | | Lookup +------- SB Device Bus | |
|
||||
| | TDM, I2C | | | | | +-------------------+ |
|
||||
| +------------------+ +------------+ +------------+ |
|
||||
| |
|
||||
+--------------------------------------------------------------------------------------------------+
|
||||
@@ -0,0 +1,58 @@
|
||||
AMB - AXI MBUS address decoding
|
||||
===============================
|
||||
|
||||
AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs.
|
||||
|
||||
The Runit offers a second level of address windows lookup. It is used to map
|
||||
transaction towards the CD BootROM, SPI0, SPI1 and Device bus (NOR).
|
||||
|
||||
The Runit contains eight configurable windows. Each window defines a contiguous,
|
||||
address space and the properties associated with that address space.
|
||||
|
||||
::
|
||||
|
||||
Unit Bank ATTR
|
||||
Device-Bus DEV_BOOT_CS 0x2F
|
||||
DEV_CS0 0x3E
|
||||
DEV_CS1 0x3D
|
||||
DEV_CS2 0x3B
|
||||
DEV_CS3 0x37
|
||||
SPI-0 SPI_A_CS0 0x1E
|
||||
SPI_A_CS1 0x5E
|
||||
SPI_A_CS2 0x9E
|
||||
SPI_A_CS3 0xDE
|
||||
SPI_A_CS4 0x1F
|
||||
SPI_A_CS5 0x5F
|
||||
SPI_A_CS6 0x9F
|
||||
SPI_A_CS7 0xDF
|
||||
SPI SPI_B_CS0 0x1A
|
||||
SPI_B_CS1 0x5A
|
||||
SPI_B_CS2 0x9A
|
||||
SPI_B_CS3 0xDA
|
||||
BOOT_ROM BOOT_ROM 0x1D
|
||||
UART UART 0x01
|
||||
|
||||
Mandatory functions
|
||||
-------------------
|
||||
|
||||
- marvell_get_amb_memory_map
|
||||
Returns the AMB windows configuration and the number of windows
|
||||
|
||||
Mandatory structures
|
||||
--------------------
|
||||
|
||||
- amb_memory_map
|
||||
Array that include the configuration of the windows. Every window/entry is a
|
||||
struct which has 2 parameters:
|
||||
|
||||
- Base address of the window
|
||||
- Attribute of the window
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
.. code:: c
|
||||
|
||||
struct addr_map_win amb_memory_map[] = {
|
||||
{0xf900, AMB_DEV_CS0_ID},
|
||||
};
|
||||
@@ -0,0 +1,33 @@
|
||||
Marvell CCU address decoding bindings
|
||||
=====================================
|
||||
|
||||
CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
|
||||
|
||||
The CCU node includes a description of the address decoding configuration.
|
||||
|
||||
Mandatory functions
|
||||
-------------------
|
||||
|
||||
- marvell_get_ccu_memory_map
|
||||
Return the CCU windows configuration and the number of windows of the
|
||||
specific AP.
|
||||
|
||||
Mandatory structures
|
||||
--------------------
|
||||
|
||||
- ccu_memory_map
|
||||
Array that includes the configuration of the windows. Every window/entry is
|
||||
a struct which has 3 parameters:
|
||||
|
||||
- Base address of the window
|
||||
- Size of the window
|
||||
- Target-ID of the window
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
.. code:: c
|
||||
|
||||
struct addr_map_win ccu_memory_map[] = {
|
||||
{0x00000000f2000000, 0x00000000e000000, IO_0_TID}, /* IO window */
|
||||
};
|
||||
@@ -0,0 +1,46 @@
|
||||
Marvell IO WIN address decoding bindings
|
||||
========================================
|
||||
|
||||
IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
|
||||
|
||||
The IO WIN includes a description of the address decoding configuration.
|
||||
|
||||
Transactions that are decoded by CCU windows as IO peripheral, have an additional
|
||||
layer of decoding. This additional address decoding layer defines one of the
|
||||
following targets:
|
||||
|
||||
- **0x0** = BootRom
|
||||
- **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
|
||||
- **0x2** = SPI direct access
|
||||
- **0x3** = PCIe registers
|
||||
- **0x4** = MCI Port
|
||||
- **0x5** = PCIe port
|
||||
|
||||
Mandatory functions
|
||||
-------------------
|
||||
|
||||
- marvell_get_io_win_memory_map
|
||||
Returns the IO windows configuration and the number of windows of the
|
||||
specific AP.
|
||||
|
||||
Mandatory structures
|
||||
--------------------
|
||||
|
||||
- io_win_memory_map
|
||||
Array that include the configuration of the windows. Every window/entry is
|
||||
a struct which has 3 parameters:
|
||||
|
||||
- Base address of the window
|
||||
- Size of the window
|
||||
- Target-ID of the window
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
.. code:: c
|
||||
|
||||
struct addr_map_win io_win_memory_map[] = {
|
||||
{0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
|
||||
{0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
|
||||
{0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/
|
||||
};
|
||||
@@ -0,0 +1,52 @@
|
||||
Marvell IOB address decoding bindings
|
||||
=====================================
|
||||
|
||||
IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
|
||||
|
||||
The IOB includes a description of the address decoding configuration.
|
||||
|
||||
IOB supports up to n (in CP110 n=24) windows for external memory transaction.
|
||||
When a transaction passes through the IOB, its address is compared to each of
|
||||
the enabled windows. If there is a hit and it passes the security checks, it is
|
||||
advanced to the target port.
|
||||
|
||||
Mandatory functions
|
||||
-------------------
|
||||
|
||||
- marvell_get_iob_memory_map
|
||||
Returns the IOB windows configuration and the number of windows
|
||||
|
||||
Mandatory structures
|
||||
--------------------
|
||||
|
||||
- iob_memory_map
|
||||
Array that includes the configuration of the windows. Every window/entry is
|
||||
a struct which has 3 parameters:
|
||||
|
||||
- Base address of the window
|
||||
- Size of the window
|
||||
- Target-ID of the window
|
||||
|
||||
Target ID options
|
||||
-----------------
|
||||
|
||||
- **0x0** = Internal configuration space
|
||||
- **0x1** = MCI0
|
||||
- **0x2** = PEX1_X1
|
||||
- **0x3** = PEX2_X1
|
||||
- **0x4** = PEX0_X4
|
||||
- **0x5** = NAND flash
|
||||
- **0x6** = RUNIT (NOR/SPI/BootRoom)
|
||||
- **0x7** = MCI1
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
.. code:: c
|
||||
|
||||
struct addr_map_win iob_memory_map[] = {
|
||||
{0x00000000f7000000, 0x0000000001000000, PEX1_TID}, /* PEX1_X1 window */
|
||||
{0x00000000f8000000, 0x0000000001000000, PEX2_TID}, /* PEX2_X1 window */
|
||||
{0x00000000f6000000, 0x0000000001000000, PEX0_TID}, /* PEX0_X4 window */
|
||||
{0x00000000f9000000, 0x0000000001000000, NAND_TID} /* NAND window */
|
||||
};
|
||||
158
arm-trusted-firmware/docs/plat/marvell/armada/porting.rst
Normal file
158
arm-trusted-firmware/docs/plat/marvell/armada/porting.rst
Normal file
@@ -0,0 +1,158 @@
|
||||
TF-A Porting Guide for Marvell Platforms
|
||||
========================================
|
||||
|
||||
This section describes how to port TF-A to a customer board, assuming that the
|
||||
SoC being used is already supported in TF-A.
|
||||
|
||||
|
||||
Source Code Structure
|
||||
---------------------
|
||||
|
||||
- The customer platform specific code shall reside under ``plat/marvell/armada/<soc family>/<soc>_cust``
|
||||
(e.g. 'plat/marvell/armada/a8k/a7040_cust').
|
||||
- The platform name for build purposes is called ``<soc>_cust`` (e.g. ``a7040_cust``).
|
||||
- The build system will reuse all files from within the soc directory, and take only the porting
|
||||
files from the customer platform directory.
|
||||
|
||||
Files that require porting are located at ``plat/marvell/armada/<soc family>/<soc>_cust`` directory.
|
||||
|
||||
|
||||
Armada-70x0/Armada-80x0 Porting
|
||||
-------------------------------
|
||||
|
||||
SoC Physical Address Map (marvell_plat_config.c)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This file describes the SoC physical memory mapping to be used for the CCU,
|
||||
IOWIN, AXI-MBUS and IOB address decode units (Refer to the functional spec for
|
||||
more details).
|
||||
|
||||
In most cases, using the default address decode windows should work OK.
|
||||
|
||||
In cases where a special physical address map is needed (e.g. Special size for
|
||||
PCIe MEM windows, large memory mapped SPI flash...), then porting of the SoC
|
||||
memory map is required.
|
||||
|
||||
.. note::
|
||||
For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please
|
||||
refer to the SoC functional spec, and under
|
||||
``docs/plat/marvell/armada/misc/mvebu-[ccu/iob/amb/io-win].rst`` files.
|
||||
|
||||
boot loader recovery (marvell_plat_config.c)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
- Background:
|
||||
|
||||
Boot rom can skip the current image and choose to boot from next position if a
|
||||
specific value (``0xDEADB002``) is returned by the ble main function. This
|
||||
feature is used for boot loader recovery by booting from a valid flash-image
|
||||
saved in next position on flash (e.g. address 2M in SPI flash).
|
||||
|
||||
Supported options to implement the skip request are:
|
||||
- GPIO
|
||||
- I2C
|
||||
- User defined
|
||||
|
||||
- Porting:
|
||||
|
||||
Under marvell_plat_config.c, implement struct skip_image that includes
|
||||
specific board parameters.
|
||||
|
||||
.. warning::
|
||||
To disable this feature make sure the struct skip_image is not implemented.
|
||||
|
||||
- Example:
|
||||
|
||||
In A7040-DB specific implementation
|
||||
(``plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c``), the image skip is
|
||||
implemented using GPIO: mpp 33 (SW5).
|
||||
|
||||
Before resetting the board make sure there is a valid image on the next flash
|
||||
address:
|
||||
|
||||
-tftp [valid address] flash-image.bin
|
||||
-sf update [valid address] 0x2000000 [size]
|
||||
|
||||
Press reset and keep pressing the button connected to the chosen GPIO pin. A
|
||||
skip image request message is printed on the screen and boot rom boots from the
|
||||
saved image at the next position.
|
||||
|
||||
DDR Porting (dram_port.c)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
This file defines the dram topology and parameters of the target board.
|
||||
|
||||
The DDR code is part of the BLE component, which is an extension of ARM Trusted
|
||||
Firmware (TF-A).
|
||||
|
||||
The DDR driver called mv_ddr is released separately apart from TF-A sources.
|
||||
|
||||
The BLE and consequently, the DDR init code is executed at the early stage of
|
||||
the boot process.
|
||||
|
||||
Each supported platform of the TF-A has its own DDR porting file called
|
||||
dram_port.c located at ``atf/plat/marvell/armada/a8k/<platform>/board`` directory.
|
||||
|
||||
Please refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed
|
||||
porting description.
|
||||
|
||||
The build target directory is "build/<platform>/release/ble".
|
||||
|
||||
Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
- Background:
|
||||
Some of the comphy's parameters value depend on the HW connection between
|
||||
the SoC and the PHY. Every board type has specific HW characteristics like
|
||||
wire length. Due to those differences some comphy parameters vary between
|
||||
board types. Therefore each board type can have its own list of values for
|
||||
all relevant comphy parameters. The PHY porting layer specifies which
|
||||
parameters need to be suited and the board designer should provide relevant
|
||||
values.
|
||||
|
||||
The PHY porting layer simplifies updating static values per board type,
|
||||
which are now grouped in one place.
|
||||
|
||||
.. note::
|
||||
The parameters for the same type of comphy may vary even for the same
|
||||
board type, it is because the lanes from comphy-x to some PHY may have
|
||||
different HW characteristic than lanes from comphy-y to the same
|
||||
(multiplexed) or other PHY.
|
||||
|
||||
- Porting:
|
||||
The porting layer for PHY was introduced in TF-A. There is one file
|
||||
``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the
|
||||
defaults. Those default parameters are used only if there is no appropriate
|
||||
phy-porting-layer.h file under: ``plat/marvell/armada/<soc
|
||||
family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h
|
||||
exists, the phy-default-porting-layer.h is not going to be included.
|
||||
|
||||
.. warning::
|
||||
Not all comphy types are already reworked to support the PHY porting
|
||||
layer, currently the porting layer is supported for XFI/SFI and SATA
|
||||
comphy types.
|
||||
|
||||
The easiest way to prepare the PHY porting layer for custom board is to copy
|
||||
existing example to a new platform:
|
||||
|
||||
- cp ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/armada/<soc family>/<platform>/board/phy-porting-layer.h"
|
||||
- adjust relevant parameters or
|
||||
- if different comphy index is used for specific feature, move it to proper table entry and then adjust.
|
||||
|
||||
.. note::
|
||||
The final table size with comphy parameters can be different, depending
|
||||
on the CP module count for given SoC type.
|
||||
|
||||
- Example:
|
||||
Example porting layer for armada-8040-db is under:
|
||||
``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h``
|
||||
|
||||
.. note::
|
||||
If there is no PHY porting layer for new platform (missing
|
||||
phy-porting-layer.h), the default values are used
|
||||
(drivers/marvell/comphy/phy-default-porting-layer.h) and the user is
|
||||
warned:
|
||||
|
||||
.. warning::
|
||||
"Using default comphy parameters - it may be required to suit them for
|
||||
your board".
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user