Updating prebuilts and/or headers

600af606544528acefdcda1ac9360385c7fb445e - nvbuild.sh
ad7dc8da66a1a95925c5d25352922f3878707e31 - nvcommon_build.sh
0907bfcdbb17c8012151b65666827033c895982c - arm-trusted-firmware.t234/package-lock.json
0014850d17c6d073452c1de344bf3e5e48c3ff1a - arm-trusted-firmware.t234/Makefile
7f3fadaf80e3c4745d24cb1a5881c7c5f4d898ba - arm-trusted-firmware.t234/.checkpatch.conf
584715f8f3c3f87ea97b9b3da77cdc7c576262bc - arm-trusted-firmware.t234/.nspect-allowlist.toml
ace10cf6c86db4d397dce5eb15be3904f60c70f9 - arm-trusted-firmware.t234/.readthedocs.yaml
e7b6512c235c4956d5e5c54a1bba110101ee7219 - arm-trusted-firmware.t234/poetry.lock
3b07f1cc18499c3a94f20780855567ecbb2406a0 - arm-trusted-firmware.t234/.commitlintrc.js
4bdcaddad6efc78faa2c744a8179fe2b722d1745 - arm-trusted-firmware.t234/readme.rst
58ac0e2c4882938ac294f7180d8d372c1a23c60c - arm-trusted-firmware.t234/.versionrc.cjs
4a2bf00f1f07dd12abeef076606cbbb954f22aa8 - arm-trusted-firmware.t234/package.json
459346b6306a9ab8abdbbc9bab327a65d5c0bd4a - arm-trusted-firmware.t234/.cz-adapter.cjs
2d62a7583b85631859c4143f08e0dc332e1cb87e - arm-trusted-firmware.t234/.gitreview
96d71bc7e0063a06f7a82508b968b73a54857d0d - arm-trusted-firmware.t234/.editorconfig
6b4f543445bf3b97440b6828e63b2efae8cc5d48 - arm-trusted-firmware.t234/pyproject.toml
d8da3627085908a5f974b45528b85dc0a41a8b75 - arm-trusted-firmware.t234/license.rst
c5b6edb1f19eb7b57761adc898d9906ccf9f5593 - arm-trusted-firmware.t234/OWNERS
dcbcc9dad91ad237daae72ab81613fa540d989ec - arm-trusted-firmware.t234/.cz.json
b509c8a6f834e67a07b5eb787d0c2f5e7c8f0ab7 - arm-trusted-firmware.t234/.ctags
693d8edcd6f6e57cb33293e518fc9f017e953dc8 - arm-trusted-firmware.t234/.nvmrc
89e8f1fd50ac707f0dcb450575a69bf86eba15d7 - arm-trusted-firmware.t234/changelog.yaml
c16e3571ab87b0ea9f8067989a5b0f97251ff8cb - arm-trusted-firmware.t234/lib/libfdt/fdt_wip.c
ea823073be5d673a06dfad272a7582df4482b150 - arm-trusted-firmware.t234/lib/libfdt/fdt_ro.c
fdf423cffe52c2e918c815f60c8bea0d7f7c8d70 - arm-trusted-firmware.t234/lib/libfdt/fdt_overlay.c
d2dc4f22a3f4d18e90f3c200fc9236e910900b67 - arm-trusted-firmware.t234/lib/libfdt/fdt_rw.c
0c0bc4ae346c1591ec8aa09a444d3aeaa3d210fb - arm-trusted-firmware.t234/lib/libfdt/fdt.c
e01b7a0052b837a4650f2c9ac75ad38c40edc583 - arm-trusted-firmware.t234/lib/libfdt/fdt_empty_tree.c
1888e43d0d65ec169628a14ff94eb9d06adb47b2 - arm-trusted-firmware.t234/lib/libfdt/fdt_strerror.c
71e3b9e723c948c08594cfa38c65a708d0ab7f88 - arm-trusted-firmware.t234/lib/libfdt/fdt_sw.c
a9e7388adeea4bb813155c62caacc545e9e98bfc - arm-trusted-firmware.t234/lib/libfdt/libfdt_internal.h
282524cbc0a8f7d16c36b9954bb4fad4c0d76c0a - arm-trusted-firmware.t234/lib/libfdt/fdt_addresses.c
90037639cf8fb4c81695f9d8aa4f15ee05af1b0d - arm-trusted-firmware.t234/lib/pmf/pmf_main.c
748a73855a307a23e9042a2467fd508bcc7e2719 - arm-trusted-firmware.t234/lib/pmf/pmf_smc.c
8102f862edb5ab07783993999c8781385e261628 - arm-trusted-firmware.t234/lib/debugfs/dev.c
78982645d4d3008984c9307ee68bfa8eeb1a43a7 - arm-trusted-firmware.t234/lib/debugfs/blobs.h
db9f0e301c7178c315a1c6e72358bae572ce85db - arm-trusted-firmware.t234/lib/debugfs/devfip.c
678b679be4c3816d85eb8d851b7f46b7393739a2 - arm-trusted-firmware.t234/lib/debugfs/debugfs_smc.c
9802d55cbbaff09010b37afad6d494d8e755eae2 - arm-trusted-firmware.t234/lib/debugfs/devroot.c
5260672b27f35a4368d3be1f6ee66ec91d4beb26 - arm-trusted-firmware.t234/lib/debugfs/dev.h
7c85c537adcb24f5e03d6c71424a2618815086e3 - arm-trusted-firmware.t234/lib/debugfs/devc.c
b686543bed166afb322167276d451afec04adc59 - arm-trusted-firmware.t234/lib/romlib/Makefile
481822cc2e7c15342af97aee4d6a88357f33ef86 - arm-trusted-firmware.t234/lib/romlib/romlib_generator.py
eb057f1c025e3c00715bfc73c35c4550fba204ce - arm-trusted-firmware.t234/lib/romlib/jmptbl.i
84d815be083f637cd9f96c31d1fddf3042e11b9a - arm-trusted-firmware.t234/lib/romlib/romlib.ld.S
d558c9ec1044a052e3ae32d32fa5e185b31bc800 - arm-trusted-firmware.t234/lib/romlib/gen_combined_bl1_romlib.sh
bb10bb4fd88d1ee33bbcbdc3fe783aeea6421835 - arm-trusted-firmware.t234/lib/romlib/init.s
b022feb15f3e84d4eefd318657af38a3a523e363 - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_entry_function_bti.S
56fc8c8a2950a0303783ced6bd0e388176043a47 - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_entry_function.S
0e6c307caa236b447ebce1b8530688dc19799210 - arm-trusted-firmware.t234/lib/romlib/templates/wrapper_bti.S
91d0e6f060cd659ba73d0db8886497a823814c65 - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_entry_reserved_bti.S
fa26b89e848f7affd6fd3be71153b55961fbf971 - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_glob_var.S
8bd9f16af17fc4a81e921654d50217d6ba334d4f - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_header.S
f9c9050fd5c89b246d718f406a9d9a13f3388a5e - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_entry_reserved.S
0598d43a54d46872be6b5e9f5a8b45597813d4ae - arm-trusted-firmware.t234/lib/romlib/templates/wrapper.S
18fdfde595d6c7a6409f3d91382d81f736bf775d - arm-trusted-firmware.t234/lib/fconf/fconf_mpmm_getter.c
eb04a6d9ab9c6c79abc707068733945ca7ea49e4 - arm-trusted-firmware.t234/lib/fconf/fconf_dyn_cfg_getter.c
792d27179cb94886b8e3d403c6e11c05bdda0a57 - arm-trusted-firmware.t234/lib/fconf/fconf_cot_getter.c
a56e2c964f2491dc1846e59e1e802dcb4e62944e - arm-trusted-firmware.t234/lib/fconf/fconf.c
9ad7e79093e5a9eee5c2b34fbfcef507564686b9 - arm-trusted-firmware.t234/lib/fconf/fconf_tbbr_getter.c
3567bc768ff2f143e4933244eb221b010bd91f80 - arm-trusted-firmware.t234/lib/fconf/fconf_amu_getter.c
cb401a0f792df9b95c613f8dbc7bd40e4a954578 - arm-trusted-firmware.t234/lib/locks/exclusive/aarch64/spinlock.S
5578b09675f79e87026c64d8253ca469bed1c0da - arm-trusted-firmware.t234/lib/locks/exclusive/aarch32/spinlock.S
db66c79ee8bc7db859a7db3b8cdf21b572da1798 - arm-trusted-firmware.t234/lib/locks/bakery/bakery_lock_normal.c
c2b314d067fb125f7d7f77f2ad93b06398c43238 - arm-trusted-firmware.t234/lib/locks/bakery/bakery_lock_coherent.c
121d77395255b9b8a1089ac9f257e5123271a4a2 - arm-trusted-firmware.t234/lib/extensions/pmuv3/aarch64/pmuv3.c
c224a46a1b416397b079caa7481121ed6d03a41f - arm-trusted-firmware.t234/lib/extensions/pmuv3/aarch32/pmuv3.c
7b10cd2b968063a4101c0e4252133a1059d29904 - arm-trusted-firmware.t234/lib/extensions/mpam/mpam.c
38ababf4127a1ac92a31f9485dfd42fc17c66fde - arm-trusted-firmware.t234/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
4fc0f4b3fea6016c5d47f226751b006e7a17bc58 - arm-trusted-firmware.t234/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
19408c082672877fc4e00dc3281cc2de4162fe20 - arm-trusted-firmware.t234/lib/extensions/sve/sve.c
69b9b55a68a218bedfb7e02f5620c395cfee184f - arm-trusted-firmware.t234/lib/extensions/trbe/trbe.c
48250a5aa4f7c0033c2614e34a070c2e85615896 - arm-trusted-firmware.t234/lib/extensions/spe/spe.c
ebe5066f50de32f019ea11419b6ef11da4604812 - arm-trusted-firmware.t234/lib/extensions/pauth/pauth_helpers.S
3c13274221c18d09899b7e8d8be37e88e2adba23 - arm-trusted-firmware.t234/lib/extensions/tcr/tcr2.c
dfebf62e45987649a709947042771374f897ccb1 - arm-trusted-firmware.t234/lib/extensions/sme/sme.c
6c920523169ecc73baa0b1836746513d12e87ee4 - arm-trusted-firmware.t234/lib/extensions/debug/debugv8p9.c
03582f2ba83c81eb87dadb3331f89bd1eb2db334 - arm-trusted-firmware.t234/lib/extensions/trf/aarch64/trf.c
bc3797c909ca4ec52ec4784ab67d73e9096a351e - arm-trusted-firmware.t234/lib/extensions/trf/aarch32/trf.c
1ee17fe9c431bda9d612efde5b701a6e51665f5c - arm-trusted-firmware.t234/lib/extensions/sysreg128/sysreg128.S
f063c227afb0e9bcf6c77f5a85108129438106c2 - arm-trusted-firmware.t234/lib/extensions/brbe/brbe.c
df6d90a9554d7a2e8872622c900dd69db242efad - arm-trusted-firmware.t234/lib/extensions/fgt/fgt2.c
1af38f4d9fcd54c0328c896c8b154ee6f996728c - arm-trusted-firmware.t234/lib/extensions/amu/amu_private.h
b7c59535736596f6c096a74b33ecc50269cf6d8d - arm-trusted-firmware.t234/lib/extensions/amu/aarch64/amu.c
f97f9c6e3eeb0054517b2b9f0758a32468a9a9f3 - arm-trusted-firmware.t234/lib/extensions/amu/aarch64/amu_helpers.S
8d9a850eda16f822a2da9e30317ebd0eac347311 - arm-trusted-firmware.t234/lib/extensions/amu/aarch32/amu.c
2d632b20837314c97922e2f7a2156de2cde88c8b - arm-trusted-firmware.t234/lib/extensions/amu/aarch32/amu_helpers.S
9bbf285e5fb015b4281d9989bf1f5cdefe96cec0 - arm-trusted-firmware.t234/lib/extensions/fpmr/fpmr.c
ad3316abca20d34d7293aac76cbfc64ce9a5c012 - arm-trusted-firmware.t234/lib/extensions/ras/std_err_record.c
4616f57dc89bb192f724bb4d34ae9e7f516e4b8a - arm-trusted-firmware.t234/lib/extensions/ras/ras_common.c
2e0b4a8eb4d69373e109f9be1a02cc409b3b9068 - arm-trusted-firmware.t234/lib/el3_runtime/simd_ctx.c
9a20231094ee9cab4a2435987bdc2aebcf9b89dd - arm-trusted-firmware.t234/lib/el3_runtime/cpu_data_array.c
925b7522c8a43da8c48b93d665e4f89b18059b4d - arm-trusted-firmware.t234/lib/el3_runtime/aarch64/context.S
7823e00fc8ac59a91343911721874f34edaee500 - arm-trusted-firmware.t234/lib/el3_runtime/aarch64/context_mgmt.c
b248c2857449f37281505ffc12499e7ce94f2ee8 - arm-trusted-firmware.t234/lib/el3_runtime/aarch64/cpu_data.S
d19f573e44d900281f2785adec1a4c5369b328e7 - arm-trusted-firmware.t234/lib/el3_runtime/aarch64/context_debug.c
a7d92facc0752c0840fcbee6f90f691658918f04 - arm-trusted-firmware.t234/lib/el3_runtime/aarch32/context_mgmt.c
dcb9b7147ff211c4c3bfc81afa41e26753797fe1 - arm-trusted-firmware.t234/lib/el3_runtime/aarch32/cpu_data.S
06f4bc9f41eeaa4be122a19cd6ff5105ff5b3666 - arm-trusted-firmware.t234/lib/psa/measured_boot_private.h
b577cd6b4f9481795aa38bdba16a06d556c005cd - arm-trusted-firmware.t234/lib/psa/rse_platform.c
eee36c863935c30bfe8c8d97e575bf298df49235 - arm-trusted-firmware.t234/lib/psa/dice_protection_environment.c
be57ec731ef978a1cb592ddcd54df181cf3854bd - arm-trusted-firmware.t234/lib/psa/cca_attestation.c
98ec93022cebd1d2bfafa3f6f1754aac502f039e - arm-trusted-firmware.t234/lib/psa/delegated_attestation.c
ded7da36471dba8afc5a2ee5c7cd83017358a01a - arm-trusted-firmware.t234/lib/psa/measured_boot.c
461f0e6549aecb25a42e26daa4990367b0c0349e - arm-trusted-firmware.t234/lib/stack_protector/stack_protector.c
4f46a17dd2d45cbfecc56cdc62335d16e7f8e9fd - arm-trusted-firmware.t234/lib/stack_protector/aarch64/asm_stack_protector.S
2a002a927728f82056d756fb1887d05d85bc76f1 - arm-trusted-firmware.t234/lib/stack_protector/aarch32/asm_stack_protector.S
5c0d29046bc86d69be79a8f490d15c6278e7c1bf - arm-trusted-firmware.t234/lib/xlat_tables/xlat_tables_common.c
ada03d858deab4a12708645a227784e1380cc81a - arm-trusted-firmware.t234/lib/xlat_tables/xlat_tables_private.h
bb74aa53a76cf8da53b1247c526a828eda4a1792 - arm-trusted-firmware.t234/lib/xlat_tables/aarch64/xlat_tables.c
6f6a68d4d740fe29efffe15b3f231637931603ca - arm-trusted-firmware.t234/lib/xlat_tables/aarch32/xlat_tables.c
35355a9c23c311ebb37e6654a0310fa8a186fd42 - arm-trusted-firmware.t234/lib/xlat_tables/aarch32/nonlpae_tables.c
1d272a148f99cc5bfa1d9d1f1d557138b845eb09 - arm-trusted-firmware.t234/lib/bl_aux_params/bl_aux_params.c
621d91c2abfb7ec906a3341bb6849212c0972fe0 - arm-trusted-firmware.t234/lib/semihosting/semihosting.c
1d3c306a7abd961df54876afd2f68397653a722d - arm-trusted-firmware.t234/lib/semihosting/aarch64/semihosting_call.S
96e457fca8175f03f288deb171768f7d390a2d85 - arm-trusted-firmware.t234/lib/semihosting/aarch32/semihosting_call.S
972bcfa9e5506820069f2681ecfc8724e161857c - arm-trusted-firmware.t234/lib/aarch64/cache_helpers.S
2c301ef78cf219d3946f1a0d8dea0fbb66b8710c - arm-trusted-firmware.t234/lib/aarch64/misc_helpers.S
7514c02332a91f81b01c38fab0c57628b5a1552e - arm-trusted-firmware.t234/lib/aarch64/armclang_printf.S
2935ae164681477772e886442e2e1addcfbb2157 - arm-trusted-firmware.t234/lib/libc/putchar.c
571f090fbb81f922731ecd747dc426eb612ec25b - arm-trusted-firmware.t234/lib/libc/strlen.c
edb57dde15d3376a064cceb642c2c2ea6cfc5659 - arm-trusted-firmware.t234/lib/libc/assert.c
82f54f160965b93a70dc958c51a0328ae0540956 - arm-trusted-firmware.t234/lib/libc/strncmp.c
b09d8dfbbff3c2a148e2323a97e5db8c3b864bab - arm-trusted-firmware.t234/lib/libc/memcmp.c
ecdb0573af2e72655f16bf065fbb5efe33c7cfbd - arm-trusted-firmware.t234/lib/libc/snprintf.c
be9487ae2df331c4b6d1e8eb831fe36f80300829 - arm-trusted-firmware.t234/lib/libc/strlcpy.c
ffb9b36696d1be240d6c300924b1b16f8b7d193a - arm-trusted-firmware.t234/lib/libc/memcpy.c
38a578098af152b953ec1c824f1abd335b84979e - arm-trusted-firmware.t234/lib/libc/abort.c
c72f1f1842a78fb427805c7447d370fc148dc89f - arm-trusted-firmware.t234/lib/libc/strtoul.c
8f8edbf780871676227a4f4130b3a9c718b3c64c - arm-trusted-firmware.t234/lib/libc/strcmp.c
da2d6f3d96f3b941a06349c46b943cce37ac6a6e - arm-trusted-firmware.t234/lib/libc/memchr.c
bacec6dd7a3b9e28603e5cfd058756eab0f892af - arm-trusted-firmware.t234/lib/libc/memmove.c
c09671253fa56542c6aa0c9bb84abbd6e6b2306d - arm-trusted-firmware.t234/lib/libc/memcpy_s.c
8c9668a348c3ffbe4509aa2246941450a7b0de00 - arm-trusted-firmware.t234/lib/libc/strtoll.c
359ff50d6cb3845b71124e0ca9942745bda9e2c5 - arm-trusted-firmware.t234/lib/libc/memset.c
8172487e3b3f801cb06d4e60707f53c4d77b483f - arm-trusted-firmware.t234/lib/libc/strchr.c
07dbfb512cae53c03504d60ec4b02bfc74c2af8a - arm-trusted-firmware.t234/lib/libc/strtol.c
82032c79de7b24a84341c8bd5d72baba75337f1e - arm-trusted-firmware.t234/lib/libc/strtoull.c
6d62f8972d334e9b7016abfa5fd60039fd045392 - arm-trusted-firmware.t234/lib/libc/strlcat.c
c64e54b9d37e79c6a5ddf5440518980b4d8023d6 - arm-trusted-firmware.t234/lib/libc/strrchr.c
06782e2bb8b5e2b70cd089f061be9c1a08621523 - arm-trusted-firmware.t234/lib/libc/memrchr.c
e7eb31dbd9893d98f8ab6cbef6a11143aa052581 - arm-trusted-firmware.t234/lib/libc/strtok.c
b4e1859698344300f46b5b4523efb8e7a22c5e3d - arm-trusted-firmware.t234/lib/libc/printf.c
9004bf8bc547abf250c43d48b20ee66119a0f325 - arm-trusted-firmware.t234/lib/libc/exit.c
cdc60a84cbcd4ae8a4fd73df6250ad538db0668a - arm-trusted-firmware.t234/lib/libc/strnlen.c
83b77c3ae8eca3bf7da4de83d82fa7b0edeff85a - arm-trusted-firmware.t234/lib/libc/puts.c
02977fbcda3d55ed39cafa721d2bd2a901f0c637 - arm-trusted-firmware.t234/lib/libc/aarch64/memset.S
e450aea2c775f055c707f053de39e7aa7ed66223 - arm-trusted-firmware.t234/lib/libc/aarch64/setjmp.S
75786d0b78f57474b1c6f960b2c8ecbc07ba830b - arm-trusted-firmware.t234/lib/libc/aarch32/memset.S
14efe65532640ad904e16c0fcfdf2a0aa8ef7892 - arm-trusted-firmware.t234/lib/aarch32/cache_helpers.S
ee1a450f356e424a2bf60417432806e1c48e8b4b - arm-trusted-firmware.t234/lib/aarch32/misc_helpers.S
f3656db9134aa2171dd45f1a9678477dd7cd96e0 - arm-trusted-firmware.t234/lib/aarch32/armclang_printf.S
e99b439f92ab3e8025a95af724ddbf92e03bf8cb - arm-trusted-firmware.t234/lib/aarch32/arm32_aeabi_divmod.c
65adc9dcdcfda338ac28944b6d78e9022351ce50 - arm-trusted-firmware.t234/lib/aarch32/arm32_aeabi_divmod_a32.S
f19e7e7ffa2bd22a6e1d0cceeca043d433fa6681 - arm-trusted-firmware.t234/lib/cpus/errata_common.c
151b3b0184be16c7d540dc87a99bccaf4801776a - arm-trusted-firmware.t234/lib/cpus/errata_report.c
6f1b0a8a7e18b98e1d7cc25071e370266244a0b6 - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_x2.S
6460b029250d2f405f1b9e625811dde8aba049e1 - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_arcadia.S
bac60e2cdc71bd54539af3a40b00694b853b6833 - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_a710.S
773c971c7fab4197843edb566f6a123d7f53fa54 - arm-trusted-firmware.t234/lib/cpus/aarch64/nevis.S
80f25f36b7c8160af1b67386572ac6649901344e - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_x4.S
5a3fca8ad8ae38716f40b2ebc56014b27be7d133 - arm-trusted-firmware.t234/lib/cpus/aarch64/neoverse_v1.S
a7d88cc794b4858c93c50a30de80da12e8f69118 - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_a715.S
fd801851b71a05fbc5920f6815d5ab8025a7f156 - arm-trusted-firmware.t234/lib/cpus/aarch64/cpuamu.c
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222366fd88fa37c34896b96be4724020febaf122 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h
9cfa6b80558dac90724c830c7c2b792099232962 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld.S
249a2bba707f4aae60e76e4d2ca07180426f3657 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/m0/src/stopwatch.c
3832f35bf0192ab6299ed6f72d97ea798c64ec01 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/m0/src/dram.c
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912b3ac53149ee0912cdc571503cbe6f5d9e5e31 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/pwm/pwm.h
81bb90565c30ebb1d2a2074e665099c5df4b3f16 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/pwm/pwm.c
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1c5f6ab9e0780ba09fc4009303d8f48ca69ba0d0 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c
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341cf7780e76c0eed9bb587ced84821148eaeba4 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
27aa9609a5b7f4a133b52b7f298cef95b6b1332a - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/dram/suspend.c
8524ea750c376402a2c507655783fb69d6ca49af - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/soc/soc.c
d6f6a92953b02dda92949d05699b4a8c09ec1ab6 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/soc/soc.h
ef5a8ce281d95041b91f8f165ef782642d022de2 - arm-trusted-firmware.t234/plat/rockchip/px30/px30_def.h
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1b86970e6e211ba1548f3469a4682db7c31577f1 - arm-trusted-firmware.t234/plat/amlogic/common/aml_mhu.c
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2321fbf75d8e96d90a1b6f6a14160c91b949cabc - arm-trusted-firmware.t234/plat/amlogic/common/aml_scpi.c
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887d16c962bbfdec5ddb366c33ffec0ad5697447 - arm-trusted-firmware.t234/plat/amlogic/common/aml_thermal.c
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03a70925292deabd473bf5ffcd0d0d95dd70456e - arm-trusted-firmware.t234/plat/amlogic/g12a/g12a_pm.c
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495f096204283e82b03abed56414e3d1a29f9b6f - arm-trusted-firmware.t234/plat/amlogic/g12a/g12a_def.h
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3389361e87f5cd5e4f7e606599032c3aa3a41b72 - arm-trusted-firmware.t234/plat/amlogic/gxbb/gxbb_def.h
25d4db1b1e385a2e45f4ffea43edbfc8bf4fef89 - arm-trusted-firmware.t234/plat/amlogic/gxbb/gxbb_common.c
704885551348b4b44d9b7b092aafc3c54533b7e0 - arm-trusted-firmware.t234/plat/amlogic/gxbb/gxbb_bl31_setup.c
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550ec6753c2e8a5f41a920ea9bfffec47ae78dc8 - arm-trusted-firmware.t234/plat/amlogic/gxl/gxl_bl31_setup.c
5ce07f2865d514a3a8979c638337a338fa110f74 - arm-trusted-firmware.t234/plat/amlogic/gxl/gxl_pm.c
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22603b51918b7c1f721eee33d26629b16cff6683 - arm-trusted-firmware.t234/plat/amlogic/gxl/include/platform_def.h
0daa3a8c1ed607bfafc9ba0daa93d2de60c3c19e - arm-trusted-firmware.t234/plat/rpi/rpi5/rpi5_setup.c
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46c13e3cff3d9c29a733d01629589bd31b37eb5e - arm-trusted-firmware.t234/plat/rpi/common/rpi3_stack_protector.c
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42b3bec4b29977924bd7bf3da9ec372d1ec2dcd4 - arm-trusted-firmware.t234/plat/rpi/common/rpi3_console_dual.c
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6362652e60de8bcc5d723a13459a55c254c8d476 - arm-trusted-firmware.t234/plat/rpi/common/rpi3_console_pl011.c
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cd6861322dab161ff32b161e169f6666527d7c58 - arm-trusted-firmware.t234/plat/rpi/common/include/plat_macros.S
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cc26f2aa2450e40b407d6c6cf3b2930941104a04 - arm-trusted-firmware.t234/plat/rpi/rpi3/include/platform_def.h
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0c2b99bf230517b6436b54afd86f9249a3276d76 - arm-trusted-firmware.t234/plat/xilinx/versal_net/sip_svc_setup.c
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3d01d365783ad5b2ce0f76df72a4a10db3d9a10d - arm-trusted-firmware.t234/plat/nvidia/tegra/soc/t234/plat_memctrl.c
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c2cd522ab9668274cd7bf26fde63e9dbc9a94f28 - arm-trusted-firmware.t234/plat/nvidia/tegra/soc/t234/plat_secondary.c
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5c0dff5a31ce3b1ccbb934f961c94488e994ba83 - arm-trusted-firmware.t234/plat/nvidia/tegra/soc/t194/plat_ras.c
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41b9c96e4ffd9d51ef07345b13dbf173adf98260 - arm-trusted-firmware.t234/plat/ti/k3/common/k3_console.c
03c91a4b96c78e27b3534215550a85d2baef4a60 - arm-trusted-firmware.t234/plat/ti/k3/common/k3_bl31_setup.c
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65543dc7d9a840040d346b740384936551691526 - arm-trusted-firmware.t234/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
1cc8b5048759dec0cddaaca704360a5e02ff0387 - arm-trusted-firmware.t234/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
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c972344f8497be61b5561d1cf3e16a3a5d065403 - arm-trusted-firmware.t234/plat/ti/k3/board/lite/include/board_def.h
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dd19c5d97b6fda42cdf7822b9932b2c6bb7999de - arm-trusted-firmware.t234/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
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3dde76eb498c889851714b3d8e6749211c62bbec - arm-trusted-firmware.t234/plat/allwinner/sun50i_h6/include/sunxi_spc.h
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03001e5fa23515aba0765c130aad123367758776 - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/sunxi_h616_dtb.c
597c7d0e25492053936d68d62e433724f752b395 - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/sunxi_power.c
5f9c46257fffc11bc9cc33e4857e303df4ef68cb - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
3aedc81b7dac5e568253b5f0b546617d87eaee95 - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
3dde76eb498c889851714b3d8e6749211c62bbec - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/include/sunxi_spc.h
1590f260f1febbedf931a1596cea2d2e437ea92b - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/include/sunxi_ccu.h
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4fbea1d1c07593e4288cbf95ad006133a753832c - arm-trusted-firmware.t234/plat/allwinner/common/sunxi_pm.c
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704da3ea1b61d5106a6172712ecf6a80b1528bf0 - arm-trusted-firmware.t234/plat/allwinner/common/arisc_off.S
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0ded87657ff47f0fe5896f1ab1d6d2f9b34f0429 - arm-trusted-firmware.t234/plat/allwinner/common/plat_helpers.S
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0f08c32e56a3d49917e94d91f1f5e67ec04f1f8b - arm-trusted-firmware.t234/plat/allwinner/common/sunxi_cpu_ops.c
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1f3580c9b5753f5e99e173cffd6e713bce84d2f4 - arm-trusted-firmware.t234/plat/allwinner/common/include/sunxi_def.h
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3fa3a563994fcf2710324634950265fc8f9d7850 - arm-trusted-firmware.t234/plat/allwinner/sun50i_r329/sunxi_power.c
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1acbdb220cff8edffa7cc7fd4808f71574b90966 - arm-trusted-firmware.t234/plat/allwinner/sun50i_r329/include/sunxi_spc.h
2870bd5728ae0e5857fadde22b048a6fcf6ee2d3 - arm-trusted-firmware.t234/plat/allwinner/sun50i_r329/include/sunxi_ccu.h
33f9c2d61b7aa3242f22100ba2694ba2709f7a1b - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_topology.c
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1b333e35df79afc9319c45ded87fe22b1e5547fc - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_security.c
8b11d0569d254ee10c03b8e7dfaebf823b7b1746 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_bl_common.c
1dc25162c504805b378176ceb2a1fac39b8fa3e2 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_ddr.c
10b56da87c85a4ad254e8e25455c6fc119d4ee23 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_bl31_setup.c
1975a45f73616d0ceb03dab4a9397cbabc1e66ce - arm-trusted-firmware.t234/plat/hisilicon/hikey/hisi_pwrc.c
132b89dc419b19bfabb3eb2450a5e74317faea11 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_io_storage.c
b8ddcea3e66690f3932ae009921566fe249feccd - arm-trusted-firmware.t234/plat/hisilicon/hikey/hisi_pwrc_sram.S
126933334b9ebdde11859016f3bbcc6ac9bbef88 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hisi_mcu.c
0071214b6af7f5e24aa92d4e7849c79c3818ed05 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_bl2_setup.c
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0472150350a0f6a23e8750e0fe14991d176d1a04 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_bl1_setup.c
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5366b77beffc310cab412735a4e4f43185e171c6 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_image_load.c
0aace28e8f75168d13d7274d81f1f906cc1b2cae - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_rotpk.S
3f90b73f27ba47848db784621dd350e6a5ec54d9 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_tbbr.c
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31f012031e8dec3fe5dab7afc9ab89deffb7fe7c - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hi6220_regs_pmctrl.h
98509207554ab836b38f580d203793668061ce40 - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hisi_sip_svc.h
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5da379773f07f291d897ea36a13ac008c78bbbe4 - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hi6220_regs_pin.h
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c54b714045ab12cfcff4363f00ce94952a40e2d6 - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hikey_layout.h
659dfae8f25d18bef4e2ac3c9b2cc07bbd255dd4 - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hi6220_regs_acpu.h
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166469bcfd5bac8ca50e33d23d40607d532f7a9f - arm-trusted-firmware.t234/plat/hisilicon/poplar/bl1_plat_setup.c
942f440e430db3a0fb9bafcb2877fa0f2b2b2206 - arm-trusted-firmware.t234/plat/hisilicon/poplar/plat_topology.c
f74fcf80665ecffb4b4fe3402223e62b707c18ea - arm-trusted-firmware.t234/plat/hisilicon/poplar/bl31_plat_setup.c
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5366b77beffc310cab412735a4e4f43185e171c6 - arm-trusted-firmware.t234/plat/hisilicon/poplar/poplar_image_load.c
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fc3d37d2191841fe6bab5841f4be4e364cf919b1 - arm-trusted-firmware.t234/plat/hisilicon/hikey960/hikey960_io_storage.c
0f1a35cf03c46fa57303de1b14fd3ec9d83d2e72 - arm-trusted-firmware.t234/plat/hisilicon/hikey960/hikey960_bl2_setup.c
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95b3fdae0d8de2d798a10e56f7071e4aa4d3b854 - arm-trusted-firmware.t234/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
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9a52294343831155772b4411f11af6c989dbd182 - arm-trusted-firmware.t234/plat/marvell/armada/a8k/a80x0/mvebu_def.h
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3f6403fd39850e34f4c3bd674ccf8170f74af43d - arm-trusted-firmware.t234/plat/marvell/armada/a8k/common/plat_bl31_setup.c
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392f1834ac5b4679e9ae724c7cf1f3a20c0e566a - arm-trusted-firmware.t234/plat/marvell/armada/a8k/common/mss/mss_bl31_setup.c
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9acdf9fa5a506b13c376584f49b42a4f437af6c5 - arm-trusted-firmware.t234/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
4b2131b48e6b858b49e7e4d819172c5bc729f213 - arm-trusted-firmware.t234/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c
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3f70fd4dd52f090e5e86093abe02a4f90c8f4353 - arm-trusted-firmware.t234/plat/marvell/armada/a3k/common/cm3_system_reset.c
4e66aa51fabafab21b8e01fa4f3d49fc8fe6a97e - arm-trusted-firmware.t234/plat/marvell/armada/a3k/common/a3700_sip_svc.c
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5ce8b4638274f9c66287b2f3662bb0bfcfc00074 - arm-trusted-firmware.t234/plat/marvell/armada/a3k/common/a3700_ea.c
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344f94187e37e08b2f532eb66281e7e28e7702c5 - arm-trusted-firmware.t234/plat/marvell/armada/a3k/common/io_addr_dec.c
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29d5aa4597a4a5d917e61847ae451ff6ab6894d5 - arm-trusted-firmware.t234/plat/arm/common/arm_transfer_list.c
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0ba5633b7ee65a26daba781e30eed64d4238eca8 - arm-trusted-firmware.t234/plat/arm/common/arm_bl1_setup.c
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310f5212c93492a9ca17bbf110947773178b8581 - arm-trusted-firmware.t234/plat/arm/common/fconf/arm_fconf_sp.c
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2147b3c541e549d0bc01f00aed57c924d90d6003 - arm-trusted-firmware.t234/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
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5562bd387d6506e0db4a62fe23b24cd1c5046754 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
151a77208d20281181da91b2119b75c4de526102 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
1e7fe4ccc25d366dfe5f6a14851dab68001bdb13 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/corstone1000_topology.c
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205b4ca0cb05e33669284a62b9c25f52ece1b8e9 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/corstone1000_pm.c
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16e3686521725b2e8cf355c2d990811fc260a02c - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
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70913ecf05a6e846d99d63213b643de746a371e8 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/include/plat_macros.S
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846d7f92ffe6c368d0d0b85ffa36409b0dd04caf - arm-trusted-firmware.t234/plat/arm/board/morello/morello_trusted_boot.c
3fcdf0172f72867955ed0a4642a76273495b9e0e - arm-trusted-firmware.t234/plat/arm/board/morello/morello_def.h
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5457ec463cc8a966e6b179d42b57efbe3129da4b - arm-trusted-firmware.t234/plat/arm/board/morello/morello_bl2_setup.c
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0105670429d8a205bc698cf69de09044501a55a1 - arm-trusted-firmware.t234/plat/arm/board/morello/morello_topology.c
42659a5e25bf580b3f178c1c4fe693c1ff420253 - arm-trusted-firmware.t234/plat/arm/board/morello/morello_bl31_setup.c
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1c3ff5d4d35a2aa211380dea2b252236f3dae0b1 - arm-trusted-firmware.t234/plat/arm/board/morello/aarch64/morello_helper.S
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3d1a55d785180dd11beb8473207268d04543695a - arm-trusted-firmware.t234/plat/arm/board/corstone700/common/corstone700_helpers.S
5f0ac09b373c85fd1d635fb4f06ea45011389b19 - arm-trusted-firmware.t234/plat/arm/board/corstone700/common/corstone700_topology.c
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0fa67a9e3baade23364e588643149159b41d951b - arm-trusted-firmware.t234/plat/arm/board/fvp_r/fvp_r_debug.S
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181e66fa9c41732917a323ee0fe465da3b5ce36d - arm-trusted-firmware.t234/plat/arm/board/fvp_r/fvp_r_stack_protector.c
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5f78d5ae0c4547371279bfc19196f01fb454e3b6 - arm-trusted-firmware.t234/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c
cb1a2983e1ba147d7e3cce2b7b48cd124ba55bd7 - arm-trusted-firmware.t234/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
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25ba9f0211c95d3e0145319f7018f2e2f8d6986c - arm-trusted-firmware.t234/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c
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512907ac88f5504ffcd2a9ea58bc0da3cae848c3 - arm-trusted-firmware.t234/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c
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5a7431e547b27575f2c9ca5a43bd106fd4705ed6 - arm-trusted-firmware.t234/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h
af1f8d5af2ee91ba0dd180c42a7b8f73b7543474 - arm-trusted-firmware.t234/plat/arm/board/fvp_ve/fvp_ve_security.c
4a175994a02eeb79a8ccc76f0b3be5ac2d45771d - arm-trusted-firmware.t234/plat/arm/board/fvp_ve/fvp_ve_private.h
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4a689338afdb70548a3c2d1adce2b5c8c1083e5d - arm-trusted-firmware.t234/plat/arm/board/fvp_ve/include/platform_def.h
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2ff5ebca71b32318bae21e3dbb7699236b9cbe61 - arm-trusted-firmware.t234/plat/arm/board/fvp_ve/aarch32/fvp_ve_helpers.S
1f68f4b41cf660f6aecbd9c91cffd25b5da791a9 - arm-trusted-firmware.t234/plat/arm/board/tc/tc_err.c
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4a9977f4650713d7e5e1dd060919eef4e2b41575 - arm-trusted-firmware.t234/plat/arm/board/tc/nv_counter_test.c
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1be9df9e373623ca11c2f078fb14545de995067b - arm-trusted-firmware.t234/plat/arm/css/common/css_bl2_setup.c
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284a0afe619de982f2bd1d4b1c625831ef7b3b5e - arm-trusted-firmware.t234/bl1/aarch64/bl1_arch_setup.c
095ac3b2483b968f263618a4bd6cdd8d6f66d321 - arm-trusted-firmware.t234/bl1/aarch32/bl1_context_mgmt.c
caf76eacd5e8708391bbf7db7315acad4b89c7fd - arm-trusted-firmware.t234/bl1/aarch32/bl1_entrypoint.S
bea69e37646041aff3c96bf107e1db48f382a1b4 - arm-trusted-firmware.t234/bl1/aarch32/bl1_exceptions.S
8d6e2008e280f848fb14017ba5ba559a10724421 - arm-trusted-firmware.t234/bl1/aarch32/bl1_arch_setup.c
85b2afc44851dc57e79c264641730d0e2eca3016 - arm-trusted-firmware.t234/bl1/tbbr/tbbr_img_desc.c
2c87153926f8a458cffc9a435e15571ba721c2fa - arm-trusted-firmware.t234/licenses/LICENSE.MIT
4b776badf454a3bcf0cc1524d1b63fd9871f6c8c - arm-trusted-firmware.t234/bl2/bl2_el3.ld.S
88bbfcb3f9b827bdab7f16cdfe892b2aa1470576 - arm-trusted-firmware.t234/bl2/bl2_image_load_v2.c
991c05cee7a30247e2edcade94405aef95480121 - arm-trusted-firmware.t234/bl2/bl2_private.h
99df04b45b026a439c20349ab80458e960dfc23c - arm-trusted-firmware.t234/bl2/bl2.ld.S
f9af212975b69e0fe4006e2c0d6ec7d1519c473a - arm-trusted-firmware.t234/bl2/bl2_main.c
62ef4221f56feaf0907dbe17cad47a9bab86bf03 - arm-trusted-firmware.t234/bl2/aarch64/bl2_el3_exceptions.S
777576955f2ae3959035c33791a33835fe6578f4 - arm-trusted-firmware.t234/bl2/aarch64/bl2_rme_entrypoint.S
a34048b4cc67bca14b7594e2c1a53b4c0376d779 - arm-trusted-firmware.t234/bl2/aarch64/bl2_el3_entrypoint.S
c426fa02b617581d2495667828e9430110cf713a - arm-trusted-firmware.t234/bl2/aarch64/bl2_entrypoint.S
247751d71fb2863f439cc217ac18c219dbf15453 - arm-trusted-firmware.t234/bl2/aarch64/bl2_run_next_image.S
776c1699268eee43ba9230cb7e785e298e56a233 - arm-trusted-firmware.t234/bl2/aarch64/bl2_arch_setup.c
44692bdbcbccddc6c4fc022d5028cacb8842376a - arm-trusted-firmware.t234/bl2/aarch32/bl2_el3_exceptions.S
aac463ba1d35408d94f960ade6d2db95d68455ab - arm-trusted-firmware.t234/bl2/aarch32/bl2_el3_entrypoint.S
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f64693060b1ef904b4abfc04b8480a0f458494c5 - arm-trusted-firmware.t234/bl2/aarch32/bl2_run_next_image.S
2534665e628b7612c3896fed4e659f3351601296 - arm-trusted-firmware.t234/bl2/aarch32/bl2_arch_setup.c

Change-Id: I806f8c263557ca545fbd1f91da80741a3e098cbd

arm-trusted-firmware.t234/docs/getting_started/build-internals.rst

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+Internal Build Options
+======================
+
+|TF-A| internally uses certain options that are not exposed directly through
+:ref:`build-options <build options>` but enabled or disabled indirectly and
+depends on certain options to be enabled or disabled.
+
+.. _build_options_internal:
+
+-  ``CTX_INCLUDE_EL2_REGS``: This boolean option provides context save/restore
+   operations when entering/exiting an EL2 execution context. This is of primary
+   interest when Armv8.4-SecEL2 or RME extension is implemented.
+   Default is 0 (disabled). This option will be set to 1 (enabled) when ``SPD=spmd``
+   and ``SPMD_SPM_AT_SEL2`` is set or when ``ENABLE_RME`` is set to 1 (enabled).
+
+- ``FFH_SUPPORT``: This boolean option provides support to enable Firmware First
+  handling (FFH) of External aborts and SError interrupts originating from lower
+  ELs which gets trapped in EL3. This option will be set to 1 (enabled) if
+  ``HANDLE_EA_EL3_FIRST_NS`` is set. Currently only NS world routes EA to EL3 but
+  in future when Secure/Realm wants to use FFH then they can introduce new macros
+  which will enable this option implicitly.
+
+-  ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in
+   tb_fw_config device tree. This flag is defined only when
+   ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp.
+
+-  ``TRUSTY_SP_FW_CONFIG``: DTC build flag to include Trusty as SP in
+   tb_fw_config device tree. This flag is defined only when
+   ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern trusty_sp.

arm-trusted-firmware.t234/docs/getting_started/docs-build.rst

@@ -0,0 +1,131 @@
+Building Documentation
+======================
+
+To create a rendered copy of this documentation locally you can use the
+`Sphinx`_ tool to build and package the plain-text documents into HTML-formatted
+pages.
+
+If you are building the documentation for the first time then you will need to
+check that you have the required software packages, as described in the
+*Prerequisites* section that follows.
+
+.. note::
+   An online copy of the documentation is available at
+   https://www.trustedfirmware.org/docs/tf-a, if you want to view a rendered
+   copy without doing a local build.
+
+Prerequisites
+-------------
+
+For building a local copy of the |TF-A| documentation you will need:
+
+- Python 3 (3.8 or later)
+- PlantUML (1.2017.15 or later)
+- `Poetry`_ (Python dependency manager)
+- Optionally, the `Dia`_ application can be installed if you need to edit
+  existing ``.dia`` diagram files, or create new ones.
+
+
+Below is an example set of instructions to get a working environment (tested on
+Ubuntu):
+
+.. code:: shell
+
+    sudo apt install python3 python3-pip plantuml [dia]
+    curl -sSL https://install.python-poetry.org | python3 -
+
+Building rendered documentation
+-------------------------------
+
+The documentation can be compiled into HTML-formatted pages from the project
+root directory by running:
+
+.. code:: shell
+
+   poetry run make doc
+
+Output from the build process will be placed in: ``docs/build/html``.
+
+Other Output Formats
+~~~~~~~~~~~~~~~~~~~~
+
+We also support building documentation in other formats. From the ``docs``
+directory of the project, run the following command to see the supported
+formats.
+
+.. code:: shell
+
+   poetry run make -C docs help
+
+To build the documentation in PDF format, additionally ensure that the following
+packages are installed:
+
+- FreeSerif font
+- latexmk
+- librsvg2-bin
+- xelatex
+- xindy
+
+Below is an example set of instructions to install the required packages
+(tested on Ubuntu):
+
+.. code:: shell
+
+	sudo apt install fonts-freefont-otf latexmk librsvg2-bin texlive-xetex xindy
+
+Once all the dependencies are installed, run the command ``poetry run make -C
+docs latexpdf`` to build the documentation. Output from the build process
+(``trustedfirmware-a.pdf``) can be found in ``docs/build/latex``.
+
+Building rendered documentation from Poetry's virtual environment
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The command ``poetry run`` used in the steps above executes the input command
+from inside the project's virtual environment. The easiest way to activate this
+virtual environment is with the ``poetry shell`` command.
+
+Running ``poetry shell`` from the directory containing this project, activates
+the same virtual environment. This creates a sub-shell through which you can
+build the documentation directly with ``make``.
+
+.. code:: shell
+
+    poetry shell
+    make doc
+
+Type ``exit`` to deactivate the virtual environment and exit this new shell. For
+other use cases, please see the official `Poetry`_ documentation.
+
+Building rendered documentation from a container
+------------------------------------------------
+
+There may be cases where you can not either install or upgrade required
+dependencies to generate the documents, so in this case, one way to
+create the documentation is through a docker container. The first step is
+to check if `docker`_ is installed in your host, otherwise check main docker
+page for installation instructions. Once installed, run the following script
+from project root directory
+
+.. code:: shell
+
+   docker run --rm -v $PWD:/tf-a sphinxdoc/sphinx \
+        bash -c 'cd /tf-a &&
+            apt-get update && apt-get install -y curl plantuml &&
+            curl -sSL https://install.python-poetry.org | python3 - &&
+            ~/.local/bin/poetry run make doc'
+
+The above command fetches the ``sphinxdoc/sphinx`` container from `docker
+hub`_, launches the container, installs documentation requirements and finally
+creates the documentation. Once done, exit the container and output from the
+build process will be placed in: ``docs/build/html``.
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+
+.. _Sphinx: http://www.sphinx-doc.org/en/master/
+.. _Poetry: https://python-poetry.org/docs/
+.. _pip homepage: https://pip.pypa.io/en/stable/
+.. _Dia: https://wiki.gnome.org/Apps/Dia
+.. _docker: https://www.docker.com/
+.. _docker hub: https://hub.docker.com/repository/docker/sphinxdoc/sphinx

arm-trusted-firmware.t234/docs/getting_started/image-terminology.rst

@@ -0,0 +1,192 @@
+Image Terminology
+=================
+
+This page contains the current name, abbreviated name and purpose of the various
+images referred to in the Trusted Firmware project.
+
+Common Image Features
+---------------------
+
+- Some of the names and abbreviated names have changed to accommodate new
+  requirements. The changed names are as backward compatible as possible to
+  minimize confusion. Where applicable, the previous names are indicated. Some
+  code, documentation and build artefacts may still refer to the previous names;
+  these will inevitably take time to catch up.
+
+- The main name change is to prefix each image with the processor it corresponds
+  to (for example ``AP_``, ``SCP_``, ...). In situations where there is no
+  ambiguity (for example, within AP specific code/documentation), it is
+  permitted to omit the processor prefix (for example, just BL1 instead of
+  ``AP_BL1``).
+
+- Previously, the format for 3rd level images had 2 forms; ``BL3`` was either
+  suffixed with a dash ("-") followed by a number (for example, ``BL3-1``) or a
+  subscript number, depending on whether rich text formatting was available.
+  This was confusing and often the dash gets omitted in practice. Therefore the
+  new form is to just omit the dash and not use subscript formatting.
+
+- The names no longer contain dash ("-") characters at all. In some places (for
+  example, function names) it's not possible to use this character. All dashes
+  are either removed or replaced by underscores ("_").
+
+- The abbreviation BL stands for BootLoader. This is a historical anomaly.
+  Clearly, many of these images are not BootLoaders, they are simply firmware
+  images. However, the BL abbreviation is now widely used and is retained for
+  backwards compatibility.
+
+- The image names are not case sensitive. For example, ``bl1`` is
+  interchangeable with ``BL1``, although mixed case should be avoided.
+
+Trusted Firmware Images
+-----------------------
+
+Firmware Image Package: ``FIP``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This is a packaging format used by TF-A to package firmware images in a single
+binary. The number and type of images that should be packed in a FIP is
+platform-specific and may include TF-A images and other firmware images
+required by the platform. For example, most platforms require a BL33 image
+which corresponds to the normal world bootloader (e.g. UEFI or U-Boot).
+
+AP Boot ROM: ``AP_BL1``
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Typically, this is the first code to execute on the AP and cannot be modified.
+Its primary purpose is to perform the minimum initialization necessary to load
+and authenticate an updateable AP firmware image into an executable RAM
+location, then hand-off control to that image.
+
+AP RAM Firmware: ``AP_BL2``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This is the 2nd stage AP firmware. It is currently also known as the "Trusted
+Boot Firmware". Its primary purpose is to perform any additional initialization
+required to load and authenticate all 3rd level firmware images into their
+executable RAM locations, then hand-off control to the EL3 Runtime Firmware.
+
+EL3 Runtime Firmware: ``AP_BL31``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Also known as "SoC AP firmware" or "EL3 monitor firmware". Its primary purpose
+is to handle transitions between the normal and secure world.
+
+Secure-EL1 Payload (SP): ``AP_BL32``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Typically this is a TEE or Trusted OS, providing runtime secure services to the
+normal world. However, it may refer to a more abstract Secure-EL1 Payload (SP).
+Note that this abbreviation should only be used in systems where there is a
+single or primary image executing at Secure-EL1. In systems where there are
+potentially multiple SPs and there is no concept of a primary SP, this
+abbreviation should be avoided; use the recommended **Other AP 3rd level
+images** abbreviation instead.
+
+AP Normal World Firmware: ``AP_BL33``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For example, UEFI or uboot. Its primary purpose is to boot a normal world OS.
+
+Other AP 3rd level images: ``AP_BL3_XXX``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The abbreviated names of the existing 3rd level images imply a load/execution
+ordering (for example, ``AP_BL31 -> AP_BL32 -> AP_BL33``).  Some systems may
+have additional images and/or a different load/execution ordering. The
+abbreviated names of the existing images are retained for backward compatibility
+but new 3rd level images should be suffixed with an underscore followed by text
+identifier, not a number.
+
+In systems where 3rd level images are provided by different vendors, the
+abbreviated name should identify the vendor as well as the image
+function. For example, ``AP_BL3_ARM_RAS``.
+
+Realm Monitor Management Firmware: ``RMM``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This is the Realm-EL2 firmware. It is required if
+:ref:`Realm Management Extension (RME)` feature is enabled. If a path to RMM
+image is not provided, TF-A builds Test Realm Payload (TRP) image by default
+and uses it as the RMM image.
+
+SCP Boot ROM: ``SCP_BL1`` (previously ``BL0``)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Typically, this is the first code to execute on the SCP and cannot be modified.
+Its primary purpose is to perform the minimum initialization necessary to load
+and authenticate an updateable SCP firmware image into an executable RAM
+location, then hand-off control to that image. This may be performed in
+conjunction with other processor firmware (for example, ``AP_BL1`` and
+``AP_BL2``).
+
+This image was previously abbreviated as ``BL0`` but in some systems, the SCP
+may directly load/authenticate its own firmware. In these systems, it doesn't
+make sense to interleave the image terminology for AP and SCP; both AP and SCP
+Boot ROMs are ``BL1`` from their own point of view.
+
+SCP RAM Firmware: ``SCP_BL2`` (previously ``BL3-0``)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This is the 2nd stage SCP firmware. It is currently also known as the "SCP
+runtime firmware" but it could potentially be an intermediate firmware if the
+SCP needs to load/authenticate multiple 3rd level images in future.
+
+This image was previously abbreviated as BL3-0 but from the SCP's point of view,
+this has always been the 2nd stage firmware. The previous name is too
+AP-centric.
+
+Firmware Update (FWU) Images
+----------------------------
+
+The terminology for these images has not been widely adopted yet but they have
+to be considered in a production Trusted Board Boot solution.
+
+AP Firmware Update Boot ROM: ``AP_NS_BL1U``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Typically, this is the first normal world code to execute on the AP during a
+firmware update operation, and cannot be modified. Its primary purpose is to
+load subsequent firmware update images from an external interface and communicate
+with ``AP_BL1`` to authenticate those images.
+
+During firmware update, there are (potentially) multiple transitions between the
+secure and normal world. The "level" of the BL image is relative to the world
+it's in so it makes sense to encode "NS" in the normal world images. The absence
+of "NS" implies a secure world image.
+
+AP Firmware Update Config: ``AP_BL2U``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This image does the minimum necessary AP secure world configuration required to
+complete the firmware update operation. It is potentially a subset of ``AP_BL2``
+functionality.
+
+SCP Firmware Update Config: ``SCP_BL2U`` (previously ``BL2-U0``)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This image does the minimum necessary SCP secure world configuration required to
+complete the firmware update operation. It is potentially a subset of
+``SCP_BL2`` functionality.
+
+AP Firmware Updater: ``AP_NS_BL2U`` (previously ``BL3-U``)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This is the 2nd stage AP normal world firmware updater. Its primary purpose is
+to load a new set of firmware images from an external interface and write them
+into non-volatile storage.
+
+Other Processor Firmware Images
+-------------------------------
+
+Some systems may have additional processors to the AP and SCP. For example, a
+Management Control Processor (MCP). Images for these processors should follow
+the same terminology, with the processor abbreviation prefix, followed by
+underscore and the level of the firmware image.
+
+For example,
+
+MCP Boot ROM: ``MCP_BL1``
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+MCP RAM Firmware: ``MCP_BL2``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

arm-trusted-firmware.t234/docs/getting_started/index.rst

@@ -0,0 +1,20 @@
+Getting Started
+===============
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Contents
+
+   prerequisites
+   docs-build
+   initial-build
+   tools-build
+   build-options
+   build-internals
+   image-terminology
+   psci-lib-integration-guide
+   rt-svc-writers-guide
+
+--------------
+
+*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*

arm-trusted-firmware.t234/docs/getting_started/initial-build.rst

@@ -0,0 +1,118 @@
+Performing an Initial Build
+===========================
+
+-  Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
+   to your cross compiler.
+
+   For AArch64:
+
+   .. code:: shell
+
+       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
+
+   For AArch32:
+
+   .. code:: shell
+
+       export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-none-eabi-
+
+   It is possible to build TF-A using Clang or Arm Compiler 6. To do so
+   ``CC`` needs to point to the clang or armclang binary, which will
+   also select the clang or armclang assembler. Arm Compiler 6 will be selected
+   when the base name of the path assigned to ``CC`` matches the string
+   'armclang'. GNU binutils are required since the TF-A build system doesn't
+   currently support Arm Scatter files. Meaning the GNU linker is used by
+   default for Arm Compiler 6. Because of this dependency, ``CROSS_COMPILE``
+   should be set as described above.
+
+   For AArch64 using Arm Compiler 6:
+
+   .. code:: shell
+
+       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
+       make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
+
+   On the other hand, Clang uses LLVM linker (LLD) and other LLVM binutils by
+   default instead of GNU utilities (LLVM linker (LLD) 14.0.0 is known to
+   work with TF-A). ``CROSS_COMPILE`` need not be set for Clang. Please note,
+   that the default linker may be manually overridden using the ``LD`` variable.
+
+   Clang will be selected when the base name of the path assigned to ``CC``
+   contains the string 'clang'. This is to allow both clang and clang-X.Y
+   to work.
+
+   For AArch64 using clang:
+
+   .. code:: shell
+
+       make CC=<path-to-clang>/bin/clang PLAT=<platform> all
+
+-  Change to the root directory of the TF-A source tree and build.
+
+   For AArch64:
+
+   .. code:: shell
+
+       make PLAT=<platform> all
+
+   For AArch32:
+
+   .. code:: shell
+
+       make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
+
+   Notes:
+
+   -  If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
+      :ref:`Build Options` document for more information on available build
+      options.
+
+   -  (AArch32 only) Currently only ``PLAT=fvp`` is supported.
+
+   -  (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
+      corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
+      provided by TF-A to demonstrate how PSCI Library can be integrated with
+      an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
+      include other runtime services, for example Trusted OS services. A guide
+      to integrate PSCI library with AArch32 EL3 Runtime Software can be found
+      at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
+
+   -  (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
+      image, is not compiled in by default. Refer to the
+      :ref:`Test Secure Payload (TSP) and Dispatcher (TSPD)` document for
+      details on building the TSP.
+
+   -  By default this produces a release version of the build. To produce a
+      debug version instead, refer to the "Debugging options" section below.
+
+   -  The build process creates products in a ``build`` directory tree, building
+      the objects and binaries for each boot loader stage in separate
+      sub-directories. The following boot loader binary files are created
+      from the corresponding ELF files:
+
+      -  ``build/<platform>/<build-type>/bl1.bin``
+      -  ``build/<platform>/<build-type>/bl2.bin``
+      -  ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
+      -  ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
+
+      where ``<platform>`` is the name of the chosen platform and ``<build-type>``
+      is either ``debug`` or ``release``. The actual number of images might differ
+      depending on the platform.
+
+-  Build products for a specific build variant can be removed using:
+
+   .. code:: shell
+
+       make DEBUG=<D> PLAT=<platform> clean
+
+   ... where ``<D>`` is ``0`` or ``1``, as specified when building.
+
+   The build tree can be removed completely using:
+
+   .. code:: shell
+
+       make realclean
+
+--------------
+
+*Copyright (c) 2020-2022, Arm Limited. All rights reserved.*

arm-trusted-firmware.t234/docs/getting_started/prerequisites.rst

@@ -0,0 +1,196 @@
+Prerequisites
+=============
+
+This document describes the software requirements for building |TF-A| for
+AArch32 and AArch64 target platforms.
+
+It may possible to build |TF-A| with combinations of software packages that are
+different from those listed below, however only the software described in this
+document can be officially supported.
+
+Getting the TF-A Source
+-----------------------
+
+Source code for |TF-A| is maintained in a Git repository hosted on
+`TrustedFirmware.org`_. To clone this repository from the server, run the following
+in your shell:
+
+.. code:: shell
+
+    git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
+
+
+Requirements
+------------
+
+======================== =====================
+        Program          Min supported version
+======================== =====================
+Arm Compiler             6.18
+Arm GNU Compiler         13.3
+Clang/LLVM               18.1.8
+Device Tree Compiler     1.6.1
+GNU make                 3.81
+mbed TLS\ [#f1]_         3.6.1
+Node.js [#f2]_           16
+OpenSSL                  1.0.0
+Poetry                   1.3.2
+QCBOR\ [#f3]_            1.2
+Sphinx\ [#f2]_           5.3.0
+======================== =====================
+
+.. [#f1] Required for Trusted Board Boot and Measured Boot.
+.. [#f2] Required only for building TF-A documentation.
+.. [#f3] Required only when enabling DICE Protection Environment support.
+
+Toolchain
+^^^^^^^^^
+
+|TF-A| can be compiled using any cross-compiler toolchain specified in the
+preceding table that target Armv7-A or Armv8-A. For AArch32 and
+AArch64 builds, the respective targets required are ``arm-none-eabi`` and
+``aarch64-none-elf``.
+
+Testing has been performed with version 13.3.Rel1 (gcc 13.3) of the Arm
+GNU compiler, which can be installed from the `Arm Developer website`_.
+
+In addition, a native compiler is required to build supporting tools.
+
+.. note::
+   Versions greater than the ones specified are likely but not guaranteed to
+   work. This is predominantly because TF-A carries its own copy of compiler-rt,
+   which may be older than the version expected by the compiler. Fixes and bug
+   reports are always welcome.
+
+.. note::
+   For instructions on how to select the cross compiler refer to
+   :ref:`Performing an Initial Build`.
+
+OpenSSL
+^^^^^^^
+
+OpenSSL is required to build the cert_create, encrypt_fw, and fiptool tools.
+
+If using OpenSSL 3, older Linux versions may require it to be built from
+source code, as it may not be available in the default package repositories.
+Please refer to the OpenSSL project documentation for more information.
+
+.. warning::
+    Versions 1.0.x and from v3.0.0 up to v3.0.6 are strongly advised against due
+    to concerns regarding security vulnerabilities!
+
+Device Tree Compiler (DTC)
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Needed if you want to rebuild the provided Flattened Device Tree (FDT)
+source files (``.dts`` files). DTC is available for Linux through the package
+repositories of most distributions.
+
+Arm Development Studio (`Arm-DS`_)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The standard software package used for debugging software on Arm development
+platforms and |FVP| models.
+
+Node.js
+^^^^^^^
+
+Highly recommended, and necessary in order to install and use the packaged
+Git hooks and helper tools. Without these tools you will need to rely on the
+CI for feedback on commit message conformance.
+
+Poetry
+^^^^^^
+
+Required for managing Python dependencies, this will allow you to reliably
+reproduce a Python environment to build documentation and run some of the
+integrated Python tools. Most importantly, it ensures your system environment
+will not be affected by dependencies in the Python scripts.
+
+For installation instructions, see the `official Poetry documentation`_.
+
+.. _prerequisites_software_and_libraries:
+
+Package Installation (Linux)
+----------------------------
+
+|TF-A| can be compiled on both Linux and Windows-based machines.
+However, we strongly recommend using a UNIX-compatible build environment.
+
+Testing is performed using Ubuntu 22.04 LTS (64-bit), but other distributions
+should also work, provided the necessary tools and libraries are installed.
+
+The following are steps to install the required packages:
+
+.. code:: shell
+
+    sudo apt install build-essential
+
+The optional packages can be installed using:
+
+.. code:: shell
+
+    sudo apt install device-tree-compiler
+
+Additionally, to install a version of Node.js compatible with TF-A's repository
+scripts, you can use the `Node Version Manager`_. To install both NVM and an
+appropriate version of Node.js, run the following **from the root directory of
+the repository**:
+
+.. code:: shell
+
+    curl -o- https://raw.githubusercontent.com/nvm-sh/nvm/v0.39.1/install.sh | bash
+    exec "$SHELL" -ic "nvm install; exec $SHELL"
+
+.. _Node Version Manager: https://github.com/nvm-sh/nvm#install--update-script
+
+Supporting Files
+----------------
+
+TF-A has been tested with pre-built binaries and file systems from `Linaro
+Release 20.01`_. Alternatively, you can build the binaries from source using
+instructions in :ref:`Performing an Initial Build`.
+
+.. _prerequisites_get_source:
+
+Additional Steps for Contributors
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+If you are planning on contributing back to TF-A, there are some things you'll
+want to know.
+
+TF-A is hosted by a `Gerrit Code Review`_ server. Gerrit requires that all
+commits include a ``Change-Id`` footer, and this footer is typically
+automatically generated by a Git hook installed by you, the developer.
+
+If you have Node.js installed already, you can automatically install this hook,
+along with any additional hooks and Javascript-based tooling that we use, by
+running from within your newly-cloned repository:
+
+.. code:: shell
+
+    npm install --no-save
+
+If you have opted **not** to install Node.js, you can install the Gerrit hook
+manually by running:
+
+.. code:: shell
+
+    curl -Lo $(git rev-parse --git-dir)/hooks/commit-msg https://review.trustedfirmware.org/tools/hooks/commit-msg
+    chmod +x $(git rev-parse --git-dir)/hooks/commit-msg
+
+You can read more about Git hooks in the *githooks* page of the Git
+documentation, available `here <https://git-scm.com/docs/githooks>`_.
+
+--------------
+
+*Copyright (c) 2021-2024, Arm Limited. All rights reserved.*
+
+.. _Arm Developer website: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
+.. _Gerrit Code Review: https://www.gerritcodereview.com/
+.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
+.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
+.. _Arm-DS: https://developer.arm.com/Tools%20and%20Software/Arm%20Development%20Studio
+.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
+.. _TrustedFirmware.org: https://www.trustedfirmware.org/
+.. _official Poetry documentation: https://python-poetry.org/docs/#installation

arm-trusted-firmware.t234/docs/getting_started/psci-lib-integration-guide.rst

@@ -0,0 +1,534 @@
+PSCI Library Integration guide for Armv8-A AArch32 systems
+==========================================================
+
+This document describes the PSCI library interface with a focus on how to
+integrate with a suitable Trusted OS for an Armv8-A AArch32 system. The PSCI
+Library implements the PSCI Standard as described in `PSCI`_ and is meant
+to be integrated with EL3 Runtime Software which invokes the PSCI Library
+interface appropriately. **EL3 Runtime Software** refers to software executing
+at the highest secure privileged mode, which is EL3 in AArch64 or Secure SVC/
+Monitor mode in AArch32, and provides runtime services to the non-secure world.
+The runtime service request is made via SMC (Secure Monitor Call) and the call
+must adhere to `SMCCC`_. In AArch32, EL3 Runtime Software may additionally
+include Trusted OS functionality. A minimal AArch32 Secure Payload, SP-MIN, is
+provided in Trusted Firmware-A (TF-A) to illustrate the usage and integration
+of the PSCI library. The description of PSCI library interface and its
+integration with EL3 Runtime Software in this document is targeted towards
+AArch32 systems.
+
+Generic call sequence for PSCI Library interface (AArch32)
+----------------------------------------------------------
+
+The generic call sequence of PSCI Library interfaces (see
+`PSCI Library Interface`_) during cold boot in AArch32
+system is described below:
+
+#. After cold reset, the EL3 Runtime Software performs its cold boot
+   initialization including the PSCI library pre-requisites mentioned in
+   `PSCI Library Interface`_, and also the necessary platform
+   setup.
+
+#. Call ``psci_setup()`` in Monitor mode.
+
+#. Optionally call ``psci_register_spd_pm_hook()`` to register callbacks to
+   do bookkeeping for the EL3 Runtime Software during power management.
+
+#. Call ``psci_prepare_next_non_secure_ctx()`` to initialize the non-secure CPU
+   context.
+
+#. Get the non-secure ``cpu_context_t`` for the current CPU by calling
+   ``cm_get_context()`` , then programming the registers in the non-secure
+   context and exiting to non-secure world. If the EL3 Runtime Software needs
+   additional configuration to be set for non-secure context, like routing
+   FIQs to the secure world, the values of the registers can be modified prior
+   to programming. See `PSCI CPU context management`_ for more
+   details on CPU context management.
+
+The generic call sequence of PSCI library interfaces during warm boot in
+AArch32 systems is described below:
+
+#. After warm reset, the EL3 Runtime Software performs the necessary warm
+   boot initialization including the PSCI library pre-requisites mentioned in
+   `PSCI Library Interface`_ (Note that the Data cache
+   **must not** be enabled).
+
+#. Call ``psci_warmboot_entrypoint()`` in Monitor mode. This interface
+   initializes/restores the non-secure CPU context as well.
+
+#. Do step 5 of the cold boot call sequence described above.
+
+The generic call sequence of PSCI library interfaces on receipt of a PSCI SMC
+on an AArch32 system is described below:
+
+#. On receipt of an SMC, save the register context as per `SMCCC`_.
+
+#. If the SMC function identifier corresponds to a SMC32 PSCI API, construct
+   the appropriate arguments and call the ``psci_smc_handler()`` interface.
+   The invocation may or may not return back to the caller depending on
+   whether the PSCI API resulted in power down of the CPU.
+
+#. If ``psci_smc_handler()`` returns, populate the return value in R0 (AArch32)/
+   X0 (AArch64) and restore other registers as per `SMCCC`_.
+
+PSCI CPU context management
+---------------------------
+
+PSCI library is in charge of initializing/restoring the non-secure CPU system
+registers according to `PSCI`_ during cold/warm boot.
+This is referred to as ``PSCI CPU Context Management``. Registers that need to
+be preserved across CPU power down/power up cycles are maintained in
+``cpu_context_t`` data structure. The initialization of other non-secure CPU
+system registers which do not require coordination with the EL3 Runtime
+Software is done directly by the PSCI library (see ``cm_prepare_el3_exit()``).
+
+The EL3 Runtime Software is responsible for managing register context
+during switch between Normal and Secure worlds. The register context to be
+saved and restored depends on the mechanism used to trigger the world switch.
+For example, if the world switch was triggered by an SMC call, then the
+registers need to be saved and restored according to `SMCCC`_. In AArch64,
+due to the tight integration with BL31, both BL31 and PSCI library
+use the same ``cpu_context_t`` data structure for PSCI CPU context management
+and register context management during world switch. This cannot be assumed
+for AArch32 EL3 Runtime Software since most AArch32 Trusted OSes already implement
+a mechanism for register context management during world switch. Hence, when
+the PSCI library is integrated with a AArch32 EL3 Runtime Software, the
+``cpu_context_t`` is stripped down for just PSCI CPU context management.
+
+During cold/warm boot, after invoking appropriate PSCI library interfaces, it
+is expected that the EL3 Runtime Software will query the ``cpu_context_t`` and
+write appropriate values to the corresponding system registers. This mechanism
+resolves 2 additional problems for AArch32 EL3 Runtime Software:
+
+#. Values for certain system registers like SCR and SCTLR cannot be
+   unilaterally determined by PSCI library and need inputs from the EL3
+   Runtime Software. Using ``cpu_context_t`` as an intermediary data store
+   allows EL3 Runtime Software to modify the register values appropriately
+   before programming them.
+
+#. The PSCI library provides appropriate LR and SPSR values (entrypoint
+   information) for exit into non-secure world. Using ``cpu_context_t`` as an
+   intermediary data store allows the EL3 Runtime Software to store these
+   values safely until it is ready for exit to non-secure world.
+
+Currently the ``cpu_context_t`` data structure for AArch32 stores the following
+registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
+
+The EL3 Runtime Software must implement accessors to get/set pointers
+to CPU context ``cpu_context_t`` data and these are described in
+`CPU Context management API`_.
+
+PSCI Library Interface
+----------------------
+
+The PSCI library implements the `PSCI`_. The interfaces to this library are
+declared in ``psci_lib.h`` and are as listed below:
+
+.. code:: c
+
+        u_register_t psci_smc_handler(uint32_t smc_fid, u_register_t x1,
+                                      u_register_t x2, u_register_t x3,
+                                      u_register_t x4, void *cookie,
+                                      void *handle, u_register_t flags);
+        int psci_setup(const psci_lib_args_t *lib_args);
+        void psci_warmboot_entrypoint(void);
+        void psci_register_spd_pm_hook(const spd_pm_ops_t *pm);
+        void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info);
+
+The CPU context data 'cpu_context_t' is programmed to the registers differently
+when PSCI is integrated with an AArch32 EL3 Runtime Software compared to
+when the PSCI is integrated with an AArch64 EL3 Runtime Software (BL31). For
+example, in the case of AArch64, there is no need to retrieve ``cpu_context_t``
+data and program the registers as it will done implicitly as part of
+``el3_exit``. The description below of the PSCI interfaces is targeted at
+integration with an AArch32 EL3 Runtime Software.
+
+The PSCI library is responsible for initializing/restoring the non-secure world
+to an appropriate state after boot and may choose to directly program the
+non-secure system registers. The PSCI generic code takes care not to directly
+modify any of the system registers affecting the secure world and instead
+returns the values to be programmed to these registers via ``cpu_context_t``.
+The EL3 Runtime Software is responsible for programming those registers and
+can use the proposed values provided in the ``cpu_context_t``, modifying the
+values if required.
+
+PSCI library needs the flexibility to access both secure and non-secure
+copies of banked registers. Hence it needs to be invoked in Monitor mode
+for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR_EL3
+(in AArch64) must be set to 0. Additional requirements for the PSCI library
+interfaces are:
+
+-  Instruction cache must be enabled
+-  Both IRQ and FIQ must be masked for the current CPU
+-  The page tables must be setup and the MMU enabled
+-  The C runtime environment must be setup and stack initialized
+-  The Data cache must be enabled prior to invoking any of the PSCI library
+   interfaces except for ``psci_warmboot_entrypoint()``. For
+   ``psci_warmboot_entrypoint()``, if the build option ``HW_ASSISTED_COHERENCY``
+   is enabled however, data caches are expected to be enabled.
+
+Further requirements for each interface can be found in the interface
+description.
+
+Interface : psci_setup()
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : const psci_lib_args_t *lib_args
+    Return   : void
+
+This function is to be called by the primary CPU during cold boot before
+any other interface to the PSCI library. It takes ``lib_args``, a const pointer
+to ``psci_lib_args_t``, as the argument. The ``psci_lib_args_t`` is a versioned
+structure and is declared in ``psci_lib.h`` header as follows:
+
+.. code:: c
+
+        typedef struct psci_lib_args {
+            /* The version information of PSCI Library Interface */
+            param_header_t        h;
+            /* The warm boot entrypoint function */
+            mailbox_entrypoint_t  mailbox_ep;
+        } psci_lib_args_t;
+
+The first field ``h``, of ``param_header_t`` type, provides the version
+information. The second field ``mailbox_ep`` is the warm boot entrypoint address
+and is used to configure the platform mailbox. Helper macros are provided in
+``psci_lib.h`` to construct the ``lib_args`` argument statically or during
+runtime. Prior to calling the ``psci_setup()`` interface, the platform setup for
+cold boot must have completed. Major actions performed by this interface are:
+
+-  Initializes architecture.
+-  Initializes PSCI power domain and state coordination data structures.
+-  Calls ``plat_setup_psci_ops()`` with warm boot entrypoint ``mailbox_ep`` as
+   argument.
+-  Calls ``cm_set_context_by_index()`` (see
+   `CPU Context management API`_) for all the CPUs in the
+   platform
+
+Interface : psci_prepare_next_non_secure_ctx()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : entry_point_info_t *next_image_info
+    Return   : void
+
+After ``psci_setup()`` and prior to exit to the non-secure world, this function
+must be called by the EL3 Runtime Software to initialize the non-secure world
+context. The non-secure world entrypoint information ``next_image_info`` (first
+argument) will be used to determine the non-secure context. After this function
+returns, the EL3 Runtime Software must retrieve the ``cpu_context_t`` (using
+cm_get_context()) for the current CPU and program the registers prior to exit
+to the non-secure world.
+
+Interface : psci_register_spd_pm_hook()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : const spd_pm_ops_t *
+    Return   : void
+
+As explained in `Secure payload power management callback`_,
+the EL3 Runtime Software may want to perform some bookkeeping during power
+management operations. This function is used to register the ``spd_pm_ops_t``
+(first argument) callbacks with the PSCI library which will be called
+appropriately during power management. Calling this function is optional and
+need to be called by the primary CPU during the cold boot sequence after
+``psci_setup()`` has completed.
+
+Interface : psci_smc_handler()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : uint32_t smc_fid, u_register_t x1,
+               u_register_t x2, u_register_t x3,
+               u_register_t x4, void *cookie,
+               void *handle, u_register_t flags
+    Return   : u_register_t
+
+This function is the top level handler for SMCs which fall within the
+PSCI service range specified in `SMCCC`_. The function ID ``smc_fid`` (first
+argument) determines the PSCI API to be called. The ``x1`` to ``x4`` (2nd to 5th
+arguments), are the values of the registers r1 - r4 (in AArch32) or x1 - x4
+(in AArch64) when the SMC is received. These are the arguments to PSCI API as
+described in `PSCI`_. The 'flags' (8th argument) is a bit field parameter
+and is detailed in 'smccc.h' header. It includes whether the call is from the
+secure or non-secure world. The ``cookie`` (6th argument) and the ``handle``
+(7th argument) are not used and are reserved for future use.
+
+The return value from this interface is the return value from the underlying
+PSCI API corresponding to ``smc_fid``. This function may not return back to the
+caller if PSCI API causes power down of the CPU. In this case, when the CPU
+wakes up, it will start execution from the warm reset address.
+
+Interface : psci_warmboot_entrypoint()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : void
+    Return   : void
+
+This function performs the warm boot initialization/restoration as mandated by
+`PSCI`_. For AArch32, on wakeup from power down the CPU resets to secure SVC
+mode and the EL3 Runtime Software must perform the prerequisite initializations
+mentioned at top of this section. This function must be called with Data cache
+disabled (unless build option ``HW_ASSISTED_COHERENCY`` is enabled) but with MMU
+initialized and enabled. The major actions performed by this function are:
+
+-  Invalidates the stack and enables the data cache.
+-  Initializes architecture and PSCI state coordination.
+-  Restores/Initializes the peripheral drivers to the required state via
+   appropriate ``plat_psci_ops_t`` hooks
+-  Restores the EL3 Runtime Software context via appropriate ``spd_pm_ops_t``
+   callbacks.
+-  Restores/Initializes the non-secure context and populates the
+   ``cpu_context_t`` for the current CPU.
+
+Upon the return of this function, the EL3 Runtime Software must retrieve the
+non-secure ``cpu_context_t`` using ``cm_get_context()`` and program the registers
+prior to exit to the non-secure world.
+
+EL3 Runtime Software dependencies
+---------------------------------
+
+The PSCI Library includes supporting frameworks like context management,
+cpu operations (cpu_ops) and per-cpu data framework. Other helper library
+functions like bakery locks and spin locks are also included in the library.
+The dependencies which must be fulfilled by the EL3 Runtime Software
+for integration with PSCI library are described below.
+
+General dependencies
+~~~~~~~~~~~~~~~~~~~~
+
+The PSCI library being a Multiprocessor (MP) implementation, EL3 Runtime
+Software must provide an SMC handling framework capable of MP adhering to
+`SMCCC`_ specification.
+
+The EL3 Runtime Software must also export cache maintenance primitives
+and some helper utilities for assert, print and memory operations as listed
+below. The TF-A source tree provides implementations for all
+these functions but the EL3 Runtime Software may use its own implementation.
+
+**Functions : assert(), memcpy(), memset(), printf()**
+
+These must be implemented as described in ISO C Standard.
+
+**Function : flush_dcache_range()**
+
+::
+
+    Argument : uintptr_t addr, size_t size
+    Return   : void
+
+This function cleans and invalidates (flushes) the data cache for memory
+at address ``addr`` (first argument) address and of size ``size`` (second argument).
+
+**Function : inv_dcache_range()**
+
+::
+
+    Argument : uintptr_t addr, size_t size
+    Return   : void
+
+This function invalidates (flushes) the data cache for memory at address
+``addr`` (first argument) address and of size ``size`` (second argument).
+
+CPU Context management API
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The CPU context management data memory is statically allocated by PSCI library
+in BSS section. The PSCI library requires the EL3 Runtime Software to implement
+APIs to store and retrieve pointers to this CPU context data. SP-MIN
+demonstrates how these APIs can be implemented but the EL3 Runtime Software can
+choose a more optimal implementation (like dedicating the secure TPIDRPRW
+system register (in AArch32) for storing these pointers).
+
+**Function : cm_set_context_by_index()**
+
+::
+
+    Argument : unsigned int cpu_idx, void *context, unsigned int security_state
+    Return   : void
+
+This function is called during cold boot when the ``psci_setup()`` PSCI library
+interface is called.
+
+This function must store the pointer to the CPU context data, ``context`` (2nd
+argument), for the specified ``security_state`` (3rd argument) and CPU identified
+by ``cpu_idx`` (first argument). The ``security_state`` will always be non-secure
+when called by PSCI library and this argument is retained for compatibility
+with BL31. The ``cpu_idx`` will correspond to the index returned by the
+``plat_core_pos_by_mpidr()`` for ``mpidr`` of the CPU.
+
+The actual method of storing the ``context`` pointers is implementation specific.
+For example, SP-MIN stores the pointers in the array ``sp_min_cpu_ctx_ptr``
+declared in ``sp_min_main.c``.
+
+**Function : cm_get_context()**
+
+::
+
+    Argument : uint32_t security_state
+    Return   : void *
+
+This function must return the pointer to the ``cpu_context_t`` structure for
+the specified ``security_state`` (first argument) for the current CPU. The caller
+must ensure that ``cm_set_context_by_index`` is called first and the appropriate
+context pointers are stored prior to invoking this API. The ``security_state``
+will always be non-secure when called by PSCI library and this argument
+is retained for compatibility with BL31.
+
+**Function : cm_get_context_by_index()**
+
+::
+
+    Argument : unsigned int cpu_idx, unsigned int security_state
+    Return   : void *
+
+This function must return the pointer to the ``cpu_context_t`` structure for
+the specified ``security_state`` (second argument) for the CPU identified by
+``cpu_idx`` (first argument). The caller must ensure that
+``cm_set_context_by_index`` is called first and the appropriate context
+pointers are stored prior to invoking this API. The ``security_state`` will
+always be non-secure when called by PSCI library and this argument is
+retained for compatibility with BL31. The ``cpu_idx`` will correspond to the
+index returned by the ``plat_core_pos_by_mpidr()`` for ``mpidr`` of the CPU.
+
+Platform API
+~~~~~~~~~~~~
+
+The platform layer abstracts the platform-specific details from the generic
+PSCI library. The following platform APIs/macros must be defined by the EL3
+Runtime Software for integration with the PSCI library.
+
+The mandatory platform APIs are:
+
+-  plat_my_core_pos
+-  plat_core_pos_by_mpidr
+-  plat_get_syscnt_freq2
+-  plat_get_power_domain_tree_desc
+-  plat_setup_psci_ops
+-  plat_reset_handler
+-  plat_panic_handler
+-  plat_get_my_stack
+
+The mandatory platform macros are:
+
+-  PLATFORM_CORE_COUNT
+-  PLAT_MAX_PWR_LVL
+-  PLAT_NUM_PWR_DOMAINS
+-  CACHE_WRITEBACK_GRANULE
+-  PLAT_MAX_OFF_STATE
+-  PLAT_MAX_RET_STATE
+-  PLAT_MAX_PWR_LVL_STATES (optional)
+-  PLAT_PCPU_DATA_SIZE (optional)
+
+The details of these APIs/macros can be found in the :ref:`Porting Guide`.
+
+All platform specific operations for power management are done via
+``plat_psci_ops_t`` callbacks registered by the platform when
+``plat_setup_psci_ops()`` API is called. The description of each of
+the callbacks in ``plat_psci_ops_t`` can be found in PSCI section of the
+:ref:`Porting Guide`. If any these callbacks are not registered, then the
+PSCI API associated with that callback will not be supported by PSCI
+library.
+
+Secure payload power management callback
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+During PSCI power management operations, the EL3 Runtime Software may
+need to perform some bookkeeping, and PSCI library provides
+``spd_pm_ops_t`` callbacks for this purpose. These hooks must be
+populated and registered by using ``psci_register_spd_pm_hook()`` PSCI
+library interface.
+
+Typical bookkeeping during PSCI power management calls include save/restore
+of the EL3 Runtime Software context. Also if the EL3 Runtime Software makes
+use of secure interrupts, then these interrupts must also be managed
+appropriately during CPU power down/power up. Any secure interrupt targeted
+to the current CPU must be disabled or re-targeted to other running CPU prior
+to power down of the current CPU. During power up, these interrupt can be
+enabled/re-targeted back to the current CPU.
+
+.. code:: c
+
+        typedef struct spd_pm_ops {
+                void (*svc_on)(u_register_t target_cpu);
+                int32_t (*svc_off)(u_register_t __unused);
+                void (*svc_suspend)(u_register_t max_off_pwrlvl);
+                void (*svc_on_finish)(u_register_t __unused);
+                void (*svc_suspend_finish)(u_register_t max_off_pwrlvl);
+                int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu);
+                int32_t (*svc_migrate_info)(u_register_t *resident_cpu);
+                void (*svc_system_off)(void);
+                void (*svc_system_reset)(void);
+        } spd_pm_ops_t;
+
+A brief description of each callback is given below:
+
+-  svc_on, svc_off, svc_on_finish
+
+   The ``svc_on``, ``svc_off`` callbacks are called during PSCI_CPU_ON,
+   PSCI_CPU_OFF APIs respectively. The ``svc_on_finish`` is called when the
+   target CPU of PSCI_CPU_ON API powers up and executes the
+   ``psci_warmboot_entrypoint()`` PSCI library interface.
+
+-  svc_suspend, svc_suspend_finish
+
+   The ``svc_suspend`` callback is called during power down bu either
+   PSCI_SUSPEND or PSCI_SYSTEM_SUSPEND APIs. The ``svc_suspend_finish`` is
+   called when the CPU wakes up from suspend and executes the
+   ``psci_warmboot_entrypoint()`` PSCI library interface. The ``max_off_pwrlvl``
+   (first parameter) denotes the highest power domain level being powered down
+   to or woken up from suspend.
+
+-  svc_system_off, svc_system_reset
+
+   These callbacks are called during PSCI_SYSTEM_OFF and PSCI_SYSTEM_RESET
+   PSCI APIs respectively.
+
+-  svc_migrate_info
+
+   This callback is called in response to PSCI_MIGRATE_INFO_TYPE or
+   PSCI_MIGRATE_INFO_UP_CPU APIs. The return value of this callback must
+   correspond to the return value of PSCI_MIGRATE_INFO_TYPE API as described
+   in `PSCI`_. If the secure payload is a Uniprocessor (UP)
+   implementation, then it must update the mpidr of the CPU it is resident in
+   via ``resident_cpu`` (first argument). The updates to ``resident_cpu`` is
+   ignored if the secure payload is a multiprocessor (MP) implementation.
+
+-  svc_migrate
+
+   This callback is only relevant if the secure payload in EL3 Runtime
+   Software is a Uniprocessor (UP) implementation and supports migration from
+   the current CPU ``from_cpu`` (first argument) to another CPU ``to_cpu``
+   (second argument). This callback is called in response to PSCI_MIGRATE
+   API. This callback is never called if the secure payload is a
+   Multiprocessor (MP) implementation.
+
+CPU operations
+~~~~~~~~~~~~~~
+
+The CPU operations (cpu_ops) framework implement power down sequence specific
+to the CPU and the details of which can be found at
+:ref:`firmware_design_cpu_ops_fwk`. The TF-A tree implements the ``cpu_ops``
+for various supported CPUs and the EL3 Runtime Software needs to include the
+required ``cpu_ops`` in its build. The start and end of the ``cpu_ops``
+descriptors must be exported by the EL3 Runtime Software via the
+``__CPU_OPS_START__`` and ``__CPU_OPS_END__`` linker symbols.
+
+The ``cpu_ops`` descriptors also include reset sequences and may include errata
+workarounds for the CPU. The EL3 Runtime Software can choose to call this
+during cold/warm reset if it does not implement its own reset sequence/errata
+workarounds.
+
+--------------
+
+*Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.*
+
+.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
+.. _SMCCC: https://developer.arm.com/docs/den0028/latest

arm-trusted-firmware.t234/docs/getting_started/rt-svc-writers-guide.rst

@@ -0,0 +1,331 @@
+EL3 Runtime Service Writer's Guide
+=====================================================
+
+Introduction
+------------
+
+This document describes how to add a runtime service to the EL3 Runtime
+Firmware component of Trusted Firmware-A (TF-A), BL31.
+
+Software executing in the normal world and in the trusted world at exception
+levels lower than EL3 will request runtime services using the Secure Monitor
+Call (SMC) instruction. These requests will follow the convention described in
+the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
+identifiers to each SMC request and describes how arguments are passed and
+results are returned.
+
+SMC Functions are grouped together based on the implementor of the service, for
+example a subset of the Function IDs are designated as "OEM Calls" (see `SMCCC`_
+for full details). The EL3 runtime services framework in BL31 enables the
+independent implementation of services for each group, which are then compiled
+into the BL31 image. This simplifies the integration of common software from
+Arm to support `PSCI`_, Secure Monitor for a Trusted OS and SoC specific
+software. The common runtime services framework ensures that SMC Functions are
+dispatched to their respective service implementation - the
+:ref:`Firmware Design` document provides details of how this is achieved.
+
+The interface and operation of the runtime services depends heavily on the
+concepts and definitions described in the `SMCCC`_, in particular SMC Function
+IDs, Owning Entity Numbers (OEN), Fast and Standard calls, and the SMC32 and
+SMC64 calling conventions. Please refer to that document for a full explanation
+of these terms.
+
+Owning Entities, Call Types and Function IDs
+--------------------------------------------
+
+The SMC Function Identifier includes a OEN field. These values and their
+meaning are described in `SMCCC`_ and summarized in table 1 below. Some entities
+are allocated a range of of OENs. The OEN must be interpreted in conjunction
+with the SMC call type, which is either *Fast* or *Yielding*. Fast calls are
+uninterruptible whereas Yielding calls can be pre-empted. The majority of
+Owning Entities only have allocated ranges for Fast calls: Yielding calls are
+reserved exclusively for Trusted OS providers or for interoperability with
+legacy 32-bit software that predates the `SMCCC`_.
+
+::
+
+    Type       OEN     Service
+    Fast        0      Arm Architecture calls
+    Fast        1      CPU Service calls
+    Fast        2      SiP Service calls
+    Fast        3      OEM Service calls
+    Fast        4      Standard Secure Service calls
+    Fast        5      Standard Hypervisor Service Calls
+    Fast        6      Vendor Specific Hypervisor Service Calls
+    Fast        7      Vendor Specific EL3 Monitor Calls
+    Fast       8-47    Reserved for future use
+    Fast      48-49    Trusted Application calls
+    Fast      50-63    Trusted OS calls
+
+    Yielding   0- 1    Reserved for existing Armv7-A calls
+    Yielding   2-63    Trusted OS Standard Calls
+
+*Table 1: Service types and their corresponding Owning Entity Numbers*
+
+Each individual entity can allocate the valid identifiers within the entity
+range as they need - it is not necessary to coordinate with other entities of
+the same type. For example, two SoC providers can use the same Function ID
+within the SiP Service calls OEN range to mean different things - as these
+calls should be specific to the SoC. The Standard Runtime Calls OEN is used for
+services defined by Arm standards, such as `PSCI`_.
+
+The SMC Function ID also indicates whether the call has followed the SMC32
+calling convention, where all parameters are 32-bit, or the SMC64 calling
+convention, where the parameters are 64-bit. The framework identifies and
+rejects invalid calls that use the SMC64 calling convention but that originate
+from an AArch32 caller.
+
+The EL3 runtime services framework uses the call type and OEN to identify a
+specific handler for each SMC call, but it is expected that an individual
+handler will be responsible for all SMC Functions within a given service type.
+
+Getting started
+---------------
+
+TF-A has a ``services`` directory in the source tree under which
+each owning entity can place the implementation of its runtime service. The
+`PSCI`_ implementation is located here in the ``lib/psci`` directory.
+
+Runtime service sources will need to include the ``runtime_svc.h`` header file.
+
+Registering a runtime service
+-----------------------------
+
+A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
+the name of the service, the range of OENs covered, the type of service and
+initialization and call handler functions.
+
+.. code:: c
+
+    #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch)
+
+-  ``_name`` is used to identify the data structure declared by this macro, and
+   is also used for diagnostic purposes
+
+-  ``_start`` and ``_end`` values must be based on the ``OEN_*`` values defined in
+   ``smccc.h``
+
+-  ``_type`` must be one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD``
+
+-  ``_setup`` is the initialization function with the ``rt_svc_init`` signature:
+
+   .. code:: c
+
+       typedef int32_t (*rt_svc_init)(void);
+
+-  ``_smch`` is the SMC handler function with the ``rt_svc_handle`` signature:
+
+   .. code:: c
+
+       typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid,
+                                         u_register_t x1, u_register_t x2,
+                                         u_register_t x3, u_register_t x4,
+                                         void *cookie,
+                                         void *handle,
+                                         u_register_t flags);
+
+Details of the requirements and behavior of the two callbacks is provided in
+the following sections.
+
+During initialization the services framework validates each declared service
+to ensure that the following conditions are met:
+
+#. The ``_start`` OEN is not greater than the ``_end`` OEN
+#. The ``_end`` OEN does not exceed the maximum OEN value (63)
+#. The ``_type`` is one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD``
+#. ``_setup`` and ``_smch`` routines have been specified
+
+``std_svc_setup.c`` provides an example of registering a runtime service:
+
+.. code:: c
+
+    /* Register Standard Service Calls as runtime service */
+    DECLARE_RT_SVC(
+            std_svc,
+            OEN_STD_START,
+            OEN_STD_END,
+            SMC_TYPE_FAST,
+            std_svc_setup,
+            std_svc_smc_handler
+    );
+
+Initializing a runtime service
+------------------------------
+
+Runtime services are initialized once, during cold boot, by the primary CPU
+after platform and architectural initialization is complete. The framework
+performs basic validation of the declared service before calling
+the service initialization function (``_setup`` in the declaration). This
+function must carry out any essential EL3 initialization prior to receiving a
+SMC Function call via the handler function.
+
+On success, the initialization function must return ``0``. Any other return value
+will cause the framework to issue a diagnostic:
+
+::
+
+    Error initializing runtime service <name of the service>
+
+and then ignore the service - the system will continue to boot but SMC calls
+will not be passed to the service handler and instead return the *Unknown SMC
+Function ID* result ``0xFFFFFFFF``.
+
+If the system must not be allowed to proceed without the service, the
+initialization function must itself cause the firmware boot to be halted.
+
+If the service uses per-CPU data this must either be initialized for all CPUs
+during this call, or be done lazily when a CPU first issues an SMC call to that
+service.
+
+Handling runtime service requests
+---------------------------------
+
+SMC calls for a service are forwarded by the framework to the service's SMC
+handler function (``_smch`` in the service declaration). This function must have
+the following signature:
+
+.. code:: c
+
+    typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid,
+                                       u_register_t x1, u_register_t x2,
+                                       u_register_t x3, u_register_t x4,
+                                       void *cookie,
+                                       void *handle,
+                                       u_register_t flags);
+
+The handler is responsible for:
+
+#. Determining that ``smc_fid`` is a valid and supported SMC Function ID,
+   otherwise completing the request with the *Unknown SMC Function ID*:
+
+   .. code:: c
+
+       SMC_RET1(handle, SMC_UNK);
+
+#. Determining if the requested function is valid for the calling security
+   state. SMC Calls can be made from Non-secure, Secure or Realm worlds and
+   the framework will forward all calls to the service handler.
+
+   The ``flags`` parameter to this function indicates the caller security state
+   in bits 0 and 5. The ``is_caller_secure(flags)``, ``is_caller_non_secure(flags)``
+   and ``is_caller_realm(flags)`` helper functions can be used to determine whether
+   the caller's security state is Secure, Non-secure or Realm respectively.
+
+   If invalid, the request should be completed with:
+
+   .. code:: c
+
+       SMC_RET1(handle, SMC_UNK);
+
+#. Truncating parameters for calls made using the SMC32 calling convention.
+   Such calls can be determined by checking the CC field in bit[30] of the
+   ``smc_fid`` parameter, for example by using:
+
+   ::
+
+       if (GET_SMC_CC(smc_fid) == SMC_32) ...
+
+   For such calls, the upper bits of the parameters x1-x4 and the saved
+   parameters X5-X7 are UNDEFINED and must be explicitly ignored by the
+   handler. This can be done by truncating the values to a suitable 32-bit
+   integer type before use, for example by ensuring that functions defined
+   to handle individual SMC Functions use appropriate 32-bit parameters.
+
+#. Providing the service requested by the SMC Function, utilizing the
+   immediate parameters x1-x4 and/or the additional saved parameters X5-X7.
+   The latter can be retrieved using the ``SMC_GET_GP(handle, ref)`` function,
+   supplying the appropriate ``CTX_GPREG_Xn`` reference, e.g.
+
+   .. code:: c
+
+       uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+
+#. Implementing the standard SMC32 Functions that provide information about
+   the implementation of the service. These are the Call Count, Implementor
+   UID and Revision Details for each service documented in section 6 of the
+   `SMCCC`_.
+
+   TF-A expects owning entities to follow this recommendation.
+
+#. Returning the result to the caller. Based on `SMCCC`_ spec, results are
+   returned in W0-W7(X0-X7) registers for SMC32(SMC64) calls from AArch64
+   state. Results are returned in R0-R7 registers for SMC32 calls from AArch32
+   state. The framework provides a family of macros to set the multi-register
+   return value and complete the handler:
+
+   .. code:: c
+
+       AArch64 state:
+
+       SMC_RET1(handle, x0);
+       SMC_RET2(handle, x0, x1);
+       SMC_RET3(handle, x0, x1, x2);
+       SMC_RET4(handle, x0, x1, x2, x3);
+       SMC_RET5(handle, x0, x1, x2, x3, x4);
+       SMC_RET6(handle, x0, x1, x2, x3, x4, x5);
+       SMC_RET7(handle, x0, x1, x2, x3, x4, x5, x6);
+       SMC_RET8(handle, x0, x1, x2, x3, x4, x5, x6, x7);
+
+       AArch32 state:
+
+       SMC_RET1(handle, r0);
+       SMC_RET2(handle, r0, r1);
+       SMC_RET3(handle, r0, r1, r2);
+       SMC_RET4(handle, r0, r1, r2, r3);
+       SMC_RET5(handle, r0, r1, r2, r3, r4);
+       SMC_RET6(handle, r0, r1, r2, r3, r4, r5);
+       SMC_RET7(handle, r0, r1, r2, r3, r4, r5, r6);
+       SMC_RET8(handle, r0, r1, r2, r3, r4, r5, r6, r7);
+
+The ``cookie`` parameter to the handler is reserved for future use and can be
+ignored. The ``handle`` is returned by the SMC handler - completion of the
+handler function must always be via one of the ``SMC_RETn()`` macros.
+
+.. note::
+   The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow
+   all of the above requirements yet.
+
+Services that contain multiple sub-services
+-------------------------------------------
+
+It is possible that a single owning entity implements multiple sub-services. For
+example, the Standard calls service handles ``0x84000000``-``0x8400FFFF`` and
+``0xC4000000``-``0xC400FFFF`` functions. Within that range, the `PSCI`_ service
+handles the ``0x84000000``-``0x8400001F`` and ``0xC4000000``-``0xC400001F`` functions.
+In that respect, `PSCI`_ is a 'sub-service' of the Standard calls service. In
+future, there could be additional such sub-services in the Standard calls
+service which perform independent functions.
+
+In this situation it may be valuable to introduce a second level framework to
+enable independent implementation of sub-services. Such a framework might look
+very similar to the current runtime services framework, but using a different
+part of the SMC Function ID to identify the sub-service. TF-A does not provide
+such a framework at present.
+
+Secure-EL1 Payload Dispatcher service (SPD)
+-------------------------------------------
+
+Services that handle SMC Functions targeting a Trusted OS, Trusted Application,
+or other Secure-EL1 Payload are special. These services need to manage the
+Secure-EL1 context, provide the *Secure Monitor* functionality of switching
+between the normal and secure worlds, deliver SMC Calls through to Secure-EL1
+and generally manage the Secure-EL1 Payload through CPU power-state transitions.
+
+TODO: Provide details of the additional work required to implement a SPD and
+the BL31 support for these services. Or a reference to the document that will
+provide this information....
+
+Additional References:
+----------------------
+
+#. :ref:`ARM SiP Services <arm sip services>`
+#. :ref:`Vendor Specific EL3 Monitor Service Calls`
+
+--------------
+
+*Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.*
+
+.. _SMCCC: https://developer.arm.com/docs/den0028/latest
+.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
+.. _ARM SiP Services: arm-sip-service.rst
+.. _Vendor Specific EL3 Monitor Service Calls: ven-el3-service.rst

arm-trusted-firmware.t234/docs/getting_started/tools-build.rst

@@ -0,0 +1,179 @@
+Building Supporting Tools
+=========================
+
+.. note::
+
+    OpenSSL 3.0 is needed in order to build the tools. A custom installation
+    can be used if not updating the OpenSSL version on the OS. In order to do
+    this, use the ``OPENSSL_DIR`` variable after the ``make`` command to
+    indicate the location of the custom OpenSSL build. Then, to run the tools,
+    use the ``LD_LIBRARY_PATH`` to indicate the location of the built
+    libraries. More info about ``OPENSSL_DIR`` can be found at
+    :ref:`Build Options`.
+
+Building and using the FIP tool
+-------------------------------
+
+The following snippets build a :ref:`FIP<Image Terminology>` for the FVP
+platform. While it is not an intrinsic part of the FIP format, a BL33 image is
+required for these examples. For the purposes of experimentation, `Trusted
+Firmware-A Tests`_ (`tftf.bin``) may be used. Refer to to the `TFTF
+documentation`_ for instructions on building a TFTF binary.
+
+The TF-A build system provides the make target ``fip`` to create a FIP file
+for the specified platform using the FIP creation tool included in the TF-A
+project. Examples below show how to build a FIP file for FVP, packaging TF-A
+and BL33 images.
+
+For AArch64:
+
+.. code:: shell
+
+    make PLAT=fvp BL33=<path-to>/bl33.bin fip
+
+For AArch32:
+
+.. code:: shell
+
+    make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
+
+The resulting FIP may be found in:
+
+::
+
+    build/fvp/<build-type>/fip.bin
+
+For advanced operations on FIP files, it is also possible to independently build
+the tool and create or modify FIPs using this tool. To do this, follow these
+steps:
+
+It is recommended to remove old artifacts before building the tool:
+
+.. code:: shell
+
+    make -C tools/fiptool clean
+
+Build the tool:
+
+.. code:: shell
+
+    make [DEBUG=1] [V=1] fiptool
+
+The tool binary can be located in:
+
+::
+
+    ./tools/fiptool/fiptool
+
+Invoking the tool with ``help`` will print a help message with all available
+options.
+
+Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
+
+.. code:: shell
+
+    ./tools/fiptool/fiptool create \
+        --tb-fw build/<platform>/<build-type>/bl2.bin \
+        --soc-fw build/<platform>/<build-type>/bl31.bin \
+        fip.bin
+
+Example 2: view the contents of an existing Firmware package:
+
+.. code:: shell
+
+    ./tools/fiptool/fiptool info <path-to>/fip.bin
+
+Example 3: update the entries of an existing Firmware package:
+
+.. code:: shell
+
+    # Change the BL2 from Debug to Release version
+    ./tools/fiptool/fiptool update \
+        --tb-fw build/<platform>/release/bl2.bin \
+        build/<platform>/debug/fip.bin
+
+Example 4: unpack all entries from an existing Firmware package:
+
+.. code:: shell
+
+    # Images will be unpacked to the working directory
+    ./tools/fiptool/fiptool unpack <path-to>/fip.bin
+
+Example 5: remove an entry from an existing Firmware package:
+
+.. code:: shell
+
+    ./tools/fiptool/fiptool remove \
+        --tb-fw build/<platform>/debug/fip.bin
+
+Note that if the destination FIP file exists, the create, update and
+remove operations will automatically overwrite it.
+
+The unpack operation will fail if the images already exist at the
+destination. In that case, use -f or --force to continue.
+
+More information about FIP can be found in the :ref:`Firmware Design` document.
+
+.. _tools_build_cert_create:
+
+Building the Certificate Generation Tool
+----------------------------------------
+
+The ``cert_create`` tool is built as part of the TF-A build process when the
+``fip`` make target is specified and TBB is enabled (as described in the
+previous section), but it can also be built separately with the following
+command:
+
+.. code:: shell
+
+    make PLAT=<platform> [DEBUG=1] [V=1] certtool
+
+For platforms that require their own IDs in certificate files, the generic
+'cert_create' tool can be built with the following command. Note that the target
+platform must define its IDs within a ``platform_oid.h`` header file for the
+build to succeed.
+
+.. code:: shell
+
+    make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
+
+``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
+verbose. The following command should be used to obtain help about the tool:
+
+.. code:: shell
+
+    ./tools/cert_create/cert_create -h
+
+.. _tools_build_enctool:
+
+Building the Firmware Encryption Tool
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``encrypt_fw`` tool is built as part of the TF-A build process when the
+``fip`` make target is specified, DECRYPTION_SUPPORT and TBB are enabled, but
+it can also be built separately with the following command:
+
+.. code:: shell
+
+    make PLAT=<platform> [DEBUG=1] [V=1] enctool
+
+``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
+verbose. The following command should be used to obtain help about the tool:
+
+.. code:: shell
+
+    ./tools/encrypt_fw/encrypt_fw -h
+
+Note that the enctool in its current implementation only supports encryption
+key to be provided in plain format. A typical implementation can very well
+extend this tool to support custom techniques to protect encryption key.
+
+Also, a user may choose to provide encryption key or nonce as an input file
+via using ``cat <filename>`` instead of a hex string.
+
+--------------
+
+*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
+
+.. _Trusted Firmware-A Tests: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/
+.. _TFTF documentation: https://trustedfirmware-a-tests.readthedocs.io/en/latest/