Updating prebuilts and/or headers

600af606544528acefdcda1ac9360385c7fb445e - nvbuild.sh
ad7dc8da66a1a95925c5d25352922f3878707e31 - nvcommon_build.sh
0907bfcdbb17c8012151b65666827033c895982c - arm-trusted-firmware.t234/package-lock.json
0014850d17c6d073452c1de344bf3e5e48c3ff1a - arm-trusted-firmware.t234/Makefile
7f3fadaf80e3c4745d24cb1a5881c7c5f4d898ba - arm-trusted-firmware.t234/.checkpatch.conf
584715f8f3c3f87ea97b9b3da77cdc7c576262bc - arm-trusted-firmware.t234/.nspect-allowlist.toml
ace10cf6c86db4d397dce5eb15be3904f60c70f9 - arm-trusted-firmware.t234/.readthedocs.yaml
e7b6512c235c4956d5e5c54a1bba110101ee7219 - arm-trusted-firmware.t234/poetry.lock
3b07f1cc18499c3a94f20780855567ecbb2406a0 - arm-trusted-firmware.t234/.commitlintrc.js
4bdcaddad6efc78faa2c744a8179fe2b722d1745 - arm-trusted-firmware.t234/readme.rst
58ac0e2c4882938ac294f7180d8d372c1a23c60c - arm-trusted-firmware.t234/.versionrc.cjs
4a2bf00f1f07dd12abeef076606cbbb954f22aa8 - arm-trusted-firmware.t234/package.json
459346b6306a9ab8abdbbc9bab327a65d5c0bd4a - arm-trusted-firmware.t234/.cz-adapter.cjs
2d62a7583b85631859c4143f08e0dc332e1cb87e - arm-trusted-firmware.t234/.gitreview
96d71bc7e0063a06f7a82508b968b73a54857d0d - arm-trusted-firmware.t234/.editorconfig
6b4f543445bf3b97440b6828e63b2efae8cc5d48 - arm-trusted-firmware.t234/pyproject.toml
d8da3627085908a5f974b45528b85dc0a41a8b75 - arm-trusted-firmware.t234/license.rst
c5b6edb1f19eb7b57761adc898d9906ccf9f5593 - arm-trusted-firmware.t234/OWNERS
dcbcc9dad91ad237daae72ab81613fa540d989ec - arm-trusted-firmware.t234/.cz.json
b509c8a6f834e67a07b5eb787d0c2f5e7c8f0ab7 - arm-trusted-firmware.t234/.ctags
693d8edcd6f6e57cb33293e518fc9f017e953dc8 - arm-trusted-firmware.t234/.nvmrc
89e8f1fd50ac707f0dcb450575a69bf86eba15d7 - arm-trusted-firmware.t234/changelog.yaml
c16e3571ab87b0ea9f8067989a5b0f97251ff8cb - arm-trusted-firmware.t234/lib/libfdt/fdt_wip.c
ea823073be5d673a06dfad272a7582df4482b150 - arm-trusted-firmware.t234/lib/libfdt/fdt_ro.c
fdf423cffe52c2e918c815f60c8bea0d7f7c8d70 - arm-trusted-firmware.t234/lib/libfdt/fdt_overlay.c
d2dc4f22a3f4d18e90f3c200fc9236e910900b67 - arm-trusted-firmware.t234/lib/libfdt/fdt_rw.c
0c0bc4ae346c1591ec8aa09a444d3aeaa3d210fb - arm-trusted-firmware.t234/lib/libfdt/fdt.c
e01b7a0052b837a4650f2c9ac75ad38c40edc583 - arm-trusted-firmware.t234/lib/libfdt/fdt_empty_tree.c
1888e43d0d65ec169628a14ff94eb9d06adb47b2 - arm-trusted-firmware.t234/lib/libfdt/fdt_strerror.c
71e3b9e723c948c08594cfa38c65a708d0ab7f88 - arm-trusted-firmware.t234/lib/libfdt/fdt_sw.c
a9e7388adeea4bb813155c62caacc545e9e98bfc - arm-trusted-firmware.t234/lib/libfdt/libfdt_internal.h
282524cbc0a8f7d16c36b9954bb4fad4c0d76c0a - arm-trusted-firmware.t234/lib/libfdt/fdt_addresses.c
90037639cf8fb4c81695f9d8aa4f15ee05af1b0d - arm-trusted-firmware.t234/lib/pmf/pmf_main.c
748a73855a307a23e9042a2467fd508bcc7e2719 - arm-trusted-firmware.t234/lib/pmf/pmf_smc.c
8102f862edb5ab07783993999c8781385e261628 - arm-trusted-firmware.t234/lib/debugfs/dev.c
78982645d4d3008984c9307ee68bfa8eeb1a43a7 - arm-trusted-firmware.t234/lib/debugfs/blobs.h
db9f0e301c7178c315a1c6e72358bae572ce85db - arm-trusted-firmware.t234/lib/debugfs/devfip.c
678b679be4c3816d85eb8d851b7f46b7393739a2 - arm-trusted-firmware.t234/lib/debugfs/debugfs_smc.c
9802d55cbbaff09010b37afad6d494d8e755eae2 - arm-trusted-firmware.t234/lib/debugfs/devroot.c
5260672b27f35a4368d3be1f6ee66ec91d4beb26 - arm-trusted-firmware.t234/lib/debugfs/dev.h
7c85c537adcb24f5e03d6c71424a2618815086e3 - arm-trusted-firmware.t234/lib/debugfs/devc.c
b686543bed166afb322167276d451afec04adc59 - arm-trusted-firmware.t234/lib/romlib/Makefile
481822cc2e7c15342af97aee4d6a88357f33ef86 - arm-trusted-firmware.t234/lib/romlib/romlib_generator.py
eb057f1c025e3c00715bfc73c35c4550fba204ce - arm-trusted-firmware.t234/lib/romlib/jmptbl.i
84d815be083f637cd9f96c31d1fddf3042e11b9a - arm-trusted-firmware.t234/lib/romlib/romlib.ld.S
d558c9ec1044a052e3ae32d32fa5e185b31bc800 - arm-trusted-firmware.t234/lib/romlib/gen_combined_bl1_romlib.sh
bb10bb4fd88d1ee33bbcbdc3fe783aeea6421835 - arm-trusted-firmware.t234/lib/romlib/init.s
b022feb15f3e84d4eefd318657af38a3a523e363 - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_entry_function_bti.S
56fc8c8a2950a0303783ced6bd0e388176043a47 - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_entry_function.S
0e6c307caa236b447ebce1b8530688dc19799210 - arm-trusted-firmware.t234/lib/romlib/templates/wrapper_bti.S
91d0e6f060cd659ba73d0db8886497a823814c65 - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_entry_reserved_bti.S
fa26b89e848f7affd6fd3be71153b55961fbf971 - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_glob_var.S
8bd9f16af17fc4a81e921654d50217d6ba334d4f - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_header.S
f9c9050fd5c89b246d718f406a9d9a13f3388a5e - arm-trusted-firmware.t234/lib/romlib/templates/jmptbl_entry_reserved.S
0598d43a54d46872be6b5e9f5a8b45597813d4ae - arm-trusted-firmware.t234/lib/romlib/templates/wrapper.S
18fdfde595d6c7a6409f3d91382d81f736bf775d - arm-trusted-firmware.t234/lib/fconf/fconf_mpmm_getter.c
eb04a6d9ab9c6c79abc707068733945ca7ea49e4 - arm-trusted-firmware.t234/lib/fconf/fconf_dyn_cfg_getter.c
792d27179cb94886b8e3d403c6e11c05bdda0a57 - arm-trusted-firmware.t234/lib/fconf/fconf_cot_getter.c
a56e2c964f2491dc1846e59e1e802dcb4e62944e - arm-trusted-firmware.t234/lib/fconf/fconf.c
9ad7e79093e5a9eee5c2b34fbfcef507564686b9 - arm-trusted-firmware.t234/lib/fconf/fconf_tbbr_getter.c
3567bc768ff2f143e4933244eb221b010bd91f80 - arm-trusted-firmware.t234/lib/fconf/fconf_amu_getter.c
cb401a0f792df9b95c613f8dbc7bd40e4a954578 - arm-trusted-firmware.t234/lib/locks/exclusive/aarch64/spinlock.S
5578b09675f79e87026c64d8253ca469bed1c0da - arm-trusted-firmware.t234/lib/locks/exclusive/aarch32/spinlock.S
db66c79ee8bc7db859a7db3b8cdf21b572da1798 - arm-trusted-firmware.t234/lib/locks/bakery/bakery_lock_normal.c
c2b314d067fb125f7d7f77f2ad93b06398c43238 - arm-trusted-firmware.t234/lib/locks/bakery/bakery_lock_coherent.c
121d77395255b9b8a1089ac9f257e5123271a4a2 - arm-trusted-firmware.t234/lib/extensions/pmuv3/aarch64/pmuv3.c
c224a46a1b416397b079caa7481121ed6d03a41f - arm-trusted-firmware.t234/lib/extensions/pmuv3/aarch32/pmuv3.c
7b10cd2b968063a4101c0e4252133a1059d29904 - arm-trusted-firmware.t234/lib/extensions/mpam/mpam.c
38ababf4127a1ac92a31f9485dfd42fc17c66fde - arm-trusted-firmware.t234/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
4fc0f4b3fea6016c5d47f226751b006e7a17bc58 - arm-trusted-firmware.t234/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
19408c082672877fc4e00dc3281cc2de4162fe20 - arm-trusted-firmware.t234/lib/extensions/sve/sve.c
69b9b55a68a218bedfb7e02f5620c395cfee184f - arm-trusted-firmware.t234/lib/extensions/trbe/trbe.c
48250a5aa4f7c0033c2614e34a070c2e85615896 - arm-trusted-firmware.t234/lib/extensions/spe/spe.c
ebe5066f50de32f019ea11419b6ef11da4604812 - arm-trusted-firmware.t234/lib/extensions/pauth/pauth_helpers.S
3c13274221c18d09899b7e8d8be37e88e2adba23 - arm-trusted-firmware.t234/lib/extensions/tcr/tcr2.c
dfebf62e45987649a709947042771374f897ccb1 - arm-trusted-firmware.t234/lib/extensions/sme/sme.c
6c920523169ecc73baa0b1836746513d12e87ee4 - arm-trusted-firmware.t234/lib/extensions/debug/debugv8p9.c
03582f2ba83c81eb87dadb3331f89bd1eb2db334 - arm-trusted-firmware.t234/lib/extensions/trf/aarch64/trf.c
bc3797c909ca4ec52ec4784ab67d73e9096a351e - arm-trusted-firmware.t234/lib/extensions/trf/aarch32/trf.c
1ee17fe9c431bda9d612efde5b701a6e51665f5c - arm-trusted-firmware.t234/lib/extensions/sysreg128/sysreg128.S
f063c227afb0e9bcf6c77f5a85108129438106c2 - arm-trusted-firmware.t234/lib/extensions/brbe/brbe.c
df6d90a9554d7a2e8872622c900dd69db242efad - arm-trusted-firmware.t234/lib/extensions/fgt/fgt2.c
1af38f4d9fcd54c0328c896c8b154ee6f996728c - arm-trusted-firmware.t234/lib/extensions/amu/amu_private.h
b7c59535736596f6c096a74b33ecc50269cf6d8d - arm-trusted-firmware.t234/lib/extensions/amu/aarch64/amu.c
f97f9c6e3eeb0054517b2b9f0758a32468a9a9f3 - arm-trusted-firmware.t234/lib/extensions/amu/aarch64/amu_helpers.S
8d9a850eda16f822a2da9e30317ebd0eac347311 - arm-trusted-firmware.t234/lib/extensions/amu/aarch32/amu.c
2d632b20837314c97922e2f7a2156de2cde88c8b - arm-trusted-firmware.t234/lib/extensions/amu/aarch32/amu_helpers.S
9bbf285e5fb015b4281d9989bf1f5cdefe96cec0 - arm-trusted-firmware.t234/lib/extensions/fpmr/fpmr.c
ad3316abca20d34d7293aac76cbfc64ce9a5c012 - arm-trusted-firmware.t234/lib/extensions/ras/std_err_record.c
4616f57dc89bb192f724bb4d34ae9e7f516e4b8a - arm-trusted-firmware.t234/lib/extensions/ras/ras_common.c
2e0b4a8eb4d69373e109f9be1a02cc409b3b9068 - arm-trusted-firmware.t234/lib/el3_runtime/simd_ctx.c
9a20231094ee9cab4a2435987bdc2aebcf9b89dd - arm-trusted-firmware.t234/lib/el3_runtime/cpu_data_array.c
925b7522c8a43da8c48b93d665e4f89b18059b4d - arm-trusted-firmware.t234/lib/el3_runtime/aarch64/context.S
7823e00fc8ac59a91343911721874f34edaee500 - arm-trusted-firmware.t234/lib/el3_runtime/aarch64/context_mgmt.c
b248c2857449f37281505ffc12499e7ce94f2ee8 - arm-trusted-firmware.t234/lib/el3_runtime/aarch64/cpu_data.S
d19f573e44d900281f2785adec1a4c5369b328e7 - arm-trusted-firmware.t234/lib/el3_runtime/aarch64/context_debug.c
a7d92facc0752c0840fcbee6f90f691658918f04 - arm-trusted-firmware.t234/lib/el3_runtime/aarch32/context_mgmt.c
dcb9b7147ff211c4c3bfc81afa41e26753797fe1 - arm-trusted-firmware.t234/lib/el3_runtime/aarch32/cpu_data.S
06f4bc9f41eeaa4be122a19cd6ff5105ff5b3666 - arm-trusted-firmware.t234/lib/psa/measured_boot_private.h
b577cd6b4f9481795aa38bdba16a06d556c005cd - arm-trusted-firmware.t234/lib/psa/rse_platform.c
eee36c863935c30bfe8c8d97e575bf298df49235 - arm-trusted-firmware.t234/lib/psa/dice_protection_environment.c
be57ec731ef978a1cb592ddcd54df181cf3854bd - arm-trusted-firmware.t234/lib/psa/cca_attestation.c
98ec93022cebd1d2bfafa3f6f1754aac502f039e - arm-trusted-firmware.t234/lib/psa/delegated_attestation.c
ded7da36471dba8afc5a2ee5c7cd83017358a01a - arm-trusted-firmware.t234/lib/psa/measured_boot.c
461f0e6549aecb25a42e26daa4990367b0c0349e - arm-trusted-firmware.t234/lib/stack_protector/stack_protector.c
4f46a17dd2d45cbfecc56cdc62335d16e7f8e9fd - arm-trusted-firmware.t234/lib/stack_protector/aarch64/asm_stack_protector.S
2a002a927728f82056d756fb1887d05d85bc76f1 - arm-trusted-firmware.t234/lib/stack_protector/aarch32/asm_stack_protector.S
5c0d29046bc86d69be79a8f490d15c6278e7c1bf - arm-trusted-firmware.t234/lib/xlat_tables/xlat_tables_common.c
ada03d858deab4a12708645a227784e1380cc81a - arm-trusted-firmware.t234/lib/xlat_tables/xlat_tables_private.h
bb74aa53a76cf8da53b1247c526a828eda4a1792 - arm-trusted-firmware.t234/lib/xlat_tables/aarch64/xlat_tables.c
6f6a68d4d740fe29efffe15b3f231637931603ca - arm-trusted-firmware.t234/lib/xlat_tables/aarch32/xlat_tables.c
35355a9c23c311ebb37e6654a0310fa8a186fd42 - arm-trusted-firmware.t234/lib/xlat_tables/aarch32/nonlpae_tables.c
1d272a148f99cc5bfa1d9d1f1d557138b845eb09 - arm-trusted-firmware.t234/lib/bl_aux_params/bl_aux_params.c
621d91c2abfb7ec906a3341bb6849212c0972fe0 - arm-trusted-firmware.t234/lib/semihosting/semihosting.c
1d3c306a7abd961df54876afd2f68397653a722d - arm-trusted-firmware.t234/lib/semihosting/aarch64/semihosting_call.S
96e457fca8175f03f288deb171768f7d390a2d85 - arm-trusted-firmware.t234/lib/semihosting/aarch32/semihosting_call.S
972bcfa9e5506820069f2681ecfc8724e161857c - arm-trusted-firmware.t234/lib/aarch64/cache_helpers.S
2c301ef78cf219d3946f1a0d8dea0fbb66b8710c - arm-trusted-firmware.t234/lib/aarch64/misc_helpers.S
7514c02332a91f81b01c38fab0c57628b5a1552e - arm-trusted-firmware.t234/lib/aarch64/armclang_printf.S
2935ae164681477772e886442e2e1addcfbb2157 - arm-trusted-firmware.t234/lib/libc/putchar.c
571f090fbb81f922731ecd747dc426eb612ec25b - arm-trusted-firmware.t234/lib/libc/strlen.c
edb57dde15d3376a064cceb642c2c2ea6cfc5659 - arm-trusted-firmware.t234/lib/libc/assert.c
82f54f160965b93a70dc958c51a0328ae0540956 - arm-trusted-firmware.t234/lib/libc/strncmp.c
b09d8dfbbff3c2a148e2323a97e5db8c3b864bab - arm-trusted-firmware.t234/lib/libc/memcmp.c
ecdb0573af2e72655f16bf065fbb5efe33c7cfbd - arm-trusted-firmware.t234/lib/libc/snprintf.c
be9487ae2df331c4b6d1e8eb831fe36f80300829 - arm-trusted-firmware.t234/lib/libc/strlcpy.c
ffb9b36696d1be240d6c300924b1b16f8b7d193a - arm-trusted-firmware.t234/lib/libc/memcpy.c
38a578098af152b953ec1c824f1abd335b84979e - arm-trusted-firmware.t234/lib/libc/abort.c
c72f1f1842a78fb427805c7447d370fc148dc89f - arm-trusted-firmware.t234/lib/libc/strtoul.c
8f8edbf780871676227a4f4130b3a9c718b3c64c - arm-trusted-firmware.t234/lib/libc/strcmp.c
da2d6f3d96f3b941a06349c46b943cce37ac6a6e - arm-trusted-firmware.t234/lib/libc/memchr.c
bacec6dd7a3b9e28603e5cfd058756eab0f892af - arm-trusted-firmware.t234/lib/libc/memmove.c
c09671253fa56542c6aa0c9bb84abbd6e6b2306d - arm-trusted-firmware.t234/lib/libc/memcpy_s.c
8c9668a348c3ffbe4509aa2246941450a7b0de00 - arm-trusted-firmware.t234/lib/libc/strtoll.c
359ff50d6cb3845b71124e0ca9942745bda9e2c5 - arm-trusted-firmware.t234/lib/libc/memset.c
8172487e3b3f801cb06d4e60707f53c4d77b483f - arm-trusted-firmware.t234/lib/libc/strchr.c
07dbfb512cae53c03504d60ec4b02bfc74c2af8a - arm-trusted-firmware.t234/lib/libc/strtol.c
82032c79de7b24a84341c8bd5d72baba75337f1e - arm-trusted-firmware.t234/lib/libc/strtoull.c
6d62f8972d334e9b7016abfa5fd60039fd045392 - arm-trusted-firmware.t234/lib/libc/strlcat.c
c64e54b9d37e79c6a5ddf5440518980b4d8023d6 - arm-trusted-firmware.t234/lib/libc/strrchr.c
06782e2bb8b5e2b70cd089f061be9c1a08621523 - arm-trusted-firmware.t234/lib/libc/memrchr.c
e7eb31dbd9893d98f8ab6cbef6a11143aa052581 - arm-trusted-firmware.t234/lib/libc/strtok.c
b4e1859698344300f46b5b4523efb8e7a22c5e3d - arm-trusted-firmware.t234/lib/libc/printf.c
9004bf8bc547abf250c43d48b20ee66119a0f325 - arm-trusted-firmware.t234/lib/libc/exit.c
cdc60a84cbcd4ae8a4fd73df6250ad538db0668a - arm-trusted-firmware.t234/lib/libc/strnlen.c
83b77c3ae8eca3bf7da4de83d82fa7b0edeff85a - arm-trusted-firmware.t234/lib/libc/puts.c
02977fbcda3d55ed39cafa721d2bd2a901f0c637 - arm-trusted-firmware.t234/lib/libc/aarch64/memset.S
e450aea2c775f055c707f053de39e7aa7ed66223 - arm-trusted-firmware.t234/lib/libc/aarch64/setjmp.S
75786d0b78f57474b1c6f960b2c8ecbc07ba830b - arm-trusted-firmware.t234/lib/libc/aarch32/memset.S
14efe65532640ad904e16c0fcfdf2a0aa8ef7892 - arm-trusted-firmware.t234/lib/aarch32/cache_helpers.S
ee1a450f356e424a2bf60417432806e1c48e8b4b - arm-trusted-firmware.t234/lib/aarch32/misc_helpers.S
f3656db9134aa2171dd45f1a9678477dd7cd96e0 - arm-trusted-firmware.t234/lib/aarch32/armclang_printf.S
e99b439f92ab3e8025a95af724ddbf92e03bf8cb - arm-trusted-firmware.t234/lib/aarch32/arm32_aeabi_divmod.c
65adc9dcdcfda338ac28944b6d78e9022351ce50 - arm-trusted-firmware.t234/lib/aarch32/arm32_aeabi_divmod_a32.S
f19e7e7ffa2bd22a6e1d0cceeca043d433fa6681 - arm-trusted-firmware.t234/lib/cpus/errata_common.c
151b3b0184be16c7d540dc87a99bccaf4801776a - arm-trusted-firmware.t234/lib/cpus/errata_report.c
6f1b0a8a7e18b98e1d7cc25071e370266244a0b6 - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_x2.S
6460b029250d2f405f1b9e625811dde8aba049e1 - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_arcadia.S
bac60e2cdc71bd54539af3a40b00694b853b6833 - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_a710.S
773c971c7fab4197843edb566f6a123d7f53fa54 - arm-trusted-firmware.t234/lib/cpus/aarch64/nevis.S
80f25f36b7c8160af1b67386572ac6649901344e - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_x4.S
5a3fca8ad8ae38716f40b2ebc56014b27be7d133 - arm-trusted-firmware.t234/lib/cpus/aarch64/neoverse_v1.S
a7d88cc794b4858c93c50a30de80da12e8f69118 - arm-trusted-firmware.t234/lib/cpus/aarch64/cortex_a715.S
fd801851b71a05fbc5920f6815d5ab8025a7f156 - arm-trusted-firmware.t234/lib/cpus/aarch64/cpuamu.c
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222366fd88fa37c34896b96be4724020febaf122 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h
9cfa6b80558dac90724c830c7c2b792099232962 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld.S
249a2bba707f4aae60e76e4d2ca07180426f3657 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/m0/src/stopwatch.c
3832f35bf0192ab6299ed6f72d97ea798c64ec01 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/m0/src/dram.c
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912b3ac53149ee0912cdc571503cbe6f5d9e5e31 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/pwm/pwm.h
81bb90565c30ebb1d2a2074e665099c5df4b3f16 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/pwm/pwm.c
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1c5f6ab9e0780ba09fc4009303d8f48ca69ba0d0 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c
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341cf7780e76c0eed9bb587ced84821148eaeba4 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
27aa9609a5b7f4a133b52b7f298cef95b6b1332a - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/dram/suspend.c
8524ea750c376402a2c507655783fb69d6ca49af - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/soc/soc.c
d6f6a92953b02dda92949d05699b4a8c09ec1ab6 - arm-trusted-firmware.t234/plat/rockchip/rk3399/drivers/soc/soc.h
ef5a8ce281d95041b91f8f165ef782642d022de2 - arm-trusted-firmware.t234/plat/rockchip/px30/px30_def.h
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1b86970e6e211ba1548f3469a4682db7c31577f1 - arm-trusted-firmware.t234/plat/amlogic/common/aml_mhu.c
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2321fbf75d8e96d90a1b6f6a14160c91b949cabc - arm-trusted-firmware.t234/plat/amlogic/common/aml_scpi.c
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887d16c962bbfdec5ddb366c33ffec0ad5697447 - arm-trusted-firmware.t234/plat/amlogic/common/aml_thermal.c
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03a70925292deabd473bf5ffcd0d0d95dd70456e - arm-trusted-firmware.t234/plat/amlogic/g12a/g12a_pm.c
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495f096204283e82b03abed56414e3d1a29f9b6f - arm-trusted-firmware.t234/plat/amlogic/g12a/g12a_def.h
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3389361e87f5cd5e4f7e606599032c3aa3a41b72 - arm-trusted-firmware.t234/plat/amlogic/gxbb/gxbb_def.h
25d4db1b1e385a2e45f4ffea43edbfc8bf4fef89 - arm-trusted-firmware.t234/plat/amlogic/gxbb/gxbb_common.c
704885551348b4b44d9b7b092aafc3c54533b7e0 - arm-trusted-firmware.t234/plat/amlogic/gxbb/gxbb_bl31_setup.c
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550ec6753c2e8a5f41a920ea9bfffec47ae78dc8 - arm-trusted-firmware.t234/plat/amlogic/gxl/gxl_bl31_setup.c
5ce07f2865d514a3a8979c638337a338fa110f74 - arm-trusted-firmware.t234/plat/amlogic/gxl/gxl_pm.c
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22603b51918b7c1f721eee33d26629b16cff6683 - arm-trusted-firmware.t234/plat/amlogic/gxl/include/platform_def.h
0daa3a8c1ed607bfafc9ba0daa93d2de60c3c19e - arm-trusted-firmware.t234/plat/rpi/rpi5/rpi5_setup.c
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46c13e3cff3d9c29a733d01629589bd31b37eb5e - arm-trusted-firmware.t234/plat/rpi/common/rpi3_stack_protector.c
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42b3bec4b29977924bd7bf3da9ec372d1ec2dcd4 - arm-trusted-firmware.t234/plat/rpi/common/rpi3_console_dual.c
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6362652e60de8bcc5d723a13459a55c254c8d476 - arm-trusted-firmware.t234/plat/rpi/common/rpi3_console_pl011.c
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cd6861322dab161ff32b161e169f6666527d7c58 - arm-trusted-firmware.t234/plat/rpi/common/include/plat_macros.S
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cc26f2aa2450e40b407d6c6cf3b2930941104a04 - arm-trusted-firmware.t234/plat/rpi/rpi3/include/platform_def.h
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0c2b99bf230517b6436b54afd86f9249a3276d76 - arm-trusted-firmware.t234/plat/xilinx/versal_net/sip_svc_setup.c
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3d01d365783ad5b2ce0f76df72a4a10db3d9a10d - arm-trusted-firmware.t234/plat/nvidia/tegra/soc/t234/plat_memctrl.c
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c2cd522ab9668274cd7bf26fde63e9dbc9a94f28 - arm-trusted-firmware.t234/plat/nvidia/tegra/soc/t234/plat_secondary.c
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5c0dff5a31ce3b1ccbb934f961c94488e994ba83 - arm-trusted-firmware.t234/plat/nvidia/tegra/soc/t194/plat_ras.c
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41b9c96e4ffd9d51ef07345b13dbf173adf98260 - arm-trusted-firmware.t234/plat/ti/k3/common/k3_console.c
03c91a4b96c78e27b3534215550a85d2baef4a60 - arm-trusted-firmware.t234/plat/ti/k3/common/k3_bl31_setup.c
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65543dc7d9a840040d346b740384936551691526 - arm-trusted-firmware.t234/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
1cc8b5048759dec0cddaaca704360a5e02ff0387 - arm-trusted-firmware.t234/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
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c972344f8497be61b5561d1cf3e16a3a5d065403 - arm-trusted-firmware.t234/plat/ti/k3/board/lite/include/board_def.h
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dd19c5d97b6fda42cdf7822b9932b2c6bb7999de - arm-trusted-firmware.t234/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
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3dde76eb498c889851714b3d8e6749211c62bbec - arm-trusted-firmware.t234/plat/allwinner/sun50i_h6/include/sunxi_spc.h
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03001e5fa23515aba0765c130aad123367758776 - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/sunxi_h616_dtb.c
597c7d0e25492053936d68d62e433724f752b395 - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/sunxi_power.c
5f9c46257fffc11bc9cc33e4857e303df4ef68cb - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
3aedc81b7dac5e568253b5f0b546617d87eaee95 - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
3dde76eb498c889851714b3d8e6749211c62bbec - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/include/sunxi_spc.h
1590f260f1febbedf931a1596cea2d2e437ea92b - arm-trusted-firmware.t234/plat/allwinner/sun50i_h616/include/sunxi_ccu.h
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4fbea1d1c07593e4288cbf95ad006133a753832c - arm-trusted-firmware.t234/plat/allwinner/common/sunxi_pm.c
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704da3ea1b61d5106a6172712ecf6a80b1528bf0 - arm-trusted-firmware.t234/plat/allwinner/common/arisc_off.S
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0ded87657ff47f0fe5896f1ab1d6d2f9b34f0429 - arm-trusted-firmware.t234/plat/allwinner/common/plat_helpers.S
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0f08c32e56a3d49917e94d91f1f5e67ec04f1f8b - arm-trusted-firmware.t234/plat/allwinner/common/sunxi_cpu_ops.c
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1f3580c9b5753f5e99e173cffd6e713bce84d2f4 - arm-trusted-firmware.t234/plat/allwinner/common/include/sunxi_def.h
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3fa3a563994fcf2710324634950265fc8f9d7850 - arm-trusted-firmware.t234/plat/allwinner/sun50i_r329/sunxi_power.c
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1acbdb220cff8edffa7cc7fd4808f71574b90966 - arm-trusted-firmware.t234/plat/allwinner/sun50i_r329/include/sunxi_spc.h
2870bd5728ae0e5857fadde22b048a6fcf6ee2d3 - arm-trusted-firmware.t234/plat/allwinner/sun50i_r329/include/sunxi_ccu.h
33f9c2d61b7aa3242f22100ba2694ba2709f7a1b - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_topology.c
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1b333e35df79afc9319c45ded87fe22b1e5547fc - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_security.c
8b11d0569d254ee10c03b8e7dfaebf823b7b1746 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_bl_common.c
1dc25162c504805b378176ceb2a1fac39b8fa3e2 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_ddr.c
10b56da87c85a4ad254e8e25455c6fc119d4ee23 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_bl31_setup.c
1975a45f73616d0ceb03dab4a9397cbabc1e66ce - arm-trusted-firmware.t234/plat/hisilicon/hikey/hisi_pwrc.c
132b89dc419b19bfabb3eb2450a5e74317faea11 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_io_storage.c
b8ddcea3e66690f3932ae009921566fe249feccd - arm-trusted-firmware.t234/plat/hisilicon/hikey/hisi_pwrc_sram.S
126933334b9ebdde11859016f3bbcc6ac9bbef88 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hisi_mcu.c
0071214b6af7f5e24aa92d4e7849c79c3818ed05 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_bl2_setup.c
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0472150350a0f6a23e8750e0fe14991d176d1a04 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_bl1_setup.c
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5366b77beffc310cab412735a4e4f43185e171c6 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_image_load.c
0aace28e8f75168d13d7274d81f1f906cc1b2cae - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_rotpk.S
3f90b73f27ba47848db784621dd350e6a5ec54d9 - arm-trusted-firmware.t234/plat/hisilicon/hikey/hikey_tbbr.c
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31f012031e8dec3fe5dab7afc9ab89deffb7fe7c - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hi6220_regs_pmctrl.h
98509207554ab836b38f580d203793668061ce40 - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hisi_sip_svc.h
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5da379773f07f291d897ea36a13ac008c78bbbe4 - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hi6220_regs_pin.h
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c54b714045ab12cfcff4363f00ce94952a40e2d6 - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hikey_layout.h
659dfae8f25d18bef4e2ac3c9b2cc07bbd255dd4 - arm-trusted-firmware.t234/plat/hisilicon/hikey/include/hi6220_regs_acpu.h
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166469bcfd5bac8ca50e33d23d40607d532f7a9f - arm-trusted-firmware.t234/plat/hisilicon/poplar/bl1_plat_setup.c
942f440e430db3a0fb9bafcb2877fa0f2b2b2206 - arm-trusted-firmware.t234/plat/hisilicon/poplar/plat_topology.c
f74fcf80665ecffb4b4fe3402223e62b707c18ea - arm-trusted-firmware.t234/plat/hisilicon/poplar/bl31_plat_setup.c
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5366b77beffc310cab412735a4e4f43185e171c6 - arm-trusted-firmware.t234/plat/hisilicon/poplar/poplar_image_load.c
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fc3d37d2191841fe6bab5841f4be4e364cf919b1 - arm-trusted-firmware.t234/plat/hisilicon/hikey960/hikey960_io_storage.c
0f1a35cf03c46fa57303de1b14fd3ec9d83d2e72 - arm-trusted-firmware.t234/plat/hisilicon/hikey960/hikey960_bl2_setup.c
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95b3fdae0d8de2d798a10e56f7071e4aa4d3b854 - arm-trusted-firmware.t234/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
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9a52294343831155772b4411f11af6c989dbd182 - arm-trusted-firmware.t234/plat/marvell/armada/a8k/a80x0/mvebu_def.h
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3f6403fd39850e34f4c3bd674ccf8170f74af43d - arm-trusted-firmware.t234/plat/marvell/armada/a8k/common/plat_bl31_setup.c
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392f1834ac5b4679e9ae724c7cf1f3a20c0e566a - arm-trusted-firmware.t234/plat/marvell/armada/a8k/common/mss/mss_bl31_setup.c
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9acdf9fa5a506b13c376584f49b42a4f437af6c5 - arm-trusted-firmware.t234/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
4b2131b48e6b858b49e7e4d819172c5bc729f213 - arm-trusted-firmware.t234/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c
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3f70fd4dd52f090e5e86093abe02a4f90c8f4353 - arm-trusted-firmware.t234/plat/marvell/armada/a3k/common/cm3_system_reset.c
4e66aa51fabafab21b8e01fa4f3d49fc8fe6a97e - arm-trusted-firmware.t234/plat/marvell/armada/a3k/common/a3700_sip_svc.c
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5ce8b4638274f9c66287b2f3662bb0bfcfc00074 - arm-trusted-firmware.t234/plat/marvell/armada/a3k/common/a3700_ea.c
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344f94187e37e08b2f532eb66281e7e28e7702c5 - arm-trusted-firmware.t234/plat/marvell/armada/a3k/common/io_addr_dec.c
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29d5aa4597a4a5d917e61847ae451ff6ab6894d5 - arm-trusted-firmware.t234/plat/arm/common/arm_transfer_list.c
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0ba5633b7ee65a26daba781e30eed64d4238eca8 - arm-trusted-firmware.t234/plat/arm/common/arm_bl1_setup.c
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310f5212c93492a9ca17bbf110947773178b8581 - arm-trusted-firmware.t234/plat/arm/common/fconf/arm_fconf_sp.c
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2147b3c541e549d0bc01f00aed57c924d90d6003 - arm-trusted-firmware.t234/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
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5562bd387d6506e0db4a62fe23b24cd1c5046754 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
151a77208d20281181da91b2119b75c4de526102 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
1e7fe4ccc25d366dfe5f6a14851dab68001bdb13 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/corstone1000_topology.c
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205b4ca0cb05e33669284a62b9c25f52ece1b8e9 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/corstone1000_pm.c
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16e3686521725b2e8cf355c2d990811fc260a02c - arm-trusted-firmware.t234/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
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70913ecf05a6e846d99d63213b643de746a371e8 - arm-trusted-firmware.t234/plat/arm/board/corstone1000/include/plat_macros.S
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846d7f92ffe6c368d0d0b85ffa36409b0dd04caf - arm-trusted-firmware.t234/plat/arm/board/morello/morello_trusted_boot.c
3fcdf0172f72867955ed0a4642a76273495b9e0e - arm-trusted-firmware.t234/plat/arm/board/morello/morello_def.h
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5457ec463cc8a966e6b179d42b57efbe3129da4b - arm-trusted-firmware.t234/plat/arm/board/morello/morello_bl2_setup.c
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0105670429d8a205bc698cf69de09044501a55a1 - arm-trusted-firmware.t234/plat/arm/board/morello/morello_topology.c
42659a5e25bf580b3f178c1c4fe693c1ff420253 - arm-trusted-firmware.t234/plat/arm/board/morello/morello_bl31_setup.c
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1c3ff5d4d35a2aa211380dea2b252236f3dae0b1 - arm-trusted-firmware.t234/plat/arm/board/morello/aarch64/morello_helper.S
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3d1a55d785180dd11beb8473207268d04543695a - arm-trusted-firmware.t234/plat/arm/board/corstone700/common/corstone700_helpers.S
5f0ac09b373c85fd1d635fb4f06ea45011389b19 - arm-trusted-firmware.t234/plat/arm/board/corstone700/common/corstone700_topology.c
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0fa67a9e3baade23364e588643149159b41d951b - arm-trusted-firmware.t234/plat/arm/board/fvp_r/fvp_r_debug.S
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181e66fa9c41732917a323ee0fe465da3b5ce36d - arm-trusted-firmware.t234/plat/arm/board/fvp_r/fvp_r_stack_protector.c
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5f78d5ae0c4547371279bfc19196f01fb454e3b6 - arm-trusted-firmware.t234/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c
cb1a2983e1ba147d7e3cce2b7b48cd124ba55bd7 - arm-trusted-firmware.t234/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
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25ba9f0211c95d3e0145319f7018f2e2f8d6986c - arm-trusted-firmware.t234/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c
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512907ac88f5504ffcd2a9ea58bc0da3cae848c3 - arm-trusted-firmware.t234/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c
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5a7431e547b27575f2c9ca5a43bd106fd4705ed6 - arm-trusted-firmware.t234/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h
af1f8d5af2ee91ba0dd180c42a7b8f73b7543474 - arm-trusted-firmware.t234/plat/arm/board/fvp_ve/fvp_ve_security.c
4a175994a02eeb79a8ccc76f0b3be5ac2d45771d - arm-trusted-firmware.t234/plat/arm/board/fvp_ve/fvp_ve_private.h
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4a689338afdb70548a3c2d1adce2b5c8c1083e5d - arm-trusted-firmware.t234/plat/arm/board/fvp_ve/include/platform_def.h
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2ff5ebca71b32318bae21e3dbb7699236b9cbe61 - arm-trusted-firmware.t234/plat/arm/board/fvp_ve/aarch32/fvp_ve_helpers.S
1f68f4b41cf660f6aecbd9c91cffd25b5da791a9 - arm-trusted-firmware.t234/plat/arm/board/tc/tc_err.c
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4a9977f4650713d7e5e1dd060919eef4e2b41575 - arm-trusted-firmware.t234/plat/arm/board/tc/nv_counter_test.c
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1be9df9e373623ca11c2f078fb14545de995067b - arm-trusted-firmware.t234/plat/arm/css/common/css_bl2_setup.c
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4b776badf454a3bcf0cc1524d1b63fd9871f6c8c - arm-trusted-firmware.t234/bl2/bl2_el3.ld.S
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2534665e628b7612c3896fed4e659f3351601296 - arm-trusted-firmware.t234/bl2/aarch32/bl2_arch_setup.c

Change-Id: I806f8c263557ca545fbd1f91da80741a3e098cbd

arm-trusted-firmware.t234/docs/security_advisories/index.rst

@@ -0,0 +1,18 @@
+Security Advisories
+===================
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Contents
+
+   security-advisory-tfv-1.rst
+   security-advisory-tfv-2.rst
+   security-advisory-tfv-3.rst
+   security-advisory-tfv-4.rst
+   security-advisory-tfv-5.rst
+   security-advisory-tfv-6.rst
+   security-advisory-tfv-7.rst
+   security-advisory-tfv-8.rst
+   security-advisory-tfv-9.rst
+   security-advisory-tfv-10.rst
+   security-advisory-tfv-11.rst

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-1.rst

@@ -0,0 +1,162 @@
+Advisory TFV-1 (CVE-2016-10319)
+===============================
+
++----------------+-------------------------------------------------------------+
+| Title          | Malformed Firmware Update SMC can result in copy of         |
+|                | unexpectedly large data into secure memory                  |
++================+=============================================================+
+| CVE ID         | `CVE-2016-10319`_                                           |
++----------------+-------------------------------------------------------------+
+| Date           | 18 Oct 2016                                                 |
++----------------+-------------------------------------------------------------+
+| Versions       | v1.2 and v1.3 (since commit `48bfb88`_)                     |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | Platforms that use AArch64 BL1 plus untrusted normal world  |
+| Affected       | firmware update code executing before BL31                  |
++----------------+-------------------------------------------------------------+
+| Impact         | Copy of unexpectedly large data into the free secure memory |
+|                | reported by BL1 platform code                               |
++----------------+-------------------------------------------------------------+
+| Fix Version    | `Pull Request #783`_                                        |
++----------------+-------------------------------------------------------------+
+| Credit         | IOActive                                                    |
++----------------+-------------------------------------------------------------+
+
+Generic Trusted Firmware (TF) BL1 code contains an SMC interface that is briefly
+available after cold reset to support the Firmware Update (FWU) feature (also
+known as recovery mode). This allows most FWU functionality to be implemented in
+the normal world, while retaining the essential image authentication
+functionality in BL1. When cold boot reaches the EL3 Runtime Software (for
+example, BL31 on AArch64 systems), the FWU SMC interface is replaced by the EL3
+Runtime SMC interface. Platforms may choose how much of this FWU functionality
+to use, if any.
+
+The BL1 FWU SMC handling code, currently only supported on AArch64, contains
+several vulnerabilities that may be exploited when *all* the following
+conditions apply:
+
+1. Platform code uses TF BL1 with the ``TRUSTED_BOARD_BOOT`` build option
+   enabled.
+
+2. Platform code arranges for untrusted normal world FWU code to be executed in
+   the cold boot path, before BL31 starts. Untrusted in this sense means code
+   that is not in ROM or has not been authenticated or has otherwise been
+   executed by an attacker.
+
+3. Platform code copies the insecure pattern described below from the ARM
+   platform version of ``bl1_plat_mem_check()``.
+
+The vulnerabilities consist of potential integer overflows in the input
+validation checks while handling the ``FWU_SMC_IMAGE_COPY`` SMC. The SMC
+implementation is designed to copy an image into secure memory for subsequent
+authentication, but the vulnerabilities may allow an attacker to copy
+unexpectedly large data into secure memory. Note that a separate vulnerability
+is required to leverage these vulnerabilities; for example a way to get the
+system to change its behaviour based on the unexpected secure memory contents.
+
+Two of the vulnerabilities are in the function ``bl1_fwu_image_copy()`` in
+``bl1/bl1_fwu.c``. These are listed below, referring to the v1.3 tagged version
+of the code:
+
+- Line 155:
+
+  .. code:: c
+
+    /*
+     * If last block is more than expected then
+     * clip the block to the required image size.
+     */
+    if (image_desc->copied_size + block_size >
+         image_desc->image_info.image_size) {
+        block_size = image_desc->image_info.image_size -
+            image_desc->copied_size;
+        WARN("BL1-FWU: Copy argument block_size > remaining image size."
+            " Clipping block_size\n");
+    }
+
+    /* Make sure the image src/size is mapped. */
+    if (bl1_plat_mem_check(image_src, block_size, flags)) {
+        WARN("BL1-FWU: Copy arguments source/size not mapped\n");
+        return -ENOMEM;
+    }
+
+    INFO("BL1-FWU: Continuing image copy in blocks\n");
+
+    /* Copy image for given block size. */
+    base_addr += image_desc->copied_size;
+    image_desc->copied_size += block_size;
+    memcpy((void *)base_addr, (const void *)image_src, block_size);
+    ...
+
+  This code fragment is executed when the image copy operation is performed in
+  blocks over multiple SMCs. ``block_size`` is an SMC argument and therefore
+  potentially controllable by an attacker. A very large value may result in an
+  integer overflow in the 1st ``if`` statement, which would bypass the check,
+  allowing an unclipped ``block_size`` to be passed into
+  ``bl1_plat_mem_check()``. If ``bl1_plat_mem_check()`` also passes, this may
+  result in an unexpectedly large copy of data into secure memory.
+
+- Line 206:
+
+  .. code:: c
+
+    /* Make sure the image src/size is mapped. */
+    if (bl1_plat_mem_check(image_src, block_size, flags)) {
+        WARN("BL1-FWU: Copy arguments source/size not mapped\n");
+        return -ENOMEM;
+    }
+
+    /* Find out how much free trusted ram remains after BL1 load */
+    mem_layout = bl1_plat_sec_mem_layout();
+    if ((image_desc->image_info.image_base < mem_layout->free_base) ||
+         (image_desc->image_info.image_base + image_size >
+          mem_layout->free_base + mem_layout->free_size)) {
+        WARN("BL1-FWU: Memory not available to copy\n");
+        return -ENOMEM;
+    }
+
+    /* Update the image size. */
+    image_desc->image_info.image_size = image_size;
+
+    /* Copy image for given size. */
+    memcpy((void *)base_addr, (const void *)image_src, block_size);
+    ...
+
+  This code fragment is executed during the 1st invocation of the image copy
+  operation. Both ``block_size`` and ``image_size`` are SMC arguments. A very
+  large value of ``image_size`` may result in an integer overflow in the 2nd
+  ``if`` statement, which would bypass the check, allowing execution to proceed.
+  If ``bl1_plat_mem_check()`` also passes, this may result in an unexpectedly
+  large copy of data into secure memory.
+
+If the platform's implementation of ``bl1_plat_mem_check()`` is correct then it
+may help prevent the above 2 vulnerabilities from being exploited. However, the
+ARM platform version of this function contains a similar vulnerability:
+
+- Line 88 of ``plat/arm/common/arm_bl1_fwu.c`` in function of
+  ``bl1_plat_mem_check()``:
+
+  .. code:: c
+
+    while (mmap[index].mem_size) {
+        if ((mem_base >= mmap[index].mem_base) &&
+            ((mem_base + mem_size)
+            <= (mmap[index].mem_base +
+            mmap[index].mem_size)))
+            return 0;
+
+        index++;
+    }
+    ...
+
+  This function checks that the passed memory region is within one of the
+  regions mapped in by ARM platforms. Here, ``mem_size`` may be the
+  ``block_size`` passed from ``bl1_fwu_image_copy()``. A very large value of
+  ``mem_size`` may result in an integer overflow and the function to incorrectly
+  return success. Platforms that copy this insecure pattern will have the same
+  vulnerability.
+
+.. _CVE-2016-10319: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2016-10319
+.. _48bfb88: https://github.com/ARM-software/arm-trusted-firmware/commit/48bfb88
+.. _Pull Request #783: https://github.com/ARM-software/arm-trusted-firmware/pull/783

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-10.rst

@@ -0,0 +1,159 @@
+Advisory TFV-10 (CVE-2022-47630)
+================================
+
++----------------+-------------------------------------------------------------+
+| Title          | Incorrect validation of X.509 certificate extensions can    |
+|                | result in an out-of-bounds read.                            |
++================+=============================================================+
+| CVE ID         | `CVE-2022-47630`_                                           |
++----------------+-------------------------------------------------------------+
+| Date           | Reported on 12 Dec 2022                                     |
++----------------+-------------------------------------------------------------+
+| Versions       | v1.2 to v2.8                                                |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | BL1 and BL2 with Trusted Boot enabled with custom,          |
+| Affected       | downstream usages of ``get_ext()`` and/or ``auth_nvctr()``  |
+|                | interfaces. Not exploitable in upstream TF-A code.          |
++----------------+-------------------------------------------------------------+
+| Impact         | Out-of-bounds read.                                         |
++----------------+-------------------------------------------------------------+
+| Fix Version    | - `fd37982a19a4a291`_ "fix(auth): forbid junk after         |
+|                |   extensions"                                               |
+|                |                                                             |
+|                | - `72460f50e2437a85`_ "fix(auth): require at least one      |
+|                |   extension to be present"                                  |
+|                |                                                             |
+|                | - `f5c51855d36e399e`_ "fix(auth): properly validate X.509   |
+|                |   extensions"                                               |
+|                |                                                             |
+|                | - `abb8f936fd0ad085`_ "fix(auth): avoid out-of-bounds read  |
+|                |   in auth_nvctr()"                                          |
+|                |                                                             |
+|                | Note that `72460f50e2437a85`_ is not fixing any             |
+|                | vulnerability per se but it is required for                 |
+|                | `f5c51855d36e399e`_ to apply cleanly.                       |
++----------------+-------------------------------------------------------------+
+| Credit         | Demi Marie Obenour, Invisible Things Lab                    |
++----------------+-------------------------------------------------------------+
+
+This security advisory describes a vulnerability in the X.509 parser used to
+parse boot certificates in TF-A trusted boot: it is possible for a crafted
+certificate to cause an out-of-bounds memory read.
+
+Note that upstream platforms are **not** affected by this. Only downstream
+platforms may be, if (and only if) the interfaces described below are used in a
+different context than seen in upstream code. Details of such context is
+described in the rest of this document.
+
+To fully understand this security advisory, it is recommended to refer to the
+following standards documents:
+
+ - `RFC 5280`_, *Internet X.509 Public Key Infrastructure Certificate and
+   Certificate Revocation List (CRL) Profile*.
+
+ - `ITU-T X.690`_, *ASN.1 encoding rules: Specification of Basic Encoding Rules
+   (BER), Canonical Encoding Rules (CER) and Distinguished Encoding Rules
+   (DER).*
+
+Bug 1: Insufficient certificate validation
+------------------------------------------
+
+The vulnerability lies in the following source file:
+``drivers/auth/mbedtls/mbedtls_x509_parser.c``. By design, ``get_ext()`` does
+not check the return value of the various ``mbedtls_*()`` functions, as
+``cert_parse()`` is assumed to have guaranteed that they will always succeed.
+However, it passes the end of an extension as the end pointer to these
+functions, whereas ``cert_parse()`` passes the end of the ``TBSCertificate``.
+Furthermore, ``cert_parse()`` does not check that the contents of the extension
+have the same length as the extension itself. It also does not check that the
+extension block extends to the end of the ``TBSCertificate``.
+
+This is a problem, as ``mbedtls_asn1_get_tag()`` leaves ``*p`` and ``*len``
+undefined on failure.  In practice, this results in ``get_ext()`` continuing to
+parse at different offsets than were used (and validated) by ``cert_parse()``,
+which means that the in-bounds guarantee provided by ``cert_parse()`` no longer
+holds.  The result is that it is possible for ``get_ext()`` to read memory past
+the end of the certificate.  This could potentially access memory with dangerous
+read side effects, or leak microarchitectural state that could theoretically be
+retrieved through some side-channel attacks as part of a more complex attack.
+
+Bug 2: Missing bounds check in ``auth_nvctr()``
+-----------------------------------------------
+``auth_nvctr()`` does not check that the buffer provided is
+long enough to hold an ``ASN.1 INTEGER``.  Since ``auth_nvctr()`` will only ever
+read 6 bytes, it is possible to read up to 6 bytes past the end of the buffer.
+
+Exploitability Analysis
+-----------------------
+
+Upstream TF-A Code
+~~~~~~~~~~~~~~~~~~
+
+In upstream TF-A code, the only caller of ``auth_nvctr()`` takes its input from
+``get_ext()``, which means that the second bug is exploitable, so is the first.
+Therefore, only the first bug need be considered.
+
+All standard chains of trust provided in TF-A source tree (that is, under
+``drivers/auth/``) require that the certificate's signature has already been
+validated prior to calling ``get_ext()``, or any function that calls ``get_ext()``.
+Platforms taking their chain of trust from a dynamic configuration file (such as
+``fdts/tbbr_cot_descriptors.dtsi``) are also safe, as signature verification will
+always be done prior to any calls to ``get_ext()`` or ``auth_nvctr()`` in this
+case, no matter the order of the properties in the file.  Therefore, it is not
+possible to exploit this vulnerability pre-authentication in upstream TF-A.
+
+Furthermore, the data read through ``get_ext()`` only
+ever gets used by the authentication framework (``drivers/auth/auth_mod.c``),
+which greatly reduces the range of inputs it will ever receive and thus the
+impact this has. Specifically, the authentication framework uses ``get_ext()``
+in three cases:
+
+ 1. Retrieving a hash from an X.509 certificate to check the integrity of a
+    child certificate (see ``auth_hash()``).
+
+ 2. Retrieving the signature details from an X.509 certificate to check its
+    authenticity and integrity (see ``auth_signature()``).
+
+ 3. Retrieving the security counter value from an X.509 certificate to protect
+    it from unauthorized rollback to a previous version (see ``auth_nvctr()``).
+
+None of these uses authentication framework write to the out-of-bounds memory,
+so no memory corruption is possible.
+
+In summary, there are 2 separate issues - one in ``get_ext()`` and another one
+in ``auth_nvctr()`` - but neither of these can be exploited in the context of
+TF-A upstream code.
+
+Only in the following 2 cases do we expect this vulnerability to be triggerable
+prior to authentication:
+
+ - The platform uses a custom chain of trust which uses the non-volatile counter
+   authentication method (``AUTH_METHOD_NV_CTR``) before the cryptographic
+   authentication method (``AUTH_METHOD_SIG``).
+
+ - The chain of trust uses a custom authentication method that calls
+   ``get_ext()`` before cryptographic authentication.
+
+Custom Image Parsers
+~~~~~~~~~~~~~~~~~~~~
+
+If the platform uses a custom image parser instead of the certificate parser,
+the bug in the certificate parser is obviously not relevant.  The bug in
+``auth_nvctr()`` *may* be relevant, but only if the returned data is:
+
+- Taken from an untrusted source (meaning that it is read prior to
+  authentication).
+
+- Not already checked to be a primitively-encoded ASN.1 tag.
+
+In particular, if the custom image parser implementation wraps a 32-bit integer
+in an ASN.1 ``INTEGER``, it is not affected.
+
+.. _CVE-2022-47630: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-47630
+.. _fd37982a19a4a291: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=fd37982a19a4a291
+.. _72460f50e2437a85: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=72460f50e2437a85
+.. _f5c51855d36e399e: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=f5c51855d36e399e
+.. _abb8f936fd0ad085: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=abb8f936fd0ad085
+.. _RFC 5280: https://www.ietf.org/rfc/rfc5280.txt
+.. _ITU-T X.690: https://www.itu.int/ITU-T/studygroups/com10/languages/X.690_1297.pdf

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-11.rst

@@ -0,0 +1,86 @@
+Advisory TFV-11 (CVE-2023-49100)
+================================
+
++----------------+-------------------------------------------------------------+
+| Title          | A Malformed SDEI SMC can cause out of bound memory read.    |
++================+=============================================================+
+| CVE ID         | `CVE-2023-49100`_                                           |
++----------------+-------------------------------------------------------------+
+| Date           | Reported on 12 Oct 2023                                     |
++----------------+-------------------------------------------------------------+
+| Versions       | TF-A releases v1.5 to v2.9                                  |
+| Affected       | LTS releases  lts-v2.8.0 to lts-v2.8.11                     |
++----------------+-------------------------------------------------------------+
+| Configurations | Platforms with SDEI support                                 |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Impact         | Denial of Service (secure world panic)                      |
++----------------+-------------------------------------------------------------+
+| Fix Version    | `a7eff3477`_ "fix(sdei): ensure that interrupt ID is valid" |
++----------------+-------------------------------------------------------------+
+| Credit         | Christian Lindenmeier `@_chli_`_                            |
+|                | Marcel Busch `@0ddc0de`_                                    |
+|                | `IT Security Infrastructures Lab`_                          |
++----------------+-------------------------------------------------------------+
+
+This security advisory describes a vulnerability in the SDEI services, where a
+rogue Non-secure caller invoking a SDEI_INTERRUPT_BIND SMC call with an invalid
+interrupt ID causes out of bound memory read.
+
+SDEI_INTERRUPT_BIND is used to bind any physical interrupt into a normal
+priority SDEI event. The interrupt can be a private peripheral interrupt
+(PPI) or a shared peripheral interrupt (SPI).
+Refer to SDEI_INTERRUPT_BIND in the `SDEI Specification`_ for further details.
+
+The vulnerability exists when the SDEI client passes an interrupt ID which
+is not implemented by the GIC. This will result in a data abort exception
+or a EL3 panic depending on the GIC version used in the system.
+
+- **GICv2 systems:**
+
+.. code:: c
+
+  Call stack:
+        sdei_interrupt_bind(interrupt ID)
+         -> plat_ic_get_interrupt_type(interrupt ID)
+           -> gicv2_get_interrupt_group(interrupt ID)
+             -> gicd_get_igroupr(distributor base, interrupt ID)
+               -> gicd_read_igroupr(distributor base, interrupt ID).
+
+  gicd_read_igroupr() will eventually do a MMIO read to an unimplemented IGROUPR
+  register. Which may cause a data abort or an access to a random EL3 memory region.
+
+- **GICv3 systems:**
+
+.. code:: c
+
+   Call stack:
+        sdei_interrupt_bind(interrupt ID)
+          -> plat_ic_get_interrupt_type(interrupt ID)
+            -> gicv3_get_interrupt_group(interrupt ID, core ID)
+              -> is_sgi_ppi(interrupt ID)
+
+   is_sgi_ppi() will end up in an EL3 panic on encountering an invalid interrupt ID.
+
+The vulnerability is fixed by ensuring that the Interrupt ID provided by the
+SDEI client is a valid PPI or SPI, otherwise return an error code indicating
+that the parameter is invalid.
+
+.. code:: c
+
+   /* Bind an SDEI event to an interrupt */
+   static int sdei_interrupt_bind(unsigned int intr_num)
+   {
+        sdei_ev_map_t *map;
+        bool retry = true, shared_mapping;
+
+        /* Interrupt must be either PPI or SPI */
+        if (!(plat_ic_is_ppi(intr_num) || plat_ic_is_spi(intr_num)))
+              return SDEI_EINVAL;
+
+.. _CVE-2023-49100: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2023-49100
+.. _a7eff3477: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=a7eff3477dcf3624c74f5217419b1a27b7ebd2aa
+.. _IT Security Infrastructures Lab: https://www.cs1.tf.fau.de/
+.. _SDEI Specification: https://developer.arm.com/documentation/den0054/latest/
+.. _@_chli_: https://twitter.com/_chli_
+.. _@0ddc0de: https://twitter.com/0ddc0de

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-2.rst

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+Advisory TFV-2 (CVE-2017-7564)
+==============================
+
++----------------+-------------------------------------------------------------+
+| Title          | Enabled secure self-hosted invasive debug interface can     |
+|                | allow normal world to panic secure world                    |
++================+=============================================================+
+| CVE ID         | `CVE-2017-7564`_                                            |
++----------------+-------------------------------------------------------------+
+| Date           | 02 Feb 2017                                                 |
++----------------+-------------------------------------------------------------+
+| Versions       | All versions up to v1.3                                     |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | All                                                         |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Impact         | Denial of Service (secure world panic)                      |
++----------------+-------------------------------------------------------------+
+| Fix Version    | 15 Feb 2017 `Pull Request #841`_                            |
++----------------+-------------------------------------------------------------+
+| Credit         | ARM                                                         |
++----------------+-------------------------------------------------------------+
+
+The ``MDCR_EL3.SDD`` bit controls AArch64 secure self-hosted invasive debug
+enablement. By default, the BL1 and BL31 images of the current version of ARM
+Trusted Firmware (TF) unconditionally assign this bit to ``0`` in the early
+entrypoint code, which enables debug exceptions from the secure world. This can
+be seen in the implementation of the ``el3_arch_init_common`` `AArch64 macro`_ .
+Given that TF does not currently contain support for this feature (for example,
+by saving and restoring the appropriate debug registers), this may allow a
+normal world attacker to induce a panic in the secure world.
+
+The ``MDCR_EL3.SDD`` bit should be assigned to ``1`` to disable debug exceptions
+from the secure world.
+
+Earlier versions of TF (prior to `commit 495f3d3`_) did not assign this bit.
+Since the bit has an architecturally ``UNKNOWN`` reset value, earlier versions
+may or may not have the same problem, depending on the platform.
+
+A similar issue applies to the ``MDCR_EL3.SPD32`` bits, which control AArch32
+secure self-hosted invasive debug enablement. TF assigns these bits to ``00``
+meaning that debug exceptions from Secure EL1 are enabled by the authentication
+interface. Therefore this issue only exists for AArch32 Secure EL1 code when
+secure privileged invasive debug is enabled by the authentication interface, at
+which point the device is vulnerable to other, more serious attacks anyway.
+
+However, given that TF contains no support for handling debug exceptions, the
+``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
+from AArch32 Secure EL1.
+
+Finally, this also issue applies to AArch32 platforms that use the TF SP_MIN
+image or integrate the `AArch32 equivalent`_ of the ``el3_arch_init_common``
+macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
+``10`` instead of ``00``
+
+.. _CVE-2017-7564: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-7564
+.. _commit 495f3d3: https://github.com/ARM-software/arm-trusted-firmware/commit/495f3d3
+.. _AArch64 macro: https://github.com/ARM-software/arm-trusted-firmware/blob/bcc2bf0/include/common/aarch64/el3_common_macros.S#L85
+.. _AArch32 equivalent: https://github.com/ARM-software/arm-trusted-firmware/blob/bcc2bf0/include/common/aarch32/el3_common_macros.S#L41
+.. _Pull Request #841: https://github.com/ARM-software/arm-trusted-firmware/pull/841

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-3.rst

@@ -0,0 +1,86 @@
+Advisory TFV-3 (CVE-2017-7563)
+==============================
+
++----------------+-------------------------------------------------------------+
+| Title          | RO memory is always executable at AArch64 Secure EL1        |
++================+=============================================================+
+| CVE ID         | `CVE-2017-7563`_                                            |
++----------------+-------------------------------------------------------------+
+| Date           | 06 Apr 2017                                                 |
++----------------+-------------------------------------------------------------+
+| Versions       | v1.3 (since `Pull Request #662`_)                           |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | AArch64 BL2, TSP or other users of xlat_tables library      |
+| Affected       | executing at AArch64 Secure EL1                             |
++----------------+-------------------------------------------------------------+
+| Impact         | Unexpected Privilege Escalation                             |
++----------------+-------------------------------------------------------------+
+| Fix Version    | `Pull Request #924`_                                        |
++----------------+-------------------------------------------------------------+
+| Credit         | ARM                                                         |
++----------------+-------------------------------------------------------------+
+
+The translation table library in ARM Trusted Firmware (TF) (under
+``lib/xlat_tables`` and ``lib/xlat_tables_v2``) provides APIs to help program
+translation tables in the MMU. The xlat\_tables client specifies its required
+memory mappings in the form of ``mmap_region`` structures.  Each ``mmap_region``
+has memory attributes represented by the ``mmap_attr_t`` enumeration type. This
+contains flags to control data access permissions (``MT_RO``/``MT_RW``) and
+instruction execution permissions (``MT_EXECUTE``/``MT_EXECUTE_NEVER``). Thus a
+mapping specifying both ``MT_RO`` and ``MT_EXECUTE_NEVER`` should result in a
+Read-Only (RO), non-executable memory region.
+
+This feature does not work correctly for AArch64 images executing at Secure EL1.
+Any memory region mapped as RO will always be executable, regardless of whether
+the client specified ``MT_EXECUTE`` or ``MT_EXECUTE_NEVER``.
+
+The vulnerability is known to affect the BL2 and Test Secure Payload (TSP)
+images on platforms that enable the ``SEPARATE_CODE_AND_RODATA`` build option,
+which includes all ARM standard platforms, and the upstream Xilinx and NVidia
+platforms. The RO data section for these images on these platforms is
+unexpectedly executable instead of non-executable. Other platforms or
+``xlat_tables`` clients may also be affected.
+
+The vulnerability primarily manifests itself after `Pull Request #662`_.  Before
+that, ``xlat_tables`` clients could not specify instruction execution
+permissions separately to data access permissions. All RO normal memory regions
+were implicitly executable. Before `Pull Request #662`_.  the vulnerability
+would only manifest itself for device memory mapped as RO; use of this mapping
+is considered rare, although the upstream QEMU platform uses this mapping when
+the ``DEVICE2_BASE`` build option is used.
+
+Note that one or more separate vulnerabilities are also required to exploit this
+vulnerability.
+
+The vulnerability is due to incorrect handling of the execute-never bits in the
+translation tables. The EL3 translation regime uses a single ``XN`` bit to
+determine whether a region is executable. The Secure EL1&0 translation regime
+handles 2 Virtual Address (VA) ranges and so uses 2 bits, ``UXN`` and ``PXN``.
+The ``xlat_tables`` library only handles the ``XN`` bit, which maps to ``UXN``
+in the Secure EL1&0 regime. As a result, this programs the Secure EL0 execution
+permissions but always leaves the memory as executable at Secure EL1.
+
+The vulnerability is mitigated by the following factors:
+
+- The xlat\_tables library ensures that all Read-Write (RW) memory regions are
+  non-executable by setting the ``SCTLR_ELx.WXN`` bit. This overrides any value
+  of the ``XN``, ``UXN`` or ``PXN`` bits in the translation tables. See the
+  ``enable_mmu()`` function:
+
+  ::
+
+      sctlr = read_sctlr_el##_el();               \
+      sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;       \
+
+- AArch32 configurations are unaffected. Here the ``XN`` bit controls execution
+  privileges of the currently executing translation regime, which is the desired
+  behaviour.
+
+- ARM TF EL3 code (for example BL1 and BL31) ensures that all non-secure memory
+  mapped into the secure world is non-executable by setting the ``SCR_EL3.SIF``
+  bit. See the ``el3_arch_init_common`` macro in ``el3_common_macros.S``.
+
+.. _CVE-2017-7563: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-7563
+.. _Pull Request #662: https://github.com/ARM-software/arm-trusted-firmware/pull/662
+.. _Pull Request #924: https://github.com/ARM-software/arm-trusted-firmware/pull/924

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-4.rst

@@ -0,0 +1,124 @@
+Advisory TFV-4 (CVE-2017-9607)
+==============================
+
++----------------+-------------------------------------------------------------+
+| Title          | Malformed Firmware Update SMC can result in copy or         |
+|                | authentication of unexpected data in secure memory in       |
+|                | AArch32 state                                               |
++================+=============================================================+
+| CVE ID         | `CVE-2017-9607`_                                            |
++----------------+-------------------------------------------------------------+
+| Date           | 20 Jun 2017                                                 |
++----------------+-------------------------------------------------------------+
+| Versions       | None (only between 22 May 2017 and 14 June 2017)            |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | Platforms that use AArch32 BL1 plus untrusted normal world  |
+| Affected       | firmware update code executing before BL31                  |
++----------------+-------------------------------------------------------------+
+| Impact         | Copy or authentication of unexpected data in the secure     |
+|                | memory                                                      |
++----------------+-------------------------------------------------------------+
+| Fix Version    | `Pull Request #979`_ (merged on 14 June 2017)               |
++----------------+-------------------------------------------------------------+
+| Credit         | ARM                                                         |
++----------------+-------------------------------------------------------------+
+
+The ``include/lib/utils_def.h`` header file provides the
+``check_uptr_overflow()`` macro, which aims at detecting arithmetic overflows
+that may occur when computing the sum of a base pointer and an offset. This
+macro evaluates to 1 if the sum of the given base pointer and offset would
+result in a value large enough to wrap around, which may lead to unpredictable
+behaviour.
+
+The macro code is at line 52, referring to the version of the code as of `commit
+c396b73`_:
+
+.. code:: c
+
+    /*
+     * Evaluates to 1 if (ptr + inc) overflows, 0 otherwise.
+     * Both arguments must be unsigned pointer values (i.e. uintptr_t).
+     */
+    #define check_uptr_overflow(ptr, inc)       \
+        (((ptr) > UINTPTR_MAX - (inc)) ? 1 : 0)
+
+This macro does not work correctly for AArch32 images. It fails to detect
+overflows when the sum of its two parameters fall into the ``[2^32, 2^64 - 1]``
+range. Therefore, any AArch32 code relying on this macro to detect such integer
+overflows is actually not protected.
+
+The buggy code has been present in ARM Trusted Firmware (TF) since `Pull Request
+#678`_ was merged (on 18 August 2016). However, the upstream code was not
+vulnerable until `Pull Request #939`_ was merged (on 22 May 2017), which
+introduced AArch32 support for the Trusted Board Boot (TBB) feature. Before
+then, the ``check_uptr_overflow()`` macro was not used in AArch32 code.
+
+The vulnerability resides in the BL1 FWU SMC handling code and it may be
+exploited when *all* the following conditions apply:
+
+- Platform code uses TF BL1 with the ``TRUSTED_BOARD_BOOT`` build option.
+
+- Platform code uses the Firmware Update (FWU) code provided in
+  ``bl1/bl1_fwu.c``, which is part of the TBB support.
+
+- TF BL1 is compiled with the ``ARCH=aarch32`` build option.
+
+In this context, the AArch32 BL1 image might fail to detect potential integer
+overflows in the input validation checks while handling the
+``FWU_SMC_IMAGE_COPY`` and ``FWU_SMC_IMAGE_AUTH`` SMCs.
+
+The ``FWU_SMC_IMAGE_COPY`` SMC handler is designed to copy an image into secure
+memory for subsequent authentication. This is implemented by the
+``bl1_fwu_image_copy()`` function, which has the following function prototype:
+
+.. code:: c
+
+     static int bl1_fwu_image_copy(unsigned int image_id,
+                        uintptr_t image_src,
+                        unsigned int block_size,
+                        unsigned int image_size,
+                        unsigned int flags)
+
+``image_src`` is an SMC argument and therefore potentially controllable by an
+attacker. A very large 32-bit value, for example ``2^32 -1``, may result in the
+sum of ``image_src`` and ``block_size`` overflowing a 32-bit type, which
+``check_uptr_overflow()`` will fail to detect.  Depending on its implementation,
+the platform-specific function ``bl1_plat_mem_check()`` might get defeated by
+these unsanitized values and allow the following memory copy operation, that
+would wrap around.  This may allow an attacker to copy unexpected data into
+secure memory if the memory is mapped in BL1's address space, or cause a fatal
+exception if it's not.
+
+The ``FWU_SMC_IMAGE_AUTH`` SMC handler is designed to authenticate an image
+resident in secure memory. This is implemented by the ``bl1_fwu_image_auth()``
+function, which has the following function prototype:
+
+.. code:: c
+
+    static int bl1_fwu_image_auth(unsigned int image_id,
+                        uintptr_t image_src,
+                        unsigned int image_size,
+                        unsigned int flags)
+
+Similarly, if an attacker has control over the ``image_src`` or ``image_size``
+arguments through the SMC interface and injects high values whose sum overflows,
+they might defeat the ``bl1_plat_mem_check()`` function and make the
+authentication module read data outside of what's normally allowed by the
+platform code or crash the platform.
+
+Note that in both cases, a separate vulnerability is required to leverage this
+vulnerability; for example a way to get the system to change its behaviour based
+on the unexpected secure memory accesses.  Moreover, the normal world FWU code
+would need to be compromised in order to send a malformed FWU SMC that triggers
+an integer overflow.
+
+The vulnerability is known to affect all ARM standard platforms when enabling
+the ``TRUSTED_BOARD_BOOT`` and ``ARCH=aarch32`` build options.  Other platforms
+may also be affected if they fulfil the above conditions.
+
+.. _CVE-2017-9607: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-9607
+.. _commit c396b73: https://github.com/ARM-software/arm-trusted-firmware/commit/c396b73
+.. _Pull Request #678: https://github.com/ARM-software/arm-trusted-firmware/pull/678
+.. _Pull Request #939: https://github.com/ARM-software/arm-trusted-firmware/pull/939
+.. _Pull Request #979: https://github.com/ARM-software/arm-trusted-firmware/pull/979

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-5.rst

@@ -0,0 +1,57 @@
+Advisory TFV-5 (CVE-2017-15031)
+===============================
+
++----------------+-------------------------------------------------------------+
+| Title          | Not initializing or saving/restoring ``PMCR_EL0`` can leak  |
+|                | secure world timing information                             |
++================+=============================================================+
+| CVE ID         | `CVE-2017-15031`_                                           |
++----------------+-------------------------------------------------------------+
+| Date           | 02 Oct 2017, updated on 04 Nov 2019                         |
++----------------+-------------------------------------------------------------+
+| Versions       | All, up to and including v2.1                               |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | All                                                         |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Impact         | Leakage of sensitive secure world timing information        |
++----------------+-------------------------------------------------------------+
+| Fix Version    | `Pull Request #1127`_ (merged on 18 October 2017)           |
+|                |                                                             |
+|                | `Commit e290a8fcbc`_ (merged on 23 August 2019)             |
+|                |                                                             |
+|                | `Commit c3e8b0be9b`_ (merged on 27 September 2019)          |
++----------------+-------------------------------------------------------------+
+| Credit         | Arm, Marek Bykowski                                         |
++----------------+-------------------------------------------------------------+
+
+The ``PMCR_EL0`` (Performance Monitors Control Register) provides details of the
+Performance Monitors implementation, including the number of counters
+implemented, and configures and controls the counters. If the ``PMCR_EL0.DP``
+bit is set to zero, the cycle counter (when enabled) counts during secure world
+execution, even when prohibited by the debug signals.
+
+Since TF-A does not save and restore ``PMCR_EL0`` when switching between the
+normal and secure worlds, normal world code can set ``PMCR_EL0.DP`` to zero to
+cause leakage of secure world timing information. This register should be added
+to the list of saved/restored registers both when entering EL3 and also
+transitioning to S-EL1.
+
+Furthermore, ``PMCR_EL0.DP`` has an architecturally ``UNKNOWN`` reset value.
+Since Arm TF does not initialize this register, it's possible that on at least
+some implementations, ``PMCR_EL0.DP`` is set to zero by default. This and other
+bits with an architecturally UNKNOWN reset value should be initialized to
+sensible default values in the secure context.
+
+The same issue exists for the equivalent AArch32 register, ``PMCR``, except that
+here ``PMCR_EL0.DP`` architecturally resets to zero.
+
+NOTE: The original pull request referenced above only fixed the issue for S-EL1
+whereas the EL3 was fixed in the later commits.
+
+.. _CVE-2017-15031: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-15031
+.. _Pull Request #1127: https://github.com/ARM-software/arm-trusted-firmware/pull/1127
+.. _Commit e290a8fcbc: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=e290a8fcbc
+.. _Commit c3e8b0be9b: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=c3e8b0be9b
+

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-6.rst

@@ -0,0 +1,148 @@
+Advisory TFV-6 (CVE-2017-5753, CVE-2017-5715, CVE-2017-5754)
+============================================================
+
++----------------+-------------------------------------------------------------+
+| Title          | Trusted Firmware-A exposure to speculative processor        |
+|                | vulnerabilities using cache timing side-channels            |
++================+=============================================================+
+| CVE ID         | `CVE-2017-5753`_ / `CVE-2017-5715`_ / `CVE-2017-5754`_      |
++----------------+-------------------------------------------------------------+
+| Date           | 03 Jan 2018 (Updated 11 Jan, 18 Jan, 26 Jan, 30 Jan and 07  |
+|                | June 2018)                                                  |
++----------------+-------------------------------------------------------------+
+| Versions       | All, up to and including v1.4                               |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | All                                                         |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Impact         | Leakage of secure world data to normal world                |
++----------------+-------------------------------------------------------------+
+| Fix Version    | `Pull Request #1214`_, `Pull Request #1228`_,               |
+|                | `Pull Request #1240`_ and `Pull Request #1405`_             |
++----------------+-------------------------------------------------------------+
+| Credit         | Google / Arm                                                |
++----------------+-------------------------------------------------------------+
+
+This security advisory describes the current understanding of the Trusted
+Firmware-A exposure to the speculative processor vulnerabilities identified by
+`Google Project Zero`_.  To understand the background and wider impact of these
+vulnerabilities on Arm systems, please refer to the `Arm Processor Security
+Update`_.
+
+Variant 1 (`CVE-2017-5753`_)
+----------------------------
+
+At the time of writing, no vulnerable patterns have been observed in upstream TF
+code, therefore no workarounds have been applied or are planned.
+
+Variant 2 (`CVE-2017-5715`_)
+----------------------------
+
+Where possible on vulnerable CPUs, Arm recommends invalidating the branch
+predictor as early as possible on entry into the secure world, before any branch
+instruction is executed. There are a number of implementation defined ways to
+achieve this.
+
+For Cortex-A57 and Cortex-A72 CPUs, the Pull Requests (PRs) in this advisory
+invalidate the branch predictor when entering EL3 by disabling and re-enabling
+the MMU.
+
+For Cortex-A73 and Cortex-A75 CPUs, the PRs in this advisory invalidate the
+branch predictor when entering EL3 by temporarily dropping into AArch32
+Secure-EL1 and executing the ``BPIALL`` instruction. This workaround is
+significantly more complex than the "MMU disable/enable" workaround. The latter
+is not effective at invalidating the branch predictor on Cortex-A73/Cortex-A75.
+
+Note that if other privileged software, for example a Rich OS kernel, implements
+its own branch predictor invalidation during context switch by issuing an SMC
+(to execute firmware branch predictor invalidation), then there is a dependency
+on the PRs in this advisory being deployed in order for those workarounds to
+work. If that other privileged software is able to workaround the vulnerability
+locally (for example by implementing "MMU disable/enable" itself), there is no
+such dependency.
+
+`Pull Request #1240`_ and `Pull Request #1405`_ optimise the earlier fixes by
+implementing a specified `CVE-2017-5715`_ workaround SMC
+(``SMCCC_ARCH_WORKAROUND_1``) for use by normal world privileged software. This
+is more efficient than calling an arbitrary SMC (for example ``PSCI_VERSION``).
+Details of ``SMCCC_ARCH_WORKAROUND_1`` can be found in the `CVE-2017-5715
+mitigation specification`_.  The specification and implementation also enable
+the normal world to discover the presence of this firmware service.
+
+On Juno R1 we measured the round trip latency for both the ``PSCI_VERSION`` and
+``SMCCC_ARCH_WORKAROUND_1`` SMCs on Cortex-A57, using both the "MMU
+disable/enable" and "BPIALL at AArch32 Secure-EL1" workarounds described above.
+This includes the time spent in test code conforming to the SMC Calling
+Convention (SMCCC) from AArch64. For the ``SMCCC_ARCH_WORKAROUND_1`` cases, the
+test code uses SMCCC v1.1, which reduces the number of general purpose registers
+it needs to save/restore. Although the ``BPIALL`` instruction is not effective
+at invalidating the branch predictor on Cortex-A57, the drop into Secure-EL1
+with MMU disabled that this workaround entails effectively does invalidate the
+branch predictor. Hence this is a reasonable comparison.
+
+The results were as follows:
+
++------------------------------------------------------------------+-----------+
+| Test                                                             | Time (ns) |
++==================================================================+===========+
+| ``PSCI_VERSION`` baseline (without PRs in this advisory)         | 515       |
++------------------------------------------------------------------+-----------+
+| ``PSCI_VERSION`` baseline (with PRs in this advisory)            | 527       |
++------------------------------------------------------------------+-----------+
+| ``PSCI_VERSION`` with "MMU disable/enable"                       | 930       |
++------------------------------------------------------------------+-----------+
+| ``SMCCC_ARCH_WORKAROUND_1`` with "MMU disable/enable"            | 386       |
++------------------------------------------------------------------+-----------+
+| ``PSCI_VERSION`` with "BPIALL at AArch32 Secure-EL1"             | 1276      |
++------------------------------------------------------------------+-----------+
+| ``SMCCC_ARCH_WORKAROUND_1`` with "BPIALL at AArch32 Secure-EL1"  | 770       |
++------------------------------------------------------------------+-----------+
+
+Due to the high severity and wide applicability of this issue, the above
+workarounds are enabled by default (on vulnerable CPUs only), despite some
+performance and code size overhead. Platforms can choose to disable them at
+compile time if they do not require them. `Pull Request #1240`_ disables the
+workarounds for unaffected upstream platforms.
+
+For vulnerable AArch32-only CPUs (for example Cortex-A8, Cortex-A9 and
+Cortex-A17), the ``BPIALL`` instruction should be used as early as possible on
+entry into the secure world. For Cortex-A8, also set ``ACTLR[6]`` to 1 during
+early processor initialization. Note that the ``BPIALL`` instruction is not
+effective at invalidating the branch predictor on Cortex-A15. For that CPU, set
+``ACTLR[0]`` to 1 during early processor initialization, and invalidate the
+branch predictor by performing an ``ICIALLU`` instruction.
+
+On AArch32 EL3 systems, the monitor and secure-SVC code is typically tightly
+integrated, for example as part of a Trusted OS. Therefore any Variant 2
+workaround should be provided by vendors of that software and is outside the
+scope of TF. However, an example implementation in the minimal AArch32 Secure
+Payload, ``SP_MIN`` is provided in `Pull Request #1228`_.
+
+Other Arm CPUs are not vulnerable to this or other variants. This includes
+Cortex-A76, Cortex-A53, Cortex-A55, Cortex-A32, Cortex-A7 and Cortex-A5.
+
+For more information about non-Arm CPUs, please contact the CPU vendor.
+
+Variant 3 (`CVE-2017-5754`_)
+----------------------------
+
+This variant is only exploitable between Exception Levels within the same
+translation regime, for example between EL0 and EL1, therefore this variant
+cannot be used to access secure memory from the non-secure world, and is not
+applicable for TF. However, Secure Payloads (for example, Trusted OS) should
+provide mitigations on vulnerable CPUs to protect themselves from exploited
+Secure-EL0 applications.
+
+The only Arm CPU vulnerable to this variant is Cortex-A75.
+
+.. _Google Project Zero: https://googleprojectzero.blogspot.co.uk/2018/01/reading-privileged-memory-with-side.html
+.. _Arm Processor Security Update: http://www.arm.com/security-update
+.. _CVE-2017-5753: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5753
+.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
+.. _CVE-2017-5754: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5754
+.. _Pull Request #1214: https://github.com/ARM-software/arm-trusted-firmware/pull/1214
+.. _Pull Request #1228: https://github.com/ARM-software/arm-trusted-firmware/pull/1228
+.. _Pull Request #1240: https://github.com/ARM-software/arm-trusted-firmware/pull/1240
+.. _Pull Request #1405: https://github.com/ARM-software/arm-trusted-firmware/pull/1405
+.. _CVE-2017-5715 mitigation specification: https://developer.arm.com/cache-speculation-vulnerability-firmware-specification

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-7.rst

@@ -0,0 +1,107 @@
+Advisory TFV-7 (CVE-2018-3639)
+==============================
+
++----------------+-------------------------------------------------------------+
+| Title          | Trusted Firmware-A exposure to cache speculation            |
+|                | vulnerability Variant 4                                     |
++================+=============================================================+
+| CVE ID         | `CVE-2018-3639`_                                            |
++----------------+-------------------------------------------------------------+
+| Date           | 21 May 2018 (Updated 7 June 2018)                           |
++----------------+-------------------------------------------------------------+
+| Versions       | All, up to and including v1.5                               |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | All                                                         |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Impact         | Leakage of secure world data to normal world                |
++----------------+-------------------------------------------------------------+
+| Fix Version    | `Pull Request #1392`_, `Pull Request #1397`_                |
++----------------+-------------------------------------------------------------+
+| Credit         | Google                                                      |
++----------------+-------------------------------------------------------------+
+
+This security advisory describes the current understanding of the Trusted
+Firmware-A (TF-A) exposure to Variant 4 of the cache speculation vulnerabilities
+identified by `Google Project Zero`_.  To understand the background and wider
+impact of these vulnerabilities on Arm systems, please refer to the `Arm
+Processor Security Update`_.
+
+At the time of writing, the TF-A project is not aware of a Variant 4 exploit
+that could be used against TF-A. It is likely to be very difficult to achieve an
+exploit against current standard configurations of TF-A, due to the limited
+interfaces into the secure world with attacker-controlled inputs. However, this
+is becoming increasingly difficult to guarantee with the introduction of complex
+new firmware interfaces, for example the `Software Delegated Exception Interface
+(SDEI)`_.  Also, the TF-A project does not have visibility of all
+vendor-supplied interfaces. Therefore, the TF-A project takes a conservative
+approach by mitigating Variant 4 in hardware wherever possible during secure
+world execution. The mitigation is enabled by setting an implementation defined
+control bit to prevent the re-ordering of stores and loads.
+
+For each affected CPU type, TF-A implements one of the two following mitigation
+approaches in `Pull Request #1392`_ and `Pull Request #1397`_.  Both approaches
+have a system performance impact, which varies for each CPU type and use-case.
+The mitigation code is enabled by default, but can be disabled at compile time
+for platforms that are unaffected or where the risk is deemed low enough.
+
+Arm CPUs not mentioned below are unaffected.
+
+Static mitigation
+-----------------
+
+For affected CPUs, this approach enables the mitigation during EL3
+initialization, following every PE reset. No mechanism is provided to disable
+the mitigation at runtime.
+
+This approach permanently mitigates the entire software stack and no additional
+mitigation code is required in other software components.
+
+TF-A implements this approach for the following affected CPUs:
+
+- Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of
+  ``CPUACTLR_EL1`` (``S3_1_C15_C2_0``).
+
+- Cortex-A73, by setting bit 3 of ``S3_0_C15_C0_0`` (not documented in the
+  Technical Reference Manual (TRM)).
+
+- Cortex-A75, by setting bit 35 (reserved in TRM) of ``CPUACTLR_EL1``
+  (``S3_0_C15_C1_0``).
+
+Dynamic mitigation
+------------------
+
+For affected CPUs, this approach also enables the mitigation during EL3
+initialization, following every PE reset. In addition, this approach implements
+``SMCCC_ARCH_WORKAROUND_2`` in the Arm architectural range to allow callers at
+lower exception levels to temporarily disable the mitigation in their execution
+context, where the risk is deemed low enough. This approach enables mitigation
+on entry to EL3, and restores the mitigation state of the lower exception level
+on exit from EL3. For more information on this approach, see `Firmware
+interfaces for mitigating cache speculation vulnerabilities`_.
+
+This approach may be complemented by additional mitigation code in other
+software components, for example code that calls ``SMCCC_ARCH_WORKAROUND_2``.
+However, even without any mitigation code in other software components, this
+approach will effectively permanently mitigate the entire software stack, since
+the default mitigation state for firmware-managed execution contexts is enabled.
+
+Since the expectation in this approach is that more software executes with the
+mitigation disabled, this may result in better system performance than the
+static approach for some systems or use-cases.  However, for other systems or
+use-cases, this performance saving may be outweighed by the additional overhead
+of ``SMCCC_ARCH_WORKAROUND_2`` calls and TF-A exception handling.
+
+TF-A implements this approach for the following affected CPU:
+
+- Cortex-A76, by setting and clearing bit 16 (reserved in TRM) of
+  ``CPUACTLR2_EL1`` (``S3_0_C15_C1_1``).
+
+.. _Google Project Zero: https://bugs.chromium.org/p/project-zero/issues/detail?id=1528
+.. _Arm Processor Security Update: http://www.arm.com/security-update
+.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
+.. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
+.. _Firmware interfaces for mitigating cache speculation vulnerabilities: https://developer.arm.com/cache-speculation-vulnerability-firmware-specification
+.. _Pull Request #1392: https://github.com/ARM-software/arm-trusted-firmware/pull/1392
+.. _Pull Request #1397: https://github.com/ARM-software/arm-trusted-firmware/pull/1397

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-8.rst

@@ -0,0 +1,103 @@
+Advisory TFV-8 (CVE-2018-19440)
+===============================
+
++----------------+-------------------------------------------------------------+
+| Title          | Not saving x0 to x3 registers can leak information from one |
+|                | Normal World SMC client to another                          |
++================+=============================================================+
+| CVE ID         | `CVE-2018-19440`_                                           |
++----------------+-------------------------------------------------------------+
+| Date           | 27 Nov 2018                                                 |
++----------------+-------------------------------------------------------------+
+| Versions       | All                                                         |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | Multiple normal world SMC clients calling into AArch64 BL31 |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Impact         | Leakage of SMC return values from one normal world SMC      |
+|                | client to another                                           |
++----------------+-------------------------------------------------------------+
+| Fix Version    | `Pull Request #1710`_                                       |
++----------------+-------------------------------------------------------------+
+| Credit         | Secmation                                                   |
++----------------+-------------------------------------------------------------+
+
+When taking an exception to EL3, BL31 saves the CPU context. The aim is to
+restore it before returning into the lower exception level software that called
+into the firmware. However, for an SMC exception, the general purpose registers
+``x0`` to ``x3`` are not part of the CPU context saved on the stack.
+
+As per the `SMC Calling Convention`_, up to 4 values may be returned to the
+caller in registers ``x0`` to ``x3``. In TF-A, these return values are written
+into the CPU context, typically using one of the ``SMC_RETx()`` macros provided
+in the ``include/lib/aarch64/smccc_helpers.h`` header file.
+
+Before returning to the caller, the ``restore_gp_registers()`` function is
+called. It restores the values of all general purpose registers taken from the
+CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
+can be seen in the ``lib/el3_runtime/aarch64/context.S`` file at line 339
+(referring to the version of the code as of `commit c385955`_):
+
+::
+
+    /*
+     * This function restores all general purpose registers except x30 from the
+     * CPU context. x30 register must be explicitly restored by the caller.
+     */
+    func restore_gp_registers
+        ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
+        ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
+
+In the case of an SMC handler that does not use all 4 return values, the
+remaining ones are left unchanged in the CPU context. As a result,
+``restore_gp_registers()`` restores the stale values saved by a previous SMC
+request (or asynchronous exception to EL3) that used these return values.
+
+In the presence of multiple normal world SMC clients, this behaviour might leak
+some of the return values from one client to another. For example, if a victim
+client first sends an SMC that returns 4 values, a malicious client may then
+send a second SMC expecting no return values (for example, a
+``SDEI_EVENT_COMPLETE`` SMC) to get the 4 return values of the victim client.
+
+In general, the responsibility for mitigating threats due to the presence of
+multiple normal world SMC clients lies with EL2 software.  When present, EL2
+software must trap SMC calls from EL1 software to ensure secure behaviour.
+
+For this reason, TF-A does not save ``x0`` to ``x3`` in the CPU context on an
+SMC synchronous exception. It has behaved this way since the first version.
+
+We can confirm that at least upstream KVM-based systems mitigate this threat,
+and are therefore unaffected by this issue. Other EL2 software should be audited
+to assess the impact of this threat.
+
+EL2 software might find mitigating this threat somewhat onerous, because for all
+SMCs it would need to be aware of which return registers contain valid data, so
+it can sanitise any unused return registers. On the other hand, mitigating this
+in EL3 is relatively easy and cheap. Therefore, TF-A will now ensure that no
+information is leaked through registers ``x0`` to ``x3``, by preserving the
+register state over the call.
+
+Note that AArch32 TF-A is not affected by this issue. The SMC handling code in
+``SP_MIN`` already saves all general purpose registers - including ``r0`` to
+``r3``, as can be seen in the ``include/lib/aarch32/smccc_macros.S`` file at
+line 19 (referring to the version of the code as of `commit c385955`_):
+
+.. code:: c
+
+    /*
+     * Macro to save the General purpose registers (r0 - r12), the banked
+     * spsr, lr, sp registers and the `scr` register to the SMC context on entry
+     * due a SMC call. The `lr` of the current mode (monitor) is expected to be
+     * already saved. The `sp` must point to the `smc_ctx_t` to save to.
+     * Additionally, also save the 'pmcr' register as this is updated whilst
+     * executing in the secure world.
+     */
+        .macro smccc_save_gp_mode_regs
+        /* Save r0 - r12 in the SMC context */
+        stm sp, {r0-r12}
+
+.. _CVE-2018-19440: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-19440
+.. _commit c385955: https://github.com/ARM-software/arm-trusted-firmware/commit/c385955
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
+.. _Pull Request #1710: https://github.com/ARM-software/arm-trusted-firmware/pull/1710

arm-trusted-firmware.t234/docs/security_advisories/security-advisory-tfv-9.rst

@@ -0,0 +1,124 @@
+Advisory TFV-9 (CVE-2022-23960)
+============================================================
+
++----------------+-------------------------------------------------------------+
+| Title          | Trusted Firmware-A exposure to speculative processor        |
+|                | vulnerabilities with branch prediction target reuse         |
++================+=============================================================+
+| CVE ID         | `CVE-2022-23960`_                                           |
++----------------+-------------------------------------------------------------+
+| Date           | 08 Mar 2022                                                 |
++----------------+-------------------------------------------------------------+
+| Versions       | All, up to and including v2.6                               |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Configurations | All                                                         |
+| Affected       |                                                             |
++----------------+-------------------------------------------------------------+
+| Impact         | Potential leakage of secure world data to normal world      |
+|                | if an attacker is able to find a TF-A exfiltration primitive|
+|                | that can be predicted as a valid branch target, and somehow |
+|                | induce misprediction onto that primitive. There are         |
+|                | currently no known exploits.                                |
++----------------+-------------------------------------------------------------+
+| Fix Version    | `Gerrit topic #spectre_bhb`_                                |
++----------------+-------------------------------------------------------------+
+| Credit         | Systems and Network Security Group at Vrije Universiteit    |
+|                | Amsterdam for CVE-2022-23960, Arm for patches               |
++----------------+-------------------------------------------------------------+
+
+This security advisory describes the current understanding of the Trusted
+Firmware-A exposure to the new speculative processor vulnerability.
+To understand the background and wider impact of these vulnerabilities on Arm
+systems, please refer to the `Arm Processor Security Update`_. The whitepaper
+referred to below describes the Spectre attack and mitigation in more detail
+including implementation specific mitigation details for all impacted Arm CPUs.
+
+
+`CVE-2022-23960`_
+-----------------
+
+Where possible on vulnerable CPUs that implement FEAT_CSV2, Arm recommends
+inserting a loop workaround with implementation specific number of iterations
+that will discard the branch history on exception entry to a higher exception
+level for the given CPU. This is done as early as possible on entry into EL3,
+before any branch instruction is executed. This is sufficient to mitigate
+Spectre-BHB on behalf of all secure world code, assuming that no secure world
+code is under attacker control.
+
+The below table lists the CPUs that mitigate against this vulnerability in
+TF-A using the loop workaround(all cores that implement FEAT_CSV2 except the
+revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
+
++----------------------+
+| Core                 |
++----------------------+
+| Cortex-A72(from r1p0)|
++----------------------+
+| Cortex-A76           |
++----------------------+
+| Cortex-A76AE         |
++----------------------+
+| Cortex-A77           |
++----------------------+
+| Cortex-A78           |
++----------------------+
+| Cortex-A78AE         |
++----------------------+
+| Cortex-A78C          |
++----------------------+
+| Cortex-X1            |
++----------------------+
+| Cortex-X2            |
++----------------------+
+| Cortex-X3            |
++----------------------+
+| Cortex-A710          |
++----------------------+
+| Cortex-A715          |
++----------------------+
+| Cortex-A720          |
++----------------------+
+| Neoverse-N1          |
++----------------------+
+| Neoverse-N2          |
++----------------------+
+| Neoverse-V1          |
++----------------------+
+| Neoverse-V2          |
++----------------------+
+| Neoverse-V3          |
++----------------------+
+
+For all other cores impacted by Spectre-BHB, some of which that do not implement
+FEAT_CSV2 and some that do e.g. Cortex-A73, the recommended mitigation is to
+flush all branch predictions via an implementation specific route.
+
+In case local workaround is not feasible, the Rich OS can invoke the SMC
+(``SMCCC_ARCH_WORKAROUND_3``) to apply the workaround. Refer to `SMCCC Calling
+Convention specification`_ for more details.
+
+`Gerrit topic #spectre_bhb`_ This patchset implements the Spectre-BHB loop
+workaround for CPUs mentioned in the above table. For CPUs supporting
+speculative barrier instruction, the loop workaround is optimised by using SB
+in place of the common DSB and ISB sequence. It also mitigates against
+this vulnerability for Cortex-A72 CPU versions that support the CSV2 feature
+(from r1p0). The patch stack also includes an implementation for a specified
+`CVE-2022-23960`_ workaround SMC(``SMCCC_ARCH_WORKAROUND_3``) for use by normal
+world privileged software. Details of ``SMCCC_ARCH_WORKAROUND_3`` can be found
+in the `SMCCC Calling Convention specification`_. The specification and
+implementation also enables the normal world to discover the presence of this
+firmware service. This patch also implements ``SMCCC_ARCH_WORKAROUND_3`` for
+Cortex-A57, Coxtex-A72, Cortex-A73 and Cortex-A75 using the existing workaround.
+for CVE-2017-5715. Cortex-A15 patch extends Spectre V2 mitigation to Spectre-BHB.
+
+The above workaround is enabled by default (on vulnerable CPUs only). Platforms
+can choose to disable them at compile time if they do not require them.
+
+For more information about non-Arm CPUs, please contact the CPU vendor.
+
+.. _Arm Processor Security Update: http://www.arm.com/security-update
+.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960
+.. _Gerrit topic #spectre_bhb: https://review.trustedfirmware.org/q/topic:"spectre_bhb"+(status:open%20OR%20status:merged)
+.. _CVE-2022-23960 mitigation specification: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
+.. _SMCCC Calling Convention specification: https://developer.arm.com/documentation/den0028/latest