Updating prebuilts and/or headers

e8aa3af98539680668d37659b7ba8f7e2becb16b - nvbuild.sh
d15f50688485e11293e0d0bd66d73655e79f7718 - nvcommon_build.sh
55bcfa0a03639a375c3f87b1d3286f526c41b207 - arm-trusted-firmware/.versionrc.js
5f8311228df51d284e4efc6c89e9d193dde99d11 - arm-trusted-firmware/.editorconfig
2b66445d7d00314222c238ee2f233a099ac6d838 - arm-trusted-firmware/.commitlintrc.js
1156a747abe8e5f2a639fe82c7e9b4b8c128428c - arm-trusted-firmware/package-lock.json
d2180c4f81067554a4fa86baaebf7cd7722d0706 - arm-trusted-firmware/Makefile
c10d9e3662b48b6da5c81ce00879a16fd8cf3d60 - arm-trusted-firmware/.cz.json
2d62a7583b85631859c4143f08e0dc332e1cb87e - arm-trusted-firmware/.gitreview
da14c19baefee3959f7c02f68db6cbe8c25d408e - arm-trusted-firmware/readme.rst
7f3fadaf80e3c4745d24cb1a5881c7c5f4d898ba - arm-trusted-firmware/.checkpatch.conf
2da4fc2430e852f43b1ec376e4783a1d4658c039 - arm-trusted-firmware/package.json
1684b8fa062fcf155fb678c6e112cf5436423ba2 - arm-trusted-firmware/changelog.yaml
d8da3627085908a5f974b45528b85dc0a41a8b75 - arm-trusted-firmware/license.rst
5c6a4c08a854ddd3d464e6d96f605ff5e28fcf28 - arm-trusted-firmware/bl31/ehf.c
75c196ade8ef57a9775c286e3c2f88b52c492e67 - arm-trusted-firmware/bl31/bl31_context_mgmt.c
ae44163001e4ade4c2e29f6afb43316e7584ee41 - arm-trusted-firmware/bl31/interrupt_mgmt.c
ccc40b094b337f6e60b8a4f2a7470ab4c1264f4f - arm-trusted-firmware/bl31/bl31_main.c
57600ae63b254bd5341c3728038049d1e9526b9a - arm-trusted-firmware/bl31/bl31.ld.S
64b21af0df86a3f591cbf9889b0990e313980048 - arm-trusted-firmware/bl31/aarch64/ea_delegate.S
7c846b0cc5af2d57b0a9ccac7bb940b95f682bce - arm-trusted-firmware/bl31/aarch64/crash_reporting.S
a6aee212d05e2c649a137adf37160a8d24360040 - arm-trusted-firmware/bl31/aarch64/runtime_exceptions.S
86ee5f1020a1ae3e8788204817e6b6fcb0da5922 - arm-trusted-firmware/bl31/aarch64/bl31_entrypoint.S
2c87153926f8a458cffc9a435e15571ba721c2fa - arm-trusted-firmware/licenses/LICENSE.MIT
8887d0d62a1b5248423fbc54ee536be3e5131d91 - arm-trusted-firmware/services/spd/opteed/opteed_private.h
04de846e914d22f5925ba665f709fd3b0793ea5c - arm-trusted-firmware/services/spd/opteed/teesmc_opteed.h
c7af1a7de6cb5d79bf42271e846f04a18df96b63 - arm-trusted-firmware/services/spd/opteed/opteed_pm.c
c8ea87fefa1ecd86c162a85206e9427be8c93afb - arm-trusted-firmware/services/spd/opteed/opteed_helpers.S
b4e16e85997824311dd82861c4c22d6ed046b817 - arm-trusted-firmware/services/spd/opteed/opteed_main.c
e6df3878f8d4759c9f52ea98cbd0d6303bd2983b - arm-trusted-firmware/services/spd/opteed/teesmc_opteed_macros.h
4577f90d8a829f8cb934271e6991bd34844e1854 - arm-trusted-firmware/services/spd/opteed/opteed_common.c
c41250dd18f5502066bab243f1a2f33acf9079f5 - arm-trusted-firmware/services/spd/tspd/tspd_private.h
36db67e2b644b85662e0440abdf6bb464032dfb1 - arm-trusted-firmware/services/spd/tspd/tspd_main.c
d68051c573aae1f65601f9c9307d095259f8de63 - arm-trusted-firmware/services/spd/tspd/tspd_pm.c
45855bd72493c075e03c590cfade6075e5656654 - arm-trusted-firmware/services/spd/tspd/tspd_common.c
f9cf95e919ab4903bc80205e402547ddebe078a8 - arm-trusted-firmware/services/spd/tspd/tspd_helpers.S
61ff410fd8dae3d3ecffc63595125321444d53c7 - arm-trusted-firmware/services/spd/tlkd/tlkd_main.c
176e5bf39535fbb39c81b2deb17ee470cac87159 - arm-trusted-firmware/services/spd/tlkd/tlkd_pm.c
c213fbde43c8075e8fe28297dd6934f2f7c5f6fa - arm-trusted-firmware/services/spd/tlkd/tlkd_common.c
e4543798b8feb237167dc8c495b7aeb079d1b290 - arm-trusted-firmware/services/spd/tlkd/tlkd_private.h
14bc8b1de264fc27498c195073dcf7c1dd736c4d - arm-trusted-firmware/services/spd/tlkd/tlkd_helpers.S
cb38cd65497ea7679a3c5ced33d2e833c2f82797 - arm-trusted-firmware/services/spd/trusty/trusty.c
ba437dffc2a576e12cd8b8b5e8331a43244754b0 - arm-trusted-firmware/services/spd/trusty/trusty_helpers.S
405a4e398e27192766391869719c952a77d4e789 - arm-trusted-firmware/services/spd/trusty/generic-arm64-smcall.c
912f672668f3beed13a6a55a3fab7666e147ea6c - arm-trusted-firmware/services/spd/trusty/sm_err.h
2bbaae4a856f5eba1f98688458729049af38a448 - arm-trusted-firmware/services/spd/trusty/generic-arm64-smcall.h
55c35f079c4fec17128f7c644425b13fd516f2e8 - arm-trusted-firmware/services/spd/trusty/smcall.h
32f05b17684cd616a34fd51c98e75162d384217a - arm-trusted-firmware/services/arm_arch_svc/arm_arch_svc_setup.c
250540ab4306221c494658c2239ffed65aa3fbd9 - arm-trusted-firmware/services/std_svc/pci_svc.c
bc64867c51e6a4f26dc11e07d3be01304f8b78e3 - arm-trusted-firmware/services/std_svc/std_svc_setup.c
3e424bb10206165d477d92627a1a6d8955152b74 - arm-trusted-firmware/services/std_svc/spmd/spmd_private.h
6da223d4cbc8ff07b002a40446860274397aa283 - arm-trusted-firmware/services/std_svc/spmd/spmd_main.c
eb2fb622fab718a44678ea1273fb7df9d3dd49be - arm-trusted-firmware/services/std_svc/spmd/spmd_pm.c
eb5c9e4113243964f83a249807ed07711dc6f145 - arm-trusted-firmware/services/std_svc/spmd/aarch64/spmd_helpers.S
45b49532e2610460e0fba1e6cbf18573f216da9e - arm-trusted-firmware/services/std_svc/rmmd/rmmd_attest.c
26be0a6e880962cffc338be91ad0f344e8aee9ef - arm-trusted-firmware/services/std_svc/rmmd/rmmd_initial_context.h
5d93ba8b111b69b7ef12b9a1ce621d9740284e41 - arm-trusted-firmware/services/std_svc/rmmd/rmmd_main.c
4268337ed8b89db9b3ad75537a8f1e2a008fc949 - arm-trusted-firmware/services/std_svc/rmmd/rmmd_private.h
51c4bc5d5a6c9b18e2f3f2c951d3f8abe0869ba2 - arm-trusted-firmware/services/std_svc/rmmd/aarch64/rmmd_helpers.S
06bef6d6d25e76eef2278253f480a4afbaebabf3 - arm-trusted-firmware/services/std_svc/rmmd/trp/trp_entry.S
6b1ef22efba95bff3270de056f0a4e2484528dee - arm-trusted-firmware/services/std_svc/rmmd/trp/linker.lds
83a9c2e476136e139d80cac740c65fee111c0ba6 - arm-trusted-firmware/services/std_svc/rmmd/trp/trp_private.h
ca2e1ed2396b9c004b00095f04cbe848e743043d - arm-trusted-firmware/services/std_svc/rmmd/trp/trp_main.c
2fd31858f771c3fa2d49ac883b8e3bb8486cebae - arm-trusted-firmware/services/std_svc/sdei/sdei_event.c
e020a86b0568edbbb8e8a93f2cee43fc4812d475 - arm-trusted-firmware/services/std_svc/sdei/sdei_intr_mgmt.c
0a593d9b9aca3739ab4d94c4aa2ecdf7481ad305 - arm-trusted-firmware/services/std_svc/sdei/sdei_main.c
b8207b17922c0b2192565df4c3bc9e1e9e726afa - arm-trusted-firmware/services/std_svc/sdei/sdei_state.c
36f054958b6c01f03eed070113b49903ce936a5d - arm-trusted-firmware/services/std_svc/sdei/sdei_private.h
ed3a4e16186524a88ed19aa95176bc233b0928fe - arm-trusted-firmware/services/std_svc/sdei/sdei_dispatch.S
0f3a50749094ad519b427c0a9c94db4f8dd32988 - arm-trusted-firmware/services/std_svc/trng/trng_entropy_pool.c
99c265f55fed0f586d388c5654338897d9e296e6 - arm-trusted-firmware/services/std_svc/trng/trng_main.c
c53e4b9cdb4eaee27196d9759c484c4faeaf7d06 - arm-trusted-firmware/services/std_svc/trng/trng_entropy_pool.h
e3e6228d6ff51d8d1940c9d13b884a9699bc1a6e - arm-trusted-firmware/services/std_svc/spm_mm/spm_mm_shim_private.h
5ddc8c374ed249405453ffb9dd8519ddc8a7a34b - arm-trusted-firmware/services/std_svc/spm_mm/spm_mm_xlat.c
79d13846ac86474d81cf97529b0dcb9876156531 - arm-trusted-firmware/services/std_svc/spm_mm/spm_mm_main.c
27e07360421aaf616722735cfdc19c90d91af4a0 - arm-trusted-firmware/services/std_svc/spm_mm/spm_mm_setup.c
9f72d160e0732ed98d19b7f82e62c8434b043846 - arm-trusted-firmware/services/std_svc/spm_mm/spm_mm_private.h
f3b6abb1b262ca29c81fe896193453e05ae2fd50 - arm-trusted-firmware/services/std_svc/spm_mm/aarch64/spm_mm_helpers.S
92bbf065b55bbb16728230902e84c1ae124cdd26 - arm-trusted-firmware/services/std_svc/spm_mm/aarch64/spm_mm_shim_exceptions.S
358ff3e13baa8507b20744e31468185b03077531 - arm-trusted-firmware/common/bl_common.c
91cec99e37b1e7e986e62eb3474f5b0d63516507 - arm-trusted-firmware/common/image_decompress.c
4e8e81d22968abbb440726d3094bc3a5bbab94c6 - arm-trusted-firmware/common/tf_crc32.c
567e84803ece6e7ea1401d347ecba84600dea543 - arm-trusted-firmware/common/uuid.c
bb6318e6a4526a2e75ed8f74f629b22fad67317e - arm-trusted-firmware/common/fdt_wrappers.c
d1831078ebc7756a3c141537c4f33b00ce2ffca0 - arm-trusted-firmware/common/fdt_fixup.c
54620aa80f910434a484672d917861106ecc2df1 - arm-trusted-firmware/common/runtime_svc.c
f4efa0610d34dd7e2935e65e54d8226cf36f94ff - arm-trusted-firmware/common/desc_image_load.c
3ccdb5028aa976066c06527a27303c4a0db57ead - arm-trusted-firmware/common/tf_log.c
b21d0924c4f52357b3815446ebd25cc4f58ad622 - arm-trusted-firmware/common/aarch64/early_exceptions.S
5354886f2c074fe74f50056321be3516724c7536 - arm-trusted-firmware/common/aarch64/debug.S
e1451e78efe19651d81b93634da02b524c4ebcab - arm-trusted-firmware/common/backtrace/backtrace.c
8ce1f388b3852351c1fa8d8001d14910363ee672 - arm-trusted-firmware/common/aarch32/debug.S
d006178768f88929b34ddd8b6f7caf6ffb1577b4 - arm-trusted-firmware/bl1/bl1_main.c
20113f49289a58e42b03525ea9427f94e093f58f - arm-trusted-firmware/bl1/bl1_private.h
653f6de57d95cb1d74a23acc6389ab9292ef0451 - arm-trusted-firmware/bl1/bl1_fwu.c
f34fa7c71b4b146c22d99ea5e88650c232833b2b - arm-trusted-firmware/bl1/bl1.ld.S
587ecb158bf5940ddc7f95250a8802df39806ef0 - arm-trusted-firmware/bl1/aarch64/bl1_context_mgmt.c
d6181e93a353f492a54a5222fe53d793cc6d46d7 - arm-trusted-firmware/bl1/aarch64/bl1_exceptions.S
5c5e2355ca375fa98ae30f56bcf2f57ea7056c71 - arm-trusted-firmware/bl1/aarch64/bl1_entrypoint.S
284a0afe619de982f2bd1d4b1c625831ef7b3b5e - arm-trusted-firmware/bl1/aarch64/bl1_arch_setup.c
095ac3b2483b968f263618a4bd6cdd8d6f66d321 - arm-trusted-firmware/bl1/aarch32/bl1_context_mgmt.c
32bd99d2c29b908009a4aea495162f0bb76949db - arm-trusted-firmware/bl1/aarch32/bl1_exceptions.S
6ef2d19cb4ab43cba39eb87d49604192b1f3b2bd - arm-trusted-firmware/bl1/aarch32/bl1_entrypoint.S
8d6e2008e280f848fb14017ba5ba559a10724421 - arm-trusted-firmware/bl1/aarch32/bl1_arch_setup.c
85b2afc44851dc57e79c264641730d0e2eca3016 - arm-trusted-firmware/bl1/tbbr/tbbr_img_desc.c
3793e73034176c719a8160e57d2216f834867aea - arm-trusted-firmware/drivers/scmi-msg/base.h
d0830b0dd0dcad2627d7e25042e0b04f9172507d - arm-trusted-firmware/drivers/scmi-msg/common.h
9a06fcf18608dead4701ec10a63da3ace748fe3d - arm-trusted-firmware/drivers/scmi-msg/smt.c
6854b6e16a5d00e32471a842ac82a42307f4fd25 - arm-trusted-firmware/drivers/scmi-msg/reset_domain.h
6494de9c4e6d28e03514a090db2224f8b96327ba - arm-trusted-firmware/drivers/scmi-msg/power_domain.h
ed00d8b9bd19e5b6e1f8ecd2721a613d1a9043ef - arm-trusted-firmware/drivers/scmi-msg/power_domain.c
a9219fa6261f43e472c7b1655189ae66022de0e2 - arm-trusted-firmware/drivers/scmi-msg/clock.h
20129a454f6019ae086f0fc760ccbe6441c75105 - arm-trusted-firmware/drivers/scmi-msg/clock.c
51f712caca20f1532dbd7a569fab515695f574f9 - arm-trusted-firmware/drivers/scmi-msg/reset_domain.c
0f8a382f7d1dc362cfb9bf7d2a7189987b1bd9f4 - arm-trusted-firmware/drivers/scmi-msg/entry.c
5d761434daa9ee97981a3e3264d4196b1b9710f7 - arm-trusted-firmware/drivers/scmi-msg/base.c
d53b18f9aba437cc5d23117338ddac6edd9ba447 - arm-trusted-firmware/drivers/clk/clk.c
f1d5a7ca46b231b4291d715aa7312bc93c8c8d3c - arm-trusted-firmware/drivers/cadence/uart/aarch64/cdns_console.S
a8b2be0d9781815f941f3b5c54c06d66869ebbb8 - arm-trusted-firmware/drivers/nxp/gic/ls_gicv3.c
cbb35d75dea21db6209d5ab41ce216af0acbd5f3 - arm-trusted-firmware/drivers/nxp/gic/ls_gicv2.c
7da82df0c542d1d8ae8e69affe9e30ba233590a2 - arm-trusted-firmware/drivers/nxp/sd/sd_mmc.c
d354d19d9f42611b3ad0f293660bac71ee3a801c - arm-trusted-firmware/drivers/nxp/flexspi/nor/flexspi_nor.h
0c3739bdd3d04953083299f803b7c30e40e3fa93 - arm-trusted-firmware/drivers/nxp/flexspi/nor/fspi.h
af21526870ded933cf4e5455fdd2935a82cea61b - arm-trusted-firmware/drivers/nxp/flexspi/nor/flexspi_nor.c
ce75912d66d9d45c7fb5514c2d883363346b1a48 - arm-trusted-firmware/drivers/nxp/flexspi/nor/fspi.c
396f26a188a6fb1077b280cdc459ee52ac4dec89 - arm-trusted-firmware/drivers/nxp/flexspi/nor/test_fspi.c
a4736e2e943ff2c95ee55ab5550d95dbf4e9fae5 - arm-trusted-firmware/drivers/nxp/interconnect/ls_cci.c
fa805a963aca474eb7b99d376fc23bf898fe4457 - arm-trusted-firmware/drivers/nxp/interconnect/ls_ccn.c
d4cf1b07b3a081078c4e7da1e354adc42f41f7ca - arm-trusted-firmware/drivers/nxp/crypto/caam/src/sec_hw_specific.c
e4343fd48fd3beed200fd430ec2f84482e7171bf - arm-trusted-firmware/drivers/nxp/crypto/caam/src/hw_key_blob.c
bb9ccbfadb1dba83a0035f9bf7b3d22a48fa01ff - arm-trusted-firmware/drivers/nxp/crypto/caam/src/sec_jr_driver.c
ba408ad853e9ef0e53ce8319419a8b3d8a3da7ed - arm-trusted-firmware/drivers/nxp/crypto/caam/src/jobdesc.c
32d20982227d5346d95e069f256ec3556d52ecfe - arm-trusted-firmware/drivers/nxp/crypto/caam/src/rng.c
eeaa299335bd10e0531ff65d6a24c6a4da294057 - arm-trusted-firmware/drivers/nxp/crypto/caam/src/caam.c
ff23fd02b2c8ce84423f099d2b1bea12faf82aec - arm-trusted-firmware/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c
eb5515126eb5fa4bef2f7976e79e3f9fd0944afa - arm-trusted-firmware/drivers/nxp/crypto/caam/src/auth/rsa.c
02475a8e210c6615aa5138943337551fc8b9087f - arm-trusted-firmware/drivers/nxp/crypto/caam/src/auth/hash.c
f29d54b17cb5dd1f602641d092227c883cb6a57b - arm-trusted-firmware/drivers/nxp/csu/csu.c
bf7712fb75e6373abf6791b46d9a4563fd00feb7 - arm-trusted-firmware/drivers/nxp/timer/nxp_timer.c
1d31a2492e42b2087d68ef756a91274f671987c7 - arm-trusted-firmware/drivers/nxp/dcfg/dcfg.c
5579fdab0db3121aceafcaf39eab316e0253aee3 - arm-trusted-firmware/drivers/nxp/sec_mon/snvs.c
3976af866b0f1353ade3d95b9d4ef92a7a2169ea - arm-trusted-firmware/drivers/nxp/ifc/nand/ifc.h
c7adb94bca0f7e2a86394a503007aacd278de299 - arm-trusted-firmware/drivers/nxp/ifc/nand/ifc_nand.c
85860d4c7284e5f15ce31d18787f687d6bde61b8 - arm-trusted-firmware/drivers/nxp/ifc/nor/ifc_nor.c
9b849f025149e6cf51b2500c8f70b38703ed5078 - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_blx_ch2
9489f5c75aa894fc166bb99b848883d0413170cb - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3_2
753107ce7c270d602a0018c1cabb0ef8e7d3c54a - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_blx_ch3
58bff9b3422ffad20520362a80a6f322da632da3 - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch2
8b7ec36599206f1c121cf2a9565bc043b6049dba - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c
cb8400c786b03ab4685825c49454f7915622e629 - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/plat_img_parser.c
e9bddb61157fc79a6db73771f3abc44b0fa2180e - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3_2
aaaf596468de0e2b0f1fd9df798408ccae3ec67c - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/cot.c
bc6fe6b33a974e9a9e2ae522e3ac00b9f7ff4967 - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3
dd7d454c97e1855bb1c228cacfecb6238f4e487d - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3
5a7943b124da3fea7995adb004eff6a0b928e921 - arm-trusted-firmware/drivers/nxp/auth/tbbr/tbbr_cot.c
06049b8071d1258dcc7829e02727d935c561fa1a - arm-trusted-firmware/drivers/nxp/tzc/plat_tzc380.c
73a87390ee3b46e2b5587087457d8a10a6f4cd35 - arm-trusted-firmware/drivers/nxp/tzc/plat_tzc400.c
d3e9bd0226d74dffd59af6ef1c8f029ca195db90 - arm-trusted-firmware/drivers/nxp/console/console_16550.c
f15b111b5f8ec4a947c36b642e6c6331bb5331a4 - arm-trusted-firmware/drivers/nxp/console/console_pl011.c
5128d83df7b28a2a4bd817b834e17b74206a84d7 - arm-trusted-firmware/drivers/nxp/console/16550_console.S
fed7a4d64f892002dd30f1e1bf50d5fbf537281d - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/dimm.c
33929846548a6a6731c652caf6050b64dea2f9d7 - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/ddrc.c
59117917987eb057fe4003d4da4c3125ea76dbc9 - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/ddr.c
442cb1d00ad113cbdc5ce076abc56124655dbe2d - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/regs.c
eaefee9029f7ccfd854a5813aae54ad816808645 - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/utility.c
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dcd0ca426668c19ab921df2fefbf2d83ca5afdd8 - arm-trusted-firmware/include/export/plat/rockchip/common/plat_params_exp.h
a628d4b48c67b17cc32449aacf6052a52eea1705 - arm-trusted-firmware/include/tools_share/uuid.h
1fda7d8e566efd28aaedd2f5d1ae43b5bf4d2705 - arm-trusted-firmware/include/tools_share/tbbr_oid.h
58d6bf8cd75f220139c010d1d5fb6e0a96d4564a - arm-trusted-firmware/include/tools_share/dualroot_oid.h
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3e0251958205aa29f860e4627e7f29098e266f1d - arm-trusted-firmware/include/tools_share/firmware_image_package.h
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7185228489bf2c4e562f37a9f927cbc31c18ced1 - arm-trusted-firmware/lib/aarch64/cache_helpers.S
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3dbb067dc92b40dd63f5ee3b50d0e88978e7e528 - arm-trusted-firmware/lib/extensions/amu/aarch32/amu_helpers.S
21d2bec3b0a822561dc68c9dab32b97d35ea848a - arm-trusted-firmware/lib/extensions/amu/aarch32/amu.c
1e8ea4b9d81a41c874fd1c0e7b3915a5337cf966 - arm-trusted-firmware/lib/extensions/mtpmu/aarch64/mtpmu.S
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4125c51fd3f075d4d291f56b53175ca0683e12eb - arm-trusted-firmware/lib/extensions/spe/spe.c
672dc9ce8ca19e9bad297552bb38f03725d544b2 - arm-trusted-firmware/lib/extensions/mpam/mpam.c
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1acd16a1b33cf990f1093d8f0ba9c0ebd7a6f719 - arm-trusted-firmware/lib/extensions/trbe/trbe.c
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250ce42c1d1df6103d9a7eb84f739a52570e85c9 - arm-trusted-firmware/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
c3816ecbb18ec120734f1bea8e79ea2ce6e4f631 - arm-trusted-firmware/lib/xlat_tables_v2/xlat_tables_core.c
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48fbcd0295e7c9d2581d235e6c80eced4a10a422 - arm-trusted-firmware/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
21604c58893e3fda032bac4d88417fff189d89ca - arm-trusted-firmware/lib/xlat_tables_v2/aarch64/enable_mmu.S
990536d736898528cf4565171fb83f57604dd3d8 - arm-trusted-firmware/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
ade75a712dde9020d79686a61994595c14f73163 - arm-trusted-firmware/lib/xlat_tables_v2/aarch32/enable_mmu.S
5c1fdfd96d90cc2df42b24e37dc31a193219049b - arm-trusted-firmware/lib/optee/optee_utils.c
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628d8395fc7f67e6d7a9a6cecba64f6594d64eb9 - arm-trusted-firmware/lib/zlib/inflate.h
db9e88b8332953972c9120c73389fa2ce03dd8f8 - arm-trusted-firmware/lib/zlib/crc32.h
a152b76b78f9245ca67db2729de72d51ecc234b0 - arm-trusted-firmware/lib/zlib/inftrees.c
3c63a7707d83991f3e074391c047b3136ff3e558 - arm-trusted-firmware/lib/zlib/inftrees.h
2f1fcc93488ac84acf984415b6ea0bd63c72aa49 - arm-trusted-firmware/lib/zlib/zutil.c
6c1114794db137af50f9b060aaade1a1a35ed784 - arm-trusted-firmware/lib/zlib/adler32.c
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4fc803c43a562b2b92a97e22300754ddfe44c603 - arm-trusted-firmware/lib/zlib/inffast.h
473b29ab06e2be461fe4aa74952fcb9bd08d9fa0 - arm-trusted-firmware/lib/zlib/zlib.h
0ef05b0d12bf2cfbbf1aa84cff0e8dcf4fc5b731 - arm-trusted-firmware/lib/zlib/zconf.h
88ea76a1b42bfc247680dd50b450923858f945fe - arm-trusted-firmware/lib/zlib/crc32.c
8bb206723f10a7635c07f3e77abad21e4e47f520 - arm-trusted-firmware/lib/zlib/tf_gunzip.c
bcf80bf32003cb4ebf4b71fd3b62b2ec5210ba95 - arm-trusted-firmware/lib/fconf/fconf_tbbr_getter.c
18fdfde595d6c7a6409f3d91382d81f736bf775d - arm-trusted-firmware/lib/fconf/fconf_mpmm_getter.c
1720429b89e9cc8c7b5f6bde6381dcd8f1e4bf0b - arm-trusted-firmware/lib/fconf/fconf_dyn_cfg_getter.c
fd4c5030299c6c43d7dcde650254301c4a185c84 - arm-trusted-firmware/lib/fconf/fconf.c
3567bc768ff2f143e4933244eb221b010bd91f80 - arm-trusted-firmware/lib/fconf/fconf_amu_getter.c
06052beb76737879a3430c42f32068e7630ce940 - arm-trusted-firmware/lib/fconf/fconf_cot_getter.c
3c63f678cd78b3c4c10b6d13ffb32f245deb8ef6 - arm-trusted-firmware/lib/stack_protector/stack_protector.c
7c77f07a1d4fda36a4af38ed18da2e22607b53e9 - arm-trusted-firmware/lib/stack_protector/aarch64/asm_stack_protector.S
c50c9ce39f46bbbfebd47c8645445585727f5b7d - arm-trusted-firmware/lib/stack_protector/aarch32/asm_stack_protector.S
35242ceafb8e7c1ac58158cde6672b601b1a88f9 - arm-trusted-firmware/lib/mpmm/mpmm.c
3ac2e5a07791e75f8ed81d0c1088a639a14142de - arm-trusted-firmware/lib/cpus/errata_report.c
23b71740924a2f46a4a3766dc7863240494c0c3e - arm-trusted-firmware/lib/cpus/aarch64/cortex_a78c.S
d16bad3d9e6b6ed0a164467a3b25e5174c38de83 - arm-trusted-firmware/lib/cpus/aarch64/neoverse_demeter.S
67a71ce51804d2c0c43d0c5b928b429383691702 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a55.S
62e253dfa61bf57bc7c8af97146dc643070630b6 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a75_pubsub.c
03c0a2d3e033df508520b527dd03c5487d139556 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a76ae.S
6c5232d349afaa099b1de4b8274de771a075d0ce - arm-trusted-firmware/lib/cpus/aarch64/cortex_a57.S
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415d7b76162c6a447101507b3181aa7434887756 - arm-trusted-firmware/plat/xilinx/versal/bl31_versal_setup.c
0f5013cb9f4dd7864aec9fdc3febb4a88c603b5f - arm-trusted-firmware/plat/xilinx/versal/versal_gicv3.c
6b87bc415258116316a3b89d124ff4be9d5fd944 - arm-trusted-firmware/plat/xilinx/versal/aarch64/versal_helpers.S
14340733608cc8031286a97ddc48222bc0ae7bb5 - arm-trusted-firmware/plat/xilinx/versal/aarch64/versal_common.c
cb6dce6031f613ae2ad69be266bc3eb2a5095a0d - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_svc_main.h
cfb673b998f65ad17832a2c1f376daa4ab836ebd - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_client.c
939082dd0654e1c9d5097e4b088ada2eefc3cc46 - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_api_sys.c
67797b5d7b79d4fe75c894faa289f6d4deac5929 - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_node.h
6aca4366f91416b1541836b7a999ff0873c61e53 - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_svc_main.c
a984b65e29e3ddb17d3c124890861519e0a53788 - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_defs.h
06ac8403ef4a152a6d5257c08766c878afc2c3e2 - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_api_sys.h
3efa1f0d849fb9568699ae3cc5e7cf111f1b8158 - arm-trusted-firmware/plat/xilinx/versal/include/versal_def.h
34e333d135956229875de69051e5d541a789cb2d - arm-trusted-firmware/plat/xilinx/versal/include/plat_private.h
d43cd481e9d0acc960fc0f51fbeb274b0ec28712 - arm-trusted-firmware/plat/xilinx/versal/include/plat_macros.S
50268618a09434af24c4a339c20a1b7b4a2e4901 - arm-trusted-firmware/plat/xilinx/versal/include/plat_ipi.h
f22539e2e0c54efb87ad926699ecb40a60fb024d - arm-trusted-firmware/plat/xilinx/versal/include/plat_pm_common.h
23d939fae06d7a162821162cec379264613379ad - arm-trusted-firmware/plat/xilinx/versal/include/platform_def.h
91da7e2e2aedb93811b290946f5b62a4b99a6e6e - arm-trusted-firmware/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
eed49df98140b8681bbbff7a1c514734c884b8aa - arm-trusted-firmware/plat/xilinx/zynqmp/plat_zynqmp.c
fc6886e5619aabaff7153e268ba005d385a73e3a - arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_ipi.c
fdef05d43dd39fc9b4d18e7933fadc3d7b388c0b - arm-trusted-firmware/plat/xilinx/zynqmp/plat_topology.c
e5c72cd4f7db3ba2c52afa5ea2a6f81048fa8876 - arm-trusted-firmware/plat/xilinx/zynqmp/plat_psci.c
614b7c2d4fab5909e7df0076f873699e84b1737a - arm-trusted-firmware/plat/xilinx/zynqmp/sip_svc_setup.c
4018dd905c37ab4e205c88450ef0d6b0a1d45041 - arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_sdei.c
9eafad8129f35d9d02d9cc93d60e653c41e3b321 - arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_ehf.c
e9430970a771c9add648211e2c05e63b0b2bf71b - arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
bca57ae928a46e00c62d44205c7238c103d89723 - arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S
cd3edf132c54e7b51bf04235b10d9de35394acda - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
e1e42c17e346cb2bdd9bcedf9491e65dcf5a101f - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.h
6a34f58d5ec913711c12c58c945dfa18659b999a - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
4738dfbb7a3a9789e0e520c2d4c7f83b635e3e9b - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
7bfba4ae2b47e068f8f5ed8aeed42daad00743c8 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_client.c
4b8489810a7c5bd8524f87d7c37edf02b747ab48 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
620a7d35e7cfe3a416c79ab84094934f41b3821e - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
4cadaaf7eb5f5f047bac44095d19052727b55a02 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
d55e25c027a7950b3a7d34551ba2af0a05e70ac4 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
63045bc978271095cfdd4cb91e9d2c3d416cdb6b - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_defs.h
d6d44bea498c26d61f58d11284635f45c0d747fa - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
4a69759072ab900e304081d6a5542761b628115d - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
04358429a766678c1ea60bc976430714db3fac40 - arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_private.h
8ede155c56692751835019579474fd5fbda5ba26 - arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_macros.S
6d98421b38c7e24ec53977e85b4776275af5d9c5 - arm-trusted-firmware/plat/xilinx/zynqmp/include/zynqmp_def.h
719fc3fa9d14be22cfb4a79dd8838b27fef9f247 - arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_ipi.h
fcc8c8052c715326e932fd7e210fe0beefa2d175 - arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_pm_common.h
606bd0aedd3a81bf175ef81f028eae35e7511725 - arm-trusted-firmware/plat/xilinx/zynqmp/include/platform_def.h
f82a0ba91d921f8782dbacd326cf93f93d406ff3 - arm-trusted-firmware/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
2c5220969ad934f5e3904f8b72774332826fb89d - arm-trusted-firmware/plat/nxp/common/aarch64/ls_helpers.S
fdb986fc3069c5b8c185c58c199bc5e56a6d1655 - arm-trusted-firmware/plat/nxp/common/aarch64/bl31_data.S
cb4accb6830f44fe050021fd6e32cca1a8acf7ee - arm-trusted-firmware/plat/nxp/common/setup/ls_bl31_setup.c
d736c2075e7e15a400e61a1db310a4d1b43bffd2 - arm-trusted-firmware/plat/nxp/common/setup/ls_image_load.c
475644583f7d46ef814913dcdcfddfa706f9f9bb - arm-trusted-firmware/plat/nxp/common/setup/ls_io_storage.c
7159132c839b1d3568d7b7b03da30f6d03e5336e - arm-trusted-firmware/plat/nxp/common/setup/ls_interrupt_mgmt.c
98e57da5931c557522da93cce9fe3bfb911d2cb0 - arm-trusted-firmware/plat/nxp/common/setup/ls_err.c
6694d9cc9520a800f00a344d9cc1c534b6e88d91 - arm-trusted-firmware/plat/nxp/common/setup/ls_bl2_el3_setup.c
e0dfec4c8847e15aeb7a774844188ab382bdd027 - arm-trusted-firmware/plat/nxp/common/setup/ls_stack_protector.c
91c2c52722651995a236e3f10e11504b1d87e098 - arm-trusted-firmware/plat/nxp/common/setup/ls_common.c
8094976b2b7aa5bbc113bbc852215f8e0513c202 - arm-trusted-firmware/plat/nxp/common/setup/aarch64/ls_bl2_mem_params_desc.c
52c5991d0ead354cd375910f00aefc81953d5681 - arm-trusted-firmware/plat/nxp/common/setup/include/plat_common.h
c8d60b0a7cea607dac9dc88673f41a4be9285d2e - arm-trusted-firmware/plat/nxp/common/setup/include/plat_macros.S
9e4c6090807eed8550b5e6acaf048f870d04011b - arm-trusted-firmware/plat/nxp/common/setup/include/bl31_data.h
4f9b26944e2ce37da586a62bdec3d03549edca60 - arm-trusted-firmware/plat/nxp/common/setup/include/mmu_def.h
7deb5f8e4cedbb8f2f2faed66426dac4607d7f04 - arm-trusted-firmware/plat/nxp/common/setup/include/ls_interrupt_mgmt.h
6edca4ab32d5c19db4706b176997f9bc4f085702 - arm-trusted-firmware/plat/nxp/common/img_loadr/load_img.h
ac50f0a2929a3c77c87203013245a30bab6a20b2 - arm-trusted-firmware/plat/nxp/common/img_loadr/load_img.c
3b5918338beab36f0f06c2b7e82c7f49a7b351bf - arm-trusted-firmware/plat/nxp/common/psci/plat_psci.c
11b25502ea937dd88b3986d358aad3eff9f39c71 - arm-trusted-firmware/plat/nxp/common/psci/aarch64/psci_utils.S
187a0bff6625818b129b5ab42039158f8126ddb3 - arm-trusted-firmware/plat/nxp/common/psci/include/plat_psci.h
08360ed6a8b3d051a5cad1cb6e001cf1600b7ac8 - arm-trusted-firmware/plat/nxp/common/ocram/ocram.h
5e45989256d4cb803eb129882666969d3d952ac6 - arm-trusted-firmware/plat/nxp/common/ocram/aarch64/ocram.S
f71b1c56189f5904469d9e69c7b5206a4bd12454 - arm-trusted-firmware/plat/nxp/common/warm_reset/plat_warm_reset.c
48b1c6e031a18037fbc338e8d3f6d0efbe6c0eca - arm-trusted-firmware/plat/nxp/common/warm_reset/plat_warm_rst.h
9c72b3ecd5d5982e63db876f7dfefb7cbac10bea - arm-trusted-firmware/plat/nxp/common/sip_svc/sip_svc.c
be62a5510efe4bb10130935015fc6c12d3b02ed4 - arm-trusted-firmware/plat/nxp/common/sip_svc/aarch64/sipsvc.S
27f86d14fd5ce72d0aaa417b4c893049acc97e1c - arm-trusted-firmware/plat/nxp/common/sip_svc/include/sipsvc.h
3a09baff31a554c63552bd51f6adea91aa05d3c1 - arm-trusted-firmware/plat/nxp/common/nv_storage/plat_nv_storage.h
193a96b82a70ef052d501107a7358ccca4890c12 - arm-trusted-firmware/plat/nxp/common/nv_storage/plat_nv_storage.c
9670a30b894318a795c85e5ee63edbe979b023b6 - arm-trusted-firmware/plat/nxp/common/fip_handler/common/platform_oid.h
5898658243b0a5f981f4c051061be8d7f7ff3a7f - arm-trusted-firmware/plat/nxp/common/fip_handler/common/plat_def_fip_uuid.h
fc286a6d896799156121d56095076ee1765cdd18 - arm-trusted-firmware/plat/nxp/common/fip_handler/common/plat_tbbr_img_def.h
e41af019a383e1c29f6cfe79b98e6812ee9e71e8 - arm-trusted-firmware/plat/nxp/common/fip_handler/fuse_fip/fuse_io_storage.c
0f0ae89b60dfac27f5f00ac6c76a3c1fbbf30e8c - arm-trusted-firmware/plat/nxp/common/fip_handler/fuse_fip/fuse_io.h
96bd522ef14fb5ff8a4247a028501ef7c4367f3a - arm-trusted-firmware/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.h
97667263a954ff77c695a93ec98b767bccf035cd - arm-trusted-firmware/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.c
dcfd794664af1da07e241e7f44705b02a86955bb - arm-trusted-firmware/plat/nxp/common/include/default/plat_default_def.h
1c0daba5be7bb7055a56df067ffc86d62af94382 - arm-trusted-firmware/plat/nxp/common/include/default/ch_3_2/soc_default_base_addr.h
962eb919fbdac8edf23f3cca5303772adc4690b0 - arm-trusted-firmware/plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h
3b4e4e380dbab1bf4ad037c20f705b6e42b5d992 - arm-trusted-firmware/plat/nxp/common/include/default/ch_3/soc_default_base_addr.h
9fecb13f267ce5c792719b3969ef19e96064d75a - arm-trusted-firmware/plat/nxp/common/include/default/ch_3/soc_default_helper_macros.h
2941f6674d8de1d2b22c22b91db3b63996c45d80 - arm-trusted-firmware/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h
764ceec06291ed492b81348c85ad37e77f32eb3a - arm-trusted-firmware/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
254c94ec21e9680a13a88c1c24d884bfb8b9479c - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_a008850.c
c693c689d519e4697e033a4df6e7da75ecaca5b7 - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_a050426.c
5f62419793539e6fbda55df6e2b3fa9e0b21b776 - arm-trusted-firmware/plat/nxp/common/soc_errata/errata.h
492965693fd60a384d16d12de2ecd89c7f522702 - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_list.h
2e0e20e6baddb412ce97b52be66cd32d6f8f367f - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_a010539.c
f925bc09cf5f24b92110d8e7eb81b6948bc855b7 - arm-trusted-firmware/plat/nxp/common/soc_errata/errata.c
0b417a1d9881a05757a25db89aa6739867cc6cff - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_a009660.c
9b61ef7f7b42a7a2448ff56ef3a4dde77d0a3c6a - arm-trusted-firmware/plat/nxp/common/tbbr/csf_tbbr.c
99de11a8e1d6aa0d67bff400dc27222a3f67bda3 - arm-trusted-firmware/plat/nxp/common/tbbr/x509_tbbr.c
003b4e0c6ab04fb9bd51037a2c976e8e9a1e90dc - arm-trusted-firmware/plat/nxp/common/tbbr/nxp_rotpk.S
1fc45a1f2166ae38c534bcf389857b89c441c5af - arm-trusted-firmware/plat/nxp/soc-ls1088a/soc.c
0f6a22f1e28fcb385608a72a297b0cbd67935113 - arm-trusted-firmware/plat/nxp/soc-ls1088a/soc.def
492d3f0900343c093e718ba1816eb94bfc3931e9 - arm-trusted-firmware/plat/nxp/soc-ls1088a/aarch64/ls1088a.S
764c8c04a6189e6992612672f9e41abde5000248 - arm-trusted-firmware/plat/nxp/soc-ls1088a/aarch64/ls1088a_helpers.S
a7f75b9047c373fb59a317bd6d2995d70aa0aefa - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/policy.h
3328578a5401038f068eded4991d6a403c5276b7 - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/plat_def.h
344959df5ba88c1bf9ce847e6735395045c1253c - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/platform.c
11e2d32b094714041c63cf972054b12b7c0db04e - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/platform_def.h
e9f8a604d5a2d30bd7a467c0b5624df132c867ee - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c
992637daa6e8a443c6f0a176079ce731d593f699 - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/policy.h
9c8add03dd402a33b546ebe338030483a6e30892 - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/plat_def.h
344959df5ba88c1bf9ce847e6735395045c1253c - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/platform.c
11e2d32b094714041c63cf972054b12b7c0db04e - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/platform_def.h
30d19335e7872d98487de84b2cc1cfad32bc26ad - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c
d1bd24409a0956382d617f97af627e582ec04d5c - arm-trusted-firmware/plat/nxp/soc-ls1088a/include/soc.h
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189fa51ba04371ccab55ac105b7dfe77c07f3552 - arm-trusted-firmware/plat/nxp/soc-lx2160a/soc.def
ed1f52b1a3d4ce48135556f32d8667c7367494d8 - arm-trusted-firmware/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S
63c93614b627d3a013d8176aa4248010115eecf0 - arm-trusted-firmware/plat/nxp/soc-lx2160a/aarch64/lx2160a_warm_rst.S
3e9660b08500144943aee803a37816f45307d66b - arm-trusted-firmware/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
e7b379eaa610c82050a0e57c194b10a794f23d91 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160ardb/policy.h
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0fe0002fb83ef9fcbbed68caa9cea3b775bfc529 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160ardb/platform_def.h
764850c7f4814c83fc8b48d4a353c5ae2836edf6 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160ardb/ddr_init.c
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2881529cc073176412af0c380690bab77add20c5 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160aqds/plat_def.h
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6701efe4878d9b4a7d1035d7d747426951d04e8b - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2162aqds/plat_def.h
85eb1ecc310643c5e3edb3761897745f5f4eaa6a - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2162aqds/platform.c
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07fb6c57566e19aa44ef34559874dfd995b582b6 - arm-trusted-firmware/plat/nxp/soc-ls1043a/soc.c
059b1c4ea6e6b540b7b01bdeb7153b4dfcacdb1b - arm-trusted-firmware/plat/nxp/soc-ls1043a/soc.def
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18db50ef3d11821179318d84b45c532d3b107226 - arm-trusted-firmware/plat/nxp/soc-ls1043a/aarch64/ls1043a.S
2e5c9db35f0a8446aa2a2a08f75f1488255df745 - arm-trusted-firmware/plat/nxp/soc-ls1043a/ls1043ardb/policy.h
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859878633110369cd34a10f6683227f6b49d0006 - arm-trusted-firmware/plat/nxp/soc-ls1043a/ls1043ardb/platform.c
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7101b940d392636f546086caa2626d9a940d9eac - arm-trusted-firmware/plat/nxp/soc-ls1028a/soc.c
490b7dbb3b819d5251283d9069f177092c665489 - arm-trusted-firmware/plat/nxp/soc-ls1028a/soc.def
033fd89d203e44c446aba6134e51e46a7d9cf324 - arm-trusted-firmware/plat/nxp/soc-ls1028a/aarch64/ls1028a_helpers.S
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8539e94b825c242859fa5c4a3c03901703c386f0 - arm-trusted-firmware/plat/nxp/soc-ls1046a/soc.c
1e814209bd02d7457755dcf4493b05a3794c811c - arm-trusted-firmware/plat/nxp/soc-ls1046a/soc.def
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06d4dda248389e306ea0cf1688bc9944d1511d03 - arm-trusted-firmware/plat/nxp/soc-ls1046a/aarch64/ls1046a_helpers.S
0fb5432862f668e38f9bbce3af181371cdecf0cd - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046ardb/policy.h
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5da46b775851344c65928890c699d7ff047606b2 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046ardb/platform.c
0f38703d163bd042c7827eaddb04ea092b30a478 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046ardb/platform_def.h
2ea7db20f6633e1dbecd9a70ed4cac89d97c2a76 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046ardb/ddr_init.c
0fb5432862f668e38f9bbce3af181371cdecf0cd - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/policy.h
39ce8f1f0afc76a2d1a98e86df076ef84d185da3 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/plat_def.h
5da46b775851344c65928890c699d7ff047606b2 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/platform.c
0f38703d163bd042c7827eaddb04ea092b30a478 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/platform_def.h
60e78557693ed12515227f051b8f55baf47ce8ae - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c
0fb5432862f668e38f9bbce3af181371cdecf0cd - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046afrwy/policy.h
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5da46b775851344c65928890c699d7ff047606b2 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046afrwy/platform.c
0f38703d163bd042c7827eaddb04ea092b30a478 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046afrwy/platform_def.h
945ec23ee2ba0c79a5e6140d043290e9afde9b2c - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c
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9ed3d544ff5ab2cfa0ea13d1fb3b59534eb90e14 - arm-trusted-firmware/plat/nxp/soc-ls1046a/include/soc.h
1e1f92bc6f801c91fde3bbe4ce99b62beb0eb7d2 - arm-trusted-firmware/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
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1e876f487cd25f4a6cd08d0a21926f5405676a07 - arm-trusted-firmware/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
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3bba3282b340c9896990c2ffcbf10d5bfb0070b2 - arm-trusted-firmware/plat/imx/imx7/common/imx7_rotpk.S
4d406209e8b278e9730968baee57f5106d424aef - arm-trusted-firmware/plat/imx/imx7/common/imx7_trusted_boot.c
7b5d73ec9d9c7e14fd48653c6e018d432654101d - arm-trusted-firmware/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c
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10003f2e608d5073c076ab1a446f4ba07c06086d - arm-trusted-firmware/plat/imx/imx7/include/imx7_def.h
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1027e5173d316fd6d9dd6588b9666b53ed9d1116 - arm-trusted-firmware/plat/imx/imx7/include/imx_regs.h
9026b30dd1244e0fa2416dac0e9f2b92c11bc83e - arm-trusted-firmware/plat/imx/common/lpuart_console.S
829a4463f8628c61fcb335a0dbd747a6050c8192 - arm-trusted-firmware/plat/imx/common/imx_sip_svc.c
03ff82e03dc9eb60e02c6e23f0c199fdd1753c9c - arm-trusted-firmware/plat/imx/common/imx_aips.c
83187f1c90615deae51e2febc0506394e8d4d444 - arm-trusted-firmware/plat/imx/common/imx_sip_handler.c
c014188b6f4a48f9dc6d6fed678081f02f8d8e86 - arm-trusted-firmware/plat/imx/common/plat_imx8_gic.c
e03b60801f58711597b0bb457ecf6e3e84c9f44e - arm-trusted-firmware/plat/imx/common/imx8_psci.c
5225b741c941cba9f489d347aae2707d99896d7d - arm-trusted-firmware/plat/imx/common/imx_csu.c
1901b0c4a5e19926a9e1b5ae437ebbeb0dc0d181 - arm-trusted-firmware/plat/imx/common/imx7_clock.c
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1b219401b9b5eb5bd8c83fa92fc68c591d48a3da - arm-trusted-firmware/plat/imx/common/imx_io_mux.c
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97029bcef11b7a8598834c9717cec7a5655b895a - arm-trusted-firmware/plat/imx/common/imx8_helpers.S
561b0822ac98206dceac588b536d745fc70829d9 - arm-trusted-firmware/plat/imx/common/imx_ehf.c
6ac985911e7e26d13c75d48a04457fbcb209b62f - arm-trusted-firmware/plat/imx/common/imx_sdei.c
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28b31b74552131c2ba5875fb7db44b22ca16b722 - arm-trusted-firmware/plat/imx/common/include/imx8qx_pads.h
2e84528c7d6b12beb2c64505a14d73bcfb03ef87 - arm-trusted-firmware/plat/imx/common/include/imx_aips.h
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1d847530cd83143e4a50b94c5499ee8c11f9d3e1 - arm-trusted-firmware/plat/imx/common/include/imx8qm_pads.h
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2507eeb7a0cd662322ea96553146f0f0dc8c6e45 - arm-trusted-firmware/plat/imx/common/include/sci/svc/timer/sci_timer_api.h
8169135849017c45a81b2c0447e940e3e5396145 - arm-trusted-firmware/plat/imx/common/aarch32/imx_uart_console.S
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65f1e12aab1c7815ccb98973525d32d30e635a1d - arm-trusted-firmware/plat/imx/common/sci/svc/misc/misc_rpc_clnt.c
1dc0e610322825b6f58ac08670b99a4598bc01f1 - arm-trusted-firmware/plat/imx/common/sci/svc/misc/sci_misc_rpc.h
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3f381087336a847b53323f6828aa61478b46a2cc - arm-trusted-firmware/plat/imx/common/sci/svc/timer/sci_timer_rpc.h
30cf1dfdd48ef57921bbd93789aaedbebd754c55 - arm-trusted-firmware/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c
7bd8d4e39f1f3905630b08a16be851097fa5ab67 - arm-trusted-firmware/plat/imx/imx8m/imx_rdc.c
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0e0933de6793e323f4c77e12a89455776a0dfe57 - arm-trusted-firmware/plat/imx/imx8m/imx8mm/imx8mm_psci.c
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be1935709a939c0480bc4cc27058482508f2596b - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_bl2_mem_params_desc.c
f822b4b589b5d418d0ea960b764bd311a32466ea - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
49f3d2caa5e653fc6cdd99c140ff61ad9d83c9c0 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/gpc.c
3d38c99169530f67aeba8526bd7cd4559981a349 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_bl2_el3_setup.c
169ab98f3d4cd7620ffef0d78f7c2329be9c1586 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_psci.c
97a556f1fc780240a2ad81127c295bd39a0c6512 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_rotpk.S
c65d55a5e1a73f615b9fe213427e4605f4b3806c - arm-trusted-firmware/plat/imx/imx8m/imx8mp/include/imx8mp_private.h
df0e3b50430ac47d2263ca8e0a4b83d46c8c0193 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/include/gpc_reg.h
f7d6a1f75a510179a6e4a7084b3d70dd9bba5734 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/include/platform_def.h
399d2117be7573ef7ddc5afb0364b90fc66d9bb6 - arm-trusted-firmware/plat/imx/imx8qx/imx8qx_bl31_setup.c
b9316c7a608b29b530aaf325e401e06f62647525 - arm-trusted-firmware/plat/imx/imx8qx/imx8qx_psci.c
06458d5a3b748df586e9ba2064614354842c162f - arm-trusted-firmware/plat/imx/imx8qx/include/sec_rsrc.h
5f45eb6e98ea9c90548afd5ee153f8d14c105e48 - arm-trusted-firmware/plat/imx/imx8qx/include/platform_def.h
9561f3046a19b5489e0aa9025135c8bb6a7d2582 - arm-trusted-firmware/plat/imx/imx8qm/imx8qm_bl31_setup.c
08a0687e7c3b77de90198dc7e5d8ca2ec448ae90 - arm-trusted-firmware/plat/imx/imx8qm/imx8qm_psci.c
6beb54a392291f2d54d207842b2620c7c344af8e - arm-trusted-firmware/plat/imx/imx8qm/include/sec_rsrc.h
1fdf9dd0a1e00cee360596ce35842f77598cbf1e - arm-trusted-firmware/plat/imx/imx8qm/include/platform_def.h
54eb696ef592336053f52bc556f47122b4e94fdc - arm-trusted-firmware/plat/rpi/rpi4/rpi4_pci_svc.c
793e163b5e60486c53f3ff36c98ab1c8f144a1bd - arm-trusted-firmware/plat/rpi/rpi4/rpi4_bl31_setup.c
5e76d520f8ea85f6710a605e2c9a4db0d1a66640 - arm-trusted-firmware/plat/rpi/rpi4/aarch64/armstub8_header.S
b1c50f058d68ea165b6dd5f45af97d2b1dd33e64 - arm-trusted-firmware/plat/rpi/rpi4/include/plat_macros.S
6a73f5496572d65332bbf4a50c3c9d4faa9af438 - arm-trusted-firmware/plat/rpi/rpi4/include/platform_def.h
e2412e3cbdcc8daaecfab85f295ee3456cf1f98d - arm-trusted-firmware/plat/rpi/rpi4/include/rpi_hw.h
4d8d91a23a19a15ff7c18f8e6e523c26cd453f2f - arm-trusted-firmware/plat/rpi/rpi4/include/plat.ld.S
11c87bf8a084123bf9a431cc289a66e23112bade - arm-trusted-firmware/plat/rpi/common/rpi3_rotpk.S
e621f46501a2d1856f297145947d1c8d89d5f990 - arm-trusted-firmware/plat/rpi/common/rpi3_image_load.c
d2d1fd0fffc8a200fd42f1b74c8c7d54c483f219 - arm-trusted-firmware/plat/rpi/common/rpi3_trusted_boot.c
41feb9d914df818ac88209ee1569e1701d794248 - arm-trusted-firmware/plat/rpi/common/rpi3_common.c
46c13e3cff3d9c29a733d01629589bd31b37eb5e - arm-trusted-firmware/plat/rpi/common/rpi3_stack_protector.c
dc79372e77a81c53ff2886832f206db2f63873b7 - arm-trusted-firmware/plat/rpi/common/rpi3_topology.c
854bc00d3c5fce60726920c1e5b1b7cd9352568a - arm-trusted-firmware/plat/rpi/common/rpi3_io_storage.c
2880e20e8241800797f95dadcd5a206d82ba45ed - arm-trusted-firmware/plat/rpi/common/rpi3_pm.c
d2456dd752e5376ca6049639fe93ef04bd5aa04f - arm-trusted-firmware/plat/rpi/common/aarch64/plat_helpers.S
c3a79cfd4e400e0a2dfa7ee5e27e50f1bcd8464b - arm-trusted-firmware/plat/rpi/common/include/rpi_shared.h
fd5000ab9d2eac8341e267b879e1ef29eaebf5d7 - arm-trusted-firmware/plat/rpi/rpi3/rpi_mbox_board.c
052815ff6a9d47f47e57d320313a74f10c8a34d3 - arm-trusted-firmware/plat/rpi/rpi3/rpi3_bl31_setup.c
20b2e08539e950f86d86538ed688408f90574454 - arm-trusted-firmware/plat/rpi/rpi3/rpi3_bl2_setup.c
d9b070fbdda2cab75cc45e6dddd9a31f84baf594 - arm-trusted-firmware/plat/rpi/rpi3/rpi3_bl1_setup.c
5a79ec05194636d3850044f358b4673a3f0b9fa0 - arm-trusted-firmware/plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c
64987d2484ce3d48cc4431fee2de9e375235bb5a - arm-trusted-firmware/plat/rpi/rpi3/include/plat_macros.S
7aeb3415e697151619997c1c184f380eb310be78 - arm-trusted-firmware/plat/rpi/rpi3/include/platform_def.h
94001fd4bfa1b8e08f4d51f437c7b006362f24fd - arm-trusted-firmware/plat/rpi/rpi3/include/rpi_hw.h
c2785b4c0937862f1abb7251642a4028a913504d - arm-trusted-firmware/plat/allwinner/sun50i_h6/sunxi_power.c
2514153e63bbcc5513712db8766fd278fa3b0d44 - arm-trusted-firmware/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
3dde76eb498c889851714b3d8e6749211c62bbec - arm-trusted-firmware/plat/allwinner/sun50i_h6/include/sunxi_spc.h
0b8b7ce5f06e24ad7b853125e17507934dfc45e5 - arm-trusted-firmware/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
1590f260f1febbedf931a1596cea2d2e437ea92b - arm-trusted-firmware/plat/allwinner/sun50i_h6/include/sunxi_ccu.h
704da3ea1b61d5106a6172712ecf6a80b1528bf0 - arm-trusted-firmware/plat/allwinner/common/arisc_off.S
e602a60b0fabfe8e91ecf654c16701712b20c3f1 - arm-trusted-firmware/plat/allwinner/common/sunxi_native_pm.c
a5e148901e32cb7feaef9ffbd00f43a2a661ea0c - arm-trusted-firmware/plat/allwinner/common/sunxi_common.c
a7dce777afe91e3a8d68aaa84d55530a9b3b66b4 - arm-trusted-firmware/plat/allwinner/common/sunxi_bl31_setup.c
385e3bbf7c85ef4e96b553e0f9760bfef1e94a3a - arm-trusted-firmware/plat/allwinner/common/sunxi_pm.c
f2bc1957fa87b9880744d070c964b7803c7bf295 - arm-trusted-firmware/plat/allwinner/common/sunxi_topology.c
b832fd1c1d7bc307d2c3698bf00ee15b93de8cb8 - arm-trusted-firmware/plat/allwinner/common/sunxi_cpu_ops.c
a9a0eca6a5cca079ee8007e0afa7f0ffd7a0cf1c - arm-trusted-firmware/plat/allwinner/common/sunxi_scpi_pm.c
0ded87657ff47f0fe5896f1ab1d6d2f9b34f0429 - arm-trusted-firmware/plat/allwinner/common/plat_helpers.S
a44feb979fffb71189cf9943a6d99946305122e2 - arm-trusted-firmware/plat/allwinner/common/sunxi_security.c
711ef06aa592d857ab47ecd0a9b7870c6fa1a5da - arm-trusted-firmware/plat/allwinner/common/include/sunxi_def.h
7d746a44b6a3bbaa1c3e923de0abdfc40393712e - arm-trusted-firmware/plat/allwinner/common/include/plat_macros.S
77455765d6d80bf4a48d7744bf6f4770b7369215 - arm-trusted-firmware/plat/allwinner/common/include/mentor_i2c_plat.h
cc00c1c7f46a2a8af976c1c0fb59681803b68d1c - arm-trusted-firmware/plat/allwinner/common/include/sunxi_private.h
4333584318d0a967851853f5fcd6c5287277246c - arm-trusted-firmware/plat/allwinner/common/include/platform_def.h
3fa3a563994fcf2710324634950265fc8f9d7850 - arm-trusted-firmware/plat/allwinner/sun50i_r329/sunxi_power.c
d430caf710295e9e77a240b785740fdde6705e26 - arm-trusted-firmware/plat/allwinner/sun50i_r329/include/sunxi_mmap.h
1acbdb220cff8edffa7cc7fd4808f71574b90966 - arm-trusted-firmware/plat/allwinner/sun50i_r329/include/sunxi_spc.h
f8fae43c9902bbf818480c6633e05fc6b751aabd - arm-trusted-firmware/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h
2870bd5728ae0e5857fadde22b048a6fcf6ee2d3 - arm-trusted-firmware/plat/allwinner/sun50i_r329/include/sunxi_ccu.h
a38730b258e2c37f114fdb3c923369bade8e7a1a - arm-trusted-firmware/plat/allwinner/sun50i_a64/sunxi_power.c
54ee3b911a552e2cd6e3802820f5cf3e09575a01 - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/core_off_arisc.h
3f4f908a2f0a6a7660d40d79215077ee248f740e - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/sunxi_mmap.h
2c5ad97e48086e62d1d58d1d8289ac4ab3153179 - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/sunxi_spc.h
a462f612d127344fc711a68e3751b31b2b7ce938 - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h
65eec287284371a887adc4c9aa1952c26be66df7 - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/sunxi_ccu.h
786942614a650ccd6930f2bd19bb42b2b539e1f9 - arm-trusted-firmware/plat/allwinner/sun50i_h616/sunxi_power.c
d9eff8a29c53d38215c1d261922df8494c88d5aa - arm-trusted-firmware/plat/allwinner/sun50i_h616/prepare_dtb.c
2b80f35aa1746d608c2eac4eec351c292e0298f0 - arm-trusted-firmware/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
3dde76eb498c889851714b3d8e6749211c62bbec - arm-trusted-firmware/plat/allwinner/sun50i_h616/include/sunxi_spc.h
0ba24eb82465b3d3ad4e293692984b972663d57c - arm-trusted-firmware/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
1590f260f1febbedf931a1596cea2d2e437ea92b - arm-trusted-firmware/plat/allwinner/sun50i_h616/include/sunxi_ccu.h
1c810633809eed169ef7ae47da01b6326b111a64 - arm-trusted-firmware/plat/amlogic/common/aml_console.c
887d16c962bbfdec5ddb366c33ffec0ad5697447 - arm-trusted-firmware/plat/amlogic/common/aml_thermal.c
f1168dcf0c90f4d7a3456d82b909e287a16875ed - arm-trusted-firmware/plat/amlogic/common/aml_topology.c
1b86970e6e211ba1548f3469a4682db7c31577f1 - arm-trusted-firmware/plat/amlogic/common/aml_mhu.c
fa91c2d51bbe34be89ba41e055f4e78eba6ac67e - arm-trusted-firmware/plat/amlogic/common/aml_efuse.c
2321fbf75d8e96d90a1b6f6a14160c91b949cabc - arm-trusted-firmware/plat/amlogic/common/aml_scpi.c
22fc306f5f9b6613312023233481baaf99493614 - arm-trusted-firmware/plat/amlogic/common/aml_sip_svc.c
61752908966c74b637938d2fa11e73c5d5373d9d - arm-trusted-firmware/plat/amlogic/common/aarch64/aml_helpers.S
74bc476713af13ff5ee94c7bdad6c5763f99e9af - arm-trusted-firmware/plat/amlogic/common/include/plat_macros.S
5240bdc42061a821a089cae1eeca3fb799e6aa1c - arm-trusted-firmware/plat/amlogic/common/include/aml_private.h
5ce07f2865d514a3a8979c638337a338fa110f74 - arm-trusted-firmware/plat/amlogic/gxl/gxl_pm.c
68a18488494ea52a108462ec30b6833447e75e62 - arm-trusted-firmware/plat/amlogic/gxl/gxl_def.h
550ec6753c2e8a5f41a920ea9bfffec47ae78dc8 - arm-trusted-firmware/plat/amlogic/gxl/gxl_bl31_setup.c
8b93edbe34b51b737299797607de4e6ff0003917 - arm-trusted-firmware/plat/amlogic/gxl/gxl_common.c
22603b51918b7c1f721eee33d26629b16cff6683 - arm-trusted-firmware/plat/amlogic/gxl/include/platform_def.h
fe8712d8d4a3787c6c2456ffcc2cc468b12bfd7e - arm-trusted-firmware/plat/amlogic/g12a/g12a_bl31_setup.c
495f096204283e82b03abed56414e3d1a29f9b6f - arm-trusted-firmware/plat/amlogic/g12a/g12a_def.h
03a70925292deabd473bf5ffcd0d0d95dd70456e - arm-trusted-firmware/plat/amlogic/g12a/g12a_pm.c
28726387d3750ce4724f9147e5e173131ee7164f - arm-trusted-firmware/plat/amlogic/g12a/g12a_common.c
8e1154709ae343cd8d783739b29005ea2b9a7c7f - arm-trusted-firmware/plat/amlogic/g12a/include/platform_def.h
3389361e87f5cd5e4f7e606599032c3aa3a41b72 - arm-trusted-firmware/plat/amlogic/gxbb/gxbb_def.h
704885551348b4b44d9b7b092aafc3c54533b7e0 - arm-trusted-firmware/plat/amlogic/gxbb/gxbb_bl31_setup.c
25d4db1b1e385a2e45f4ffea43edbfc8bf4fef89 - arm-trusted-firmware/plat/amlogic/gxbb/gxbb_common.c
80fbc4757d8f389dc885b90a5eef8c0c4f6e23c2 - arm-trusted-firmware/plat/amlogic/gxbb/gxbb_pm.c
d558f98c64955249d21b9227149b68808cb3e358 - arm-trusted-firmware/plat/amlogic/gxbb/include/platform_def.h
7fdb79ffddbe1ee7f1b2c543a1eaa07f2671a2ca - arm-trusted-firmware/plat/amlogic/axg/axg_pm.c
c60f26b9eb14d703065a758062f9c76e4e70f8ed - arm-trusted-firmware/plat/amlogic/axg/axg_def.h
3667781fa0058dcdd1cff5587b45c798978c7966 - arm-trusted-firmware/plat/amlogic/axg/axg_bl31_setup.c
d3c822e681ab6d5016ae06adb88ca9aeb6073aba - arm-trusted-firmware/plat/amlogic/axg/axg_common.c
faf31bdcea206b83c40fbe2d878c14fa8327a37a - arm-trusted-firmware/plat/amlogic/axg/include/platform_def.h
5e22516412e81af7bbc52e0e460447cf2d1d63f3 - arm-trusted-firmware/plat/common/plat_log_common.c
cd74e2d1ac7f09f4ced54eecf4bed38f973bbdfb - arm-trusted-firmware/plat/common/plat_gicv3.c
c7afb73f40f0759cd775aec59723f92f7dd54435 - arm-trusted-firmware/plat/common/plat_bl1_common.c
ebb8418a3c0ba1d0d9362005c17fc4a3fb03cf1f - arm-trusted-firmware/plat/common/plat_gicv2.c
dd38f3a1079a17328d48c8cb719713d4de7361a6 - arm-trusted-firmware/plat/common/ubsan.c
ca3750949173b2315d20907e7c6da4a66f32a5cf - arm-trusted-firmware/plat/common/plat_bl_common.c
8020a28923a271101b29516f4997bb7a1b8a6708 - arm-trusted-firmware/plat/common/plat_spmd_manifest.c
ec9195d2ba3b66b6f4258c18a36b14a5cf41ac55 - arm-trusted-firmware/plat/common/plat_psci_common.c
6ae1755d17b7040c038dd8b2e6c6880e2bb60394 - arm-trusted-firmware/plat/common/aarch64/plat_common.c
8be9392135f6389b22910a9e22011c2e5abc6708 - arm-trusted-firmware/plat/common/aarch64/crash_console_helpers.S
8bf3a22931bb5a18034f1275429068834943cb9e - arm-trusted-firmware/plat/common/aarch64/plat_ehf.c
53568d8d4a43005d8a1be8a379cf0f4b7ddc5637 - arm-trusted-firmware/plat/common/aarch64/platform_helpers.S
1fe60996e262523b671b678aa41a510a2cfa2ce9 - arm-trusted-firmware/plat/common/aarch64/platform_up_stack.S
785a7be686f124f8b30c5f96bbdc9670988f49c2 - arm-trusted-firmware/plat/common/aarch64/platform_mp_stack.S
05ebeff6ee2416ab2697799fb338367a03b0ba75 - arm-trusted-firmware/plat/common/aarch32/plat_common.c
c8eab49f9d5326ffc974d2ba7c05bd411df90eb1 - arm-trusted-firmware/plat/common/aarch32/crash_console_helpers.S
01fc909940aee253c9e140248811b8c4fc5d25b4 - arm-trusted-firmware/plat/common/aarch32/platform_helpers.S
f742befce701fed79ec16b324c92409b36838226 - arm-trusted-firmware/plat/common/aarch32/plat_sp_min_common.c
79f7a0e7df796600cfad4b11f4bf7dbafb65a4ea - arm-trusted-firmware/plat/common/aarch32/platform_up_stack.S
578b46ce0ccf74ba18ce1747df871537294d4ddf - arm-trusted-firmware/plat/common/aarch32/platform_mp_stack.S
36144ebe1637da9185e2256593f8aa7307d0cccb - arm-trusted-firmware/plat/common/tbbr/plat_tbbr.c
43da4a7bd6435c6cc7d733e6363a59cacabb9ef5 - arm-trusted-firmware/plat/brcm/common/brcm_mhu.c
c02bbae941528cbae0665016d62e54bfffb74444 - arm-trusted-firmware/plat/brcm/common/brcm_bl2_setup.c
389238486613bb86c6032f788a4605c782e7475c - arm-trusted-firmware/plat/brcm/common/brcm_gicv3.c
48faf64df1848d8493a3f273494ea883a4aafb0c - arm-trusted-firmware/plat/brcm/common/brcm_common.c
9b8db7387e47af68fc183fe909d3060d65438cb2 - arm-trusted-firmware/plat/brcm/common/brcm_io_storage.c
d083c67e189d3cd3712a827a23e28d0aaf2964d1 - arm-trusted-firmware/plat/brcm/common/brcm_bl31_setup.c
02ea7c4006c2910720bf4a85c3766c293d4cb8e5 - arm-trusted-firmware/plat/brcm/common/brcm_mhu.h
2ef6d891873792dd5af17cc1091f369c0865c70d - arm-trusted-firmware/plat/brcm/common/brcm_image_load.c
6d6865834cfc5ce82506bf1ef6df2e3cb196e028 - arm-trusted-firmware/plat/brcm/common/brcm_scpi.c
7c0af43209d486bb7d9b76b244d3fc5ec97b4328 - arm-trusted-firmware/plat/brcm/common/brcm_bl2_mem_params_desc.c
303c81103a6ebbdf9e4afc16b17d17195a5b9238 - arm-trusted-firmware/plat/brcm/common/brcm_scpi.h
43088754fcc9a1fcbb6308988d79eca0c2771d5a - arm-trusted-firmware/plat/brcm/common/brcm_ccn.c
a794cd95a890c951acc5192426abc008b4213a8f - arm-trusted-firmware/plat/brcm/board/common/chip_id.h
eeff346a4c2b6893ad0fa417570e747058627c11 - arm-trusted-firmware/plat/brcm/board/common/cmn_sec.h
2d3a08ac4729a455bffd5c4c70365350fec69e23 - arm-trusted-firmware/plat/brcm/board/common/bcm_elog_ddr.h
779be799404c9562032c8c586f3a3b23835ad722 - arm-trusted-firmware/plat/brcm/board/common/board_arm_trusted_boot.c
801bb1cdab4baf3440ac23728e6190881af4264f - arm-trusted-firmware/plat/brcm/board/common/bcm_elog_ddr.c
c0ecc823e4de1814edd6bf48321b6317c448b16d - arm-trusted-firmware/plat/brcm/board/common/sbl_util.c
2cf7d5accbb22d89a3c89c768604f667a23bef52 - arm-trusted-firmware/plat/brcm/board/common/sbl_util.h
dfc2e7fae9dd66b664758412e1f4c06762246ed6 - arm-trusted-firmware/plat/brcm/board/common/cmn_sec.c
5f45cc70d813bf16880f4f1f4a246ad6114fbb78 - arm-trusted-firmware/plat/brcm/board/common/cmn_plat_util.h
aaa8593ded989c77280d5a16f541eefd45c62067 - arm-trusted-firmware/plat/brcm/board/common/cmn_plat_def.h
eca89f1edcb0c3fc702ac123a55821cde16106bb - arm-trusted-firmware/plat/brcm/board/common/err.c
9eda9f547bdfb6e83ef3c8d82d849e1e4cb68252 - arm-trusted-firmware/plat/brcm/board/common/brcm_mbedtls.c
b2a5352558dc92001c80e614a9b293a1eb19573a - arm-trusted-firmware/plat/brcm/board/common/plat_setup.c
a731b4badf1cf5a90a0ab197b39a2723e4c85dd9 - arm-trusted-firmware/plat/brcm/board/common/platform_common.c
9635661f5e56e9ab172dcec943257465bf36e634 - arm-trusted-firmware/plat/brcm/board/common/bcm_elog.c
500e36754a0240001fe7b400bf8d4806a06de6ee - arm-trusted-firmware/plat/brcm/board/common/timer_sync.c
c124ba5ec6d9fc3e8f1f0b72d3852473ab67e998 - arm-trusted-firmware/plat/brcm/board/common/board_common.c
515e3aecc5237dcc8197e4e8ed7fd7d15765d808 - arm-trusted-firmware/plat/brcm/board/common/bcm_console.c
ac2b64132debec3b54ae614c64dac69067b39291 - arm-trusted-firmware/plat/brcm/board/stingray/aarch64/plat_helpers.S
b4637f982a40118b9d83d3908d0b189d3524bce0 - arm-trusted-firmware/plat/brcm/board/stingray/driver/plat_emmc.c
4573848f39ea4bfceb55e0932f0494af8b890d1d - arm-trusted-firmware/plat/brcm/board/stingray/driver/sr_usb.h
7cc68c731d1d4e967a6b258c94afef74800e2c27 - arm-trusted-firmware/plat/brcm/board/stingray/driver/usb.c
483849480279e54ca28e4177fea05d6bd3cd36d7 - arm-trusted-firmware/plat/brcm/board/stingray/driver/ihost_pll_config.c
1071f5589a11aaf7354868d034e149b27d48adc6 - arm-trusted-firmware/plat/brcm/board/stingray/driver/swreg.c
13bbb4dc261e840997a59d4e914f071835d33fab - arm-trusted-firmware/plat/brcm/board/stingray/driver/usb_phy.c
eed068af90592502021f8e15b556ae302cd8db87 - arm-trusted-firmware/plat/brcm/board/stingray/driver/ddr/soc/include/board_family.h
d0dacd8fc79f78cee10bd8513550abf93624afe2 - arm-trusted-firmware/plat/brcm/board/stingray/driver/ext_sram_init/ext_sram_init.c
46e832c20411ea4d2bcbcf1cc8968149375047f4 - arm-trusted-firmware/plat/brcm/board/stingray/driver/ext_sram_init/ext_sram_init.h
76dbcdb10f12f01d94b3c70d2f8562b0cc8b233a - arm-trusted-firmware/plat/brcm/board/stingray/include/paxb.h
a6bea74c09e847241ba6a156aff89b12670cc98b - arm-trusted-firmware/plat/brcm/board/stingray/include/scp_cmd.h
2c4acf78dfd7c25c281471b6717273ff7920fea8 - arm-trusted-firmware/plat/brcm/board/stingray/include/ncsi.h
4bc4735b9e7c2a5eab8ae91a28d110dd24a42d75 - arm-trusted-firmware/plat/brcm/board/stingray/include/sdio.h
eeabf0e8e4cda99b503b2ea41298aff2d87e1278 - arm-trusted-firmware/plat/brcm/board/stingray/include/ddr_init.h
cc26d153c04427651e12bf00d19497e5bd8cb7a3 - arm-trusted-firmware/plat/brcm/board/stingray/include/platform_usb.h
1dea9a2af71a56fe60929b854a2c73220603d2be - arm-trusted-firmware/plat/brcm/board/stingray/include/timer_sync.h
10104d7d5d9eeeb545dea9ac306deb2c5cf46036 - arm-trusted-firmware/plat/brcm/board/stingray/include/plat_macros.S
b0a1c672d4d7095f6e7ec5305e084cb3a29a790e - arm-trusted-firmware/plat/brcm/board/stingray/include/bl33_info.h
bd25c5d9d7605649bc1d1dee9a734ccb130101c3 - arm-trusted-firmware/plat/brcm/board/stingray/include/fsx.h
8c57e437d9f4b2b49f005f899624af9b47121102 - arm-trusted-firmware/plat/brcm/board/stingray/include/crmu_def.h
90c98d478915f89433c419b06613a52965aeeef6 - arm-trusted-firmware/plat/brcm/board/stingray/include/sr_utils.h
2817bede11ad2da4d5612a155f5a76e30b62de62 - arm-trusted-firmware/plat/brcm/board/stingray/include/paxc.h
bbaec5f331d8cf8f24898a8d172190c5f7940b6a - arm-trusted-firmware/plat/brcm/board/stingray/include/ihost_pm.h
491a5116f054df365b530dc8b09613f1178c2d8a - arm-trusted-firmware/plat/brcm/board/stingray/include/sr_def.h
e7629876236e444ee69e40c96440f3f24b16fefe - arm-trusted-firmware/plat/brcm/board/stingray/include/usb_phy.h
0ef862af40a95d70feda6b8367e6e7452e90099b - arm-trusted-firmware/plat/brcm/board/stingray/include/board_info.h
2ef5c016a1130291e30fb58c1e1b397bb15a531c - arm-trusted-firmware/plat/brcm/board/stingray/include/platform_sotp.h
d823df9c59408673229302e557a65ad1c404e047 - arm-trusted-firmware/plat/brcm/board/stingray/include/platform_def.h
9765542d155d4fc37ee167eda672c6a33030ca8c - arm-trusted-firmware/plat/brcm/board/stingray/include/iommu.h
0228e24fbe8ff775ac7a709f272d375a8e7aa3bf - arm-trusted-firmware/plat/brcm/board/stingray/include/scp_utils.h
1e67ee0873eb29816b418096b514d39c3aeb7d27 - arm-trusted-firmware/plat/brcm/board/stingray/include/swreg.h
77916c4c9e55da373b1b66dba19dfed0034cde48 - arm-trusted-firmware/plat/brcm/board/stingray/src/bl31_setup.c
52a5e5247c12940390abe486ab490a1d8929feb4 - arm-trusted-firmware/plat/brcm/board/stingray/src/paxb.c
863c6f32899af28cd9a60fb273bdc02a29100114 - arm-trusted-firmware/plat/brcm/board/stingray/src/sr_paxb_phy.c
0283858faf5651d4db16f0e4b8bcaadd40bcabe1 - arm-trusted-firmware/plat/brcm/board/stingray/src/scp_cmd.c
d746f7070f366ac250b3766606d2de76a6192436 - arm-trusted-firmware/plat/brcm/board/stingray/src/fsx.c
e9f5650def0bf0c03c50ad69056cf6ff9d71a715 - arm-trusted-firmware/plat/brcm/board/stingray/src/tz_sec.c
d15b82eea2aaa023805036e829ee46cd08ea72ed - arm-trusted-firmware/plat/brcm/board/stingray/src/iommu.c
f89deabe82fe9129f1dde3fb24e57c940e008913 - arm-trusted-firmware/plat/brcm/board/stingray/src/bl2_setup.c
085cb8e4f6dd01efc01f633680e7db315718c304 - arm-trusted-firmware/plat/brcm/board/stingray/src/ihost_pm.c
072e5bc5c72a860c50c3413898b60dd18931b100 - arm-trusted-firmware/plat/brcm/board/stingray/src/ncsi.c
c01d8b9f9c48a1185129c492ab1f8ce1134ed892 - arm-trusted-firmware/plat/brcm/board/stingray/src/scp_utils.c
1fd2e7122a0c63a14a64215ae5750097f050841b - arm-trusted-firmware/plat/brcm/board/stingray/src/brcm_pm_ops.c
062b1d173f23bc015ebb5c790f890e5f2a6934e1 - arm-trusted-firmware/plat/brcm/board/stingray/src/paxc.c
78d2915d5c3a6c4b75eb97c897cd4e58b4d5b962 - arm-trusted-firmware/plat/brcm/board/stingray/src/topology.c
9b0afdae90ec3159bd428d4b9f586d84a0cb55b3 - arm-trusted-firmware/plat/brcm/board/stingray/src/sdio.c
75de08bf7cc548fc88463a459efa719ce9dae276 - arm-trusted-firmware/plat/brcm/board/stingray/src/pm.c
16002a1a28f7ec581aae95aba10964655f89c5dc - arm-trusted-firmware/plat/qemu/common/qemu_pm.c
c154631e1880ac14882cbb7ec28846bcac331126 - arm-trusted-firmware/plat/qemu/common/qemu_bl31_setup.c
95a9e39672a85b16243df6db511e352e068b90ee - arm-trusted-firmware/plat/qemu/common/qemu_bl1_setup.c
00fcc8b29bf97f9ede1c2dfbe40db7ef83c72695 - arm-trusted-firmware/plat/qemu/common/qemu_spmd_manifest.c
2085009221c46e8e62ac297e819084f4b6087615 - arm-trusted-firmware/plat/qemu/common/qemu_rotpk.S
8ebb840a06cb6dddf6c0fd5fe4a612f832842576 - arm-trusted-firmware/plat/qemu/common/qemu_bl2_mem_params_desc.c
ec654aff1a7a4e282bbbe2dc13b2042b9534eb61 - arm-trusted-firmware/plat/qemu/common/qemu_gicv3.c
d78bd11a3e46b66140586c01d9f834a788316251 - arm-trusted-firmware/plat/qemu/common/qemu_gicv2.c
2154f29a91decb99dc45f21e790dd6e0d1da88e1 - arm-trusted-firmware/plat/qemu/common/qemu_private.h
ce499ea5552f0a580d2d730cd86b20a544fb4759 - arm-trusted-firmware/plat/qemu/common/qemu_console.c
fcbaa96813c363c3db4933b80039d532e1252dc7 - arm-trusted-firmware/plat/qemu/common/qemu_io_storage.c
51d8305f79f4736a224811e549fd92ffee6e2134 - arm-trusted-firmware/plat/qemu/common/qemu_spm.c
a58c658f18083c55761b946dd01b034df662dada - arm-trusted-firmware/plat/qemu/common/topology.c
854064daf74a72113baf3004985576f30ed85540 - arm-trusted-firmware/plat/qemu/common/qemu_image_load.c
3ca3d10548276087940fd7af8f274b1b68378322 - arm-trusted-firmware/plat/qemu/common/qemu_stack_protector.c
3a64a36aaab153d084cd63cb8041cb8e4554c206 - arm-trusted-firmware/plat/qemu/common/qemu_common.c
21efcb8ca3eeadb04af0ad8b5dbff0a548221482 - arm-trusted-firmware/plat/qemu/common/qemu_bl2_setup.c
b70358ad6ace724f6125a704a64bd882bb7e5e13 - arm-trusted-firmware/plat/qemu/common/qemu_trusted_boot.c
fe635c884df368ae689c259f9ac0787b17064bb4 - arm-trusted-firmware/plat/qemu/common/aarch64/plat_helpers.S
f58716f140fa8f450f8073fca6f98a8eda79bbc2 - arm-trusted-firmware/plat/qemu/common/include/plat_macros.S
674a4514924db14c06277e39651b46250347d7a4 - arm-trusted-firmware/plat/qemu/common/aarch32/plat_helpers.S
553cd30299445b034280689989176963a39f2b4d - arm-trusted-firmware/plat/qemu/common/sp_min/sp_min_setup.c
dc0cb18de3dee5963f78466b58e002bc816d526b - arm-trusted-firmware/plat/qemu/qemu/include/platform_def.h
f2efe87ffe7cd41bf5ac442c75b40fb2593a8fbb - arm-trusted-firmware/plat/qemu/qemu_sbsa/sbsa_topology.c
a3366d3ea9b4a5a823b365b0a4fe16dd24af7388 - arm-trusted-firmware/plat/qemu/qemu_sbsa/sbsa_private.h
151cea63605746875bff4fceaa296485033aa280 - arm-trusted-firmware/plat/qemu/qemu_sbsa/sbsa_pm.c
46b611bd4d5b4370f104fdcc62cf5da040ec7970 - arm-trusted-firmware/plat/qemu/qemu_sbsa/include/platform_def.h
e4e4584414cea9a632b613da62b76c3999974c0c - arm-trusted-firmware/plat/socionext/uniphier/uniphier_console.h
006db753e22b1119a67d4f76bd213bf3de08be09 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_gicv3.c
30d16489f342eed522b276128737ad41acb82ba9 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_helpers.S
69a2371870f65a855d9ff7c728f2e9c32882aa2c - arm-trusted-firmware/plat/socionext/uniphier/uniphier_bl2_setup.c
21ef9559c64415fef54f3373f28fde4fa86d92d3 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_topology.c
2b022afd58ed2221e8abc99099867eab0c42c326 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_emmc.c
d342acec84b75ea4f64204404f0a54b4158920e1 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_usb.c
26621302eaceca62d3b0e8224c6c14d5ea08df38 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_xlat_setup.c
5fa3e198d6ad7a764cb058e6e88fa12a0d8ffe85 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_nand.c
ab09cd5d8d3222857a607791bee8b31359314aa9 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_bl31_setup.c
91e3ef5fbfd42b725b57f2608d1934a5c717de3b - arm-trusted-firmware/plat/socionext/uniphier/uniphier_tbbr.c
516680ab29649a33ea07ffa922f3b18448e61e55 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_psci.c
05b8fac4f5d6b8cee9465b541e992f27f071fe8f - arm-trusted-firmware/plat/socionext/uniphier/uniphier_console.S
7518b6009c736b543504a3f84be4cbd20e8d9f0c - arm-trusted-firmware/plat/socionext/uniphier/uniphier_scp.c
eca523ec19dc113ddd19b9427a6651cd6ebe6bb3 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_soc_info.c
ad344a675d5f4bf3287a6e32451b462c3ea7d29c - arm-trusted-firmware/plat/socionext/uniphier/uniphier_rotpk.S
8a0a08bd7b9292bd5b334bc91ad422838eb83118 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_cci.c
7cb14fc4ccfe79fe8ffb080b91337e263775111d - arm-trusted-firmware/plat/socionext/uniphier/uniphier_syscnt.c
d94b79f813abf374eef409d04968fce943a3ef84 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_boot_device.c
30db57b3d947cfae86d4cb1fbd7d79f7365fe01d - arm-trusted-firmware/plat/socionext/uniphier/uniphier_smp.S
dd16d7be9af0988718096ec4af552732207ad390 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_console_setup.c
98c1438c270db5db7bd6f971cb928420df53c1b7 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_image_desc.c
456820f5853d3f1676ee19bf63b9c360ed9a80a8 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_io_storage.c
b445ddffd2167b6758d19874673ec99f3f2a1d30 - arm-trusted-firmware/plat/socionext/uniphier/uniphier.h
8bea3f2da202b83b97d9b86e32cb50d5c17cae7e - arm-trusted-firmware/plat/socionext/uniphier/include/plat_macros.S
e35ee40c042c15de97496be4f1d9c81b960cc3da - arm-trusted-firmware/plat/socionext/uniphier/include/platform_def.h
d181839ef722d36e8a51c126deb67a2eae64c527 - arm-trusted-firmware/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
72b5553a5bdc53509ecf17a4d93cbfa1e3d06c8c - arm-trusted-firmware/plat/socionext/synquacer/sq_helpers.S
f43a62ef3a99346a097b8813441539c5354436fc - arm-trusted-firmware/plat/socionext/synquacer/sq_ccn.c
9b1262ca8c6950227a294b789fb3e53dfa2086b1 - arm-trusted-firmware/plat/socionext/synquacer/sq_topology.c
8286dff95425dddb9a5b25ffda50460831781793 - arm-trusted-firmware/plat/socionext/synquacer/sq_xlat_setup.c
a32f17d7db01cfb7a14811a914ba2066581d29a1 - arm-trusted-firmware/plat/socionext/synquacer/sq_spm.c
3db81e971dc630ca534efcd02840b2ee0fc01794 - arm-trusted-firmware/plat/socionext/synquacer/sq_psci.c
f9ac11a5c154783dbbb6fbdf6485867b754f511e - arm-trusted-firmware/plat/socionext/synquacer/sq_bl31_setup.c
b60ee8850906f76ada82b2db19c8656ed9c12d9a - arm-trusted-firmware/plat/socionext/synquacer/sq_gicv3.c
e431465e90b8b68ce2922ff400c2e6953eaeea9d - arm-trusted-firmware/plat/socionext/synquacer/drivers/scp/sq_scmi.c
f57f50699d6a8f3902d4673f01ec3ff0d6931d29 - arm-trusted-firmware/plat/socionext/synquacer/drivers/scp/sq_scp.c
f8fe95fbe1e35e8c328ec5a197b76c329feda4bd - arm-trusted-firmware/plat/socionext/synquacer/drivers/scpi/sq_scpi.h
b6784404cec981a185e6f44ef689f28b7d9513e3 - arm-trusted-firmware/plat/socionext/synquacer/drivers/scpi/sq_scpi.c
ebfc7926ca7e342e5cec3fed564e68be76a80fdd - arm-trusted-firmware/plat/socionext/synquacer/drivers/mhu/sq_mhu.h
961c660b9e7a5641523d5d23b5396c2a2a67746e - arm-trusted-firmware/plat/socionext/synquacer/drivers/mhu/sq_mhu.c
09ba9cfb7c8be52484c3cff427668fc7d2524219 - arm-trusted-firmware/plat/socionext/synquacer/include/sq_common.h
9f24e8fcbc08c61f43c8041c0464cae65fe01ce8 - arm-trusted-firmware/plat/socionext/synquacer/include/plat_macros.S
25666183a169e48e144659003b018f40881b4590 - arm-trusted-firmware/plat/socionext/synquacer/include/platform_def.h
ef74e9cda94f07bf3061b037195287d609c0c6b4 - arm-trusted-firmware/plat/socionext/synquacer/include/plat.ld.S
09dd0d32acc68693a9cc4e6edda975b30b997a7d - arm-trusted-firmware/plat/hisilicon/poplar/plat_pm.c
4df6d997a517a03b7120733e3ff6f1a2634caa47 - arm-trusted-firmware/plat/hisilicon/poplar/bl2_plat_setup.c
077745456537a78c6a462ecaf23835c3ac381a92 - arm-trusted-firmware/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c
5366b77beffc310cab412735a4e4f43185e171c6 - arm-trusted-firmware/plat/hisilicon/poplar/poplar_image_load.c
43b6cb88b4528db3610c0591b417afee9f8e086f - arm-trusted-firmware/plat/hisilicon/poplar/plat_storage.c
942f440e430db3a0fb9bafcb2877fa0f2b2b2206 - arm-trusted-firmware/plat/hisilicon/poplar/plat_topology.c
166469bcfd5bac8ca50e33d23d40607d532f7a9f - arm-trusted-firmware/plat/hisilicon/poplar/bl1_plat_setup.c
706af98521027fbfb3cb50742e9203904186ccfb - arm-trusted-firmware/plat/hisilicon/poplar/poplar_gicv2.c
575e7801ee2435ca3d3bc588117235189cba8fa2 - arm-trusted-firmware/plat/hisilicon/poplar/bl31_plat_setup.c
5b726e62a784d7660009ac2235ebf2d76dc809ad - arm-trusted-firmware/plat/hisilicon/poplar/aarch64/poplar_helpers.S
ef034cd3245b78dec24c714d8ffbb7e9b490427c - arm-trusted-firmware/plat/hisilicon/poplar/aarch64/platform_common.c
54bc2fcf8fb31777a2eee36c5b61246cc0fa0a17 - arm-trusted-firmware/plat/hisilicon/poplar/include/poplar_layout.h
2bc481728aac66acbe669f76aa6dd84c3f4e88a7 - arm-trusted-firmware/plat/hisilicon/poplar/include/plat_private.h
7309b02ef23609fb839b029b295bffaf714cdc1a - arm-trusted-firmware/plat/hisilicon/poplar/include/plat_macros.S
e8d837174e3274ddbcd923af88d3e19e1af8c06a - arm-trusted-firmware/plat/hisilicon/poplar/include/platform_def.h
5333986fb9d6df5ca3e50aad616e8c1422eafdd2 - arm-trusted-firmware/plat/hisilicon/poplar/include/hi3798cv200.h
b8ddcea3e66690f3932ae009921566fe249feccd - arm-trusted-firmware/plat/hisilicon/hikey/hisi_pwrc_sram.S
1975a45f73616d0ceb03dab4a9397cbabc1e66ce - arm-trusted-firmware/plat/hisilicon/hikey/hisi_pwrc.c
0aace28e8f75168d13d7274d81f1f906cc1b2cae - arm-trusted-firmware/plat/hisilicon/hikey/hikey_rotpk.S
030496606ff67ba16f47be9282a04338261e38ea - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
126933334b9ebdde11859016f3bbcc6ac9bbef88 - arm-trusted-firmware/plat/hisilicon/hikey/hisi_mcu.c
3f90b73f27ba47848db784621dd350e6a5ec54d9 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_tbbr.c
e90b7c0a59b785560e233605f2968b642d26fcdb - arm-trusted-firmware/plat/hisilicon/hikey/hisi_sip_svc.c
bca37120bec0db88310c0e711220bd8301c8b932 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_pm.c
1dc25162c504805b378176ceb2a1fac39b8fa3e2 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_ddr.c
b0603f49d7b1252e6774be83ed95232695f1f263 - arm-trusted-firmware/plat/hisilicon/hikey/hisi_ipc.c
e5479e33302a43e627013dbe10bbcca8ccdbf8b5 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl31_setup.c
33f9c2d61b7aa3242f22100ba2694ba2709f7a1b - arm-trusted-firmware/plat/hisilicon/hikey/hikey_topology.c
cfc7af573fbb40bb702a616d8f0bf02b017a3e0b - arm-trusted-firmware/plat/hisilicon/hikey/hisi_dvfs.c
5366b77beffc310cab412735a4e4f43185e171c6 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_image_load.c
132b89dc419b19bfabb3eb2450a5e74317faea11 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_io_storage.c
8b11d0569d254ee10c03b8e7dfaebf823b7b1746 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl_common.c
1b333e35df79afc9319c45ded87fe22b1e5547fc - arm-trusted-firmware/plat/hisilicon/hikey/hikey_security.c
0472150350a0f6a23e8750e0fe14991d176d1a04 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl1_setup.c
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0071214b6af7f5e24aa92d4e7849c79c3818ed05 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl2_setup.c
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31f012031e8dec3fe5dab7afc9ab89deffb7fe7c - arm-trusted-firmware/plat/hisilicon/hikey/include/hi6220_regs_pmctrl.h
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b9c87b1b0f989e816c65163d00ead7cd68b4b6bc - arm-trusted-firmware/plat/hisilicon/hikey/include/hi6553.h
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95b6af34fbda29b2cef5ecaa3ecf9deb1f7a48cb - arm-trusted-firmware/plat/hisilicon/hikey/include/hisi_mcu.h
39568f02d9e541a653aaa3d8503e9976203e27b5 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl2_setup.c
0cd271eb1db1372ebacbc89a1ab7e6b858522177 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_topology.c
19471da73d6d6e0316b89091e8034b65252676ea - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl1_setup.c
e7130fd49b764ab203b1f70d8c04929b17c338a1 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_tbbr.c
df960717d8f3e8b3111b85c464d02214767ffe67 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_rotpk.S
9921f6f68c3b333297fb84f0c74626e02e31182e - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c
3b43870e172a97e6682dc9e7adeb7ee54b219ce1 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_mcu_load.c
b4ec4794171dff334edac55b287dbba42365301a - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl_common.c
6c598ab11230d9af7684a342f64de0ef3aafd2e7 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl31_setup.c
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e521b7127c97a6dc50d62a6fb23613467dfa5c91 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_boardid.c
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755c811030252ea484722f83c6773b03bcd1aecf - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_image_load.c
e5d1ee45233d19ae915b7dcde9d177ac30ff3c59 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_pm.c
1178b52937b1f59d49a4b24807fedf6800893f18 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_io_storage.c
33e4f92c8882961c556666d4e463a0cd932589bb - arm-trusted-firmware/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S
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168bc920b2828c8478a977c1e6b9e597791c0e45 - arm-trusted-firmware/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c
4a0475ff7dac46ea547e623a9a83071f69b5a4b7 - arm-trusted-firmware/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.h
4abee183dc860ea0fe600bb9b19e3c4a0a3d6773 - arm-trusted-firmware/plat/hisilicon/hikey960/drivers/ipc/hisi_ipc.c
9b6172a308464c71e87f1f420cb1df10ceb7bfb4 - arm-trusted-firmware/plat/hisilicon/hikey960/include/hisi_ipc.h
201bc8884be1cfb9b4f87f3fcc6ccf3aeec268d8 - arm-trusted-firmware/plat/hisilicon/hikey960/include/hi3660_hkadc.h
390e28e24c8915a9f956b1a1de0cafa7306bf9ed - arm-trusted-firmware/plat/hisilicon/hikey960/include/hi3660.h
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b1be891afebf5d255da6f6dcb865725241f566b9 - arm-trusted-firmware/plat/hisilicon/hikey960/include/hi3660_crg.h
8274c219bcba2090fe7e6e628abe65c7c3780d33 - arm-trusted-firmware/plat/mediatek/mt8183/plat_pm.c
3cb5ee19a3d0915879c602a240e4affb4a0d7c94 - arm-trusted-firmware/plat/mediatek/mt8183/plat_debug.c
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c7ae3ce6e37f4d27b8733d9c3b1bafa8add40a8b - arm-trusted-firmware/plat/mediatek/mt8183/aarch64/platform_common.c
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015badf34dbdf2955bc1dc9f4b22627bde8f9f9c - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/mce/aarch64/nvg_helpers.S
34e8d1c4e060805a3f55969aabbd211dc6b08fbd - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
34309aaec4559a7c2094873802490b96b9cf9dc1 - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
ce1df43aa2a9700b9c00f14be842646284b3ee3d - arm-trusted-firmware/plat/nvidia/tegra/scat/bl31.scat
348ad39495b7209e9858421f7bd1a02f9712a410 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_pauth.c
97542646c951833f68e49c013c2d309b885aab65 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gicv2.c
bbb547cc93729fd63ae5da22480a94dc84ad6fbf - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_sip_calls.c
7832f9e627bdeb224b72a22840b7b4cd3354b962 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_stack_protector.c
9a23652352c01545d80c980df50b0d1965df8131 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gicv3.c
c7104ef4a0ccb4a2ceb01951a0c8442349cf4ca7 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_delay_timer.c
c97649b9bd33d9e7f4268f6ddc79d603a3a317f2 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_fiq_glue.c
ab066b0f80239a20f5613a9c2bf4862d9c02e2c2 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_bl31_setup.c
8617ceef396a9a7f9b5e9e1a4866cede187f6ba6 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_sdei.c
6356a0b128a435ef5faa1bb6922a5fcc571926ea - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_platform.c
0c5a65d7362595eff6d472ba23ccde7af61d9ce8 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_io_storage.c
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d25c56f572cf7b3618f7567d502c1ee11dec2bae - arm-trusted-firmware/plat/nvidia/tegra/drivers/smmu/smmu.c
8d9b8ebe2f8407dfc849bee6942b55d0a9c76d41 - arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp/bpmp.c
58fc3b165ee7a61397eef3e9f2065858876ce9de - arm-trusted-firmware/plat/nvidia/tegra/drivers/spe/shared_console.S
4d04fd613146842b18904061da84f5958c44b16b - arm-trusted-firmware/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c
fb218e655fd6a3d77f969fce9cd6cb5dd0a6c5b2 - arm-trusted-firmware/plat/nvidia/tegra/drivers/gpcdma/gpcdma.c
2a6016cc527d04ca332373c0d14542d5176aebf8 - arm-trusted-firmware/plat/nvidia/tegra/drivers/psc/psc_mailbox.c
0f53c08fb6e10d933fd28d9f021ccfb0e48212fe - arm-trusted-firmware/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
4dbec584881036aa37e59b66185d958a695a455d - arm-trusted-firmware/plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c
6f1dca2fba8be7758cfe4395226b2e4be820e3f1 - arm-trusted-firmware/plat/nvidia/tegra/drivers/pmc/pmc.c
bbc86d9dee6c505651fa862133b686ea1e1af43e - arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp_ipc/intf.c
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458bed9c52c48caaa9c30822f0d20359e56e044f - arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp_ipc/ivc.h
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949736009adf4b730b592ef786e3d66eaf769d8c - arm-trusted-firmware/plat/nvidia/tegra/include/plat_macros.S
61343b0647173b58eec236e5f6781f95ee64f5d2 - arm-trusted-firmware/plat/nvidia/tegra/include/tegra_platform.h
11b45c0f4e3d96795a403b588930c354305a52d1 - arm-trusted-firmware/plat/nvidia/tegra/include/platform_def.h
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2aec61855e1e16a88683b573ae88e337484a01cb - arm-trusted-firmware/plat/nvidia/tegra/include/t234/tegra234_ras_private.h
21b9ecfaf14f5a5aed16e18cf1643f78e890a096 - arm-trusted-firmware/plat/nvidia/tegra/include/t234/tegra234_private.h
624f3a27eab52b8c97c1d391c9bf0aba2a48ff48 - arm-trusted-firmware/plat/nvidia/tegra/include/t234/tegra_def.h
2693485a6a4c24984696bab65e09494c4af953a6 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/psc_mailbox.h
7eee98bf96c4e615e71244fad2270fe3ac7bca96 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/spe.h
b01b1d6699848ec430ef6c7ff1fa536c611ac8d8 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/bpmp.h
ecb6bb2512f5f946927baadc3238cacaf9e9c42f - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/flowctrl.h
dd094069cb1a5bb53cf55c4e87b2364925c1e25c - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/mce.h
eccbd7dbdb2b149abd38a48ddd5f6b0f292373b7 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/memctrl_v2.h
fa073698981deb8685410d390184a2fea2477d8d - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/smmu.h
0005633528a5228ce544a5fe3fc8b984d26eff95 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/gpcdma.h
97366374236e04da0a203c6df1ed7e93325e40f5 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/memctrl.h
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e4e77bfcd8d045ecce243b060298bf229cbf3941 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/security_engine.h
4aa146b81da8a061bda6540907c37d5ec6569962 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/tegra_gic.h
1ad3acb2c35dab529632e51cfd8a1977d0a3e495 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/pmc.h
d99d1382679e0a53fedf1afb4781358524154b54 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
0770b19832587bf494cdf6a16cf0af55ef4e3eba - arm-trusted-firmware/plat/nvidia/tegra/include/t194/tegra194_private.h
65dcb16996ba6f5480b25b088c00618a8401e2b0 - arm-trusted-firmware/plat/nvidia/tegra/include/t194/tegra194_ras_private.h
249831518e8554837fb8750d200cb4b786c2d683 - arm-trusted-firmware/plat/nvidia/tegra/include/t194/tegra_def.h
412a883e42794de7909b0a3076864c06874a0764 - arm-trusted-firmware/plat/nvidia/tegra/include/t210/tegra_def.h
68ec103aabc7cf1ba96e9f802589f232bf63e8fb - arm-trusted-firmware/plat/nvidia/tegra/include/t186/tegra186_private.h
80ba76cba14e63964ee35830536886c24581020c - arm-trusted-firmware/plat/nvidia/tegra/include/t186/tegra_mc_def.h
00ba4a09814b790749853248a68f57c1bf5d8a77 - arm-trusted-firmware/plat/nvidia/tegra/include/t186/tegra_def.h
fc8ce0bab3e269ab289babbc37c5ffea6c1105c1 - arm-trusted-firmware/plat/nvidia/tegra/include/lib/profiler.h
fbecdf95d5fb90503336b712a6955a36a635aac0 - arm-trusted-firmware/plat/nvidia/tegra/lib/debug/profiler.c
d9c373f0351531965e8097178bbc13ede3af7485 - arm-trusted-firmware/plat/renesas/rzg/bl2_plat_setup.c
ffd1e457886f1089d9c344f701ec17dc97f8f074 - arm-trusted-firmware/plat/renesas/common/rcar_common.c
716e1c7c79baa403b9c5d0ef120f23d8cac8e802 - arm-trusted-firmware/plat/renesas/common/plat_pm.c
514484b073de3f03a0c25885d1947529d0863273 - arm-trusted-firmware/plat/renesas/common/bl2_secure_setting.c
ea086669ab75f559b2e65b291fea3af158c18bd2 - arm-trusted-firmware/plat/renesas/common/bl2_plat_mem_params_desc.c
ae71ad3a55f0e9c013697f9775e6c12c0ff7bd74 - arm-trusted-firmware/plat/renesas/common/bl2_cpg_init.c
d414d4d769295e5a493cf3e77c9c51626ee0e6fb - arm-trusted-firmware/plat/renesas/common/bl2_interrupt_error.c
12b42e58567a9ecd3d1d63318cb5ec7011a41573 - arm-trusted-firmware/plat/renesas/common/plat_storage.c
a977937122b0a3096d2974c21e1d01713d54ef5b - arm-trusted-firmware/plat/renesas/common/plat_topology.c
5f9406be82d4cf619e442556228de3e2d1283e39 - arm-trusted-firmware/plat/renesas/common/plat_image_load.c
9e2b414041c35052396135ebdc28539af32c2593 - arm-trusted-firmware/plat/renesas/common/bl31_plat_setup.c
3c4b66c3e0e2ea740399f2ac87b9c61af5c45031 - arm-trusted-firmware/plat/renesas/common/aarch64/platform_common.c
2b4770445484da2ea7c1061c5e772905f5f9eda9 - arm-trusted-firmware/plat/renesas/common/aarch64/plat_helpers.S
f99514b828a7a7fe6f0063a291c023d74a2c9bd2 - arm-trusted-firmware/plat/renesas/common/include/rcar_def.h
72226e12e556432cb547181aa73e0d55c5c8777f - arm-trusted-firmware/plat/renesas/common/include/plat_macros.S
2f021b7dce5115d413267052dd5b471ceff900cf - arm-trusted-firmware/plat/renesas/common/include/rcar_private.h
aa601d2e26e65cab57efac1579ef07d5a4966f23 - arm-trusted-firmware/plat/renesas/common/include/rcar_version.h
939b904cc911a51e5bfd33fc817d5c5b22e55400 - arm-trusted-firmware/plat/renesas/common/include/platform_def.h
f4aa97332efbbc8e20e48e338443fd3b9c208830 - arm-trusted-firmware/plat/renesas/common/include/plat.ld.S
64ef91e2bf3528ac94c8eb79c5c3f80113257721 - arm-trusted-firmware/plat/renesas/common/include/registers/lifec_registers.h
f5943232ea7fe8a4717cdaa5d1f371ec634c8074 - arm-trusted-firmware/plat/renesas/common/include/registers/cpg_registers.h
f773e9cbe28c8c27bd7013b66cd612cd63f790fc - arm-trusted-firmware/plat/renesas/common/include/registers/axi_registers.h
954d720bbb952517040ea8c1648e94dcd01de552 - arm-trusted-firmware/plat/renesas/rcar/bl2_plat_setup.c
65b77a7dbb8e28f892af2bf3b76eff17c87a9cbd - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130/mvebu_def.h
147f2e7e737cb6a5eb1dd98a0deed8c0462d2041 - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c
a1f884a99e9e14ac83551e73429b0cf7a2c5aa0d - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
2311f962795291fdd649a3acb3d3fcee85e19d11 - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
60baba93a9e38f989d8f3fdfb045849d1edc2d69 - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/marvell_plat_config.c
79f7407103c1059afb212382689fff9c6a4f4350 - arm-trusted-firmware/plat/marvell/armada/common/marvell_io_storage.c
6ea11f2ef3d7978e714cdf621aeb7c8719c7edf3 - arm-trusted-firmware/plat/marvell/armada/common/marvell_bl1_setup.c
e8797c2639ec349e76fc1946c984275c010e4cc0 - arm-trusted-firmware/plat/marvell/armada/common/marvell_console.c
2c689ed8bfb3abf1dc9ea37ffaa8aa9479649eac - arm-trusted-firmware/plat/marvell/armada/common/marvell_bl31_setup.c
c785e8c07a0fa5d01b9ecf8eee873f7a18697e3a - arm-trusted-firmware/plat/marvell/armada/common/mrvl_sip_svc.c
5f97ccaef3ab26b2710ad26fb0fdbd9facfd0b7d - arm-trusted-firmware/plat/marvell/armada/common/marvell_gicv3.c
59510c739cc2d9619a9a5c21e1cbf1bb05094867 - arm-trusted-firmware/plat/marvell/armada/common/marvell_pm.c
69ee13cde36accbde0f355f89f9cc2b5d1aa2cb9 - arm-trusted-firmware/plat/marvell/armada/common/marvell_image_load.c
9fa0f4b8209945eb39ccee90bcc305efbe10f211 - arm-trusted-firmware/plat/marvell/armada/common/marvell_gicv2.c
c6e2fab47d050265fe94d5ce57fd1a3a684da2c9 - arm-trusted-firmware/plat/marvell/armada/common/marvell_topology.c
db23baf6374a79472a4b930f1fd68144d4f314a1 - arm-trusted-firmware/plat/marvell/armada/common/marvell_bl2_setup.c
0ff28a152c1c0997120e1e3a5fe654f1ae19ac60 - arm-trusted-firmware/plat/marvell/armada/common/marvell_cci.c
1a879218f61e83b5068e40a2b093fdb4ab851a4d - arm-trusted-firmware/plat/marvell/armada/common/marvell_ddr_info.c
ea896d0f1d011e14c4411020d73d083c22eac783 - arm-trusted-firmware/plat/marvell/armada/common/plat_delay_timer.c
daa5b1a54bfa63c73acf8429940662cd450f1eb9 - arm-trusted-firmware/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c
a71cc21b90eb5b1d29b125e9c98c3e50f9a145bc - arm-trusted-firmware/plat/marvell/armada/common/aarch64/marvell_helpers.S
0842c4cae12a7c22367b83357a2c824d060dee67 - arm-trusted-firmware/plat/marvell/armada/common/aarch64/marvell_common.c
872e517062b5b548f6de42424dfb8290309f6773 - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_scp_bootloader.h
5cecfb1042c66b79c4c4c9bc5961fd91b34c880f - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_scp_bl2_format.h
44573513efade3da9aa2ca94c3d4069a8af646fd - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_mem.h
0bb02e303d4c696fe34379bc2d5dd9f2fe16229d - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_scp_bootloader.c
56e5fda520a793a37c7e8daa1ecfe2354b26e99e - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_ipc_drv.c
42d2fb2461687118d1f9e79ed2ae2a274cc91c45 - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_ipc_drv.h
d00c0cf869839d6cd370b5b6c58e8d066705e2e1 - arm-trusted-firmware/plat/marvell/armada/a3k/common/marvell_plat_config.c
40c2d9f804ed183a8befa38d61bdd2164d711b34 - arm-trusted-firmware/plat/marvell/armada/a3k/common/plat_pm.c
344f94187e37e08b2f532eb66281e7e28e7702c5 - arm-trusted-firmware/plat/marvell/armada/a3k/common/io_addr_dec.c
f1d76afaec515fb65236190a9aced6e0ae2b4d8b - arm-trusted-firmware/plat/marvell/armada/a3k/common/a3700_ea.c
4e66aa51fabafab21b8e01fa4f3d49fc8fe6a97e - arm-trusted-firmware/plat/marvell/armada/a3k/common/a3700_sip_svc.c
f0aaac82be8c1b465622b1b82d8514de62c2e937 - arm-trusted-firmware/plat/marvell/armada/a3k/common/dram_win.c
a8ca841fb42e9bb5a9c071732f25138003b82d96 - arm-trusted-firmware/plat/marvell/armada/a3k/common/plat_cci.c
1b64a7198143a5ec5cbe075762bfc0f47e7eded0 - arm-trusted-firmware/plat/marvell/armada/a3k/common/cm3_system_reset.c
6a97369a4a693cf002e5f5f6ece32516e5978068 - arm-trusted-firmware/plat/marvell/armada/a3k/common/aarch64/a3700_common.c
80f0ae31f4c2b57b330b01be44b293f6aa2cef72 - arm-trusted-firmware/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
965bc32da1f0ff9aa830bcede48eaca19cbe3b29 - arm-trusted-firmware/plat/marvell/armada/a3k/common/aarch64/plat_helpers.S
12bd9050e1d74b888a3866cf8ff79d17103fd0f2 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/plat_macros.S
6c89be0e3e7e102687ce8d216227785edce4db33 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/ddr_info.h
0e8b8f431e24f28a92fcd4fb9d46eb87a1113db4 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/io_addr_dec.h
71cc1316bcad08255d76ad0ad858f47d681be60d - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
58c7ff47a2230af870313a655dcab4f22dd64957 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/dram_win.h
61ab3a7cf4de99459f74b40ee4aa7c4c063f92ab - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/platform_def.h
6a269296c2d98fb8f6f4c1736696c4e6081cbc88 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/a3700_pm.h
2cecd73b6df5a49196420939a6810672640ce165 - arm-trusted-firmware/plat/marvell/armada/a3k/a3700/mvebu_def.h
716620282caf3210c15f6795e996035311a8ddd8 - arm-trusted-firmware/plat/marvell/armada/a3k/a3700/plat_bl31_setup.c
8f4af50a0df849dd31970be55e943ee4302b0472 - arm-trusted-firmware/plat/marvell/armada/a3k/a3700/board/pm_src.c
9a52294343831155772b4411f11af6c989dbd182 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_puzzle/mvebu_def.h
f1c6500edd19c1540f562c4ea2dba8443a7cd419 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_puzzle/board/marvell_plat_config.c
4d33d263a3f05c3d8f3400a45afc2dd7f1792669 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c
7bdf0ea1da45eaab8f21dca700b29582ccc57d0a - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
266ed9c2a714504a190f6bdd10db0d40815a428a - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_pm.c
3f6403fd39850e34f4c3bd674ccf8170f74af43d - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_bl31_setup.c
bc3edb20ef2a7baebacce2c631f800cb6d206bbc - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_bl1_setup.c
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c96d4c2fac061ca1e3be3600ee8748de11d20ed0 - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_pm_trace.c
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04e2455b39d088cb56ccb73dac9c842fb6f6b7eb - arm-trusted-firmware/plat/marvell/armada/a8k/common/ble/ble.ld.S
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0b8ef1037611c38ba89966b1da4ef153e47b4fb4 - arm-trusted-firmware/plat/rockchip/rk3368/rk3368_def.h
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c03dbe37ab69ed71bbbc9100b47ff77d3c1f19e9 - arm-trusted-firmware/plat/rockchip/rk3368/include/plat.ld.S
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1f63c15382d48351f3d1c1709e7428545ce2cb72 - arm-trusted-firmware/plat/rockchip/common/rockchip_sip_svc.c
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258f177b9b9412883f714cff3406818288eca04f - arm-trusted-firmware/plat/rockchip/common/aarch64/pmu_sram_cpus_on.S
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bcf5a24d5d284bc2b87c3b5299a9f548df4bc95f - arm-trusted-firmware/plat/rockchip/rk3288/drivers/pmu/pmu.c
db1ef060ee221e9b61acbb781c42ed42e926b26e - arm-trusted-firmware/plat/rockchip/rk3288/drivers/pmu/plat_pmu_macros.S
0454e2aefd623a64760090a825f3cb0c26b0a3ca - arm-trusted-firmware/plat/rockchip/rk3288/include/plat_sip_calls.h
58f0ccc10fae70932566781c7c34457a239e027c - arm-trusted-firmware/plat/rockchip/rk3288/include/plat_sp_min.ld.S
0a2a001f434d83ab306c453b6d60f886a0b59a96 - arm-trusted-firmware/plat/rockchip/rk3288/include/platform_def.h
1321792bce42c44c3fed91fea86cceca52486ffa - arm-trusted-firmware/plat/rockchip/rk3288/include/shared/bl32_param.h
a5a361643c76bc6ad4e5bf4bef498e6de89c4065 - arm-trusted-firmware/plat/ti/k3/common/k3_gicv3.c
4677f1e48833ef10dc9d9ed492dfe849c8466b05 - arm-trusted-firmware/plat/ti/k3/common/k3_console.c
170634ac25c995303394743ee26ab4f2265800ca - arm-trusted-firmware/plat/ti/k3/common/k3_topology.c
96d874b239805cfedc0fadfd9f07eed0e423a919 - arm-trusted-firmware/plat/ti/k3/common/k3_helpers.S
55b3083cc472c5a3e1808d642b6c6516d19c34be - arm-trusted-firmware/plat/ti/k3/common/k3_psci.c
fd1bbe596ff44d2104431c2924e172d0ef4c5b34 - arm-trusted-firmware/plat/ti/k3/common/k3_bl31_setup.c
d3624f3dc097829d1b9f6b277bd1aebe77963d97 - arm-trusted-firmware/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
27b2ba24623a62aa30daea138411571e17aeb579 - arm-trusted-firmware/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
55f8380907084a69006d5211123aef60fc51400d - arm-trusted-firmware/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
3ebfed887a97b672cad608bc064e08075f4e2a29 - arm-trusted-firmware/plat/ti/k3/common/drivers/ti_sci/ti_sci.h
e81feb55a2328c2ec32fadd561eaf24eb58ae202 - arm-trusted-firmware/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
da89ff4506058f3e90a127f4e7d79a7d86057bfd - arm-trusted-firmware/plat/ti/k3/include/plat_macros.S
015fe87701fa82cd48501c2915505c611e20e933 - arm-trusted-firmware/plat/ti/k3/include/k3_gicv3.h
33ec06e0674715932071745b37498c738414ee8f - arm-trusted-firmware/plat/ti/k3/include/platform_def.h
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c82ee96d8fb1841fd3068f489a697625a217aebe - arm-trusted-firmware/plat/ti/k3/board/lite/include/board_def.h
85bfc710f2f6c79b7c0e025f6f6e653d16f39bb7 - arm-trusted-firmware/plat/ti/k3/board/generic/include/board_def.h
3139c2b0c93ae17696224f59b5486f65e1649dc7 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_gic.c
6a49ad3765ad1a5c42b66eea4f7aeed6c721fdc2 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_stm32image_def.h
c0910ed9fa547ff95728b0592ee3be13b3615d98 - arm-trusted-firmware/plat/st/stm32mp1/bl2_plat_setup.c
10b1e53e6d0c0b259d531d284d6b2f64978ff33d - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_boot_device.c
f171c1cd88d3ea2070a747ca519f7d6b9e8257f5 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_usb_dfu.c
743906eebddff48371349626564704fa54fcdd27 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1.ld.S
dacc55b49253b5d86f120fe7e2ed1de0aaadadcc - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_private.c
7b00ed042c247bac94b4766cb42dddc0e21764fc - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_scmi.c
4ee1c481f43d2f2b9798ffc1f9c6cafa4d1cc371 - arm-trusted-firmware/plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c
c7727e6a5eb36a39432103f9641b5d1c522fb1a7 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_def.h
77c94644e0ef95316e08e0a339fb16a856ae5d97 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_dbgmcu.c
9ad0a2f43f8a0c69c26073e06425579f59986e7b - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_pm.c
e53bc6a3ed66be157fcca494d961241c4a067815 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_security.c
ec9fe0a8eec79fee1d3dd34bf1a969b8f0b93f4a - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_shared_resources.c
82d557ad976b6dfd8dcdce69b68986e9be70cd5a - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1.S
0f0baced38fb65393cd300bdc024b68e707f5f4b - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_topology.c
b900c2f6ef836a0f77c00c851815a09220d8c5e3 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_fconf_firewall.c
71c56ab2e235cc9495de74461f1e2035229c09c0 - arm-trusted-firmware/plat/st/stm32mp1/plat_image_load.c
d0b4272a97d261d88b6bff05bd2162e0d939ffbb - arm-trusted-firmware/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
43753b990fdb953ffc38ef29474ef4af453444b7 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_stack_protector.c
3cdcc47dcc28c6e6de2c940df01b5c91d95af92c - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_helper.S
edb672bfa3c76059c60544793fb08658398cb3b2 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_fip_def.h
58a5d9c283fcb21c6328e65dda44190d07fe6bb2 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_syscfg.c
406790007d4d597b108faf9871360acfa7cdcf23 - arm-trusted-firmware/plat/st/stm32mp1/services/stm32mp1_svc_setup.c
89ab811529f632c51fa5e732be395bac1ea89887 - arm-trusted-firmware/plat/st/stm32mp1/services/bsec_svc.c
3b882920ab056c9bbc38be63b2715e1d796109c4 - arm-trusted-firmware/plat/st/stm32mp1/services/bsec_svc.h
34bda94b3b92d9b971e0e52f26c98293f35800df - arm-trusted-firmware/plat/st/stm32mp1/include/stm32mp1_private.h
7eaf59b974175885a0dfccf0b42c774580444f92 - arm-trusted-firmware/plat/st/stm32mp1/include/stm32mp1_smc.h
d12872b893bf8db2b51b7243dd638bf34e9d6cfa - arm-trusted-firmware/plat/st/stm32mp1/include/stm32mp1_dbgmcu.h
6d6391c62306978263be31d559221680ed9b6025 - arm-trusted-firmware/plat/st/stm32mp1/include/stm32mp1_shared_resources.h
0cbf680fead56b073a247b36589a06e814bf8995 - arm-trusted-firmware/plat/st/stm32mp1/include/boot_api.h
6a9fdf66f28b06f20ed4b08bed769e38d88e5995 - arm-trusted-firmware/plat/st/stm32mp1/include/platform_def.h
86477b53739886930268a20a1950ef8cb2a1c279 - arm-trusted-firmware/plat/st/stm32mp1/sp_min/sp_min_setup.c
ad3aca5d4f9af9d21c376f972399e2cbbb7102e8 - arm-trusted-firmware/plat/st/common/bl2_stm32_io_storage.c
46faa99b227394b11051186b86a163d67c081adc - arm-trusted-firmware/plat/st/common/stm32cubeprogrammer_usb.c
356f823bccc7081e026233c6fb511c0602208101 - arm-trusted-firmware/plat/st/common/usb_dfu.c
278442fbef0471df0addfc2b3ce1b10552541e65 - arm-trusted-firmware/plat/st/common/stm32cubeprogrammer_uart.c
0d0e487dbff201564fae2a5f2e0bc45059a3ad3d - arm-trusted-firmware/plat/st/common/stm32mp_common.c
79d69f4be6d9e1fc494884f41f92bede1b67c8ff - arm-trusted-firmware/plat/st/common/stm32mp_dt.c
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7a33a3419c93c0bbb21a2c8df792965674477cbf - arm-trusted-firmware/plat/st/common/bl2_io_storage.c
b6a6f8374d7f3eadc9cd9b6ad93f62ed12f6851f - arm-trusted-firmware/plat/st/common/stm32mp_fconf_io.c
2a0d6172df32ead3a019d2cbc33e260c3aeba294 - arm-trusted-firmware/plat/st/common/include/stm32mp_common.h
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dd7ae18098736e737a0482a59de65f64d5edd503 - arm-trusted-firmware/plat/st/common/include/stm32cubeprogrammer.h
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667de698f76e8d0b6d6f1b85f8012f3bed27e925 - arm-trusted-firmware/plat/arm/common/arm_ccn.c
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c3c969f538ef3f3853d867a2c9c020723e5adc66 - arm-trusted-firmware/plat/arm/common/arm_tzc_dmc500.c
1f2643d0dcc34c7b46895a5dd300de2674cc1274 - arm-trusted-firmware/plat/arm/common/arm_dyn_cfg_helpers.c
8d5a41b0cad025e83538d4508b8de54c96dd6be8 - arm-trusted-firmware/plat/arm/common/arm_pm.c
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61b4b6215ec4cf4e050d7a14359bfdc2b64e2d8e - arm-trusted-firmware/plat/arm/common/arm_sip_svc.c
53d385569ada7ff06030853184930078d8a2e4d8 - arm-trusted-firmware/plat/arm/common/arm_cci.c
3b628c17fd98697338a0997a380df8a81c7d2e66 - arm-trusted-firmware/plat/arm/common/arm_bl2u_setup.c
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5f8fb896e304dbb204531641566de21b2e53a426 - arm-trusted-firmware/plat/arm/common/arm_tzc400.c
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70afb2dd0a66c2a2b6eb5bfaf16df448d90e029d - arm-trusted-firmware/plat/arm/common/arm_io_storage.c
420e2c07ae07c6152cc914a3b464ec17f2f92843 - arm-trusted-firmware/plat/arm/common/arm_bl31_setup.c
6e9da80beed8b267a6c15c88f8b25e81d8b7bda4 - arm-trusted-firmware/plat/arm/common/arm_bl1_setup.c
845db666afafcf708e365edd5461d9071f72c738 - arm-trusted-firmware/plat/arm/common/arm_gicv3.c
dd2c481628c54d07d905a85f08e527943473d31b - arm-trusted-firmware/plat/arm/common/arm_nor_psci_mem_protect.c
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6ee204b0e2a5012ad4dcef1cfe9fe884590bfb8c - arm-trusted-firmware/plat/arm/common/aarch64/execution_state_switch.c
1177013eddcf476b6a6d1f3367ae319363663450 - arm-trusted-firmware/plat/arm/common/aarch64/arm_pauth.c
425d4b8c29564ce790babb9ea3fcc7ad80224fc6 - arm-trusted-firmware/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
cc6a2551546758984d250e491c5c077149044f98 - arm-trusted-firmware/plat/arm/common/aarch64/arm_helpers.S
8543903cea745c6c6709fd524622d3d5d3fd8df2 - arm-trusted-firmware/plat/arm/common/aarch64/arm_sdei.c
17e3af5dfebbe4a8933589c7b3c67e14faa7dc12 - arm-trusted-firmware/plat/arm/common/trp/arm_trp_setup.c
361186531a919bdc7825945fec639bf0db44800f - arm-trusted-firmware/plat/arm/common/fconf/fconf_nv_cntr_getter.c
dce55e77a6a4b9da7a42be37f5bba717d0c353e0 - arm-trusted-firmware/plat/arm/common/fconf/fconf_sdei_getter.c
ac62b3ab6e132e1747dbd2ffd6f40a72b4270235 - arm-trusted-firmware/plat/arm/common/fconf/fconf_sec_intr_config.c
a666a9d920e0637f17e51eff519cc94c115b1ef7 - arm-trusted-firmware/plat/arm/common/fconf/arm_fconf_io.c
fc971d9e587662fd23f35aa2dfbf0abf23c9da74 - arm-trusted-firmware/plat/arm/common/fconf/fconf_ethosn_getter.c
3ddfbb8ae3448f315371d7a3a814bea1d055cd3a - arm-trusted-firmware/plat/arm/common/fconf/arm_fconf_sp.c
cacda44b3716b65a5c30eedd17ed5a1335b8597b - arm-trusted-firmware/plat/arm/common/tsp/arm_tsp_setup.c
43a64183c368a80bc24e370c93889989a49bfca3 - arm-trusted-firmware/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
8c6171b381cfc6eca906ce2f7e2e6658895380ca - arm-trusted-firmware/plat/arm/common/aarch32/arm_helpers.S
3237cf84bb44f0cc5b45b74d69d2934525543135 - arm-trusted-firmware/plat/arm/common/sp_min/arm_sp_min_setup.c
5072fa161b5fff3742a05eb8b9def551087be013 - arm-trusted-firmware/plat/arm/css/sgm/sgm_interconnect.c
bf1abf676327ef4b5c2fbe971bf5c59f9eea2511 - arm-trusted-firmware/plat/arm/css/sgm/sgm_security.c
6986ea7e2525388afa6171359d9f0c71de119e6e - arm-trusted-firmware/plat/arm/css/sgm/sgm_bl1_setup.c
fc6ffe0f853fbf9871294d23c034cf4eb00a0b99 - arm-trusted-firmware/plat/arm/css/sgm/sgm_mmap_config.c
fb1634b97815fe2a2d9fcc807b394bdf1a034423 - arm-trusted-firmware/plat/arm/css/sgm/sgm_bl31_setup.c
408a01ed446d78cc578fa633ca47d7068ede3735 - arm-trusted-firmware/plat/arm/css/sgm/sgm_topology.c
6a32e8055bf1477d80b315a472542bc3c28106d5 - arm-trusted-firmware/plat/arm/css/sgm/sgm_plat_config.c
d55a2717a5f47927531e46527bd40fb912dd16f2 - arm-trusted-firmware/plat/arm/css/sgm/aarch64/css_sgm_helpers.S
883fce52c6e023b9718833ef01eff53d740f4b22 - arm-trusted-firmware/plat/arm/css/sgm/include/sgm_plat_config.h
21772c91952bd2813284b444505fc85183bed867 - arm-trusted-firmware/plat/arm/css/sgm/include/plat_macros.S
c9020cce76399dabf8d4bf04257761ee38ea4d60 - arm-trusted-firmware/plat/arm/css/sgm/include/sgm_variant.h
6c95a3344c3a15036b1db884d62a972e802699ed - arm-trusted-firmware/plat/arm/css/sgm/include/sgm_base_platform_def.h
00d4810ce12b4356434c80bbf98203811ee07a32 - arm-trusted-firmware/plat/arm/css/sgm/fdts/sgm_tb_fw_config.dts
5e82b47a941edb5ba37196b7aefe2a54e3bd2f81 - arm-trusted-firmware/plat/arm/css/sgm/tsp/sgm_tsp_setup.c
da446db6b40b974a31d66ba55f23047f28d3f748 - arm-trusted-firmware/plat/arm/css/sgi/sgi_interconnect.c
a12ad9fe2e578f1c9186976a41033a398307aba6 - arm-trusted-firmware/plat/arm/css/sgi/sgi_ras.c
5c168081100ace91d38be064d9d21551630d21c0 - arm-trusted-firmware/plat/arm/css/sgi/sgi_image_load.c
c6341f0f666b8a901520e32310b18a323af9f925 - arm-trusted-firmware/plat/arm/css/sgi/sgi_topology.c
31824343e1235090b12b73c827b8cbf02ba4d0e4 - arm-trusted-firmware/plat/arm/css/sgi/sgi_plat_v2.c
7a79c4c409726322831974860de49b71547d6feb - arm-trusted-firmware/plat/arm/css/sgi/sgi_bl31_setup.c
b33a69c22fcc5e0d8abd886b78b557633834d721 - arm-trusted-firmware/plat/arm/css/sgi/sgi_plat.c
aeb8a1b51452a7c1b9088cd2cc5f0c6ab2590b45 - arm-trusted-firmware/plat/arm/css/sgi/aarch64/sgi_helper.S
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3bb8192919eea022c0cfa99a7d87f8ecd4588256 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_base_platform_def.h
468e61508695c6dc9df856865e295b59c32a54e3 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_soc_platform_def.h
b45c063aa1fdf9280c52020500ae6e83d71244c5 - arm-trusted-firmware/plat/arm/css/sgi/include/plat_macros.S
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4e4ddcdd110f807b8dcbd6b440a4b4f5c2f9e83b - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_variant.h
c388d0822e5ef0bf97db4c66ab46d4088421f0e6 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h
7617a0e9164a7f90465861eedd913dabf15379f8 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
138c1bc36bb3c91d2b2d9f5ac1702aa0975c850c - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h
f00b456e46701cc6a1e2b31fdd93091805ab0809 - arm-trusted-firmware/plat/arm/css/common/css_bl1_setup.c
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3693a7e757b2541552b2c91c91a0dba2d6a0a8de - arm-trusted-firmware/plat/arm/board/rdn2/rdn2_security.c
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0edacdd0dc4a2af6f50c21ccdf98244fe72c6730 - arm-trusted-firmware/plat/arm/board/common/board_arm_trusted_boot.c
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cdb90754cb9118d6571aad9c3846b2c410f708d1 - arm-trusted-firmware/plat/arm/board/common/protpk/arm_protpk_rsa_sha256.bin
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0b886935846ab1d278829932851b6cc492f106cc - arm-trusted-firmware/plat/arm/board/juno/juno_bl31_setup.c
53c5a79a63bf1f5551016da97e29bf8702e32ad3 - arm-trusted-firmware/plat/arm/board/juno/juno_def.h
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6cea3743018f1d02cac51c8d78a92561ea46ce14 - arm-trusted-firmware/plat/arm/board/juno/juno_bl2_setup.c
49553a7fbab54730a1b3de994aa92810c35025da - arm-trusted-firmware/plat/arm/board/juno/jmptbl.i
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07f098d234d16533d40b505e91dbb1aae1712650 - arm-trusted-firmware/plat/arm/board/juno/juno_security.c
17d854b860806d6ad8af6ee63952524a3bcbd9e9 - arm-trusted-firmware/plat/arm/board/juno/juno_pm.c
419b6382a2607911be10024a6287e69289234326 - arm-trusted-firmware/plat/arm/board/juno/juno_topology.c
0ff3d7a6c51d9752cc2a86bb19e800a94245eea2 - arm-trusted-firmware/plat/arm/board/juno/juno_stack_protector.c
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805360ecd38e071b1f2e9b60704130be813557e2 - arm-trusted-firmware/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
319dfb0515299119770970eb5953825ab7abd95c - arm-trusted-firmware/plat/arm/board/juno/aarch32/juno_helpers.S
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4497a7586471f072a94ff5a066931c86dcb6fd2d - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_security.c
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5a64604c368489c4585ba4e01e129b3687e5d8ff - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
4b16feb977654bc82a89a104dc5b31b167bf17d1 - arm-trusted-firmware/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S
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af1f8d5af2ee91ba0dd180c42a7b8f73b7543474 - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_security.c
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007839db0f0e5c02b3362ce770b02771a47faa27 - arm-trusted-firmware/plat/arm/board/a5ds/a5ds_topology.c
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2ce9cd0a5ef399a537316089ff1451da165bdd42 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S
1f85fcf3a3d2c0bd5a8c5e848a4841400b54f9fe - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_private.h
486d3021b7aeeb557efb82cafa7337d3d3041fb7 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_bl1_main.c
8e7bab3de835fbccc87f8d20b8acecc011d4fcaa - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_debug.S
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1c209493074be7ae85b1aafe237784f10e2b7093 - arm-trusted-firmware/plat/arm/board/rdv1/rdv1_topology.c
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77c37592e064ebc47319196a2468d4a75a6ff7de - arm-trusted-firmware/plat/arm/board/rdv1/fdts/rdv1_tb_fw_config.dts
3d1a55d785180dd11beb8473207268d04543695a - arm-trusted-firmware/plat/arm/board/corstone700/common/corstone700_helpers.S
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aa3d4b5a511124fc6ae5cd9244633af5ae0ab4a9 - arm-trusted-firmware/plat/arm/board/rde1edge/rde1edge_security.c
7be90ba89049185165cc3d60d523a66fd7a1a0bf - arm-trusted-firmware/plat/arm/board/rde1edge/include/platform_def.h
e5b638c1ab3d0ee37ca9b8702ee4262358c3559b - arm-trusted-firmware/plat/arm/board/rde1edge/fdts/rde1edge_fw_config.dts
0397a242841f6193faacaba41c8326032a1e7729 - arm-trusted-firmware/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts
1477905828689906107808c1098cccb0a22dc73b - arm-trusted-firmware/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
d4a49ec110e03192903aeabeae1df36bca1cae8a - arm-trusted-firmware/plat/arm/board/rdv1mc/rdv1mc_plat.c
3f70fab8ee8fcd7926df2c977d9380f53cbbb9f6 - arm-trusted-firmware/plat/arm/board/rdv1mc/rdv1mc_security.c
866a21334d0661b2dde96c9ea5c2e2c99e649ab3 - arm-trusted-firmware/plat/arm/board/rdv1mc/rdv1mc_trusted_boot.c
04538cf26382d09d8e2c07c0b46f13a5b099236a - arm-trusted-firmware/plat/arm/board/rdv1mc/rdv1mc_topology.c
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05ecf6ab819a6a6ca826e872d3c1fa6a21c7e7ef - arm-trusted-firmware/plat/arm/board/rdv1mc/include/platform_def.h
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0e3644e6d15833cfd15ee928af181e156ec27e8a - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
810d8a4c9a7dff63b504d43fa4691f19cdf86b3b - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
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19591a34444effbe25bc3245bb68e6462bda0024 - arm-trusted-firmware/plat/arm/board/fvp/fvp_pm.c
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10c7154aeb64129154f13657841ad8f9aee6af85 - arm-trusted-firmware/plat/arm/board/fvp/fvp_trusted_boot.c
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a1e4c883f6912bad1724268901a148f96250854a - arm-trusted-firmware/plat/arm/board/fvp/fvp_realm_attest_key.c
fa75b4ccee6e6d8604b819da30a1ed892db70b15 - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl1_setup.c
87220bf30d58a155c2f10f38418d094db212e5b6 - arm-trusted-firmware/plat/arm/board/fvp/fvp_private.h
df0b10a5b65cf57a485f5eb846e0cfa7e64c429b - arm-trusted-firmware/plat/arm/board/fvp/fvp_io_storage.c
d25e9c719859733739581faecd38cfa80443aa83 - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2_measured_boot.c
71418933f8bb76fa971723d4cb9bc6748a009f33 - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2_el3_setup.c
d62b302ac0bf1976ed0084160aeba061e325a6c3 - arm-trusted-firmware/plat/arm/board/fvp/fvp_plat_attest_token.c
a3147836e6e11bb9b651753fee98a99b2f81062b - arm-trusted-firmware/plat/arm/board/fvp/fvp_common.c
394a425b1d229fbbad1173c1371edc737857d5f2 - arm-trusted-firmware/plat/arm/board/fvp/jmptbl.i
0c3494f4c7e2590865b69abf91d4b49be1ea469d - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl31_setup.c
20e8179e5c61147fc2d627dbb503babac430603c - arm-trusted-firmware/plat/arm/board/fvp/fvp_def.h
6f76c4d8ae1abb640a62785bfc535bcb485f9511 - arm-trusted-firmware/plat/arm/board/fvp/fvp_topology.c
aed35e7aa732be73eef26face244c3acdee67640 - arm-trusted-firmware/plat/arm/board/fvp/fvp_console.c
223e1339e343160feab72cff7621103ada50dbc9 - arm-trusted-firmware/plat/arm/board/fvp/fvp_common_measured_boot.c
1924351967826f1ad9898254b30419ba2e7fb9cc - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2u_setup.c
0a86ad28b6ae96f93bdbcc32be32335d3e8250e9 - arm-trusted-firmware/plat/arm/board/fvp/fvp_err.c
d5a6187ffa8ab68518e9d896c2d50bbf600d68cd - arm-trusted-firmware/plat/arm/board/fvp/aarch64/fvp_helpers.S
3f4bcd29ccbf7cd09dfe8275846469b38db62e2f - arm-trusted-firmware/plat/arm/board/fvp/aarch64/fvp_ras.c
83e404fdd5bc4dda0b68b92d365d6e9b047f13d3 - arm-trusted-firmware/plat/arm/board/fvp/fconf/fconf_nt_config_getter.c
10fc5531e7b7d5ac9ffba191f525b64179843eae - arm-trusted-firmware/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
84180022623ad574044b9436e62202ee5635c6ae - arm-trusted-firmware/plat/arm/board/fvp/include/fconf_hw_config_getter.h
aed581dcf8acf86f277ecf028cc1eec4f0c081fc - arm-trusted-firmware/plat/arm/board/fvp/include/plat_macros.S
12b7439bee5ead5da71eb5a42a9c5cc493f9c7fc - arm-trusted-firmware/plat/arm/board/fvp/include/fvp_critical_data.h
aaff5cd1241ce58ab9627da89fb4860390a0864b - arm-trusted-firmware/plat/arm/board/fvp/include/fconf_nt_config_getter.h
c7af81d092cd74c1eba0402a02368b53f801c235 - arm-trusted-firmware/plat/arm/board/fvp/include/platform_def.h
1f6772f1b9358e6acc890bc4475a57f68cebc72d - arm-trusted-firmware/plat/arm/board/fvp/include/plat.ld.S
df9f20c998402fb612824aeec7d618e97e023cb8 - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
7dd67253d1f53292fbdd750b1360cace93220e02 - arm-trusted-firmware/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
aba68daa32f394274fa0c7b3ebb2d77514e105da - arm-trusted-firmware/plat/arm/board/fvp/fdts/event_log.dtsi
33a1a8c0c5e1f8f806d0dbe69adab509f55301be - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_nt_fw_config.dts
5601a00daf6c8ba481f1addc03652d97efe84a3c - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_soc_fw_config.dts
b8ba7eb0ce440dedebafa08a9e3ffde066832d0a - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_fw_config.dts
b1406e98f75e782442a0fdfe50c8aad26cf5aeb5 - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
26761d08528feec31bb15a854b65dd46629135fe - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_tsp_fw_config.dts
43a2362473fca426e3a62517552c20c2a629a563 - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
b59b8589b390aaea5c26a9621713fe3d78e47e8b - arm-trusted-firmware/plat/arm/board/fvp/tsp/fvp_tsp_setup.c
2c7ccf1e47b4fdac9dc7745e506f4194cce2e498 - arm-trusted-firmware/plat/arm/board/fvp/aarch32/fvp_helpers.S
6adce62f756dc0792fb3a4d6aa6cec60e0b54117 - arm-trusted-firmware/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
561594e99d3e16d7826006d518e141e9a58eadec - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_security.c
ba9b8a6b4b36804eb8c8aee5b17845c85db8a845 - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_plat.c
851570d1add4283d5a01ff4893f1558decb2d6e9 - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_topology.c
7d37a6f29bbe666c9db7538d4d7a123d1ab40b17 - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_err.c
866a21334d0661b2dde96c9ea5c2e2c99e649ab3 - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_trusted_boot.c
97f84a745ae8fccb804dc7e0ba50b85d46ed4198 - arm-trusted-firmware/plat/arm/board/rdn1edge/include/platform_def.h
5d0744ed59fc75ba7204d9d0083fbc0cd64e74d6 - arm-trusted-firmware/plat/arm/board/rdn1edge/fdts/rdn1edge_fw_config.dts
869fa43b401d5d394651f9d1bd9eb784b7ebb14d - arm-trusted-firmware/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts
a87583e95c695a2bf6af550cd6fbbffb3eae3961 - arm-trusted-firmware/plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
d115cd145587e366c9c6d02d47cc7ea610f7791f - arm-trusted-firmware/plat/arm/board/morello/morello_security.c
c855687b5adb537f1a56e37496a708864bd72650 - arm-trusted-firmware/plat/arm/board/morello/morello_bl1_setup.c
275ff8fd1cb66a02cc8ca9b9494035d3aa7f8ebf - arm-trusted-firmware/plat/arm/board/morello/morello_image_load.c
59b5177c9b302f117bea58642d758d747224eaed - arm-trusted-firmware/plat/arm/board/morello/morello_interconnect.c
ab6ec67031b519490edd2bdd7efb973f91af2453 - arm-trusted-firmware/plat/arm/board/morello/morello_bl31_setup.c
846d7f92ffe6c368d0d0b85ffa36409b0dd04caf - arm-trusted-firmware/plat/arm/board/morello/morello_trusted_boot.c
021dca0ec2928f72c45e98a602338d8a2bb08cc2 - arm-trusted-firmware/plat/arm/board/morello/morello_err.c
710e4ce5fe08ed123d1977361a4bbf49dff07ba9 - arm-trusted-firmware/plat/arm/board/morello/morello_def.h
eae232f83e8fef4997f24f4cce1d598178a8eab0 - arm-trusted-firmware/plat/arm/board/morello/morello_plat.c
9e616a8e89120ae9b614d9bae16f0de9aa886778 - arm-trusted-firmware/plat/arm/board/morello/morello_bl2_setup.c
0105670429d8a205bc698cf69de09044501a55a1 - arm-trusted-firmware/plat/arm/board/morello/morello_topology.c
1c3ff5d4d35a2aa211380dea2b252236f3dae0b1 - arm-trusted-firmware/plat/arm/board/morello/aarch64/morello_helper.S
5361abb465b0253014c38facafec374dd284699a - arm-trusted-firmware/plat/arm/board/morello/include/plat_macros.S
e1eb7e2194a62fcfa63e0d92da3567386d98a24d - arm-trusted-firmware/plat/arm/board/morello/include/platform_def.h
a95b1476c52a6213400f2402811d15e5d82d7d83 - arm-trusted-firmware/plat/arm/board/morello/fdts/morello_tb_fw_config.dts
bf30791c97940cf78bee90bb458a53b2480a4154 - arm-trusted-firmware/plat/arm/board/morello/fdts/morello_nt_fw_config.dts
9c4c899115425303ba08c836c2a6ca740418160b - arm-trusted-firmware/plat/arm/board/morello/fdts/morello_fw_config.dts
0ca4a4d2749cd227831e57d361b8c16ee0f3cf03 - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_gicv3.c
ef779e5f985f2ebef6d66a83442695603c463465 - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_def.h
bdf16498e248d1d87d012aca5001940fb8328395 - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_private.h
15269f87cab6dfa65ce9cbaacbb13ee9cf2af583 - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_pm.c
86553039cac69d2003776608e4a3172af5f6263d - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_console.c
1cfbd3237d5138875eda5a3f57ebd08f452c4992 - arm-trusted-firmware/plat/arm/board/arm_fpga/kernel_trampoline.S
70fd1afdd7b31d55ddd95d7018ba66095315083e - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_topology.c
89a8aeb02e2a9467d783383e96d830647443b99d - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_bl31_setup.c
78391ad4c170cb70d2db6ad5639108f4f6020dc6 - arm-trusted-firmware/plat/arm/board/arm_fpga/rom_trampoline.S
fe445cbd11196fc3c69cdcbc6be5cdbc4354026b - arm-trusted-firmware/plat/arm/board/arm_fpga/build_axf.ld.S
205b5febc22c83179a2fc6c9005499ef61e8f347 - arm-trusted-firmware/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S
87820ef2083d1576c3d29546b46fb922eafa3737 - arm-trusted-firmware/plat/arm/board/arm_fpga/include/plat_macros.S
6631f2221faec011381242d2e2011d9eda3e9780 - arm-trusted-firmware/plat/arm/board/arm_fpga/include/platform_def.h

Change-Id: I9cb415bc8012c3bcb1f2820256c6da8202bfc0ec

arm-trusted-firmware/docs/design/alt-boot-flows.rst

@@ -0,0 +1,84 @@
+Alternative Boot Flows
+======================
+
+EL3 payloads alternative boot flow
+----------------------------------
+
+On a pre-production system, the ability to execute arbitrary, bare-metal code at
+the highest exception level is required. It allows full, direct access to the
+hardware, for example to run silicon soak tests.
+
+Although it is possible to implement some baremetal secure firmware from
+scratch, this is a complex task on some platforms, depending on the level of
+configuration required to put the system in the expected state.
+
+Rather than booting a baremetal application, a possible compromise is to boot
+``EL3 payloads`` through TF-A instead. This is implemented as an alternative
+boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
+other BL images and passing control to BL31. It reduces the complexity of
+developing EL3 baremetal code by:
+
+-  putting the system into a known architectural state;
+-  taking care of platform secure world initialization;
+-  loading the SCP_BL2 image if required by the platform.
+
+When booting an EL3 payload on Arm standard platforms, the configuration of the
+TrustZone controller is simplified such that only region 0 is enabled and is
+configured to permit secure access only. This gives full access to the whole
+DRAM to the EL3 payload.
+
+The system is left in the same state as when entering BL31 in the default boot
+flow. In particular:
+
+-  Running in EL3;
+-  Current state is AArch64;
+-  Little-endian data access;
+-  All exceptions disabled;
+-  MMU disabled;
+-  Caches disabled.
+
+.. _alt_boot_flows_el3_payload:
+
+Booting an EL3 payload
+~~~~~~~~~~~~~~~~~~~~~~
+
+The EL3 payload image is a standalone image and is not part of the FIP. It is
+not loaded by TF-A. Therefore, there are 2 possible scenarios:
+
+-  The EL3 payload may reside in non-volatile memory (NVM) and execute in
+   place. In this case, booting it is just a matter of specifying the right
+   address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
+
+-  The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
+   run-time.
+
+To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
+used. The infinite loop that it introduces in BL1 stops execution at the right
+moment for a debugger to take control of the target and load the payload (for
+example, over JTAG).
+
+It is expected that this loading method will work in most cases, as a debugger
+connection is usually available in a pre-production system. The user is free to
+use any other platform-specific mechanism to load the EL3 payload, though.
+
+
+Preloaded BL33 alternative boot flow
+------------------------------------
+
+Some platforms have the ability to preload BL33 into memory instead of relying
+on TF-A to load it. This may simplify packaging of the normal world code and
+improve performance in a development environment. When secure world cold boot
+is complete, TF-A simply jumps to a BL33 base address provided at build time.
+
+For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
+used when compiling TF-A. For example, the following command will create a FIP
+without a BL33 and prepare to jump to a BL33 image loaded at address
+0x80000000:
+
+.. code:: shell
+
+    make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*

arm-trusted-firmware/docs/design/auth-framework.rst

@@ -0,0 +1,980 @@
+Authentication Framework & Chain of Trust
+=========================================
+
+The aim of this document is to describe the authentication framework
+implemented in Trusted Firmware-A (TF-A). This framework fulfills the
+following requirements:
+
+#. It should be possible for a platform port to specify the Chain of Trust in
+   terms of certificate hierarchy and the mechanisms used to verify a
+   particular image/certificate.
+
+#. The framework should distinguish between:
+
+   -  The mechanism used to encode and transport information, e.g. DER encoded
+      X.509v3 certificates to ferry Subject Public Keys, hashes and non-volatile
+      counters.
+
+   -  The mechanism used to verify the transported information i.e. the
+      cryptographic libraries.
+
+The framework has been designed following a modular approach illustrated in the
+next diagram:
+
+::
+
+        +---------------+---------------+------------+
+        | Trusted       | Trusted       | Trusted    |
+        | Firmware      | Firmware      | Firmware   |
+        | Generic       | IO Framework  | Platform   |
+        | Code i.e.     | (IO)          | Port       |
+        | BL1/BL2 (GEN) |               | (PP)       |
+        +---------------+---------------+------------+
+               ^               ^               ^
+               |               |               |
+               v               v               v
+         +-----------+   +-----------+   +-----------+
+         |           |   |           |   | Image     |
+         | Crypto    |   | Auth      |   | Parser    |
+         | Module    |<->| Module    |<->| Module    |
+         | (CM)      |   | (AM)      |   | (IPM)     |
+         |           |   |           |   |           |
+         +-----------+   +-----------+   +-----------+
+               ^                               ^
+               |                               |
+               v                               v
+        +----------------+             +-----------------+
+        | Cryptographic  |             | Image Parser    |
+        | Libraries (CL) |             | Libraries (IPL) |
+        +----------------+             +-----------------+
+                      |                |
+                      |                |
+                      |                |
+                      v                v
+                     +-----------------+
+                     | Misc. Libs e.g. |
+                     | ASN.1 decoder   |
+                     |                 |
+                     +-----------------+
+
+        DIAGRAM 1.
+
+This document describes the inner details of the authentication framework and
+the abstraction mechanisms available to specify a Chain of Trust.
+
+Framework design
+----------------
+
+This section describes some aspects of the framework design and the rationale
+behind them. These aspects are key to verify a Chain of Trust.
+
+Chain of Trust
+~~~~~~~~~~~~~~
+
+A CoT is basically a sequence of authentication images which usually starts with
+a root of trust and culminates in a single data image. The following diagram
+illustrates how this maps to a CoT for the BL31 image described in the
+`TBBR-Client specification`_.
+
+::
+
+        +------------------+       +-------------------+
+        | ROTPK/ROTPK Hash |------>| Trusted Key       |
+        +------------------+       | Certificate       |
+                                   | (Auth Image)      |
+                                  /+-------------------+
+                                 /            |
+                                /             |
+                               /              |
+                              /               |
+                             L                v
+        +------------------+       +-------------------+
+        | Trusted World    |------>| BL31 Key          |
+        | Public Key       |       | Certificate       |
+        +------------------+       | (Auth Image)      |
+                                   +-------------------+
+                                  /           |
+                                 /            |
+                                /             |
+                               /              |
+                              /               v
+        +------------------+ L     +-------------------+
+        | BL31 Content     |------>| BL31 Content      |
+        | Certificate PK   |       | Certificate       |
+        +------------------+       | (Auth Image)      |
+                                   +-------------------+
+                                  /           |
+                                 /            |
+                                /             |
+                               /              |
+                              /               v
+        +------------------+ L     +-------------------+
+        | BL31 Hash        |------>| BL31 Image        |
+        |                  |       | (Data Image)      |
+        +------------------+       |                   |
+                                   +-------------------+
+
+        DIAGRAM 2.
+
+The root of trust is usually a public key (ROTPK) that has been burnt in the
+platform and cannot be modified.
+
+Image types
+~~~~~~~~~~~
+
+Images in a CoT are categorised as authentication and data images. An
+authentication image contains information to authenticate a data image or
+another authentication image. A data image is usually a boot loader binary, but
+it could be any other data that requires authentication.
+
+Component responsibilities
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For every image in a Chain of Trust, the following high level operations are
+performed to verify it:
+
+#. Allocate memory for the image either statically or at runtime.
+
+#. Identify the image and load it in the allocated memory.
+
+#. Check the integrity of the image as per its type.
+
+#. Authenticate the image as per the cryptographic algorithms used.
+
+#. If the image is an authentication image, extract the information that will
+   be used to authenticate the next image in the CoT.
+
+In Diagram 1, each component is responsible for one or more of these operations.
+The responsibilities are briefly described below.
+
+TF-A Generic code and IO framework (GEN/IO)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+These components are responsible for initiating the authentication process for a
+particular image in BL1 or BL2. For each BL image that requires authentication,
+the Generic code asks recursively the Authentication module what is the parent
+image until either an authenticated image or the ROT is reached. Then the
+Generic code calls the IO framework to load the image and calls the
+Authentication module to authenticate it, following the CoT from ROT to Image.
+
+TF-A Platform Port (PP)
+^^^^^^^^^^^^^^^^^^^^^^^
+
+The platform is responsible for:
+
+#. Specifying the CoT for each image that needs to be authenticated. Details of
+   how a CoT can be specified by the platform are explained later. The platform
+   also specifies the authentication methods and the parsing method used for
+   each image.
+
+#. Statically allocating memory for each parameter in each image which is
+   used for verifying the CoT, e.g. memory for public keys, hashes etc.
+
+#. Providing the ROTPK or a hash of it.
+
+#. Providing additional information to the IPM to enable it to identify and
+   extract authentication parameters contained in an image, e.g. if the
+   parameters are stored as X509v3 extensions, the corresponding OID must be
+   provided.
+
+#. Fulfill any other memory requirements of the IPM and the CM (not currently
+   described in this document).
+
+#. Export functions to verify an image which uses an authentication method that
+   cannot be interpreted by the CM, e.g. if an image has to be verified using a
+   NV counter, then the value of the counter to compare with can only be
+   provided by the platform.
+
+#. Export a custom IPM if a proprietary image format is being used (described
+   later).
+
+Authentication Module (AM)
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+It is responsible for:
+
+#. Providing the necessary abstraction mechanisms to describe a CoT. Amongst
+   other things, the authentication and image parsing methods must be specified
+   by the PP in the CoT.
+
+#. Verifying the CoT passed by GEN by utilising functionality exported by the
+   PP, IPM and CM.
+
+#. Tracking which images have been verified. In case an image is a part of
+   multiple CoTs then it should be verified only once e.g. the Trusted World
+   Key Certificate in the TBBR-Client spec. contains information to verify
+   SCP_BL2, BL31, BL32 each of which have a separate CoT. (This
+   responsibility has not been described in this document but should be
+   trivial to implement).
+
+#. Reusing memory meant for a data image to verify authentication images e.g.
+   in the CoT described in Diagram 2, each certificate can be loaded and
+   verified in the memory reserved by the platform for the BL31 image. By the
+   time BL31 (the data image) is loaded, all information to authenticate it
+   will have been extracted from the parent image i.e. BL31 content
+   certificate. It is assumed that the size of an authentication image will
+   never exceed the size of a data image. It should be possible to verify this
+   at build time using asserts.
+
+Cryptographic Module (CM)
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The CM is responsible for providing an API to:
+
+#. Verify a digital signature.
+#. Verify a hash.
+
+The CM does not include any cryptography related code, but it relies on an
+external library to perform the cryptographic operations. A Crypto-Library (CL)
+linking the CM and the external library must be implemented. The following
+functions must be provided by the CL:
+
+.. code:: c
+
+    void (*init)(void);
+    int (*verify_signature)(void *data_ptr, unsigned int data_len,
+                            void *sig_ptr, unsigned int sig_len,
+                            void *sig_alg, unsigned int sig_alg_len,
+                            void *pk_ptr, unsigned int pk_len);
+    int (*verify_hash)(void *data_ptr, unsigned int data_len,
+                       void *digest_info_ptr, unsigned int digest_info_len);
+
+These functions are registered in the CM using the macro:
+
+.. code:: c
+
+    REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash);
+
+``_name`` must be a string containing the name of the CL. This name is used for
+debugging purposes.
+
+Image Parser Module (IPM)
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The IPM is responsible for:
+
+#. Checking the integrity of each image loaded by the IO framework.
+#. Extracting parameters used for authenticating an image based upon a
+   description provided by the platform in the CoT descriptor.
+
+Images may have different formats (for example, authentication images could be
+x509v3 certificates, signed ELF files or any other platform specific format).
+The IPM allows to register an Image Parser Library (IPL) for every image format
+used in the CoT. This library must implement the specific methods to parse the
+image. The IPM obtains the image format from the CoT and calls the right IPL to
+check the image integrity and extract the authentication parameters.
+
+See Section "Describing the image parsing methods" for more details about the
+mechanism the IPM provides to define and register IPLs.
+
+Authentication methods
+~~~~~~~~~~~~~~~~~~~~~~
+
+The AM supports the following authentication methods:
+
+#. Hash
+#. Digital signature
+
+The platform may specify these methods in the CoT in case it decides to define
+a custom CoT instead of reusing a predefined one.
+
+If a data image uses multiple methods, then all the methods must be a part of
+the same CoT. The number and type of parameters are method specific. These
+parameters should be obtained from the parent image using the IPM.
+
+#. Hash
+
+   Parameters:
+
+   #. A pointer to data to hash
+   #. Length of the data
+   #. A pointer to the hash
+   #. Length of the hash
+
+   The hash will be represented by the DER encoding of the following ASN.1
+   type:
+
+   ::
+
+       DigestInfo ::= SEQUENCE {
+           digestAlgorithm  DigestAlgorithmIdentifier,
+           digest           Digest
+       }
+
+   This ASN.1 structure makes it possible to remove any assumption about the
+   type of hash algorithm used as this information accompanies the hash. This
+   should allow the Cryptography Library (CL) to support multiple hash
+   algorithm implementations.
+
+#. Digital Signature
+
+   Parameters:
+
+   #. A pointer to data to sign
+   #. Length of the data
+   #. Public Key Algorithm
+   #. Public Key value
+   #. Digital Signature Algorithm
+   #. Digital Signature value
+
+   The Public Key parameters will be represented by the DER encoding of the
+   following ASN.1 type:
+
+   ::
+
+       SubjectPublicKeyInfo  ::=  SEQUENCE  {
+           algorithm         AlgorithmIdentifier{PUBLIC-KEY,{PublicKeyAlgorithms}},
+           subjectPublicKey  BIT STRING  }
+
+   The Digital Signature Algorithm will be represented by the DER encoding of
+   the following ASN.1 types.
+
+   ::
+
+       AlgorithmIdentifier {ALGORITHM:IOSet } ::= SEQUENCE {
+           algorithm         ALGORITHM.&id({IOSet}),
+           parameters        ALGORITHM.&Type({IOSet}{@algorithm}) OPTIONAL
+       }
+
+   The digital signature will be represented by:
+
+   ::
+
+       signature  ::=  BIT STRING
+
+The authentication framework will use the image descriptor to extract all the
+information related to authentication.
+
+Specifying a Chain of Trust
+---------------------------
+
+A CoT can be described as a set of image descriptors linked together in a
+particular order. The order dictates the sequence in which they must be
+verified. Each image has a set of properties which allow the AM to verify it.
+These properties are described below.
+
+The PP is responsible for defining a single or multiple CoTs for a data image.
+Unless otherwise specified, the data structures described in the following
+sections are populated by the PP statically.
+
+Describing the image parsing methods
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The parsing method refers to the format of a particular image. For example, an
+authentication image that represents a certificate could be in the X.509v3
+format. A data image that represents a boot loader stage could be in raw binary
+or ELF format. The IPM supports three parsing methods. An image has to use one
+of the three methods described below. An IPL is responsible for interpreting a
+single parsing method. There has to be one IPL for every method used by the
+platform.
+
+#. Raw format: This format is effectively a nop as an image using this method
+   is treated as being in raw binary format e.g. boot loader images used by
+   TF-A. This method should only be used by data images.
+
+#. X509V3 method: This method uses industry standards like X.509 to represent
+   PKI certificates (authentication images). It is expected that open source
+   libraries will be available which can be used to parse an image represented
+   by this method. Such libraries can be used to write the corresponding IPL
+   e.g. the X.509 parsing library code in mbed TLS.
+
+#. Platform defined method: This method caters for platform specific
+   proprietary standards to represent authentication or data images. For
+   example, The signature of a data image could be appended to the data image
+   raw binary. A header could be prepended to the combined blob to specify the
+   extents of each component. The platform will have to implement the
+   corresponding IPL to interpret such a format.
+
+The following enum can be used to define these three methods.
+
+.. code:: c
+
+    typedef enum img_type_enum {
+        IMG_RAW,            /* Binary image */
+        IMG_PLAT,           /* Platform specific format */
+        IMG_CERT,           /* X509v3 certificate */
+        IMG_MAX_TYPES,
+    } img_type_t;
+
+An IPL must provide functions with the following prototypes:
+
+.. code:: c
+
+    void init(void);
+    int check_integrity(void *img, unsigned int img_len);
+    int get_auth_param(const auth_param_type_desc_t *type_desc,
+                          void *img, unsigned int img_len,
+                          void **param, unsigned int *param_len);
+
+An IPL for each type must be registered using the following macro:
+
+.. code:: c
+
+    REGISTER_IMG_PARSER_LIB(_type, _name, _init, _check_int, _get_param)
+
+-  ``_type``: one of the types described above.
+-  ``_name``: a string containing the IPL name for debugging purposes.
+-  ``_init``: initialization function pointer.
+-  ``_check_int``: check image integrity function pointer.
+-  ``_get_param``: extract authentication parameter function pointer.
+
+The ``init()`` function will be used to initialize the IPL.
+
+The ``check_integrity()`` function is passed a pointer to the memory where the
+image has been loaded by the IO framework and the image length. It should ensure
+that the image is in the format corresponding to the parsing method and has not
+been tampered with. For example, RFC-2459 describes a validation sequence for an
+X.509 certificate.
+
+The ``get_auth_param()`` function is passed a parameter descriptor containing
+information about the parameter (``type_desc`` and ``cookie``) to identify and
+extract the data corresponding to that parameter from an image. This data will
+be used to verify either the current or the next image in the CoT sequence.
+
+Each image in the CoT will specify the parsing method it uses. This information
+will be used by the IPM to find the right parser descriptor for the image.
+
+Describing the authentication method(s)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+As part of the CoT, each image has to specify one or more authentication methods
+which will be used to verify it. As described in the Section "Authentication
+methods", there are three methods supported by the AM.
+
+.. code:: c
+
+    typedef enum {
+        AUTH_METHOD_NONE,
+        AUTH_METHOD_HASH,
+        AUTH_METHOD_SIG,
+        AUTH_METHOD_NUM
+    } auth_method_type_t;
+
+The AM defines the type of each parameter used by an authentication method. It
+uses this information to:
+
+#. Specify to the ``get_auth_param()`` function exported by the IPM, which
+   parameter should be extracted from an image.
+
+#. Correctly marshall the parameters while calling the verification function
+   exported by the CM and PP.
+
+#. Extract authentication parameters from a parent image in order to verify a
+   child image e.g. to verify the certificate image, the public key has to be
+   obtained from the parent image.
+
+.. code:: c
+
+    typedef enum {
+        AUTH_PARAM_NONE,
+        AUTH_PARAM_RAW_DATA,        /* Raw image data */
+        AUTH_PARAM_SIG,         /* The image signature */
+        AUTH_PARAM_SIG_ALG,     /* The image signature algorithm */
+        AUTH_PARAM_HASH,        /* A hash (including the algorithm) */
+        AUTH_PARAM_PUB_KEY,     /* A public key */
+    } auth_param_type_t;
+
+The AM defines the following structure to identify an authentication parameter
+required to verify an image.
+
+.. code:: c
+
+    typedef struct auth_param_type_desc_s {
+        auth_param_type_t type;
+        void *cookie;
+    } auth_param_type_desc_t;
+
+``cookie`` is used by the platform to specify additional information to the IPM
+which enables it to uniquely identify the parameter that should be extracted
+from an image. For example, the hash of a BL3x image in its corresponding
+content certificate is stored in an X509v3 custom extension field. An extension
+field can only be identified using an OID. In this case, the ``cookie`` could
+contain the pointer to the OID defined by the platform for the hash extension
+field while the ``type`` field could be set to ``AUTH_PARAM_HASH``. A value of 0 for
+the ``cookie`` field means that it is not used.
+
+For each method, the AM defines a structure with the parameters required to
+verify the image.
+
+.. code:: c
+
+    /*
+     * Parameters for authentication by hash matching
+     */
+    typedef struct auth_method_param_hash_s {
+        auth_param_type_desc_t *data;   /* Data to hash */
+        auth_param_type_desc_t *hash;   /* Hash to match with */
+    } auth_method_param_hash_t;
+
+    /*
+     * Parameters for authentication by signature
+     */
+    typedef struct auth_method_param_sig_s {
+        auth_param_type_desc_t *pk; /* Public key */
+        auth_param_type_desc_t *sig;    /* Signature to check */
+        auth_param_type_desc_t *alg;    /* Signature algorithm */
+        auth_param_type_desc_t *tbs;    /* Data signed */
+    } auth_method_param_sig_t;
+
+The AM defines the following structure to describe an authentication method for
+verifying an image
+
+.. code:: c
+
+    /*
+     * Authentication method descriptor
+     */
+    typedef struct auth_method_desc_s {
+        auth_method_type_t type;
+        union {
+            auth_method_param_hash_t hash;
+            auth_method_param_sig_t sig;
+        } param;
+    } auth_method_desc_t;
+
+Using the method type specified in the ``type`` field, the AM finds out what field
+needs to access within the ``param`` union.
+
+Storing Authentication parameters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+A parameter described by ``auth_param_type_desc_t`` to verify an image could be
+obtained from either the image itself or its parent image. The memory allocated
+for loading the parent image will be reused for loading the child image. Hence
+parameters which are obtained from the parent for verifying a child image need
+to have memory allocated for them separately where they can be stored. This
+memory must be statically allocated by the platform port.
+
+The AM defines the following structure to store the data corresponding to an
+authentication parameter.
+
+.. code:: c
+
+    typedef struct auth_param_data_desc_s {
+        void *auth_param_ptr;
+        unsigned int auth_param_len;
+    } auth_param_data_desc_t;
+
+The ``auth_param_ptr`` field is initialized by the platform. The ``auth_param_len``
+field is used to specify the length of the data in the memory.
+
+For parameters that can be obtained from the child image itself, the IPM is
+responsible for populating the ``auth_param_ptr`` and ``auth_param_len`` fields
+while executing the ``img_get_auth_param()`` function.
+
+The AM defines the following structure to enable an image to describe the
+parameters that should be extracted from it and used to verify the next image
+(child) in a CoT.
+
+.. code:: c
+
+    typedef struct auth_param_desc_s {
+        auth_param_type_desc_t type_desc;
+        auth_param_data_desc_t data;
+    } auth_param_desc_t;
+
+Describing an image in a CoT
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+An image in a CoT is a consolidation of the following aspects of a CoT described
+above.
+
+#. A unique identifier specified by the platform which allows the IO framework
+   to locate the image in a FIP and load it in the memory reserved for the data
+   image in the CoT.
+
+#. A parsing method which is used by the AM to find the appropriate IPM.
+
+#. Authentication methods and their parameters as described in the previous
+   section. These are used to verify the current image.
+
+#. Parameters which are used to verify the next image in the current CoT. These
+   parameters are specified only by authentication images and can be extracted
+   from the current image once it has been verified.
+
+The following data structure describes an image in a CoT.
+
+.. code:: c
+
+    typedef struct auth_img_desc_s {
+        unsigned int img_id;
+        const struct auth_img_desc_s *parent;
+        img_type_t img_type;
+        const auth_method_desc_t *const img_auth_methods;
+        const auth_param_desc_t *const authenticated_data;
+    } auth_img_desc_t;
+
+A CoT is defined as an array of pointers to ``auth_image_desc_t`` structures
+linked together by the ``parent`` field. Those nodes with no parent must be
+authenticated using the ROTPK stored in the platform.
+
+Implementation example
+----------------------
+
+This section is a detailed guide explaining a trusted boot implementation using
+the authentication framework. This example corresponds to the Applicative
+Functional Mode (AFM) as specified in the TBBR-Client document. It is
+recommended to read this guide along with the source code.
+
+The TBBR CoT
+~~~~~~~~~~~~
+
+CoT specific to BL1 and BL2 can be found in ``drivers/auth/tbbr/tbbr_cot_bl1.c``
+and ``drivers/auth/tbbr/tbbr_cot_bl2.c`` respectively. The common CoT used across
+BL1 and BL2 can be found in ``drivers/auth/tbbr/tbbr_cot_common.c``.
+This CoT consists of an array of pointers to image descriptors and it is
+registered in the framework using the macro ``REGISTER_COT(cot_desc)``, where
+``cot_desc`` must be the name of the array (passing a pointer or any other
+type of indirection will cause the registration process to fail).
+
+The number of images participating in the boot process depends on the CoT.
+There is, however, a minimum set of images that are mandatory in TF-A and thus
+all CoTs must present:
+
+-  ``BL2``
+-  ``SCP_BL2`` (platform specific)
+-  ``BL31``
+-  ``BL32`` (optional)
+-  ``BL33``
+
+The TBBR specifies the additional certificates that must accompany these images
+for a proper authentication. Details about the TBBR CoT may be found in the
+:ref:`Trusted Board Boot` document.
+
+Following the :ref:`Porting Guide`, a platform must provide unique
+identifiers for all the images and certificates that will be loaded during the
+boot process. If a platform is using the TBBR as a reference for trusted boot,
+these identifiers can be obtained from ``include/common/tbbr/tbbr_img_def.h``.
+Arm platforms include this file in ``include/plat/arm/common/arm_def.h``. Other
+platforms may also include this file or provide their own identifiers.
+
+**Important**: the authentication module uses these identifiers to index the
+CoT array, so the descriptors location in the array must match the identifiers.
+
+Each image descriptor must specify:
+
+-  ``img_id``: the corresponding image unique identifier defined by the platform.
+-  ``img_type``: the image parser module uses the image type to call the proper
+   parsing library to check the image integrity and extract the required
+   authentication parameters. Three types of images are currently supported:
+
+   -  ``IMG_RAW``: image is a raw binary. No parsing functions are available,
+      other than reading the whole image.
+   -  ``IMG_PLAT``: image format is platform specific. The platform may use this
+      type for custom images not directly supported by the authentication
+      framework.
+   -  ``IMG_CERT``: image is an x509v3 certificate.
+
+-  ``parent``: pointer to the parent image descriptor. The parent will contain
+   the information required to authenticate the current image. If the parent
+   is NULL, the authentication parameters will be obtained from the platform
+   (i.e. the BL2 and Trusted Key certificates are signed with the ROT private
+   key, whose public part is stored in the platform).
+-  ``img_auth_methods``: this points to an array which defines the
+   authentication methods that must be checked to consider an image
+   authenticated. Each method consists of a type and a list of parameter
+   descriptors. A parameter descriptor consists of a type and a cookie which
+   will point to specific information required to extract that parameter from
+   the image (i.e. if the parameter is stored in an x509v3 extension, the
+   cookie will point to the extension OID). Depending on the method type, a
+   different number of parameters must be specified. This pointer should not be
+   NULL.
+   Supported methods are:
+
+   -  ``AUTH_METHOD_HASH``: the hash of the image must match the hash extracted
+      from the parent image. The following parameter descriptors must be
+      specified:
+
+      -  ``data``: data to be hashed (obtained from current image)
+      -  ``hash``: reference hash (obtained from parent image)
+
+   -  ``AUTH_METHOD_SIG``: the image (usually a certificate) must be signed with
+      the private key whose public part is extracted from the parent image (or
+      the platform if the parent is NULL). The following parameter descriptors
+      must be specified:
+
+      -  ``pk``: the public key (obtained from parent image)
+      -  ``sig``: the digital signature (obtained from current image)
+      -  ``alg``: the signature algorithm used (obtained from current image)
+      -  ``data``: the data to be signed (obtained from current image)
+
+-  ``authenticated_data``: this array pointer indicates what authentication
+   parameters must be extracted from an image once it has been authenticated.
+   Each parameter consists of a parameter descriptor and the buffer
+   address/size to store the parameter. The CoT is responsible for allocating
+   the required memory to store the parameters. This pointer may be NULL.
+
+In the ``tbbr_cot*.c`` file, a set of buffers are allocated to store the parameters
+extracted from the certificates. In the case of the TBBR CoT, these parameters
+are hashes and public keys. In DER format, an RSA-4096 public key requires 550
+bytes, and a hash requires 51 bytes. Depending on the CoT and the authentication
+process, some of the buffers may be reused at different stages during the boot.
+
+Next in that file, the parameter descriptors are defined. These descriptors will
+be used to extract the parameter data from the corresponding image.
+
+Example: the BL31 Chain of Trust
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Four image descriptors form the BL31 Chain of Trust:
+
+.. code:: c
+
+    static const auth_img_desc_t trusted_key_cert = {
+            .img_id = TRUSTED_KEY_CERT_ID,
+            .img_type = IMG_CERT,
+            .parent = NULL,
+            .img_auth_methods =  (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+                    [0] = {
+                            .type = AUTH_METHOD_SIG,
+                            .param.sig = {
+                                    .pk = &subject_pk,
+                                    .sig = &sig,
+                                    .alg = &sig_alg,
+                                    .data = &raw_data
+                            }
+                    },
+                    [1] = {
+                            .type = AUTH_METHOD_NV_CTR,
+                            .param.nv_ctr = {
+                                    .cert_nv_ctr = &trusted_nv_ctr,
+                                    .plat_nv_ctr = &trusted_nv_ctr
+                            }
+                    }
+            },
+            .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+                    [0] = {
+                            .type_desc = &trusted_world_pk,
+                            .data = {
+                                    .ptr = (void *)trusted_world_pk_buf,
+                                    .len = (unsigned int)PK_DER_LEN
+                            }
+                    },
+                    [1] = {
+                            .type_desc = &non_trusted_world_pk,
+                            .data = {
+                                    .ptr = (void *)non_trusted_world_pk_buf,
+                                    .len = (unsigned int)PK_DER_LEN
+                            }
+                    }
+            }
+    };
+    static const auth_img_desc_t soc_fw_key_cert = {
+            .img_id = SOC_FW_KEY_CERT_ID,
+            .img_type = IMG_CERT,
+            .parent = &trusted_key_cert,
+            .img_auth_methods =  (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+                    [0] = {
+                            .type = AUTH_METHOD_SIG,
+                            .param.sig = {
+                                    .pk = &trusted_world_pk,
+                                    .sig = &sig,
+                                    .alg = &sig_alg,
+                                    .data = &raw_data
+                            }
+                    },
+                    [1] = {
+                            .type = AUTH_METHOD_NV_CTR,
+                            .param.nv_ctr = {
+                                    .cert_nv_ctr = &trusted_nv_ctr,
+                                    .plat_nv_ctr = &trusted_nv_ctr
+                            }
+                    }
+            },
+            .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+                    [0] = {
+                            .type_desc = &soc_fw_content_pk,
+                            .data = {
+                                    .ptr = (void *)content_pk_buf,
+                                    .len = (unsigned int)PK_DER_LEN
+                            }
+                    }
+            }
+    };
+    static const auth_img_desc_t soc_fw_content_cert = {
+            .img_id = SOC_FW_CONTENT_CERT_ID,
+            .img_type = IMG_CERT,
+            .parent = &soc_fw_key_cert,
+            .img_auth_methods =  (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+                    [0] = {
+                            .type = AUTH_METHOD_SIG,
+                            .param.sig = {
+                                    .pk = &soc_fw_content_pk,
+                                    .sig = &sig,
+                                    .alg = &sig_alg,
+                                    .data = &raw_data
+                            }
+                    },
+                    [1] = {
+                            .type = AUTH_METHOD_NV_CTR,
+                            .param.nv_ctr = {
+                                    .cert_nv_ctr = &trusted_nv_ctr,
+                                    .plat_nv_ctr = &trusted_nv_ctr
+                            }
+                    }
+            },
+            .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+                    [0] = {
+                            .type_desc = &soc_fw_hash,
+                            .data = {
+                                    .ptr = (void *)soc_fw_hash_buf,
+                                    .len = (unsigned int)HASH_DER_LEN
+                            }
+                    },
+                    [1] = {
+                            .type_desc = &soc_fw_config_hash,
+                            .data = {
+                                    .ptr = (void *)soc_fw_config_hash_buf,
+                                    .len = (unsigned int)HASH_DER_LEN
+                            }
+                    }
+            }
+    };
+    static const auth_img_desc_t bl31_image = {
+            .img_id = BL31_IMAGE_ID,
+            .img_type = IMG_RAW,
+            .parent = &soc_fw_content_cert,
+            .img_auth_methods =  (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+                    [0] = {
+                            .type = AUTH_METHOD_HASH,
+                            .param.hash = {
+                                    .data = &raw_data,
+                                    .hash = &soc_fw_hash
+                            }
+                    }
+            }
+    };
+
+The **Trusted Key certificate** is signed with the ROT private key and contains
+the Trusted World public key and the Non-Trusted World public key as x509v3
+extensions. This must be specified in the image descriptor using the
+``img_auth_methods`` and ``authenticated_data`` arrays, respectively.
+
+The Trusted Key certificate is authenticated by checking its digital signature
+using the ROTPK. Four parameters are required to check a signature: the public
+key, the algorithm, the signature and the data that has been signed. Therefore,
+four parameter descriptors must be specified with the authentication method:
+
+-  ``subject_pk``: parameter descriptor of type ``AUTH_PARAM_PUB_KEY``. This type
+   is used to extract a public key from the parent image. If the cookie is an
+   OID, the key is extracted from the corresponding x509v3 extension. If the
+   cookie is NULL, the subject public key is retrieved. In this case, because
+   the parent image is NULL, the public key is obtained from the platform
+   (this key will be the ROTPK).
+-  ``sig``: parameter descriptor of type ``AUTH_PARAM_SIG``. It is used to extract
+   the signature from the certificate.
+-  ``sig_alg``: parameter descriptor of type ``AUTH_PARAM_SIG``. It is used to
+   extract the signature algorithm from the certificate.
+-  ``raw_data``: parameter descriptor of type ``AUTH_PARAM_RAW_DATA``. It is used
+   to extract the data to be signed from the certificate.
+
+Once the signature has been checked and the certificate authenticated, the
+Trusted World public key needs to be extracted from the certificate. A new entry
+is created in the ``authenticated_data`` array for that purpose. In that entry,
+the corresponding parameter descriptor must be specified along with the buffer
+address to store the parameter value. In this case, the ``trusted_world_pk``
+descriptor is used to extract the public key from an x509v3 extension with OID
+``TRUSTED_WORLD_PK_OID``. The BL31 key certificate will use this descriptor as
+parameter in the signature authentication method. The key is stored in the
+``trusted_world_pk_buf`` buffer.
+
+The **BL31 Key certificate** is authenticated by checking its digital signature
+using the Trusted World public key obtained previously from the Trusted Key
+certificate. In the image descriptor, we specify a single authentication method
+by signature whose public key is the ``trusted_world_pk``. Once this certificate
+has been authenticated, we have to extract the BL31 public key, stored in the
+extension specified by ``soc_fw_content_pk``. This key will be copied to the
+``content_pk_buf`` buffer.
+
+The **BL31 certificate** is authenticated by checking its digital signature
+using the BL31 public key obtained previously from the BL31 Key certificate.
+We specify the authentication method using ``soc_fw_content_pk`` as public key.
+After authentication, we need to extract the BL31 hash, stored in the extension
+specified by ``soc_fw_hash``. This hash will be copied to the
+``soc_fw_hash_buf`` buffer.
+
+The **BL31 image** is authenticated by calculating its hash and matching it
+with the hash obtained from the BL31 certificate. The image descriptor contains
+a single authentication method by hash. The parameters to the hash method are
+the reference hash, ``soc_fw_hash``, and the data to be hashed. In this case,
+it is the whole image, so we specify ``raw_data``.
+
+The image parser library
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+The image parser module relies on libraries to check the image integrity and
+extract the authentication parameters. The number and type of parser libraries
+depend on the images used in the CoT. Raw images do not need a library, so
+only an x509v3 library is required for the TBBR CoT.
+
+Arm platforms will use an x509v3 library based on mbed TLS. This library may be
+found in ``drivers/auth/mbedtls/mbedtls_x509_parser.c``. It exports three
+functions:
+
+.. code:: c
+
+    void init(void);
+    int check_integrity(void *img, unsigned int img_len);
+    int get_auth_param(const auth_param_type_desc_t *type_desc,
+                       void *img, unsigned int img_len,
+                       void **param, unsigned int *param_len);
+
+The library is registered in the framework using the macro
+``REGISTER_IMG_PARSER_LIB()``. Each time the image parser module needs to access
+an image of type ``IMG_CERT``, it will call the corresponding function exported
+in this file.
+
+The build system must be updated to include the corresponding library and
+mbed TLS sources. Arm platforms use the ``arm_common.mk`` file to pull the
+sources.
+
+The cryptographic library
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The cryptographic module relies on a library to perform the required operations,
+i.e. verify a hash or a digital signature. Arm platforms will use a library
+based on mbed TLS, which can be found in
+``drivers/auth/mbedtls/mbedtls_crypto.c``. This library is registered in the
+authentication framework using the macro ``REGISTER_CRYPTO_LIB()`` and exports
+four functions:
+
+.. code:: c
+
+    void init(void);
+    int verify_signature(void *data_ptr, unsigned int data_len,
+                         void *sig_ptr, unsigned int sig_len,
+                         void *sig_alg, unsigned int sig_alg_len,
+                         void *pk_ptr, unsigned int pk_len);
+    int verify_hash(void *data_ptr, unsigned int data_len,
+                    void *digest_info_ptr, unsigned int digest_info_len);
+    int auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr,
+                     size_t len, const void *key, unsigned int key_len,
+                     unsigned int key_flags, const void *iv,
+                     unsigned int iv_len, const void *tag,
+                     unsigned int tag_len)
+
+The mbedTLS library algorithm support is configured by both the
+``TF_MBEDTLS_KEY_ALG`` and ``TF_MBEDTLS_KEY_SIZE`` variables.
+
+-  ``TF_MBEDTLS_KEY_ALG`` can take in 3 values: `rsa`, `ecdsa` or `rsa+ecdsa`.
+   This variable allows the Makefile to include the corresponding sources in
+   the build for the various algorithms. Setting the variable to `rsa+ecdsa`
+   enables support for both rsa and ecdsa algorithms in the mbedTLS library.
+
+-  ``TF_MBEDTLS_KEY_SIZE`` sets the supported RSA key size for TFA. Valid values
+   include 1024, 2048, 3072 and 4096.
+
+-  ``TF_MBEDTLS_USE_AES_GCM`` enables the authenticated decryption support based
+   on AES-GCM algorithm. Valid values are 0 and 1.
+
+.. note::
+   If code size is a concern, the build option ``MBEDTLS_SHA256_SMALLER`` can
+   be defined in the platform Makefile. It will make mbed TLS use an
+   implementation of SHA-256 with smaller memory footprint (~1.5 KB less) but
+   slower (~30%).
+
+--------------
+
+*Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.*
+
+.. _TBBR-Client specification: https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a

arm-trusted-firmware/docs/design/cpu-specific-build-macros.rst

@@ -0,0 +1,605 @@
+Arm CPU Specific Build Macros
+=============================
+
+This document describes the various build options present in the CPU specific
+operations framework to enable errata workarounds and to enable optimizations
+for a specific CPU on a platform.
+
+Security Vulnerability Workarounds
+----------------------------------
+
+TF-A exports a series of build flags which control which security
+vulnerability workarounds should be applied at runtime.
+
+-  ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
+   `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
+   of the PEs in the system need the workaround. Setting this flag to 0 provides
+   no performance benefit for non-affected platforms, it just helps to comply
+   with the recommendation in the spec regarding workaround discovery.
+   Defaults to 1.
+
+-  ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
+   `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
+   the default value of 1 even on platforms that are unaffected by
+   CVE-2018-3639, in order to comply with the recommendation in the spec
+   regarding workaround discovery.
+
+-  ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
+   `CVE-2018-3639`_. This build option should be set to 1 if the target
+   platform contains at least 1 CPU that requires dynamic mitigation.
+   Defaults to 0.
+
+-  ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_.
+   This build option should be set to 1 if the target platform contains at
+   least 1 CPU that requires this mitigation. Defaults to 1.
+
+.. _arm_cpu_macros_errata_workarounds:
+
+CPU Errata Workarounds
+----------------------
+
+TF-A exports a series of build flags which control the errata workarounds that
+are applied to each CPU by the reset handler. The errata details can be found
+in the CPU specific errata documents published by Arm:
+
+-  `Cortex-A53 MPCore Software Developers Errata Notice`_
+-  `Cortex-A57 MPCore Software Developers Errata Notice`_
+-  `Cortex-A72 MPCore Software Developers Errata Notice`_
+
+The errata workarounds are implemented for a particular revision or a set of
+processor revisions. This is checked by the reset handler at runtime. Each
+errata workaround is identified by its ``ID`` as specified in the processor's
+errata notice document. The format of the define used to enable/disable the
+errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
+is for example ``A57`` for the ``Cortex_A57`` CPU.
+
+Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to
+write errata workaround functions.
+
+All workarounds are disabled by default. The platform is responsible for
+enabling these workarounds according to its requirement by defining the
+errata workaround build flags in the platform specific makefile. In case
+these workarounds are enabled for the wrong CPU revision then the errata
+workaround is not applied. In the DEBUG build, this is indicated by
+printing a warning to the crash console.
+
+In the current implementation, a platform which has more than 1 variant
+with different revisions of a processor has no runtime mechanism available
+for it to specify which errata workarounds should be enabled or not.
+
+The value of the build flags is 0 by default, that is, disabled. A value of 1
+will enable it.
+
+For Cortex-A9, the following errata build flags are defined :
+
+-  ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
+   CPU. This needs to be enabled for all revisions of the CPU.
+
+For Cortex-A15, the following errata build flags are defined :
+
+-  ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
+   CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
+
+-  ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
+   CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
+
+For Cortex-A17, the following errata build flags are defined :
+
+-  ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
+   CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
+
+-  ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
+   CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
+
+For Cortex-A35, the following errata build flags are defined :
+
+-  ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
+   CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
+
+For Cortex-A53, the following errata build flags are defined :
+
+-  ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
+   CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
+
+-  ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
+   CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
+
+-  ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
+   CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
+
+-  ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
+   CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
+
+-  ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
+   link time to Cortex-A53 CPU. This needs to be enabled for some variants of
+   revision <= r0p4. This workaround can lead the linker to create ``*.stub``
+   sections.
+
+-  ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
+   CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
+   r0p4 and onwards, this errata is enabled by default in hardware.
+
+-  ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
+   to Cortex-A53 CPU.  This needs to be enabled for some variants of revision
+   <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
+   which are 4kB aligned.
+
+-  ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
+   CPUs. Though the erratum is present in every revision of the CPU,
+   this workaround is only applied to CPUs from r0p3 onwards, which feature
+   a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
+   Earlier revisions of the CPU have other errata which require the same
+   workaround in software, so they should be covered anyway.
+
+-  ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all
+   revisions of Cortex-A53 CPU.
+
+For Cortex-A55, the following errata build flags are defined :
+
+-  ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+-  ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+-  ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+-  ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
+   CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
+
+-  ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
+   CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
+
+-  ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
+   CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
+
+-  ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all
+   revisions of Cortex-A55 CPU.
+
+For Cortex-A57, the following errata build flags are defined :
+
+-  ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+-  ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+-  ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+-  ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+-  ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
+
+-  ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+-  ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+-  ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+-  ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
+
+-  ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
+
+-  ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
+   CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
+
+-  ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all
+   revisions of Cortex-A57 CPU.
+
+For Cortex-A72, the following errata build flags are defined :
+
+-  ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
+   CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
+
+-  ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all
+   revisions of Cortex-A72 CPU.
+
+For Cortex-A73, the following errata build flags are defined :
+
+-  ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+-  ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
+   CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
+
+For Cortex-A75, the following errata build flags are defined :
+
+-  ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+-  ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
+    CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
+For Cortex-A76, the following errata build flags are defined :
+
+-  ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
+
+-  ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+
+-  ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
+   revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
+   limitation of errata framework this errata is applied to all revisions
+   of Cortex-A76 CPU.
+
+-  ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+
+-  ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
+
+For Cortex-A77, the following errata build flags are defined :
+
+-  ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
+   CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
+
+-  ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
+   CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+-  ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
+   CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+-  ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
+   CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
+
+For Cortex-A78, the following errata build flags are defined :
+
+-  ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
+   CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
+
+-  ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
+   CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
+
+-  ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78
+   CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
+   issue but there is no workaround for that revision.
+
+-  ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
+   CPU. This needs to be enabled for revisions r0p0 and r1p0.
+
+-  ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
+   CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
+
+-  ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78
+   CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
+   is still open.
+
+-  ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78
+   CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
+   is present in r0p0 but there is no workaround. It is still open.
+
+For Cortex-A78 AE, the following errata build flags are defined :
+
+- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
+   Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
+   This erratum is still open.
+
+- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to
+  Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
+  erratum is still open.
+
+- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to
+  Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
+  erratum is still open.
+
+- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to
+  Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
+  erratum is still open.
+
+For Neoverse N1, the following errata build flags are defined :
+
+-  ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
+
+-  ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
+
+-  ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+
+-  ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
+   CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
+   revisions r0p0, r1p0, and r2p0 there is no workaround.
+
+For Neoverse V1, the following errata build flags are defined :
+
+-  ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
+   CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
+   in r1p1.
+
+-  ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1
+   CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
+   in r1p1.
+
+-  ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1
+   CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
+   in r1p1.
+
+-  ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1
+   CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
+
+-  ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1
+   CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
+   CPU.
+
+-  ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1
+   CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
+   issue is present in r0p0 as well but there is no workaround for that
+   revision.  It is still open.
+
+-  ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1
+   CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
+   CPU.  It is still open.
+
+-  ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1
+   CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
+   It is still open.
+
+-  ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1
+   CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
+   issue is present in r0p0 as well but there is no workaround for that
+   revision.  It is still open.
+
+For Cortex-A710, the following errata build flags are defined :
+
+-  ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
+   Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+   r2p0 of the CPU. It is still open.
+
+-  ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to
+   Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+   r2p0 of the CPU. It is still open.
+
+-  ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
+   and is still open.
+
+-  ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is still open.
+
+-  ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
+   is still open.
+
+-  ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is still open.
+
+-  ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is fixed in r2p1.
+
+-  ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is fixed in r2p1.
+
+-  ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is fixed in r2p1.
+
+For Neoverse N2, the following errata build flags are defined :
+
+-  ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
+
+-  ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+-  ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+-  ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+-  ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+-  ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+-  ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+-  ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+-  ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+-  ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
+   CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+For Cortex-X2, the following errata build flags are defined :
+
+-  ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
+   CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
+   it is still open.
+
+-  ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
+   CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
+   it is still open.
+
+-  ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
+   CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
+
+-  ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to
+   Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+   r2p0 of the CPU, it is fixed in r2p1.
+
+-  ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to
+   Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+   r2p0 of the CPU, it is fixed in r2p1.
+
+-  ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to
+   Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+   r2p0 of the CPU, it is fixed in r2p1.
+
+For Cortex-A510, the following errata build flags are defined :
+
+-  ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is
+   fixed in r0p1.
+
+-  ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
+   r0p2, r0p3 and r1p0, it is fixed in r1p1.
+
+-  ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
+   r0p2, it is fixed in r0p3.
+
+-  ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
+   in r0p3. The issue is also present in r0p0 and r0p1 but there is no
+   workaround for those revisions.
+
+-  ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to
+   Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
+   r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
+   ENABLE_MPMM=1.
+
+-  ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to
+   Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
+   r0p3 and r1p0, it is fixed in r1p1.
+
+-  ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to
+   Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
+   r0p3 and r1p0, it is fixed in r1p1.
+
+DSU Errata Workarounds
+----------------------
+
+Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
+Shared Unit) errata. The DSU errata details can be found in the respective Arm
+documentation:
+
+- `Arm DSU Software Developers Errata Notice`_.
+
+Each erratum is identified by an ``ID``, as defined in the DSU errata notice
+document. Thus, the build flags which enable/disable the errata workarounds
+have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
+of DSU errata workarounds are similar to `CPU errata workarounds`_.
+
+For DSU errata, the following build flags are defined:
+
+-  ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
+   affected DSU configurations. This errata applies only for those DSUs that
+   revision is r0p0 (on r0p1 it is fixed). However, please note that this
+   workaround results in increased DSU power consumption on idle.
+
+-  ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
+   affected DSU configurations. This errata applies only for those DSUs that
+   contain the ACP interface **and** the DSU revision is older than r2p0 (on
+   r2p0 it is fixed). However, please note that this workaround results in
+   increased DSU power consumption on idle.
+
+CPU Specific optimizations
+--------------------------
+
+This section describes some of the optimizations allowed by the CPU micro
+architecture that can be enabled by the platform as desired.
+
+-  ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
+   Cortex-A57 cluster power down sequence by not flushing the Level 1 data
+   cache. The L1 data cache and the L2 unified cache are inclusive. A flush
+   of the L2 by set/way flushes any dirty lines from the L1 as well. This
+   is a known safe deviation from the Cortex-A57 TRM defined power down
+   sequence. Each Cortex-A57 based platform must make its own decision on
+   whether to use the optimization.
+
+-  ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
+   hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
+   in a way most programmers expect, and will most probably result in a
+   significant speed degradation to any code that employs them. The Armv8-A
+   architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
+   the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
+   flag enforces this behaviour. This needs to be enabled only for revisions
+   <= r0p3 of the CPU and is enabled by default.
+
+-  ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
+   ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
+   enabled only for revisions <= r1p2 of the CPU and is enabled by default,
+   as recommended in section "4.7 Non-Temporal Loads/Stores" of the
+   `Cortex-A57 Software Optimization Guide`_.
+
+- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
+   streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
+   this bit only if their memory system meets the requirement that cache
+   line fill requests from the Cortex-A57 processor are atomic. Each
+   Cortex-A57 based platform must make its own decision on whether to use
+   the optimization. This flag is disabled by default.
+
+-  ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
+   level cache(LLC) is present in the system, and that the DataSource field
+   on the master CHI interface indicates when data is returned from the LLC.
+   This is used to control how the LL_CACHE* PMU events count.
+   Default value is 0 (Disabled).
+
+--------------
+
+*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.*
+
+.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
+.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
+.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960
+.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
+.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
+.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
+.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
+.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html

arm-trusted-firmware/docs/design/index.rst

@@ -0,0 +1,21 @@
+System Design
+=============
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Contents
+   :numbered:
+
+   alt-boot-flows
+   auth-framework
+   cpu-specific-build-macros
+   firmware-design
+   interrupt-framework-design
+   psci-pd-tree
+   reset-design
+   trusted-board-boot
+   trusted-board-boot-build
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*

arm-trusted-firmware/docs/design/psci-pd-tree.rst

@@ -0,0 +1,304 @@
+PSCI Power Domain Tree Structure
+================================
+
+Requirements
+------------
+
+#. A platform must export the ``plat_get_aff_count()`` and
+   ``plat_get_aff_state()`` APIs to enable the generic PSCI code to
+   populate a tree that describes the hierarchy of power domains in the
+   system. This approach is inflexible because a change to the topology
+   requires a change in the code.
+
+   It would be much simpler for the platform to describe its power domain tree
+   in a data structure.
+
+#. The generic PSCI code generates MPIDRs in order to populate the power domain
+   tree. It also uses an MPIDR to find a node in the tree. The assumption that
+   a platform will use exactly the same MPIDRs as generated by the generic PSCI
+   code is not scalable. The use of an MPIDR also restricts the number of
+   levels in the power domain tree to four.
+
+   Therefore, there is a need to decouple allocation of MPIDRs from the
+   mechanism used to populate the power domain topology tree.
+
+#. The current arrangement of the power domain tree requires a binary search
+   over the sibling nodes at a particular level to find a specified power
+   domain node. During a power management operation, the tree is traversed from
+   a 'start' to an 'end' power level. The binary search is required to find the
+   node at each level. The natural way to perform this traversal is to
+   start from a leaf node and follow the parent node pointer to reach the end
+   level.
+
+   Therefore, there is a need to define data structures that implement the tree in
+   a way which facilitates such a traversal.
+
+#. The attributes of a core power domain differ from the attributes of power
+   domains at higher levels. For example, only a core power domain can be identified
+   using an MPIDR. There is no requirement to perform state coordination while
+   performing a power management operation on the core power domain.
+
+   Therefore, there is a need to implement the tree in a way which facilitates this
+   distinction between a leaf and non-leaf node and any associated
+   optimizations.
+
+--------------
+
+Design
+------
+
+Describing a power domain tree
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To fulfill requirement 1., the existing platform APIs
+``plat_get_aff_count()`` and ``plat_get_aff_state()`` have been
+removed. A platform must define an array of unsigned chars such that:
+
+#. The first entry in the array specifies the number of power domains at the
+   highest power level implemented in the platform. This caters for platforms
+   where the power domain tree does not have a single root node, for example,
+   the FVP has two cluster power domains at the highest level (1).
+
+#. Each subsequent entry corresponds to a power domain and contains the number
+   of power domains that are its direct children.
+
+#. The size of the array minus the first entry will be equal to the number of
+   non-leaf power domains.
+
+#. The value in each entry in the array is used to find the number of entries
+   to consider at the next level. The sum of the values (number of children) of
+   all the entries at a level specifies the number of entries in the array for
+   the next level.
+
+The following example power domain topology tree will be used to describe the
+above text further. The leaf and non-leaf nodes in this tree have been numbered
+separately.
+
+::
+
+                                         +-+
+                                         |0|
+                                         +-+
+                                        /   \
+                                       /     \
+                                      /       \
+                                     /         \
+                                    /           \
+                                   /             \
+                                  /               \
+                                 /                 \
+                                /                   \
+                               /                     \
+                            +-+                       +-+
+                            |1|                       |2|
+                            +-+                       +-+
+                           /   \                     /   \
+                          /     \                   /     \
+                         /       \                 /       \
+                        /         \               /         \
+                     +-+           +-+         +-+           +-+
+                     |3|           |4|         |5|           |6|
+                     +-+           +-+         +-+           +-+
+            +---+-----+    +----+----|     +----+----+     +----+-----+-----+
+            |   |     |    |    |    |     |    |    |     |    |     |     |
+            |   |     |    |    |    |     |    |    |     |    |     |     |
+            v   v     v    v    v    v     v    v    v     v    v     v     v
+          +-+  +-+   +-+  +-+  +-+  +-+   +-+  +-+  +-+   +-+  +--+  +--+  +--+
+          |0|  |1|   |2|  |3|  |4|  |5|   |6|  |7|  |8|   |9|  |10|  |11|  |12|
+          +-+  +-+   +-+  +-+  +-+  +-+   +-+  +-+  +-+   +-+  +--+  +--+  +--+
+
+This tree is defined by the platform as the array described above as follows:
+
+.. code:: c
+
+        #define PLAT_NUM_POWER_DOMAINS       20
+        #define PLATFORM_CORE_COUNT          13
+        #define PSCI_NUM_NON_CPU_PWR_DOMAINS \
+                           (PLAT_NUM_POWER_DOMAINS - PLATFORM_CORE_COUNT)
+
+        unsigned char plat_power_domain_tree_desc[] = { 1, 2, 2, 2, 3, 3, 3, 4};
+
+Removing assumptions about MPIDRs used in a platform
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To fulfill requirement 2., it is assumed that the platform assigns a
+unique number (core index) between ``0`` and ``PLAT_CORE_COUNT - 1`` to each core
+power domain. MPIDRs could be allocated in any manner and will not be used to
+populate the tree.
+
+``plat_core_pos_by_mpidr(mpidr)`` will return the core index for the core
+corresponding to the MPIDR. It will return an error (-1) if an MPIDR is passed
+which is not allocated or corresponds to an absent core. The semantics of this
+platform API have changed since it is required to validate the passed MPIDR. It
+has been made a mandatory API as a result.
+
+Another mandatory API, ``plat_my_core_pos()`` has been added to return the core
+index for the calling core. This API provides a more lightweight mechanism to get
+the index since there is no need to validate the MPIDR of the calling core.
+
+The platform should assign the core indices (as illustrated in the diagram above)
+such that, if the core nodes are numbered from left to right, then the index
+for a core domain will be the same as the index returned by
+``plat_core_pos_by_mpidr()`` or ``plat_my_core_pos()`` for that core. This
+relationship allows the core nodes to be allocated in a separate array
+(requirement 4.) during ``psci_setup()`` in such an order that the index of the
+core in the array is the same as the return value from these APIs.
+
+Dealing with holes in MPIDR allocation
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+For platforms where the number of allocated MPIDRs is equal to the number of
+core power domains, for example, Juno and FVPs, the logic to convert an MPIDR to
+a core index should remain unchanged. Both Juno and FVP use a simple collision
+proof hash function to do this.
+
+It is possible that on some platforms, the allocation of MPIDRs is not
+contiguous or certain cores have been disabled. This essentially means that the
+MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs
+used by the platform is not equal to the number of core power domains.
+
+The platform could adopt one of the following approaches to deal with this
+scenario:
+
+#. Implement more complex logic to convert a valid MPIDR to a core index while
+   maintaining the relationship described earlier. This means that the power
+   domain tree descriptor will not describe any core power domains which are
+   disabled or absent. Entries will not be allocated in the tree for these
+   domains.
+
+#. Treat unallocated MPIDRs and disabled cores as absent but still describe them
+   in the power domain descriptor, that is, the number of core nodes described
+   is equal to the size of the range of MPIDRs allocated. This approach will
+   lead to memory wastage since entries will be allocated in the tree but will
+   allow use of a simpler logic to convert an MPIDR to a core index.
+
+Traversing through and distinguishing between core and non-core power domains
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To fulfill requirement 3 and 4, separate data structures have been defined
+to represent leaf and non-leaf power domain nodes in the tree.
+
+.. code:: c
+
+    /*******************************************************************************
+     * The following two data structures implement the power domain tree. The tree
+     * is used to track the state of all the nodes i.e. power domain instances
+     * described by the platform. The tree consists of nodes that describe CPU power
+     * domains i.e. leaf nodes and all other power domains which are parents of a
+     * CPU power domain i.e. non-leaf nodes.
+     ******************************************************************************/
+    typedef struct non_cpu_pwr_domain_node {
+        /*
+         * Index of the first CPU power domain node level 0 which has this node
+         * as its parent.
+         */
+        unsigned int cpu_start_idx;
+
+        /*
+         * Number of CPU power domains which are siblings of the domain indexed
+         * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
+         * -> cpu_start_idx + ncpus' have this node as their parent.
+         */
+        unsigned int ncpus;
+
+        /* Index of the parent power domain node */
+        unsigned int parent_node;
+
+        -----
+    } non_cpu_pd_node_t;
+
+    typedef struct cpu_pwr_domain_node {
+        u_register_t mpidr;
+
+        /* Index of the parent power domain node */
+        unsigned int parent_node;
+
+        -----
+    } cpu_pd_node_t;
+
+The power domain tree is implemented as a combination of the following data
+structures.
+
+.. code:: c
+
+    non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
+    cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
+
+Populating the power domain tree
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``populate_power_domain_tree()`` function in ``psci_setup.c`` implements the
+algorithm to parse the power domain descriptor exported by the platform to
+populate the two arrays. It is essentially a breadth-first-search. The nodes for
+each level starting from the root are laid out one after another in the
+``psci_non_cpu_pd_nodes`` and ``psci_cpu_pd_nodes`` arrays as follows:
+
+::
+
+    psci_non_cpu_pd_nodes -> [[Level 3 nodes][Level 2 nodes][Level 1 nodes]]
+    psci_cpu_pd_nodes -> [Level 0 nodes]
+
+For the example power domain tree illustrated above, the ``psci_cpu_pd_nodes``
+will be populated as follows. The value in each entry is the index of the parent
+node. Other fields have been ignored for simplicity.
+
+::
+
+                          +-------------+     ^
+                    CPU0  |      3      |     |
+                          +-------------+     |
+                    CPU1  |      3      |     |
+                          +-------------+     |
+                    CPU2  |      3      |     |
+                          +-------------+     |
+                    CPU3  |      4      |     |
+                          +-------------+     |
+                    CPU4  |      4      |     |
+                          +-------------+     |
+                    CPU5  |      4      |     | PLATFORM_CORE_COUNT
+                          +-------------+     |
+                    CPU6  |      5      |     |
+                          +-------------+     |
+                    CPU7  |      5      |     |
+                          +-------------+     |
+                    CPU8  |      5      |     |
+                          +-------------+     |
+                    CPU9  |      6      |     |
+                          +-------------+     |
+                    CPU10 |      6      |     |
+                          +-------------+     |
+                    CPU11 |      6      |     |
+                          +-------------+     |
+                    CPU12 |      6      |     v
+                          +-------------+
+
+The ``psci_non_cpu_pd_nodes`` array will be populated as follows. The value in
+each entry is the index of the parent node.
+
+::
+
+                          +-------------+     ^
+                    PD0   |      -1     |     |
+                          +-------------+     |
+                    PD1   |      0      |     |
+                          +-------------+     |
+                    PD2   |      0      |     |
+                          +-------------+     |
+                    PD3   |      1      |     | PLAT_NUM_POWER_DOMAINS -
+                          +-------------+     | PLATFORM_CORE_COUNT
+                    PD4   |      1      |     |
+                          +-------------+     |
+                    PD5   |      2      |     |
+                          +-------------+     |
+                    PD6   |      2      |     |
+                          +-------------+     v
+
+Each core can find its node in the ``psci_cpu_pd_nodes`` array using the
+``plat_my_core_pos()`` function. When a core is turned on, the normal world
+provides an MPIDR. The ``plat_core_pos_by_mpidr()`` function is used to validate
+the MPIDR before using it to find the corresponding core node. The non-core power
+domain nodes do not need to be identified.
+
+--------------
+
+*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.*

arm-trusted-firmware/docs/design/reset-design.rst

@@ -0,0 +1,161 @@
+CPU Reset
+=========
+
+This document describes the high-level design of the framework to handle CPU
+resets in Trusted Firmware-A (TF-A). It also describes how the platform
+integrator can tailor this code to the system configuration to some extent,
+resulting in a simplified and more optimised boot flow.
+
+This document should be used in conjunction with the :ref:`Firmware Design`
+document which provides greater implementation details around the reset code,
+specifically for the cold boot path.
+
+General reset code flow
+-----------------------
+
+The TF-A reset code is implemented in BL1 by default. The following high-level
+diagram illustrates this:
+
+|Default reset code flow|
+
+This diagram shows the default, unoptimised reset flow. Depending on the system
+configuration, some of these steps might be unnecessary. The following sections
+guide the platform integrator by indicating which build options exclude which
+steps, depending on the capability of the platform.
+
+.. note::
+   If BL31 is used as the TF-A entry point instead of BL1, the diagram
+   above is still relevant, as all these operations will occur in BL31 in
+   this case. Please refer to section 6 "Using BL31 entrypoint as the reset
+   address" for more information.
+
+Programmable CPU reset address
+------------------------------
+
+By default, TF-A assumes that the CPU reset address is not programmable.
+Therefore, all CPUs start at the same address (typically address 0) whenever
+they reset. Further logic is then required to identify whether it is a cold or
+warm boot to direct CPUs to the right execution path.
+
+If the reset vector address (reflected in the reset vector base address register
+``RVBAR_EL3``) is programmable then it is possible to make each CPU start directly
+at the right address, both on a cold and warm reset. Therefore, the boot type
+detection can be skipped, resulting in the following boot flow:
+
+|Reset code flow with programmable reset address|
+
+To enable this boot flow, compile TF-A with ``PROGRAMMABLE_RESET_ADDRESS=1``.
+This option only affects the TF-A reset image, which is BL1 by default or BL31 if
+``RESET_TO_BL31=1``.
+
+On both the FVP and Juno platforms, the reset vector address is not programmable
+so both ports use ``PROGRAMMABLE_RESET_ADDRESS=0``.
+
+Cold boot on a single CPU
+-------------------------
+
+By default, TF-A assumes that several CPUs may be released out of reset.
+Therefore, the cold boot code has to arbitrate access to hardware resources
+shared amongst CPUs. This is done by nominating one of the CPUs as the primary,
+which is responsible for initialising shared hardware and coordinating the boot
+flow with the other CPUs.
+
+If the platform guarantees that only a single CPU will ever be brought up then
+no arbitration is required. The notion of primary/secondary CPU itself no longer
+applies. This results in the following boot flow:
+
+|Reset code flow with single CPU released out of reset|
+
+To enable this boot flow, compile TF-A with ``COLD_BOOT_SINGLE_CPU=1``. This
+option only affects the TF-A reset image, which is BL1 by default or BL31 if
+``RESET_TO_BL31=1``.
+
+On both the FVP and Juno platforms, although only one core is powered up by
+default, there are platform-specific ways to release any number of cores out of
+reset. Therefore, both platform ports use ``COLD_BOOT_SINGLE_CPU=0``.
+
+Programmable CPU reset address, Cold boot on a single CPU
+---------------------------------------------------------
+
+It is obviously possible to combine both optimisations on platforms that have
+a programmable CPU reset address and which release a single CPU out of reset.
+This results in the following boot flow:
+
+
+|Reset code flow with programmable reset address and single CPU released out of reset|
+
+To enable this boot flow, compile TF-A with both ``COLD_BOOT_SINGLE_CPU=1``
+and ``PROGRAMMABLE_RESET_ADDRESS=1``. These options only affect the TF-A reset
+image, which is BL1 by default or BL31 if ``RESET_TO_BL31=1``.
+
+Using BL31 entrypoint as the reset address
+------------------------------------------
+
+On some platforms the runtime firmware (BL3x images) for the application
+processors are loaded by some firmware running on a secure system processor
+on the SoC, rather than by BL1 and BL2 running on the primary application
+processor. For this type of SoC it is desirable for the application processor
+to always reset to BL31 which eliminates the need for BL1 and BL2.
+
+TF-A provides a build-time option ``RESET_TO_BL31`` that includes some additional
+logic in the BL31 entry point to support this use case.
+
+In this configuration, the platform's Trusted Boot Firmware must ensure that
+BL31 is loaded to its runtime address, which must match the CPU's ``RVBAR_EL3``
+reset vector base address, before the application processor is powered on.
+Additionally, platform software is responsible for loading the other BL3x images
+required and providing entry point information for them to BL31. Loading these
+images might be done by the Trusted Boot Firmware or by platform code in BL31.
+
+Although the Arm FVP platform does not support programming the reset base
+address dynamically at run-time, it is possible to set the initial value of the
+``RVBAR_EL3`` register at start-up. This feature is provided on the Base FVP
+only.
+
+It allows the Arm FVP port to support the ``RESET_TO_BL31`` configuration, in
+which case the ``bl31.bin`` image must be loaded to its run address in Trusted
+SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
+address. See the :ref:`Arm Fixed Virtual Platforms (FVP)` for details of running
+the FVP models in this way.
+
+Although technically it would be possible to program the reset base address with
+the right support in the SCP firmware, this is currently not implemented so the
+Juno port doesn't support the ``RESET_TO_BL31`` configuration.
+
+The ``RESET_TO_BL31`` configuration requires some additions and changes in the
+BL31 functionality:
+
+Determination of boot path
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+In this configuration, BL31 uses the same reset framework and code as the one
+described for BL1 above. Therefore, it is affected by the
+``PROGRAMMABLE_RESET_ADDRESS`` and ``COLD_BOOT_SINGLE_CPU`` build options in the
+same way.
+
+In the default, unoptimised BL31 reset flow, on a warm boot a CPU is directed
+to the PSCI implementation via a platform defined mechanism. On a cold boot,
+the platform must place any secondary CPUs into a safe state while the primary
+CPU executes a modified BL31 initialization, as described below.
+
+Platform initialization
+~~~~~~~~~~~~~~~~~~~~~~~
+
+In this configuration, when the CPU resets to BL31 there are no parameters that
+can be passed in registers by previous boot stages. Instead, the platform code
+in BL31 needs to know, or be able to determine, the location of the BL32 (if
+required) and BL33 images and provide this information in response to the
+``bl31_plat_get_next_image_ep_info()`` function.
+
+Additionally, platform software is responsible for carrying out any security
+initialisation, for example programming a TrustZone address space controller.
+This might be done by the Trusted Boot Firmware or by platform code in BL31.
+
+--------------
+
+*Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.*
+
+.. |Default reset code flow| image:: ../resources/diagrams/default_reset_code.png
+.. |Reset code flow with programmable reset address| image:: ../resources/diagrams/reset_code_no_boot_type_check.png
+.. |Reset code flow with single CPU released out of reset| image:: ../resources/diagrams/reset_code_no_cpu_check.png
+.. |Reset code flow with programmable reset address and single CPU released out of reset| image:: ../resources/diagrams/reset_code_no_checks.png

arm-trusted-firmware/docs/design/trusted-board-boot-build.rst

@@ -0,0 +1,115 @@
+Building FIP images with support for Trusted Board Boot
+=======================================================
+
+Trusted Board Boot primarily consists of the following two features:
+
+-  Image Authentication, described in :ref:`Trusted Board Boot`, and
+-  Firmware Update, described in :ref:`Firmware Update (FWU)`
+
+The following steps should be followed to build FIP and (optionally) FWU_FIP
+images with support for these features:
+
+#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
+   modules by checking out a recent version of the `mbed TLS Repository`_. It
+   is important to use a version that is compatible with TF-A and fixes any
+   known security vulnerabilities. See `mbed TLS Security Center`_ for more
+   information. See the :ref:`Prerequisites` document for the appropriate
+   version of mbed TLS to use.
+
+   The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
+   source files the modules depend upon.
+   ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
+   options required to build the mbed TLS sources.
+
+   Note that the mbed TLS library is licensed under the Apache version 2.0
+   license. Using mbed TLS source code will affect the licensing of TF-A
+   binaries that are built using this library.
+
+#. To build the FIP image, ensure the following command line variables are set
+   while invoking ``make`` to build TF-A:
+
+   -  ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
+   -  ``TRUSTED_BOARD_BOOT=1``
+   -  ``GENERATE_COT=1``
+
+   By default, this will use the Chain of Trust described in the TBBR-client
+   document. To select a different one, use the ``COT`` build option.
+
+   In the case of Arm platforms, the location of the ROTPK hash must also be
+   specified at build time. The following locations are currently supported (see
+   ``ARM_ROTPK_LOCATION`` build option):
+
+   -  ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
+      root-key storage registers present in the platform. On Juno, these
+      registers are read-only. On FVP Base and Cortex models, the registers
+      are also read-only, but the value can be specified using the command line
+      option ``bp.trusted_key_storage.public_key`` when launching the model.
+      On Juno board, the default value corresponds to an ECDSA-SECP256R1 public
+      key hash, whose private part is not currently available.
+
+   -  ``ARM_ROTPK_LOCATION=devel_rsa``: use the default hash located in
+      ``plat/arm/board/common/rotpk/arm_rotpk_rsa_sha256.bin``. Enforce
+      generation of the new hash if ``ROT_KEY`` is specified.
+
+   -  ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the default hash located in
+      ``plat/arm/board/common/rotpk/arm_rotpk_ecdsa_sha256.bin``. Enforce
+      generation of the new hash if ``ROT_KEY`` is specified.
+
+   Example of command line using RSA development keys:
+
+   .. code:: shell
+
+       MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
+       make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1        \
+       ARM_ROTPK_LOCATION=devel_rsa                                    \
+       ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem        \
+       BL33=<path-to>/<bl33_image>                                     \
+       all fip
+
+   The result of this build will be the bl1.bin and the fip.bin binaries. This
+   FIP will include the certificates corresponding to the selected Chain of
+   Trust. These certificates can also be found in the output build directory.
+
+#. The optional FWU_FIP contains any additional images to be loaded from
+   Non-Volatile storage during the :ref:`Firmware Update (FWU)` process. To build the
+   FWU_FIP, any FWU images required by the platform must be specified on the
+   command line. On Arm development platforms like Juno, these are:
+
+   -  NS_BL2U. The AP non-secure Firmware Updater image.
+   -  SCP_BL2U. The SCP Firmware Update Configuration image.
+
+   Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
+   targets using RSA development:
+
+   ::
+
+       MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
+       make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1              \
+       ARM_ROTPK_LOCATION=devel_rsa                                    \
+       ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem        \
+       BL33=<path-to>/<bl33_image>                                     \
+       SCP_BL2=<path-to>/<scp_bl2_image>                               \
+       SCP_BL2U=<path-to>/<scp_bl2u_image>                             \
+       NS_BL2U=<path-to>/<ns_bl2u_image>                               \
+       all fip fwu_fip
+
+   .. note::
+      The BL2U image will be built by default and added to the FWU_FIP.
+      The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
+      to the command line above.
+
+   .. note::
+      Building and installing the non-secure and SCP FWU images (NS_BL1U,
+      NS_BL2U and SCP_BL2U) is outside the scope of this document.
+
+   The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
+   Both the FIP and FWU_FIP will include the certificates corresponding to the
+   selected Chain of Trust. These certificates can also be found in the output
+   build directory.
+
+--------------
+
+*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+
+.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
+.. _mbed TLS Security Center: https://tls.mbed.org/security

arm-trusted-firmware/docs/design/trusted-board-boot.rst

@@ -0,0 +1,263 @@
+Trusted Board Boot
+==================
+
+The Trusted Board Boot (TBB) feature prevents malicious firmware from running on
+the platform by authenticating all firmware images up to and including the
+normal world bootloader. It does this by establishing a Chain of Trust using
+Public-Key-Cryptography Standards (PKCS).
+
+This document describes the design of Trusted Firmware-A (TF-A) TBB, which is an
+implementation of the `Trusted Board Boot Requirements (TBBR)`_ specification,
+Arm DEN0006D. It should be used in conjunction with the
+:ref:`Firmware Update (FWU)` design document, which implements a specific aspect
+of the TBBR.
+
+Chain of Trust
+--------------
+
+A Chain of Trust (CoT) starts with a set of implicitly trusted components. On
+the Arm development platforms, these components are:
+
+-  A SHA-256 hash of the Root of Trust Public Key (ROTPK). It is stored in the
+   trusted root-key storage registers. Alternatively, a development ROTPK might
+   be used and its hash embedded into the BL1 and BL2 images (only for
+   development purposes).
+
+-  The BL1 image, on the assumption that it resides in ROM so cannot be
+   tampered with.
+
+The remaining components in the CoT are either certificates or boot loader
+images. The certificates follow the `X.509 v3`_ standard. This standard
+enables adding custom extensions to the certificates, which are used to store
+essential information to establish the CoT.
+
+In the TBB CoT all certificates are self-signed. There is no need for a
+Certificate Authority (CA) because the CoT is not established by verifying the
+validity of a certificate's issuer but by the content of the certificate
+extensions. To sign the certificates, different signature schemes are available,
+please refer to the :ref:`Build Options` for more details.
+
+The certificates are categorised as "Key" and "Content" certificates. Key
+certificates are used to verify public keys which have been used to sign content
+certificates. Content certificates are used to store the hash of a boot loader
+image. An image can be authenticated by calculating its hash and matching it
+with the hash extracted from the content certificate. Various hash algorithms
+are supported to calculate all hashes, please refer to the :ref:`Build Options`
+for more details.. The public keys and hashes are included as non-standard
+extension fields in the `X.509 v3`_ certificates.
+
+The keys used to establish the CoT are:
+
+-  **Root of trust key**
+
+   The private part of this key is used to sign the BL2 content certificate and
+   the trusted key certificate. The public part is the ROTPK.
+
+-  **Trusted world key**
+
+   The private part is used to sign the key certificates corresponding to the
+   secure world images (SCP_BL2, BL31 and BL32). The public part is stored in
+   one of the extension fields in the trusted world certificate.
+
+-  **Non-trusted world key**
+
+   The private part is used to sign the key certificate corresponding to the
+   non secure world image (BL33). The public part is stored in one of the
+   extension fields in the trusted world certificate.
+
+-  **BL3X keys**
+
+   For each of SCP_BL2, BL31, BL32 and BL33, the private part is used to
+   sign the content certificate for the BL3X image. The public part is stored
+   in one of the extension fields in the corresponding key certificate.
+
+The following images are included in the CoT:
+
+-  BL1
+-  BL2
+-  SCP_BL2 (optional)
+-  BL31
+-  BL33
+-  BL32 (optional)
+
+The following certificates are used to authenticate the images.
+
+-  **BL2 content certificate**
+
+   It is self-signed with the private part of the ROT key. It contains a hash
+   of the BL2 image.
+
+-  **Trusted key certificate**
+
+   It is self-signed with the private part of the ROT key. It contains the
+   public part of the trusted world key and the public part of the non-trusted
+   world key.
+
+-  **SCP_BL2 key certificate**
+
+   It is self-signed with the trusted world key. It contains the public part of
+   the SCP_BL2 key.
+
+-  **SCP_BL2 content certificate**
+
+   It is self-signed with the SCP_BL2 key. It contains a hash of the SCP_BL2
+   image.
+
+-  **BL31 key certificate**
+
+   It is self-signed with the trusted world key. It contains the public part of
+   the BL31 key.
+
+-  **BL31 content certificate**
+
+   It is self-signed with the BL31 key. It contains a hash of the BL31 image.
+
+-  **BL32 key certificate**
+
+   It is self-signed with the trusted world key. It contains the public part of
+   the BL32 key.
+
+-  **BL32 content certificate**
+
+   It is self-signed with the BL32 key. It contains a hash of the BL32 image.
+
+-  **BL33 key certificate**
+
+   It is self-signed with the non-trusted world key. It contains the public
+   part of the BL33 key.
+
+-  **BL33 content certificate**
+
+   It is self-signed with the BL33 key. It contains a hash of the BL33 image.
+
+The SCP_BL2 and BL32 certificates are optional, but they must be present if the
+corresponding SCP_BL2 or BL32 images are present.
+
+Trusted Board Boot Sequence
+---------------------------
+
+The CoT is verified through the following sequence of steps. The system panics
+if any of the steps fail.
+
+-  BL1 loads and verifies the BL2 content certificate. The issuer public key is
+   read from the verified certificate. A hash of that key is calculated and
+   compared with the hash of the ROTPK read from the trusted root-key storage
+   registers. If they match, the BL2 hash is read from the certificate.
+
+   .. note::
+      The matching operation is platform specific and is currently
+      unimplemented on the Arm development platforms.
+
+-  BL1 loads the BL2 image. Its hash is calculated and compared with the hash
+   read from the certificate. Control is transferred to the BL2 image if all
+   the comparisons succeed.
+
+-  BL2 loads and verifies the trusted key certificate. The issuer public key is
+   read from the verified certificate. A hash of that key is calculated and
+   compared with the hash of the ROTPK read from the trusted root-key storage
+   registers. If the comparison succeeds, BL2 reads and saves the trusted and
+   non-trusted world public keys from the verified certificate.
+
+The next two steps are executed for each of the SCP_BL2, BL31 & BL32 images.
+The steps for the optional SCP_BL2 and BL32 images are skipped if these images
+are not present.
+
+-  BL2 loads and verifies the BL3x key certificate. The certificate signature
+   is verified using the trusted world public key. If the signature
+   verification succeeds, BL2 reads and saves the BL3x public key from the
+   certificate.
+
+-  BL2 loads and verifies the BL3x content certificate. The signature is
+   verified using the BL3x public key. If the signature verification succeeds,
+   BL2 reads and saves the BL3x image hash from the certificate.
+
+The next two steps are executed only for the BL33 image.
+
+-  BL2 loads and verifies the BL33 key certificate. If the signature
+   verification succeeds, BL2 reads and saves the BL33 public key from the
+   certificate.
+
+-  BL2 loads and verifies the BL33 content certificate. If the signature
+   verification succeeds, BL2 reads and saves the BL33 image hash from the
+   certificate.
+
+The next step is executed for all the boot loader images.
+
+-  BL2 calculates the hash of each image. It compares it with the hash obtained
+   from the corresponding content certificate. The image authentication succeeds
+   if the hashes match.
+
+The Trusted Board Boot implementation spans both generic and platform-specific
+BL1 and BL2 code, and in tool code on the host build machine. The feature is
+enabled through use of specific build flags as described in
+:ref:`Build Options`.
+
+On the host machine, a tool generates the certificates, which are included in
+the FIP along with the boot loader images. These certificates are loaded in
+Trusted SRAM using the IO storage framework. They are then verified by an
+Authentication module included in TF-A.
+
+The mechanism used for generating the FIP and the Authentication module are
+described in the following sections.
+
+Authentication Framework
+------------------------
+
+The authentication framework included in TF-A provides support to implement
+the desired trusted boot sequence. Arm platforms use this framework to
+implement the boot requirements specified in the
+`Trusted Board Boot Requirements (TBBR)`_ document.
+
+More information about the authentication framework can be found in the
+:ref:`Authentication Framework & Chain of Trust` document.
+
+Certificate Generation Tool
+---------------------------
+
+The ``cert_create`` tool is built and runs on the host machine as part of the
+TF-A build process when ``GENERATE_COT=1``. It takes the boot loader images
+and keys as inputs (keys must be in PEM format) and generates the
+certificates (in DER format) required to establish the CoT. New keys can be
+generated by the tool in case they are not provided. The certificates are then
+passed as inputs to the ``fiptool`` utility for creating the FIP.
+
+The certificates are also stored individually in the output build directory.
+
+The tool resides in the ``tools/cert_create`` directory. It uses the OpenSSL SSL
+library version to generate the X.509 certificates. The specific version of the
+library that is required is given in the :ref:`Prerequisites` document.
+
+Instructions for building and using the tool can be found at
+:ref:`tools_build_cert_create`.
+
+Authenticated Encryption Framework
+----------------------------------
+
+The authenticated encryption framework included in TF-A provides support to
+implement the optional firmware encryption feature. This feature can be
+optionally enabled on platforms to implement the optional requirement:
+R060_TBBR_FUNCTION as specified in the `Trusted Board Boot Requirements (TBBR)`_
+document.
+
+Firmware Encryption Tool
+------------------------
+
+The ``encrypt_fw`` tool is built and runs on the host machine as part of the
+TF-A build process when ``DECRYPTION_SUPPORT != none``. It takes the plain
+firmware image as input and generates the encrypted firmware image which can
+then be passed as input to the ``fiptool`` utility for creating the FIP.
+
+The encrypted firmwares are also stored individually in the output build
+directory.
+
+The tool resides in the ``tools/encrypt_fw`` directory. It uses OpenSSL SSL
+library version 1.0.1 or later to do authenticated encryption operation.
+Instructions for building and using the tool can be found in the
+:ref:`tools_build_enctool`.
+
+--------------
+
+*Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.*
+
+.. _X.509 v3: https://tools.ietf.org/rfc/rfc5280.txt
+.. _Trusted Board Boot Requirements (TBBR): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a