mirror of
git://nv-tegra.nvidia.com/tegra/optee-src/atf.git
synced 2025-12-22 09:21:26 +03:00
Updating prebuilts and/or headers
d15f50688485e11293e0d0bd66d73655e79f7718 - nvcommon_build.sh 600af606544528acefdcda1ac9360385c7fb445e - nvbuild.sh b59696219da8c2717d6dbc9c849992987bca93cc - arm-trusted-firmware/.commitlintrc.js e3ed21e226909ec6866c0b56d967c274a54d9a02 - arm-trusted-firmware/package.json 2d62a7583b85631859c4143f08e0dc332e1cb87e - arm-trusted-firmware/.gitreview 49917248e01f92d5e2004b5729b9e342a40aae80 - arm-trusted-firmware/Makefile 7f3fadaf80e3c4745d24cb1a5881c7c5f4d898ba - arm-trusted-firmware/.checkpatch.conf 55bcfa0a03639a375c3f87b1d3286f526c41b207 - arm-trusted-firmware/.versionrc.js 5f8311228df51d284e4efc6c89e9d193dde99d11 - arm-trusted-firmware/.editorconfig 827aec79d725715df06ae1ec5b5b6378a4132040 - arm-trusted-firmware/changelog.yaml c10d9e3662b48b6da5c81ce00879a16fd8cf3d60 - arm-trusted-firmware/.cz.json 0555d5f984963f02d51ce35187ffa47d2494fa53 - arm-trusted-firmware/.nvmrc da14c19baefee3959f7c02f68db6cbe8c25d408e - arm-trusted-firmware/readme.rst 4be1608ee9ecffe46579874302bb223b8f8d2b89 - arm-trusted-firmware/package-lock.json d8da3627085908a5f974b45528b85dc0a41a8b75 - arm-trusted-firmware/license.rst 2d32dba27247198d6cd35d150dc8eeba3c8ed8ff - arm-trusted-firmware/bl2u/bl2u.ld.S 0cd1ab24947e0ea5ce307a171756d88683d36cde - arm-trusted-firmware/bl2u/bl2u_main.c 0227b9aa908915e602a5839d4229f7832e99c76b - arm-trusted-firmware/bl2u/aarch32/bl2u_entrypoint.S 1df1aad13ba7e2ed5cb1ae4a6200d169a1715578 - arm-trusted-firmware/bl2u/aarch64/bl2u_entrypoint.S b3620caffa1984c87c94e9a3c1a0fd54bcbf4302 - arm-trusted-firmware/tools/encrypt_fw/Makefile 08dcc81abf0dd5a951f1d7cb36e2d05628055bec - arm-trusted-firmware/tools/encrypt_fw/include/cmd_opt.h f37ed62897799b6165569c0842904eb6fe5d21d5 - arm-trusted-firmware/tools/encrypt_fw/include/encrypt.h 843248736f6bce43a9ac3f11f9bfa6a094face5a - arm-trusted-firmware/tools/encrypt_fw/include/debug.h 29f5f62fba8f9c0fb9e528df8a7c5f9a264d9bad - arm-trusted-firmware/tools/encrypt_fw/src/cmd_opt.c 5093ed93e150e683b735ad26979460536e2419f3 - arm-trusted-firmware/tools/encrypt_fw/src/main.c 93d36734d229d79068472d13bb173cb9b1537d9d - arm-trusted-firmware/tools/encrypt_fw/src/encrypt.c e6383f5a328565a9ebbfef64899ed79956fb48a1 - arm-trusted-firmware/tools/conventional-changelog-tf-a/package.json 9bdff25d946a2c61d8312e1f53c49802d66d3577 - arm-trusted-firmware/tools/conventional-changelog-tf-a/index.js 5e9ebb4c1ffaf478200ddbd8bd5bbef2b0f2d2f6 - arm-trusted-firmware/tools/conventional-changelog-tf-a/templates/commit-section.hbs da39a3ee5e6b4b0d3255bfef95601890afd80709 - arm-trusted-firmware/tools/conventional-changelog-tf-a/templates/footer.hbs bdd671375b10dbdabd4f1f87941d3071e275ff64 - arm-trusted-firmware/tools/conventional-changelog-tf-a/templates/commit.hbs 65198bc7a494eba7c91745808f3ada1e3034659a - arm-trusted-firmware/tools/conventional-changelog-tf-a/templates/note.hbs 85453d72f48122ba14bd00512fac19ef0fc42d07 - arm-trusted-firmware/tools/conventional-changelog-tf-a/templates/template.hbs 1d1032e5160d84f70af7f7ab6dddaf003244f768 - arm-trusted-firmware/tools/conventional-changelog-tf-a/templates/note-section.hbs 99f27ae0dfb07952b2130a819e32599cfc2d78c6 - arm-trusted-firmware/tools/conventional-changelog-tf-a/templates/header.hbs 2bbefb66f05e50612c3b0d215f0bd185e076cf20 - arm-trusted-firmware/tools/marvell/doimage/Makefile 0ec11eeb14668d925e198fc42145f8b0fd3d02d8 - arm-trusted-firmware/tools/marvell/doimage/doimage.c c8f9244b21f28bb382b1befed8dce13e4eae06f9 - arm-trusted-firmware/tools/marvell/doimage/secure/csk_priv_pem2.key f35a6333e76f3fb2bed05bad996a131317f5ac9d - arm-trusted-firmware/tools/marvell/doimage/secure/csk_priv_pem3.key f848ecb51058182d4c908f7c9a88561dbdce34bd - arm-trusted-firmware/tools/marvell/doimage/secure/kak_priv_pem.key 8602871bb27d59d5b5ce180448e1ceb232027bad - arm-trusted-firmware/tools/marvell/doimage/secure/csk_priv_pem1.key 954bc6cdf269e0eaa9581057657a1e2bf9621f38 - arm-trusted-firmware/tools/marvell/doimage/secure/csk_priv_pem0.key 8fc012a12a4398216ad6fd4b97199ccd159711e5 - arm-trusted-firmware/tools/marvell/doimage/secure/sec_img_7K.cfg 5b6535dd6c94832d3113588ea938b9526b06b0fc - arm-trusted-firmware/tools/marvell/doimage/secure/sec_img_8K.cfg d11fbb00e7e7d26b6b9470205838a13be7259b0c - arm-trusted-firmware/tools/sptool/sp_mk_generator.py aeb453284713e6bac634404236fab26ae7b17c6e - arm-trusted-firmware/tools/sptool/Makefile 94e9758f25bc25bb3cf28c26f021394ee7ab7c76 - arm-trusted-firmware/tools/sptool/sptool.py d1d13fd8efcddd123f275316a3a9bdec7f51b1f5 - arm-trusted-firmware/tools/sptool/spactions.py 01000b7d50599a58601322b9a12174d81bd80571 - arm-trusted-firmware/tools/renesas/rzg_layout_create/sa0.ld.S f51f929a6294d60d681b03dbf0f3f1fe0835fa3a - arm-trusted-firmware/tools/renesas/rzg_layout_create/sa0.c 4085a8d4104eac744977d5ec6feacf08b8a1283a - arm-trusted-firmware/tools/renesas/rzg_layout_create/sa6.c 8c2b63db003e2e330f2af95b94c2132bc2fc9725 - arm-trusted-firmware/tools/renesas/rzg_layout_create/sa6.ld.S 3d9335fb1238d08df68e2770f69a0e1bec960069 - arm-trusted-firmware/tools/renesas/rzg_layout_create/makefile a728eb1898ea80778d60fcf57b727f977c29ec98 - arm-trusted-firmware/tools/renesas/rcar_layout_create/sa0.ld.S 213e1746ba029a55b6baf19ac0d8863713811b64 - arm-trusted-firmware/tools/renesas/rcar_layout_create/sa0.c b4ecd67c81a19d47e59f9a72dd81fc392fff3aea - arm-trusted-firmware/tools/renesas/rcar_layout_create/sa6.c c6acebe37afdaba95dbaf9f814eb4bba5dd989a9 - arm-trusted-firmware/tools/renesas/rcar_layout_create/sa6.ld.S ba6ab775fd9474718d717b35f4220e716f7b7ae6 - arm-trusted-firmware/tools/renesas/rcar_layout_create/makefile 58ef2523c26b02365fb70cb1cebc29cba026be23 - arm-trusted-firmware/tools/amlogic/Makefile 12473d63d565d1782e4e3273a27c29c04adaf86f - arm-trusted-firmware/tools/amlogic/doimage.c 3d16696dce452bf99b18bdd1a964fe7ad191477b - arm-trusted-firmware/tools/nxp/cert_create_helper/include/pdef_tbb_ext.h 46fb0f5a24245e631af2a4690c0d7202204c0e54 - arm-trusted-firmware/tools/nxp/cert_create_helper/include/pdef_tbb_cert.h 621d8ec57a445f0149ebb8b216ef913ed05f8754 - arm-trusted-firmware/tools/nxp/cert_create_helper/include/pdef_tbb_key.h f328e450c8ae941e8109578f1721860acbfafbbe - arm-trusted-firmware/tools/nxp/cert_create_helper/src/pdef_tbb_cert.c 506a53ab2e813a5ce578765b25e1e3fe0f1e643e - arm-trusted-firmware/tools/nxp/cert_create_helper/src/pdef_tbb_key.c 4065b3a492865b1f4525586a648df384bf7c961a - arm-trusted-firmware/tools/nxp/cert_create_helper/src/pdef_tbb_ext.c ee87af83d314b14a8d8a41acb7fa47c97f7dda56 - arm-trusted-firmware/tools/nxp/plat_fiptool/plat_def_uuid_config.c 294a1e169dc8c2e940e56cad57a08e5d4adb3b9f - arm-trusted-firmware/tools/nxp/create_pbl/Makefile 6883483605723caec745103ffaafc790ec284c8d - arm-trusted-firmware/tools/nxp/create_pbl/create_pbl.c 2ec990b299f9fd69d0e0a85e98faba9055f56bab - arm-trusted-firmware/tools/nxp/create_pbl/README d66ad3c8e97d38face17234980203ac71836e11f - arm-trusted-firmware/tools/nxp/create_pbl/byte_swap.c 1474476f05acda23a8bb1e859fcc314baf5a4fda - arm-trusted-firmware/tools/stm32image/Makefile 75e7e633ff5fcf6dca970eef0c2acd786d23f188 - arm-trusted-firmware/tools/stm32image/stm32image.c 96a3fe32a70fc5d7ef351718fbf944ccc04d431d - arm-trusted-firmware/tools/memory/print_memory_map.py 3e405383b6376569f5f9c3443607b970223b6cb8 - arm-trusted-firmware/tools/cert_create/Makefile 134c6c14b6a384f0e036827b128d4adf08612d9a - arm-trusted-firmware/tools/cert_create/include/cmd_opt.h 8b842068cbb1b417974e3790f0b22384fd832557 - arm-trusted-firmware/tools/cert_create/include/cert.h 0a307fbdd842fe9ae8212a2362b356addf0a38df - arm-trusted-firmware/tools/cert_create/include/sha.h e811f0559d11bef9f60e7037563e74106ee1a4a0 - arm-trusted-firmware/tools/cert_create/include/key.h 843248736f6bce43a9ac3f11f9bfa6a094face5a - arm-trusted-firmware/tools/cert_create/include/debug.h 492b505667cc68b67b20bf6bfc9fbd84bd06e701 - arm-trusted-firmware/tools/cert_create/include/ext.h 0c696ba78f7d568469b58576262a035b3074ae67 - arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_ext.h 728ba9b1bbfe33e0ca3e33eb166f04922947e3e3 - arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_key.h a015fcfd89d3e63781911e5134884343975d6284 - arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_cert.h cea4dea6df116896b98ab50dd4ffcfed6918217a - arm-trusted-firmware/tools/cert_create/include/cca/cca_cot.h 596785e69869c848d5fdb306b8084f282876abe7 - arm-trusted-firmware/tools/cert_create/include/dualroot/cot.h be863190f00aa6265cc9d462c89dea146f1acc0c - arm-trusted-firmware/tools/cert_create/src/sha.c ff9e1a5c3c367224d54ebf6f55bf996b0ba5f190 - arm-trusted-firmware/tools/cert_create/src/cert.c 141db0ebbb3519ad3f12eef3776040eb6d3e7995 - arm-trusted-firmware/tools/cert_create/src/ext.c a9191ea8a1afb334786e038f658601f93beebf24 - arm-trusted-firmware/tools/cert_create/src/key.c 29f5f62fba8f9c0fb9e528df8a7c5f9a264d9bad - arm-trusted-firmware/tools/cert_create/src/cmd_opt.c b1fc9078f968b3df8ee4a6b0f4904babccb5964f - arm-trusted-firmware/tools/cert_create/src/main.c c5571efb1999abfd481ddccdf9cfa8db65d5e440 - arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_key.c a71f6edc951824d84282d7f0262e1ebd260a5a38 - arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_cert.c 11fe1d417bcbf3a47d588f48d738d47a156b9c49 - arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_ext.c 32c65756f07a7b64355c8c9c6837c2dc818201fd - arm-trusted-firmware/tools/cert_create/src/cca/cot.c 87b7868a92308d1b74bbf003f8fb00f89c405d2c - arm-trusted-firmware/tools/cert_create/src/dualroot/cot.c 3d5b607383dc4f856b78413d5717b3dd825ef661 - arm-trusted-firmware/tools/fiptool/tbbr_config.c 65980df1c7c0151645806394b329a65285fe5869 - arm-trusted-firmware/tools/fiptool/Makefile 12207fca29ab69b8fccc71ef7a95f9d551ec744f - arm-trusted-firmware/tools/fiptool/win_posix.c ac76d7753d0fb5d60a4fcebb22f8a4a5c8f48040 - arm-trusted-firmware/tools/fiptool/fiptool.c 6dcc9e2c01e4d8e4c0b531154c0598192ba190c7 - arm-trusted-firmware/tools/fiptool/fiptool_platform.h 323e507fdf87c7d4a94d0bbbaa72bd905c2d641d - arm-trusted-firmware/tools/fiptool/win_posix.h ff33081f63178813dd9c9235d17538954c29d7c6 - arm-trusted-firmware/tools/fiptool/fiptool.h 30931543e94deea26c28007433bf6d837f1839aa - arm-trusted-firmware/tools/fiptool/tbbr_config.h d47913d50cdf551a4f0677629c59c1464b96f606 - arm-trusted-firmware/tools/fiptool/Makefile.msvc c725cbfb19ba6bb974427a20390a478e1a9e45ac - arm-trusted-firmware/tools/fiptool/fiptool bef42ef1a358ce195d045dd1ff0aab9e20bc0af0 - arm-trusted-firmware/drivers/partition/partition.c 58ee2053df744e8e7840e5687f4ecfb2cd7a572e - arm-trusted-firmware/drivers/partition/gpt.c 7ff3e84af33c3fcf6ee55936d6400a52d52203b4 - arm-trusted-firmware/drivers/mentor/i2c/mi2cv.c c83fb1312ae05c6e624572806f085c6919f189af - arm-trusted-firmware/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S 1fa3c347f937895d6e5869cff641faf35158d0e0 - arm-trusted-firmware/drivers/intel/soc/stratix10/io/s10_memmap_qspi.c 6da3edf3b8285ad337a0fca3a94279c2fc1cee92 - arm-trusted-firmware/drivers/scmi-msg/base.c 0f8a382f7d1dc362cfb9bf7d2a7189987b1bd9f4 - arm-trusted-firmware/drivers/scmi-msg/entry.c 3793e73034176c719a8160e57d2216f834867aea - arm-trusted-firmware/drivers/scmi-msg/base.h 6854b6e16a5d00e32471a842ac82a42307f4fd25 - arm-trusted-firmware/drivers/scmi-msg/reset_domain.h d0830b0dd0dcad2627d7e25042e0b04f9172507d - arm-trusted-firmware/drivers/scmi-msg/common.h a9219fa6261f43e472c7b1655189ae66022de0e2 - arm-trusted-firmware/drivers/scmi-msg/clock.h 9a06fcf18608dead4701ec10a63da3ace748fe3d - arm-trusted-firmware/drivers/scmi-msg/smt.c 6494de9c4e6d28e03514a090db2224f8b96327ba - arm-trusted-firmware/drivers/scmi-msg/power_domain.h 87e2ccd433b23fc20ba9c6b329c0e70654df069e - arm-trusted-firmware/drivers/scmi-msg/power_domain.c 4df3d4456a8ec6d6ea78baf7e573f0357ddc3196 - arm-trusted-firmware/drivers/scmi-msg/clock.c 51f712caca20f1532dbd7a569fab515695f574f9 - arm-trusted-firmware/drivers/scmi-msg/reset_domain.c 366c422651f720b64f0d606e537b12713c405d8e - arm-trusted-firmware/drivers/fwu/fwu.c 27de4bff9c8b262626a7c87cd68c10f73b9cd88f - arm-trusted-firmware/drivers/measured_boot/rss/rss_measured_boot.c 150bd08bfbcc1de20e05b6d07950021df0a46322 - arm-trusted-firmware/drivers/measured_boot/event_log/event_print.c 78a4b08176acfbe2acf5b4bf9ef646887f76877c - arm-trusted-firmware/drivers/measured_boot/event_log/event_log.c 8e0afaebcd5d1ed41d30457bdb8543f3617640eb - arm-trusted-firmware/drivers/synopsys/emmc/dw_mmc.c 1d5e94fb3b734e7c9eb7b1628230f3d140a8e958 - arm-trusted-firmware/drivers/synopsys/ufs/dw_ufs.c e352b30931747ba506a85329d7c6fe69935dd5b0 - arm-trusted-firmware/drivers/marvell/ccu.c 857ba1731ec174905f4cccd68d02bdd3abf08b6e - arm-trusted-firmware/drivers/marvell/amb_adec.c d0ef41df34b7a9ed1d587f10727ba0ee57d04c83 - arm-trusted-firmware/drivers/marvell/ddr_phy_access.h 6256615787b3a1bb1f9b4fc3d64794006722b859 - arm-trusted-firmware/drivers/marvell/ap807_clocks_init.c a275b56587e6c0c05df6a7985ad0cf0e2216e4f8 - arm-trusted-firmware/drivers/marvell/comphy.h c8524aa6f76d32913ffaffda10350b753e429b5b - arm-trusted-firmware/drivers/marvell/ddr_phy_access.c e082e89bfcb90fcea87099285d6eb142fff1f589 - arm-trusted-firmware/drivers/marvell/io_win.c 77e98f136f88749eb01cf7092f9d086cae652384 - arm-trusted-firmware/drivers/marvell/thermal.c b724830f0762dc7701cc9fd88c863c7b53f405c5 - arm-trusted-firmware/drivers/marvell/iob.c f00e9719e8be0259cb5e171298f2ffb0d09c4fef - arm-trusted-firmware/drivers/marvell/gwin.c 6dc9f5af1b3c165888d4faae36b6da72adb6faf0 - arm-trusted-firmware/drivers/marvell/cache_llc.c c523b2dcff8e39c5cacc416584d42aa530a93315 - arm-trusted-firmware/drivers/marvell/mci.c 10ce6fa5d5bbc4205013818f591e235cbcadccd1 - arm-trusted-firmware/drivers/marvell/mg_conf_cm3/mg_conf_cm3.h f89de6e4fae5d6f6d1778f6c5a92d7f25ab403b9 - arm-trusted-firmware/drivers/marvell/mg_conf_cm3/mg_conf_cm3.c 9a1f55dbc2fc4e8ca97f9af3e7d435f1bddfd83c - arm-trusted-firmware/drivers/marvell/mochi/cp110_setup.c bb5f60fb041d3fbc6812ce56b8976c686be8105a - arm-trusted-firmware/drivers/marvell/mochi/ap807_setup.c cd9af6970ea49226ec63b2b04d0b06b86d503eae - arm-trusted-firmware/drivers/marvell/mochi/apn806_setup.c 041d0631d9cb0fe39ee3d1f8d20629d3d2225f86 - arm-trusted-firmware/drivers/marvell/comphy/phy-comphy-3700.h dc409874b01f2f616b65f4f9e8497ba172fb2535 - arm-trusted-firmware/drivers/marvell/comphy/phy-comphy-cp110.c 52740dfd3574268d954c81e6a708c55188bca7e1 - arm-trusted-firmware/drivers/marvell/comphy/comphy-cp110.h 6b20ef2ea4fdeded083ed64a100d2e10cc8c4fdb - arm-trusted-firmware/drivers/marvell/comphy/phy-comphy-3700.c 4fc44238fa459de070b3ffae100986f736c5e3d2 - arm-trusted-firmware/drivers/marvell/comphy/phy-default-porting-layer.h 1ceb9ca7a78559ee70cb2833d391d99c2ccb3334 - arm-trusted-firmware/drivers/marvell/comphy/phy-comphy-common.h db0bb43d5c002bc3633403571c9e8c06da7c0ead - arm-trusted-firmware/drivers/marvell/comphy/phy-comphy-cp110.h 02f2c79a0efffc643c301848b83a26b232291cec - arm-trusted-firmware/drivers/marvell/uart/a3700_console.S 282cbabd8ee584e3d6c2657cd202c11bbbf31685 - arm-trusted-firmware/drivers/marvell/mc_trustzone/mc_trustzone.c 6426cc04f9e4ae36d19a6624130d17fd035ba491 - arm-trusted-firmware/drivers/marvell/mc_trustzone/mc_trustzone.h 5a1bf4459a810008901d22e77f2e66c2af4ca7f9 - arm-trusted-firmware/drivers/marvell/secure_dfx_access/dfx.h 12a1ccf32210f9e1106d8d27942f264ab96f58fd - arm-trusted-firmware/drivers/marvell/secure_dfx_access/armada_thermal.c e586fb95d55e301bd75a1db9d6ac7b843f45984f - arm-trusted-firmware/drivers/marvell/secure_dfx_access/misc_dfx.c 78d0bb21fe92f684f28119691c173b36006dbbb5 - arm-trusted-firmware/drivers/io/io_semihosting.c fe0286bc53aeb4cae686fb9d63d9ffe2283cf119 - arm-trusted-firmware/drivers/io/io_dummy.c 78ab979470824d9703736ca6da3735d7c11fcba1 - arm-trusted-firmware/drivers/io/io_mtd.c 88a6a7b48a8b3da04a2a2bb9d5bcb70f03c372d3 - arm-trusted-firmware/drivers/io/io_encrypted.c 858e3130488ef425faa5341098347a0cd446a49d - arm-trusted-firmware/drivers/io/io_memmap.c bb264060cf147f5fd4feae216d66ad8c9c66f891 - arm-trusted-firmware/drivers/io/io_fip.c a28c85766eedc583fd38c5f1cb94aa9d5caf8935 - arm-trusted-firmware/drivers/io/io_block.c 2975f82e852f74ac877b00bfa9bcaa8c3baec7e2 - arm-trusted-firmware/drivers/io/io_storage.c cf240f037fbcd65fb3db19fb6994d2f4aaaa52f9 - arm-trusted-firmware/drivers/ti/uart/aarch32/16550_console.S b98ff0dbd7f6535bc154869089df5f242b23f799 - arm-trusted-firmware/drivers/ti/uart/aarch64/16550_console.S 5dda361745c9b337192dcd67fc63865e04a3a8a5 - arm-trusted-firmware/drivers/allwinner/sunxi_rsb.c c841aaad58e92f728c90bb7cab1771d2578be18a - arm-trusted-firmware/drivers/allwinner/sunxi_msgbox.c 304398c75526a767b8b3caaeb5722e41955e9803 - arm-trusted-firmware/drivers/allwinner/axp/common.c f3f36bb92d56df7e9785cc98f6b13594df6404c0 - arm-trusted-firmware/drivers/allwinner/axp/axp803.c 956dadae6d826687fecfa1b522fd8b5c4fdfc764 - arm-trusted-firmware/drivers/allwinner/axp/axp805.c 3325b2a520df18fb8bd8859eafba82aa1c89eec1 - arm-trusted-firmware/drivers/rambus/trng_ip_76.c 1c897f5bd19b9a4c18e905afda282375cbf4f5ba - arm-trusted-firmware/drivers/arm/sp804/sp804_delay_timer.c ed924dc3ed7f91ecff8a2e441fa5152d9fe2b9de - arm-trusted-firmware/drivers/arm/tzc/tzc_common_private.h d0a784c19a578becbc821a36080372d78af9b3b5 - arm-trusted-firmware/drivers/arm/tzc/tzc380.c 0e845129705069d3fce0df742ab8d56a7966edbc - arm-trusted-firmware/drivers/arm/tzc/tzc_dmc620.c b2e58e1a761614ee8bb95e48797500fcd9f66c4c - arm-trusted-firmware/drivers/arm/tzc/tzc_dmc500.c 73c05b4fdb011d3783f2f3f3ed7285ca58a63cc9 - arm-trusted-firmware/drivers/arm/tzc/tzc400.c 59fdfb949b22174750e33899b9da3ea46b68cb55 - arm-trusted-firmware/drivers/arm/mhu/mhu_v2_x.c ee300c3d8a13beaaeab8e002f85252f3243c6196 - arm-trusted-firmware/drivers/arm/mhu/mhu_wrapper_v2_x.c 3d01d5ef8bb71e4cb7447ff707a12be97a6fdf8d - arm-trusted-firmware/drivers/arm/mhu/mhu_v2_x.h 91c557c46edc8be3bd2e4c2efcf9ef8693a9fc0e - arm-trusted-firmware/drivers/arm/pl011/aarch32/pl011_console.S c0c5af62081f2d6628a6de94cd6a9507723228e3 - arm-trusted-firmware/drivers/arm/pl011/aarch64/pl011_console.S 6dfee94cccd0efeaeda770f83e1d10227886d137 - arm-trusted-firmware/drivers/arm/css/mhu/css_mhu.c 4f259f1ca4437445346bfd338702c7c257c31470 - arm-trusted-firmware/drivers/arm/css/mhu/css_mhu_doorbell.c b81d931e597cde97768e39fdad4325133c31b76d - arm-trusted-firmware/drivers/arm/css/scmi/scmi_ap_core_proto.c e76c3b0b1252232e7854b8af9db8a9ce94192cd1 - arm-trusted-firmware/drivers/arm/css/scmi/scmi_pwr_dmn_proto.c 12e2ef4efff1bfd584d3424cee31bbcbaf0f9a1c - arm-trusted-firmware/drivers/arm/css/scmi/scmi_private.h 1530ff134d89ce18b2380b7d03828ec84c8eca25 - arm-trusted-firmware/drivers/arm/css/scmi/scmi_common.c 50defd7dfa4e38cf230f830fa7e03358ccfcdbb0 - arm-trusted-firmware/drivers/arm/css/scmi/scmi_sys_pwr_proto.c 13cf0f0a02adf3ae0f9e2bdbe493ba7c9b58ddf5 - arm-trusted-firmware/drivers/arm/css/scmi/vendor/scmi_sq.c e4a68362e5109d4e46f1d720d9b02c8fb20a88c1 - arm-trusted-firmware/drivers/arm/css/scmi/vendor/scmi_sq.h 9b45f1ebc9a189e59d1fdade91bde81f2ea110c0 - arm-trusted-firmware/drivers/arm/css/scpi/css_scpi.c 63385bff4d38a1fd8628c6ed6191b7faf316e32e - arm-trusted-firmware/drivers/arm/css/scp/css_pm_scmi.c 4faf8ddbac2e8bfc4ab77ba7365ff0c50187a2d4 - arm-trusted-firmware/drivers/arm/css/scp/css_sds.c 80686a47331e2b609be783462ef53eb0ad73279e - arm-trusted-firmware/drivers/arm/css/scp/css_pm_scpi.c 7aaa9f31ec7c9d36e48fb2d95a6b3895cbef43ae - arm-trusted-firmware/drivers/arm/css/scp/css_bom_bootloader.c 9fdd5749ba87bd5ded91306fd6826fa2cf990806 - arm-trusted-firmware/drivers/arm/css/sds/sds_private.h 595853f3864138408a5e5b51034dd366cc9a3b7a - arm-trusted-firmware/drivers/arm/css/sds/sds.c f55aeff6049754049ad1b23958094a7dd255200f - arm-trusted-firmware/drivers/arm/css/sds/aarch32/sds_helpers.S e609accbdf6501d2f83400b84b7690aaa2bca38a - arm-trusted-firmware/drivers/arm/css/sds/aarch64/sds_helpers.S 9697dd84615aa7c7da7ffe22eb0e3a38c6ace390 - arm-trusted-firmware/drivers/arm/sbsa/sbsa.c 3777989a45b625cf209fc89bcf8a91a468f52a3a - arm-trusted-firmware/drivers/arm/scu/scu.c df810ee9c134e5de1debb48a4c781c4035b51490 - arm-trusted-firmware/drivers/arm/smmu/smmu_v3.c 9cb6b217ac9499219fd1bb05530709e1ed53c3ff - arm-trusted-firmware/drivers/arm/ccn/ccn.c 79f4ef16ca7e0a07b86de03a9a04dcb9c6c3673d - arm-trusted-firmware/drivers/arm/ccn/ccn_private.h a9cab74a3aa9f59289ec4dac11558cb1e6e3c2a4 - arm-trusted-firmware/drivers/arm/cci/cci.c 31ef802ad00e05b63c669590dfaabdf50f6dc1c0 - arm-trusted-firmware/drivers/arm/rss/rss_comms.c 3ce50e410941317b749451e95df2de7ad4083ec0 - arm-trusted-firmware/drivers/arm/rss/rss_comms_protocol.h 23d3c56471d88bc7b73b5d90aca4edcb79ed99fd - arm-trusted-firmware/drivers/arm/rss/rss_comms_protocol.c d9298b0781d1c7c184b5f6cfbf9115b4c000d2ca - arm-trusted-firmware/drivers/arm/rss/rss_comms_protocol_embed.h cec2461c19054afc1ada016bd066dd8e45e5aa71 - arm-trusted-firmware/drivers/arm/rss/rss_comms_protocol_pointer_access.c c75d2dea4af643bd41e21e4cb3292256a011b37a - arm-trusted-firmware/drivers/arm/rss/rss_comms_protocol_pointer_access.h 714eb0bf069cd63f3650f5cc319cd7a87c126711 - arm-trusted-firmware/drivers/arm/rss/rss_comms_protocol_embed.c fcdbc7d1ba6dd59840b82ac787ebf67cf36fe4eb - arm-trusted-firmware/drivers/arm/sp805/sp805.c 960e4d083c1d4f31df54f443dbe23554889af0de - arm-trusted-firmware/drivers/arm/pl061/pl061_gpio.c 7ea86417141ac8cc3dbdaeef3d0e6ef1bc61fb86 - arm-trusted-firmware/drivers/arm/ethosn/ethosn_smc.c 668315548e4d6f930b744983a6542e01f81caae2 - arm-trusted-firmware/drivers/arm/fvp/fvp_pwrc.c db459127881b48c38d4a09029085afba2bb00f59 - arm-trusted-firmware/drivers/arm/dsu/ppu.c 64e24a32626429bd2dad6a02c91a123b79fe7528 - arm-trusted-firmware/drivers/arm/dcc/dcc_console.c 28b6eb0d5d5856997722ea707dd42c5ad7448dd1 - arm-trusted-firmware/drivers/arm/gic/common/gic_common_private.h 47db01b738865c987fa5dbb3656b6b1dab2df5d7 - arm-trusted-firmware/drivers/arm/gic/common/gic_common.c 4a9feb6bac69eae58a96dbe9cf60951196201404 - arm-trusted-firmware/drivers/arm/gic/v2/gicv2_main.c 20000ccb435ae8423c5a2294ecb47fd7961e90f2 - arm-trusted-firmware/drivers/arm/gic/v2/gicv2_helpers.c 0325f0421798955c9df7f963bd6f917152f3f9fc - arm-trusted-firmware/drivers/arm/gic/v2/gicdv2_helpers.c 8f83171e122be92a8d5e4b0c5ecb35e4918ead83 - arm-trusted-firmware/drivers/arm/gic/v2/gicv2_private.h 16963041f34d65707d92f6e089edd696458ab62f - arm-trusted-firmware/drivers/arm/gic/v3/gic600ae_fmu_helpers.c 73bb04bd3b4d9fbaec23c129c93b2e89e276c7d5 - arm-trusted-firmware/drivers/arm/gic/v3/gicrv3_helpers.c 0cdfd59744b1db36c123258d6ed80a21b369e0cc - arm-trusted-firmware/drivers/arm/gic/v3/arm_gicv3_common.c 01283b5e981a95cea7219519d7db8300d1924af5 - arm-trusted-firmware/drivers/arm/gic/v3/gic600_multichip_private.h 938bac5f799ce22772ba636bb4ceeca512eccba4 - arm-trusted-firmware/drivers/arm/gic/v3/gicv3_helpers.c 736cd9f59b4b2ae65ddc093bd132bea8ace60805 - arm-trusted-firmware/drivers/arm/gic/v3/gicdv3_helpers.c 7737340fec1ab656ef4ac2544dd9484007923edc - arm-trusted-firmware/drivers/arm/gic/v3/gicv3_private.h 77f2a04a1cb74cca5c315472a5453a7848d82ce7 - arm-trusted-firmware/drivers/arm/gic/v3/gic600ae_fmu.c fbf3df49d7768247f3e146a5075f4c15888ca564 - arm-trusted-firmware/drivers/arm/gic/v3/gicv3_main.c 109d15a64f03156aa3df55d84454e92488712f73 - arm-trusted-firmware/drivers/arm/gic/v3/gic600_multichip.c 97201a04362eb764f203b4fb0835f8c0ca01af21 - arm-trusted-firmware/drivers/arm/gic/v3/gic-x00.c ecd654f25b5590f6fd4dfb3c349577da03a78337 - arm-trusted-firmware/drivers/rpi3/sdhost/rpi3_sdhost.c 5506b6895fb8d1c468b2bcaeb55a18fba8ecdcff - arm-trusted-firmware/drivers/rpi3/rng/rpi3_rng.c 4ea1ee0ec57ab6b190434f6a4d1e2724559db181 - arm-trusted-firmware/drivers/rpi3/gpio/rpi3_gpio.c 1529e10e42582df4a41e7632598e85d97dd59ebb - arm-trusted-firmware/drivers/rpi3/mailbox/rpi3_mbox.c 5bf3028d91229a2bab7d9be2fbf3db5b63dbdac5 - arm-trusted-firmware/drivers/cfi/v2m/v2m_flash.c ba3873513a76a74ceff9f6818187870191d1faba - arm-trusted-firmware/drivers/renesas/rcar/cpld/ulcb_cpld.h c2b1735bd5896fe759c99cc8b22c392af5bb841b - arm-trusted-firmware/drivers/renesas/rcar/cpld/ulcb_cpld.c 3ae8c8947fe42e322d70fb7903ada181bfd006ed - arm-trusted-firmware/drivers/renesas/rcar/pfc/pfc_init.c 6fb897befbc4164b71d8975b2d5322b9e77412b4 - arm-trusted-firmware/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c 3802b683cd17e49eba932611e33205446291cde4 - arm-trusted-firmware/drivers/renesas/rcar/pfc/M3/pfc_init_m3.h c7dfaadbc4d96d1fceadc4fae5536b1e1a9cdd59 - arm-trusted-firmware/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c c248864592a61213518c8881be85e4f65fe0a3a2 - arm-trusted-firmware/drivers/renesas/rcar/pfc/E3/pfc_init_e3.h a7f9c2cb5010e2bfe1f501830a449d314d447ce7 - arm-trusted-firmware/drivers/renesas/rcar/pfc/D3/pfc_init_d3.h 6465a6a55c524b8ffb1dca351757b9d96e79d203 - arm-trusted-firmware/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c b9d9644305cbbf1e06e176a46903dd18819761a4 - arm-trusted-firmware/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.h cc2f31ac87f68592bc44f9d3435c79d99e7dc0e6 - arm-trusted-firmware/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c 8472797f3f7c7a334dd21719d4dd718c5df01e47 - arm-trusted-firmware/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.h 7a112959b420ec60382c2d5688ddced8ca0affd4 - arm-trusted-firmware/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c 5eda21c234b108bb6ed5b65d5e58825ec9ac0210 - arm-trusted-firmware/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.h 83dad15a244674be1d30dc0200428aa0e82090e6 - arm-trusted-firmware/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c ed9b151f951387e31b4a9fc5a26f0d4621beaf13 - arm-trusted-firmware/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c 1a2dd6951973faf90ec734331605c3fb336bde9f - arm-trusted-firmware/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.h cb0d0e4e929b276e850cc30884ddfd8846a9048f - arm-trusted-firmware/drivers/renesas/rcar/qos/qos_common.h 50775f0e3315375d2b392a52b57df2e19834d985 - arm-trusted-firmware/drivers/renesas/rcar/qos/qos_init.h bab2ef59fc4f4088c90466ebb4823889a1bf3996 - arm-trusted-firmware/drivers/renesas/rcar/qos/qos_init.c 7e2114420402542982a251fc6b54152f32b0dd88 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c 6b699b1443429c5428b8a7056804ed3da10f02f8 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h 2717b8ac46d4da69ba6b99a7f25097f9e314aad3 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h 8aa68f57355243a72231c3848caec899565cf5da - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v11.h 758dc7396c31d1186836e5ed6c7cafd0a678b4f6 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.h bf20ed2160ab9535cba30cc680a7bf881b5a442a - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h 7cbcad70fd46dc5761bb14b31f104d6806752af8 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt195.h a6126e66f35f584f38379a6ee5529fed08edf8d8 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h 77f8e84524f8a31cd4e5261eca8974eec4bd131a - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h 8c12bb78bc33032ca8926351b3eedbe5b2b4c81b - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c 2a066b2fcd7583651082fa57bbf12dfe4352326f - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v10_mstat.h ec016158b5c3b5502240e5835181cf7929e6fb5e - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v10.h 10f2fc91f336438e4f2073ea1a665d5d67fb79c7 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c a3a502f90241a6c8f8be7ed9af2e0b6cfe9e59e5 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_qoswt390.h f1b2a6505d48a1a6566f88c1e80b4f27cb09896e - arm-trusted-firmware/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h 6dea13df81dd5a2913039ff42dcb9216eb922586 - arm-trusted-firmware/drivers/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h 48f7ee0d258f661040d23d898a98d0bc9c066613 - arm-trusted-firmware/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.h 81d4efe56b1d9f4c44c942700d01a9ede1677bae - arm-trusted-firmware/drivers/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h 114cb09f888b76f0b1356fb126a483be754d2cd6 - arm-trusted-firmware/drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c b8ba25ef62d360d72dd17d26934062bc0eeea376 - arm-trusted-firmware/drivers/renesas/rcar/qos/D3/qos_init_d3_mstat.h fb1b1122066b12b184582d53d643246b1a414b3b - arm-trusted-firmware/drivers/renesas/rcar/qos/D3/qos_init_d3.c c2f5bcbfd3751341e871e36cd4d2f278b2a4150d - arm-trusted-firmware/drivers/renesas/rcar/qos/D3/qos_init_d3.h d50c2a6a6c4e4910f4fabd7c774ce1986b97ea19 - arm-trusted-firmware/drivers/renesas/rcar/qos/V3M/qos_init_v3m.c 70405034a321bd4ced206115508ab438f2f536f6 - arm-trusted-firmware/drivers/renesas/rcar/qos/V3M/qos_init_v3m.h 21ada158d24d4473b1e20f73c499f4d5600e3c8b - arm-trusted-firmware/drivers/renesas/rcar/qos/V3M/qos_init_v3m_mstat.h f5fd4a9a5d50b214bc6ebdebed3c35ae0f1f2be4 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h 6ea58175e376d869ac3c2a4f103d934df3c2c465 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h 8b5287985d180436c31df99d29c586fa8ddf0f26 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c 59c0f7639b01b8af843d8142eb013348e6a1ba18 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h 7329eefcfc343e2cafffcbc3a208b34789e57968 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.h 7c805660400d6f609148f8124439843b39232355 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c 504bd76520d259ea03e8b93380c763a3c17ffeb0 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h 23507b41fbfc9c3a39c4c3f5daf7562d67d10b1b - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h 8eea8028ec6b2cd4e6e1c5e0a8d8fd9af01ff4fd - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h f0db0106cc97b359f7a0ab316784658b79e9d544 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h 12e645da3e7fc81893eb36796412a928fc06e57e - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c b7890473a9576eca8081825037d037349512add5 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c a6934a3af85414d49cca5e5d99e162bbe9ca133b - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v10.h 630b48fd35a697ed4d1daa03bfc67d0d299a2776 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.h 824a3717d01b009cea509c61015e64d1722fc212 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v10_mstat.h 811eb1fecd60de207e7c92a5986acb80e7ecf0f3 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h bd60292a364659d7f11eeecac384213969357c04 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h 8dbbe234d937dcc1acc85648ecf831824fb5fa48 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c dae17d610957cce3799fa9c9946c0196c67d46ac - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v11_mstat.h bc682493eeddc9cec3b24b5dd37418a00e0c064a - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h 7131d3227d06785258892fe7a42df3c91cc8c9f9 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v20.h 700940ac5d64f4902064fbf6670e6e59150d9fd0 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v30.h 8623a6e816d06c37ce20ab1b6e410fc23c052d43 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h f8c08f7eee854de735ce3c60a3e23d3f74fd73f8 - arm-trusted-firmware/drivers/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h 60944cd086bb0354e4747ae185b5149ae3f85f72 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.h aa7f8d7b49fdee6efbfc48acf8e8bddb01fd52a4 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h 96354da81a56cb6373ff756124b8eee42409bfca - arm-trusted-firmware/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h 4c577e5e3e00506da4ab89990b8dae561786e20a - arm-trusted-firmware/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h 3d6b988f34914a47bf479526f1f10849a2ae3ae5 - arm-trusted-firmware/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c 2bb5c4f7c8795b5aeecf3a8997f515c4890514ae - arm-trusted-firmware/drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h cf8b9626df3b3f81ae4674acc1f379aaf9eea1b5 - arm-trusted-firmware/drivers/renesas/rcar/board/board.c ef114d85e930b49c92bef6398031e37cb6afcbb3 - arm-trusted-firmware/drivers/renesas/rcar/board/board.h 96023687d119cdc2a88f0f96847b71070be44d0e - arm-trusted-firmware/drivers/renesas/common/common.c eb5eaa562bc901bbcea6e5e722e629a4ffe14fa3 - arm-trusted-firmware/drivers/renesas/common/ddr_regs.h b31c95edffddbecf9d51e7ba6d57f59b07381718 - arm-trusted-firmware/drivers/renesas/common/qos_reg.h d4b40e69b2bea69f35d8d12ed25d623c4bafc89e - arm-trusted-firmware/drivers/renesas/common/pfc_regs.h d18f211fb0f471b7b72797133ccf3a89ff3fe561 - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_mount.c 1f0175831d01e9a83091abf339b764707fa15732 - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_interrupt.c 1806c4fed1e8009245193be345f42a0bc99a88ff - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_cmd.c ae1066faf4581bdf2b74fc79c6880b4541c50262 - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_hal.h 9c78d4764ec4942f586af7e70fa2906b79718e72 - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_def.h e3d0fe455add19648ab1dab17abbf8a036851187 - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_read.c 53d888462033b6fd9f510352b7ef5a997db98215 - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_std.h b95edfb86992c01b146085a6a3a6fa260f62cfb1 - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_config.h 7526f3b1661670d99bae978d76b826697f8eafcc - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_registers.h da6c00a918a45fb21f34a94a1153a619126f856e - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_init.c e38e56acce60e8f8ba79bf52ebdccbfbb84e60e7 - arm-trusted-firmware/drivers/renesas/common/emmc/emmc_utility.c 3567bb0ce5e977a1fe4ee5a8fed4db8dc67ccca3 - arm-trusted-firmware/drivers/renesas/common/ddr/dram_sub_func.h f6092db4bdf15b55332ebf36fb13af42ee1b8f8e - arm-trusted-firmware/drivers/renesas/common/ddr/dram_sub_func.c bbe9ec354aa9a66731a4a68b1214e7c88433e78e - arm-trusted-firmware/drivers/renesas/common/ddr/boot_init_dram.h 55a51a3127d0a24e084fc5ad73c0ddc5d5b2fe3b - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_a/boot_init_dram_regdef.h 24c58c71c66617770ef83cfba554a31128de8f35 - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c b5212a79f0a8c1abb0c5088b5730968747253bd9 - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c f5798c0927729a362f779e583438e52a2da51faf - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c d8448100b460ddc591a2eefae6d2d0abecab166a - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h b014a41cf8b77ed434dc0aaeae7efd1a154065c4 - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/ddr_regdef.h 1f8f7c4a456ce374f80860dcefeb3a1eed7e1b7d - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h 178140849c7796c20b8a14ef9af086d4ffb485f1 - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h e40feff18e0868d48c4bdcc23024fa824eb612ad - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h 56a16c8b12428935f7d194f7bdbda33ebc432e4f - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3.h fe75f352b6a7e1643f0857f578e85a4c301d504f - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c 94ab11fdbe4c8a942cb23f6604e8a013e0c6c083 - arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c ba0424f1fb02f541d26148c808ee8576203fae19 - arm-trusted-firmware/drivers/renesas/common/dma/dma_driver.c 81389d507ab4f6c15c8302b9d4a550e929350170 - arm-trusted-firmware/drivers/renesas/common/iic_dvfs/iic_dvfs.h 197394f4b9c3387bbbe8ade40aed6fd5ba67cd49 - arm-trusted-firmware/drivers/renesas/common/iic_dvfs/iic_dvfs.c c11df9b69a5d8144823fe6b09c8aee8c6dac3579 - arm-trusted-firmware/drivers/renesas/common/pwrc/call_sram.S 11290dbdcaf0fc67e9947d59e3177ac503f1276c - arm-trusted-firmware/drivers/renesas/common/pwrc/pwrc.c 6173062885150750f1c102edb35796e50d6a012a - arm-trusted-firmware/drivers/renesas/common/pwrc/pwrc.h d954a56fdaa915b42433e7f02b933ff5a7f4d553 - arm-trusted-firmware/drivers/renesas/common/io/io_memdrv.h 7c0cd66835bf24e2086572d390e9e42847b2cc7c - arm-trusted-firmware/drivers/renesas/common/io/io_rcar.h 94592c6b00d8f46906214144913018912da2cdb1 - arm-trusted-firmware/drivers/renesas/common/io/io_emmcdrv.h 4c9c3edfff804648e78fdb6173511fedc8d655c9 - arm-trusted-firmware/drivers/renesas/common/io/io_rcar.c cc69cc1cdbf38f685bfb8c4e843841fc12c17072 - arm-trusted-firmware/drivers/renesas/common/io/io_private.h 7e6776a062962247d7356aa2a4e3db30e8ec9a35 - arm-trusted-firmware/drivers/renesas/common/io/io_common.h ff8a273a7c0157436d3d58824bb0822c1e4c8880 - arm-trusted-firmware/drivers/renesas/common/io/io_emmcdrv.c 2a9a321a7d2d3f302f63914ea61c0b24ef77ae46 - arm-trusted-firmware/drivers/renesas/common/io/io_memdrv.c 04d76f4dff98e3290cc3b56689eea7eae6973401 - arm-trusted-firmware/drivers/renesas/common/avs/avs_driver.h f6c548f6ac120c9eae0551d5ca111a654a28e241 - arm-trusted-firmware/drivers/renesas/common/avs/avs_driver.c db6311bc705a8c1d60a616425947adcee84d1063 - arm-trusted-firmware/drivers/renesas/common/delay/micro_delay.h 724917ae7e24d07722880d4b74d6a9730336be06 - arm-trusted-firmware/drivers/renesas/common/delay/micro_delay.c 5737620466366563b17443ac716f582a4a0e1e8b - arm-trusted-firmware/drivers/renesas/common/rpc/rpc_registers.h 23d0235cda981605fc638d9031316ff71003ea9f - arm-trusted-firmware/drivers/renesas/common/rpc/rpc_driver.c 648595ebf99d157ff5bec437919b34a18258b411 - arm-trusted-firmware/drivers/renesas/common/scif/scif.S f81a020bdd63ac732719bf014ffb749bc0f35bba - arm-trusted-firmware/drivers/renesas/common/console/rcar_printf.h e285ce8fb65a4579da74f1406d12000d292f45ad - arm-trusted-firmware/drivers/renesas/common/console/rcar_printf.c 26bba8a723b7f85d907e8da853e41cb0ec1bc46c - arm-trusted-firmware/drivers/renesas/common/console/rcar_console.S fe518460e8298941fd3ff47df2330afba56085ca - arm-trusted-firmware/drivers/renesas/common/rom/rom_api.c 08b9d46b2389e6316b27218e1e80071e3891915b - arm-trusted-firmware/drivers/renesas/common/rom/rom_api.h 8e9c2ed157c641c0bec372759c5f0d1a29495392 - arm-trusted-firmware/drivers/renesas/common/watchdog/swdt.c 3a2172abc0cd0c826ca5c1f958e47c616e2d0c2c - arm-trusted-firmware/drivers/renesas/common/auth/auth_mod.c 45854b76c28a405b83a3ad2f7975038a6a8a34c1 - arm-trusted-firmware/drivers/renesas/rzg/pfc/pfc_init.c fb75fabcb7a5cccd23dafcb83996362d131b28e4 - arm-trusted-firmware/drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c 3e16dde8ddd77df4368ed97df8dedfcd363f2195 - arm-trusted-firmware/drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.h 08bed1ad3f35993a6b63c3a553c0cd1f817cdf72 - arm-trusted-firmware/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h 313d480f7fd9b09de41195d3fe75df7e06b8fad2 - arm-trusted-firmware/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c fa65175525fa82bac340b43f6d95f68574a6cd59 - arm-trusted-firmware/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h 987d099de106542df3c8adb7613b27edcfd5cb76 - arm-trusted-firmware/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c 9850cfe7fffb94712b5526ba4dd947a9cec6efbf - arm-trusted-firmware/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c 42cec83a589b1e8282a06dc496c09fa4d8019bdf - arm-trusted-firmware/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h 4186c27c3850565f08118234f39f3224a0094fb6 - arm-trusted-firmware/drivers/renesas/rzg/qos/qos_common.h 2802b6fb340525ddb96baca00341a6a25f703c74 - arm-trusted-firmware/drivers/renesas/rzg/qos/qos_init.h fa11d997720f3e8e38a41e393a485385f56a4981 - arm-trusted-firmware/drivers/renesas/rzg/qos/qos_init.c 7262dc7de38f8216be32a2cf973c4077da6a5ced - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.h 49c7e8143b952aa89509efb296f2a3d848f1fcf1 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.h 17c66fa0e8ef76563d00547c6c281d4fcd025dbf - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10_mstat.h 8146506bb0d47e4499b692d8a0b0d168c697db9a - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c d1c7d38c66ff34e537261485132cb0beb3ab4765 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11_mstat195.h ba3202740e2551524bc86abc295cc82374fea770 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30_mstat195.h 5cf260b6fef6d9a6c0ddbe6c45bed9d54daf027e - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c 4120c27434066995e75487d1311e78e2dcf57cb3 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c 4fc3b8212dd33e6a33a9bbf4b96d0ffdb7032083 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30_qoswt390.h ae6bc783ddb0cb6feec22e234a5383965ad75a8b - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.h e074216ecbdf97f24cb3e12cc7f5d8e5c99721b5 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11_qoswt390.h c9bbbceaf55fd9cdcf0943b427f8b302c902199f - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30_qoswt195.h 3ebe3831af51ff6dd31f04c19ed726ea47d12ffb - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11_qoswt195.h 1ebeec74f28d94d33ad88f9e3cb8abeb2ff4462b - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11_mstat390.h 046e1d3b18c291d99e7f1f95658f5a6bb9f7c207 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30_mstat390.h a084e9fcbfdc195d063eee7f1561a5b311238aa2 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c 05c9d8b400726b0d87a72783f40f17a2a061c31b - arm-trusted-firmware/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h 6a2add07f71f904a80881847adbb4576860c245d - arm-trusted-firmware/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h 0d2a4685c4bd34d6ec121270bc38ec212c7b1e0a - arm-trusted-firmware/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h 2e4f2532cb1b9aee27f82677a76fc8598ae3e720 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h 6bfed6bf0d3eb45780762fbb929d5d57eaeaaedd - arm-trusted-firmware/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h 635fa9d52596ee34cf2cbf85617657684fb653c1 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h d0a732f21ab78828c622303f2eb7f2ab8e85c92a - arm-trusted-firmware/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h d1016ddc5354d7e63a3ef654ae6899c8c078ce00 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h 98bd2a7be1d0dcdf1cc534ac4dfa0adf7b3bd752 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c 80605fd39dfaf3536b1da46e80b450127a5ac723 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c 3ca890e94b8943ef7719c09f20c3a71ad9e60295 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h 33416277d7d82e170d6f1d7ef205870c003c8aff - arm-trusted-firmware/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h 282efe9d196e496f3be41e3be701e9dc02c1bfc5 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h 330b138c5e24e14484fbdcc38db468c06168918a - arm-trusted-firmware/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h 7c37eb45f9f11ee9f370e775f741dd1075944a69 - arm-trusted-firmware/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h fe1e1e2a68a2409c85008f78bb7f4048be6dc1c9 - arm-trusted-firmware/drivers/renesas/rzg/board/board.c 8ae500671f7227739bb3b389ee74418bae4974ee - arm-trusted-firmware/drivers/renesas/rzg/board/board.h d168b6d956520878eedb32253c74bf920e673e3c - arm-trusted-firmware/drivers/mtd/nand/core.c 47003ec4d5650ecd811ae9fe4404621c369f61c6 - arm-trusted-firmware/drivers/mtd/nand/raw_nand.c 122bf5d15d1cdbcad5bee82566c57049e3fc5bb5 - arm-trusted-firmware/drivers/mtd/nand/spi_nand.c 46c3bb0a303498f1a79fd2bc48b1becffddbfd71 - arm-trusted-firmware/drivers/mtd/spi-mem/spi_mem.c eefd56420faeb9d836077b23eea175eb7e022871 - arm-trusted-firmware/drivers/mtd/nor/spi_nor.c 583e038383081fb802062fbb6ad8c3e3060afba4 - arm-trusted-firmware/drivers/amlogic/crypto/sha_dma.c 4e52ca94a347a31cef85fc1cbbd480490ff065b1 - arm-trusted-firmware/drivers/amlogic/console/aarch64/meson_console.S 2c62b0520671d8adb8f7b250aa4e12e75f2ce112 - arm-trusted-firmware/drivers/console/multi_console.c b837201998c7093cf24c9131e39734b99ab455be - arm-trusted-firmware/drivers/console/aarch32/skeleton_console.S 48cb55cb2ee35cd09c7a0759acecc0e5facfe576 - arm-trusted-firmware/drivers/console/aarch64/skeleton_console.S 4d4a54387d150a350256330d8c15f4b4c7759b24 - arm-trusted-firmware/drivers/mmc/mmc.c 1d31a2492e42b2087d68ef756a91274f671987c7 - arm-trusted-firmware/drivers/nxp/dcfg/dcfg.c 59117917987eb057fe4003d4da4c3125ea76dbc9 - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/ddr.c eaefee9029f7ccfd854a5813aae54ad816808645 - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/utility.c fed7a4d64f892002dd30f1e1bf50d5fbf537281d - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/dimm.c e083ea048179544e9c8e52f7a48d7c315f03a475 - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/README.odt 442cb1d00ad113cbdc5ce076abc56124655dbe2d - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/regs.c 33929846548a6a6731c652caf6050b64dea2f9d7 - arm-trusted-firmware/drivers/nxp/ddr/nxp-ddr/ddrc.c 7c05bf68f35c9cbbeb751db67f075cc1bc864b72 - arm-trusted-firmware/drivers/nxp/ddr/phy-gen2/messages.h 615d63c64fe8bc4cb7cca7eceb4b1079c1f903a0 - arm-trusted-firmware/drivers/nxp/ddr/phy-gen2/phy.c 9c36d85b72ea62f1b3e6d8df34efe02d50c468ca - arm-trusted-firmware/drivers/nxp/ddr/phy-gen2/pie.h aac92f8b51eb5a99b8c6c1b861b65d8ed56c92b9 - arm-trusted-firmware/drivers/nxp/ddr/phy-gen2/csr.h f222d8d69c33519c4908bafaaeb6a2482f35bb20 - arm-trusted-firmware/drivers/nxp/ddr/phy-gen2/phy.h ac55bbcc1387d5092bdce1d236686694d82f2a87 - arm-trusted-firmware/drivers/nxp/ddr/phy-gen2/ddr4fw.h 8ced20b50814e640a734b45571534428a03235aa - arm-trusted-firmware/drivers/nxp/ddr/phy-gen2/input.h 6ba34d8cf6a1e66a6b8781b632305c8192f8c47f - arm-trusted-firmware/drivers/nxp/ddr/phy-gen1/phy.c d9b4015568e26bddf900e57b2034588011dc76fe - arm-trusted-firmware/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.c 7e7c03a074969dc0547afeb5dbe289ae008dae93 - arm-trusted-firmware/drivers/nxp/qspi/qspi.c bf7712fb75e6373abf6791b46d9a4563fd00feb7 - arm-trusted-firmware/drivers/nxp/timer/nxp_timer.c 1c9fa968ab5e023d06dcdbe0d3d12847d4e13273 - arm-trusted-firmware/drivers/nxp/pmu/pmu.c 73a87390ee3b46e2b5587087457d8a10a6f4cd35 - arm-trusted-firmware/drivers/nxp/tzc/plat_tzc400.c 06049b8071d1258dcc7829e02727d935c561fa1a - arm-trusted-firmware/drivers/nxp/tzc/plat_tzc380.c f29d54b17cb5dd1f602641d092227c883cb6a57b - arm-trusted-firmware/drivers/nxp/csu/csu.c d354d19d9f42611b3ad0f293660bac71ee3a801c - arm-trusted-firmware/drivers/nxp/flexspi/nor/flexspi_nor.h 0c3739bdd3d04953083299f803b7c30e40e3fa93 - arm-trusted-firmware/drivers/nxp/flexspi/nor/fspi.h af21526870ded933cf4e5455fdd2935a82cea61b - arm-trusted-firmware/drivers/nxp/flexspi/nor/flexspi_nor.c ce75912d66d9d45c7fb5514c2d883363346b1a48 - arm-trusted-firmware/drivers/nxp/flexspi/nor/fspi.c 396f26a188a6fb1077b280cdc459ee52ac4dec89 - arm-trusted-firmware/drivers/nxp/flexspi/nor/test_fspi.c 3a182ddb4f6fa33eaf8b5ae0c60f6bdf113f4fcc - arm-trusted-firmware/drivers/nxp/i2c/i2c.c 5579fdab0db3121aceafcaf39eab316e0253aee3 - arm-trusted-firmware/drivers/nxp/sec_mon/snvs.c c7adb94bca0f7e2a86394a503007aacd278de299 - arm-trusted-firmware/drivers/nxp/ifc/nand/ifc_nand.c 3976af866b0f1353ade3d95b9d4ef92a7a2169ea - arm-trusted-firmware/drivers/nxp/ifc/nand/ifc.h 85860d4c7284e5f15ce31d18787f687d6bde61b8 - arm-trusted-firmware/drivers/nxp/ifc/nor/ifc_nor.c 904d53ac1f2e9c98f1e176eae19be267e985db33 - arm-trusted-firmware/drivers/nxp/sfp/fuse_prov.c e87ea077dcc89cfad504b38c454094873eb4bbae - arm-trusted-firmware/drivers/nxp/sfp/sfp.c bb9ccbfadb1dba83a0035f9bf7b3d22a48fa01ff - arm-trusted-firmware/drivers/nxp/crypto/caam/src/sec_jr_driver.c ba408ad853e9ef0e53ce8319419a8b3d8a3da7ed - arm-trusted-firmware/drivers/nxp/crypto/caam/src/jobdesc.c eeaa299335bd10e0531ff65d6a24c6a4da294057 - arm-trusted-firmware/drivers/nxp/crypto/caam/src/caam.c 32d20982227d5346d95e069f256ec3556d52ecfe - arm-trusted-firmware/drivers/nxp/crypto/caam/src/rng.c d4cf1b07b3a081078c4e7da1e354adc42f41f7ca - arm-trusted-firmware/drivers/nxp/crypto/caam/src/sec_hw_specific.c e4343fd48fd3beed200fd430ec2f84482e7171bf - arm-trusted-firmware/drivers/nxp/crypto/caam/src/hw_key_blob.c 02475a8e210c6615aa5138943337551fc8b9087f - arm-trusted-firmware/drivers/nxp/crypto/caam/src/auth/hash.c eb5515126eb5fa4bef2f7976e79e3f9fd0944afa - arm-trusted-firmware/drivers/nxp/crypto/caam/src/auth/rsa.c ff23fd02b2c8ce84423f099d2b1bea12faf82aec - arm-trusted-firmware/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c f15b111b5f8ec4a947c36b642e6c6331bb5331a4 - arm-trusted-firmware/drivers/nxp/console/console_pl011.c 5128d83df7b28a2a4bd817b834e17b74206a84d7 - arm-trusted-firmware/drivers/nxp/console/16550_console.S d3e9bd0226d74dffd59af6ef1c8f029ca195db90 - arm-trusted-firmware/drivers/nxp/console/console_16550.c 45cce82acdd1f75c2e31f56de0a27738ec712b09 - arm-trusted-firmware/drivers/nxp/gpio/nxp_gpio.c 7da82df0c542d1d8ae8e69affe9e30ba233590a2 - arm-trusted-firmware/drivers/nxp/sd/sd_mmc.c cbb35d75dea21db6209d5ab41ce216af0acbd5f3 - arm-trusted-firmware/drivers/nxp/gic/ls_gicv2.c a8b2be0d9781815f941f3b5c54c06d66869ebbb8 - arm-trusted-firmware/drivers/nxp/gic/ls_gicv3.c fa805a963aca474eb7b99d376fc23bf898fe4457 - arm-trusted-firmware/drivers/nxp/interconnect/ls_ccn.c a4736e2e943ff2c95ee55ab5550d95dbf4e9fae5 - arm-trusted-firmware/drivers/nxp/interconnect/ls_cci.c 5a7943b124da3fea7995adb004eff6a0b928e921 - arm-trusted-firmware/drivers/nxp/auth/tbbr/tbbr_cot.c dd7d454c97e1855bb1c228cacfecb6238f4e487d - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3 753107ce7c270d602a0018c1cabb0ef8e7d3c54a - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_blx_ch3 e9bddb61157fc79a6db73771f3abc44b0fa2180e - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3_2 9489f5c75aa894fc166bb99b848883d0413170cb - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3_2 aaaf596468de0e2b0f1fd9df798408ccae3ec67c - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/cot.c 9b849f025149e6cf51b2500c8f70b38703ed5078 - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_blx_ch2 58bff9b3422ffad20520362a80a6f322da632da3 - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch2 bc6fe6b33a974e9a9e2ae522e3ac00b9f7ff4967 - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3 cb8400c786b03ab4685825c49454f7915622e629 - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/plat_img_parser.c 8b7ec36599206f1c121cf2a9565bc043b6049dba - arm-trusted-firmware/drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c d53b18f9aba437cc5d23117338ddac6edd9ba447 - arm-trusted-firmware/drivers/clk/clk.c 9b9a1876a8dd35bdd34baeedd3e531617f4b2e03 - arm-trusted-firmware/drivers/brcm/iproc_gpio.c 2f55d6018c61491a206aef1e089af2001db52b87 - arm-trusted-firmware/drivers/brcm/rng.c e8c6d05d166788f91925b45e27853f92f98251e5 - arm-trusted-firmware/drivers/brcm/scp.c 490663a4660be758e46f4878a43d7cb947b072e0 - arm-trusted-firmware/drivers/brcm/spi_sf.c df0910b2680c7694f0b75737fda7682a8712fb64 - arm-trusted-firmware/drivers/brcm/spi_flash.c 340b2a1703f14c42abdade167ac06919ec7deed5 - arm-trusted-firmware/drivers/brcm/chimp.c 99056505e9afb98d0bf6b55cbc9c64814734d610 - arm-trusted-firmware/drivers/brcm/sotp.c 9156a544c31c11073920be56fe54eb346a8b018b - arm-trusted-firmware/drivers/brcm/ocotp.c d89024f769cfa2a2d90ab6fb83691b494227d848 - arm-trusted-firmware/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.c a70c96d7324a040b39217a657625b8b369ed65f9 - arm-trusted-firmware/drivers/brcm/emmc/emmc_csl_sdcmd.c f9de2aeddc61d9a8b63a2bb3d10edd5e5459ac61 - arm-trusted-firmware/drivers/brcm/emmc/emmc_chal_sd.c 1e16b849ee30029570c17198cc65dd8c232fbd53 - arm-trusted-firmware/drivers/brcm/emmc/emmc_csl_sdcard.c c9c8847417d95e3ba03ff5c005edbe8a088cee14 - arm-trusted-firmware/drivers/brcm/mdio/mdio.c 26f0937fbff1f7b2effe7d035d4e6d2c2a9c463f - arm-trusted-firmware/drivers/brcm/i2c/i2c.c 653b6a961a19436e1cdba80c2b3b153c1d89a954 - arm-trusted-firmware/drivers/brcm/spi/iproc_qspi.c 2dc1c9032a1e64aa390c69bcdf0a42359e402b5a - arm-trusted-firmware/drivers/brcm/spi/iproc_spi.c de63fe21caac7ce499c3a244965fca77766a1d19 - arm-trusted-firmware/drivers/brcm/spi/iproc_qspi.h ce21f868c36b01e16d2dde4ee71bc03079ea8aea - arm-trusted-firmware/drivers/ufs/ufs.c 0d32873988a7299902bc11961218f9034c494f5b - arm-trusted-firmware/drivers/delay_timer/generic_delay_timer.c a5328f6dfd065a9ddc6acad1d5ea28176f33e623 - arm-trusted-firmware/drivers/delay_timer/delay_timer.c 0fc051c6d2c2e54cfe39b37cf1a1f85f883f31e3 - arm-trusted-firmware/drivers/usb/usb_device.c 627856de3e6c6e4ff2ba2bf3dc3803a13f08d1bb - arm-trusted-firmware/drivers/gpio/gpio.c d45d152334200ea2acdee930619eff5f1fbbfb5a - arm-trusted-firmware/drivers/st/ddr/stm32mp1_ddr.c f5e59973fc84a601316882610f6aa00a70ec8e1f - arm-trusted-firmware/drivers/st/ddr/stm32mp_ram.c 5ed9e1be8f844737db535ecd2e049e7d820af601 - arm-trusted-firmware/drivers/st/ddr/stm32mp_ddr_test.c 4a37a23560ebb26a66cba83a6a77aafee65a783a - arm-trusted-firmware/drivers/st/ddr/stm32mp_ddr.c 9e30ea137b7c1d34dfae32a3c5180396f6fa8bb1 - arm-trusted-firmware/drivers/st/ddr/stm32mp1_ram.c 88fb79719982f0a2687d7f693109e940e3cdba9f - arm-trusted-firmware/drivers/st/ddr/stm32mp1_ddr_helpers.c 6b50346722811da8d96bca6f539f0d5e772d467e - arm-trusted-firmware/drivers/st/reset/stm32mp1_reset.c 3115ec9f675484992db63c431789119715bababf - arm-trusted-firmware/drivers/st/etzpc/etzpc.c 9d7512560e4e1f8767fd18a115db9ee7ff100448 - arm-trusted-firmware/drivers/st/i2c/stm32_i2c.c baededfb86b8f337d27173f84b9cc1bac0556f62 - arm-trusted-firmware/drivers/st/io/io_mmc.c 42561883ec1c33fa7b8c4134042881d8af161697 - arm-trusted-firmware/drivers/st/uart/stm32_uart.c 04e6cbb0cd577fd8a0a84b3317a1457713b09021 - arm-trusted-firmware/drivers/st/uart/aarch32/stm32_console.S 7cd712709ee54122f0bf0cc5f0eff50166a1a8e7 - arm-trusted-firmware/drivers/st/spi/stm32_qspi.c a9d894b2465b17dff1217d99ed6752861aadc069 - arm-trusted-firmware/drivers/st/iwdg/stm32_iwdg.c 58eaa2b888dc1594940adc6331de8506a0a0fc0d - arm-trusted-firmware/drivers/st/crypto/stm32_rng.c 8fbf68e33356bf54059248192071e44d439b2685 - arm-trusted-firmware/drivers/st/crypto/stm32_hash.c 46e48c0777848fdd355ac6908ee9fda7823b32dd - arm-trusted-firmware/drivers/st/crypto/stm32_saes.c 2ee47d9ef92d939c04550b897788d8db8ef32c72 - arm-trusted-firmware/drivers/st/crypto/stm32_pka.c 31f2612aff5d24d64b3826cbe5c7a9f93ff7eb70 - arm-trusted-firmware/drivers/st/pmic/stm32mp_pmic.c dc5909c790f8267bcb9bbc047b904810550cb78b - arm-trusted-firmware/drivers/st/pmic/stpmic1.c 1c77b842fc094c883b8e6abc3522e2a5ed4ebb3d - arm-trusted-firmware/drivers/st/regulator/regulator_core.c f01b87c2b668e9cc15338565f21d115dbeaf62cc - arm-trusted-firmware/drivers/st/regulator/regulator_fixed.c def00bc3c52b54611ea6f11a6f5206cf0b3cc08a - arm-trusted-firmware/drivers/st/fmc/stm32_fmc2_nand.c 2e0e694179a7407d3c52e14e4264529939a41346 - arm-trusted-firmware/drivers/st/mmc/stm32_sdmmc2.c 534de6340fd97a005497175ba39c713369af1bc1 - arm-trusted-firmware/drivers/st/clk/stm32mp1_clk.c d2dbddd33af86dd0aac5d8131190fd03318b8d37 - arm-trusted-firmware/drivers/st/clk/stm32mp_clkfunc.c 74cc5d3e4e87fe9c6d8a3053b7ff8f962d8ebc22 - arm-trusted-firmware/drivers/st/clk/clk-stm32-core.h 78cd40b3ceb4813269f92f4b19bd56e61c47775e - arm-trusted-firmware/drivers/st/clk/clk-stm32-core.c 1af1b80b044fd14625b31a2116f4b27540df0436 - arm-trusted-firmware/drivers/st/clk/clk-stm32mp13.c 07bb0b5fe46d4ebca6c6e1feee9d8a9e7d83d6a5 - arm-trusted-firmware/drivers/st/usb/stm32mp1_usb.c 5324162d65037588a526042c0e40fab08cab0e73 - arm-trusted-firmware/drivers/st/gpio/stm32_gpio.c 2f6084a9d8f84bf599746cd3288b02a0d4755d3c - arm-trusted-firmware/drivers/st/bsec/bsec2.c 585da572d5f482cb72a4f638613aa50d70c6c7d8 - arm-trusted-firmware/drivers/auth/auth_mod.c 44e83e929d4f2094130ef7eac57924938d928b4a - arm-trusted-firmware/drivers/auth/crypto_mod.c 639d42262958e84f1bd83a574ec62649802513a1 - arm-trusted-firmware/drivers/auth/img_parser_mod.c 62b38ec608a3b1763bbd31827be93360dc10c4d3 - arm-trusted-firmware/drivers/auth/tbbr/tbbr_cot_bl2.c fbcbbd0aa417147f5e544e91c47edef162f6aa41 - arm-trusted-firmware/drivers/auth/tbbr/tbbr_cot_common.c 98690b7915852b4a6a1950623e848b467186a09e - arm-trusted-firmware/drivers/auth/tbbr/tbbr_cot_bl1_r64.c efedb0eaa10e440edf6b73b4b2df6a6d164066da - arm-trusted-firmware/drivers/auth/tbbr/tbbr_cot_bl1.c ce571262a7191f38e6027eb3e2f40c2f4fd30f7b - arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_x509_parser.c a8d6f94b03e1803e193538a42d7ffde5608c2dcc - arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_crypto.c aa57938a1ca87b1c2d69b27e2cb210dd52b72f92 - arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_common.c 1527e9ad692eabc3e379a8f7f0a4eecc68b9f9bb - arm-trusted-firmware/drivers/auth/cryptocell/712/cryptocell_crypto.c 0931c7209af239bcc95387de431d932bf01175ec - arm-trusted-firmware/drivers/auth/cryptocell/712/cryptocell_plat_helpers.c 83b5fe72e5687844a537e60af3cc9eff031f301f - arm-trusted-firmware/drivers/auth/cryptocell/713/cryptocell_crypto.c 6e817c6fdbf62d3e636fe69752f1f0bb9281c3a8 - arm-trusted-firmware/drivers/auth/cryptocell/713/cryptocell_plat_helpers.c 5499f39ea8f0f05a6707623dc19883bd2e2bf9ad - arm-trusted-firmware/drivers/auth/cca/cot.c ea1ff4dd6466dd5bba2280092f7ad0037f0e3791 - arm-trusted-firmware/drivers/auth/dualroot/cot.c f1d5a7ca46b231b4291d715aa7312bc93c8c8d3c - arm-trusted-firmware/drivers/cadence/uart/aarch64/cdns_console.S b0d5b078d9666eb577b6d96327526056a9c5ff46 - arm-trusted-firmware/drivers/imx/timer/imx_gpt.h e7fdf9ac8aa8e62e2b82e935887ea9fa71277e50 - arm-trusted-firmware/drivers/imx/timer/imx_gpt.c 11d6bed45c0c1633f53d1a14e935db95a494322d - arm-trusted-firmware/drivers/imx/usdhc/imx_usdhc.h d92351086a1b0b0b82cfa7bab9e352d5725339d7 - arm-trusted-firmware/drivers/imx/usdhc/imx_usdhc.c 30ead9b9f8c8e8a0d0443291726c90dcc10f24ef - arm-trusted-firmware/drivers/imx/uart/imx_uart.c bf6cd6123996ffba448042a934561a9845514132 - arm-trusted-firmware/drivers/imx/uart/imx_uart.h 2b9b4163928ad22b375942df6a419ac25791d15b - arm-trusted-firmware/drivers/imx/uart/imx_crash_uart.S cdd7c87e02f5cae26200b35f5869f20aa1a526cc - arm-trusted-firmware/docs/Makefile 6ed663c771aeb62483d6fe28a0cc11214c1e7750 - arm-trusted-firmware/docs/glossary.rst 02656aa026adc776af57feae6e51d79c8de8023a - arm-trusted-firmware/docs/conf.py e7276917f515f2830c41e9dd00970b894cc29849 - arm-trusted-firmware/docs/index.rst 0677c6b28a895fccae194309f759b9f4e0f4c9f5 - arm-trusted-firmware/docs/requirements.in 4c19f3b1b029cf431f24a7962ff15c2bd6dd3dfa - arm-trusted-firmware/docs/change-log.md 0b02d28e0d9881fab1b08360d2d9bbef021685c0 - arm-trusted-firmware/docs/license.rst 09adea43d8f4b0d89eb8870b1929cc81db514153 - arm-trusted-firmware/docs/getting_started/porting-guide.rst 017d049b66bc58f569acc3b9c87d84d478079a9d - arm-trusted-firmware/docs/getting_started/tools-build.rst ab9746571396728fc3439e2b8b69029d62b04b9b - arm-trusted-firmware/docs/getting_started/docs-build.rst 2fdcac38ddbe4646ffd988332a38d48fcc99f6ee - arm-trusted-firmware/docs/getting_started/index.rst 97122206fcc716ab5581232da8de4685ba9e7df9 - arm-trusted-firmware/docs/getting_started/rt-svc-writers-guide.rst ea589f8d2331859fb82d01e811ff64f7a61d6cf0 - arm-trusted-firmware/docs/getting_started/build-options.rst 680ce58128fcb0d64a591c7d91f8a97d144262c1 - arm-trusted-firmware/docs/getting_started/psci-lib-integration-guide.rst 42c9d8a0f17ea5de05d6dcae315e8c0cba8de638 - arm-trusted-firmware/docs/getting_started/initial-build.rst efd35bc15acfdda2c050b24c14261bf972c22f1e - arm-trusted-firmware/docs/getting_started/prerequisites.rst 70e219856337d42a79ce2091e96aa0417481faa2 - arm-trusted-firmware/docs/getting_started/image-terminology.rst d2201aab60e237cccd20ad636c8ad4224d7f0571 - arm-trusted-firmware/docs/components/romlib-design.rst bab05fc9be3e570a12664a942578603a8f8adb80 - arm-trusted-firmware/docs/components/ras.rst aca3aea7df00338e307623d4735b027b76f48985 - arm-trusted-firmware/docs/components/platform-interrupt-controller-API.rst b8d62ed8d8e52992c481b3f032a11c132ddc32ca - arm-trusted-firmware/docs/components/mpmm.rst 11abe92eab64d997319223639ad2693b7f7c8535 - arm-trusted-firmware/docs/components/arm-sip-service.rst d5a9296555dcd8acf889da22585e3915a8c850a0 - arm-trusted-firmware/docs/components/ffa-manifest-binding.rst cf41dde09be49dec17eb22f1925eca76e9fdcc64 - arm-trusted-firmware/docs/components/firmware-update.rst aad88bd5389ed6f896f0324b2673358b92552305 - arm-trusted-firmware/docs/components/secure-partition-manager.rst 75d075c879040f97f06e2a7b3b6bd34df86b48ac - arm-trusted-firmware/docs/components/activity-monitors.rst 963a2ee9d3bf60564d3ab545fed12694fec33fff - arm-trusted-firmware/docs/components/cot-binding.rst 692a02d80bc805bfa8254d3dd7c0a0e0f59c3d2e - arm-trusted-firmware/docs/components/index.rst 72ac59432a0693df36a09334d6f57a6f9491189f - arm-trusted-firmware/docs/components/granule-protection-tables-design.rst 3018701b7ef2e5eca172d3608726f506c4b22909 - arm-trusted-firmware/docs/components/debugfs-design.rst 8a1dffa8292f295ef5014ac04a74011b4aeea398 - arm-trusted-firmware/docs/components/exception-handling.rst 5064b1a7d15e72b127c8fbacf8f11b087446958a - arm-trusted-firmware/docs/components/secure-partition-manager-mm.rst ca2c86b55376dc70e6bbbb76058286ac38e35ba0 - arm-trusted-firmware/docs/components/sdei.rst 3da44d82cb6da71e3c958b934387a61322c1ae3a - arm-trusted-firmware/docs/components/realm-management-extension.rst 8b703775ae98bb7ffdad5b0c311d14da5187547c - arm-trusted-firmware/docs/components/rmm-el3-comms-spec.rst 602d20bd46337be44a23550620a7a1f748130fb9 - arm-trusted-firmware/docs/components/xlat-tables-lib-v2-design.rst 27010f32c64633e838ad226428134580c6275e87 - arm-trusted-firmware/docs/components/el3-spmc.rst f39c4c5b080cb5537f0260d9f3e477e02aa63bfa - arm-trusted-firmware/docs/components/measured_boot/index.rst e289a8345f0c801d0e1d079b94c6752a31a28396 - arm-trusted-firmware/docs/components/measured_boot/event_log.rst a1e612df3549c8a9375b1969131a0b13e7fdf61f - arm-trusted-firmware/docs/components/fconf/fconf_properties.rst d795da44f403a2a0bc4010ba95915fcabbef3c31 - arm-trusted-firmware/docs/components/fconf/amu-bindings.rst c3411adb08049c0735f5b9be29bc976bbcde69c8 - arm-trusted-firmware/docs/components/fconf/index.rst 10529cbd50c1b2a10d7bf7669a515a30f564db2c - arm-trusted-firmware/docs/components/fconf/mpmm-bindings.rst 68d992f28a446b0ffe6adad209b6189f9f0dd6a9 - arm-trusted-firmware/docs/components/spd/trusty-dispatcher.rst 16ccf6b90697399bd4231bdb3ca642c8d9ec5c0e - arm-trusted-firmware/docs/components/spd/pnc-dispatcher.rst e583074d9e81fffee8804f560b145fa486f1aba8 - arm-trusted-firmware/docs/components/spd/optee-dispatcher.rst 714f4840f1b5579f9bc25776cbd19e891afd9b0a - arm-trusted-firmware/docs/components/spd/index.rst 5d7421fde74010efb451e6e515079f37ec3227e2 - arm-trusted-firmware/docs/components/spd/tlk-dispatcher.rst 3fe053ce17752ae01f7d815a5df51f4887d2749f - arm-trusted-firmware/docs/_static/css/custom.css 9fcde12a65498faac5c43825aec87d7fd0f2ecb2 - arm-trusted-firmware/docs/process/security-hardening.rst 3f4a6d7ff70fb05d5b604632a17c4f84f8c5ab3a - arm-trusted-firmware/docs/process/faq.rst bfb4f8dc9ec952cc5582f0a704de50db89072cf8 - arm-trusted-firmware/docs/process/code-review-guidelines.rst 2a682dc1f89020ac9bd841e6397c1ebab7fb2938 - arm-trusted-firmware/docs/process/platform-ports-policy.rst 38500afb172ba24913cb9043ad8a6bde354423c6 - arm-trusted-firmware/docs/process/index.rst 3a4d85651ee64cc9eeb924af2325478bcf1f71e2 - arm-trusted-firmware/docs/process/coding-style.rst 4f023e7a9c8522b900e5272f9027d525fc39ea76 - arm-trusted-firmware/docs/process/contributing.rst a65ae06a31227e864eee126f340bfed0d8525c39 - arm-trusted-firmware/docs/process/security.rst f41d124257ae7d42cbb3abdd59f1acaeddcb978e - arm-trusted-firmware/docs/process/coding-guidelines.rst 0a632eddc1198fe547c7a02626ccf014ce9b9d87 - arm-trusted-firmware/docs/process/commit-style.rst 556090a5f980031e56bccbb5c6d93f41384aad09 - arm-trusted-firmware/docs/plat/intel-stratix10.rst 2a492964dd82db785e381f828fae2b2a729f6749 - arm-trusted-firmware/docs/plat/meson-gxbb.rst 9bfeb07c04a47aacac6ae649f75799c894e74067 - arm-trusted-firmware/docs/plat/mt8183.rst b4e4939c027168061216b513705a698e3b671665 - arm-trusted-firmware/docs/plat/imx8m.rst 8e3ce138f467e85c87bf7353409179dc327d4cee - arm-trusted-firmware/docs/plat/stm32mp1.rst ec1405c631e48598eee9a57a19fa05a90f2a9620 - arm-trusted-firmware/docs/plat/qemu.rst 7a5cf9900f3f2725b5731ae9a0834d29329e090f - arm-trusted-firmware/docs/plat/xilinx-versal.rst 4905e051c0a996867dcc2389b8bd5430b0741699 - arm-trusted-firmware/docs/plat/imx8.rst a928b648d0677930c926401b40e335f052e97be5 - arm-trusted-firmware/docs/plat/mt8195.rst 84cb8ce1de6f042d0693d8a1a4bb2265ef8a7ed0 - arm-trusted-firmware/docs/plat/meson-axg.rst a80443b8a04209092463f6005843be7eb0dc832d - arm-trusted-firmware/docs/plat/rpi3.rst 45f03fd73a50f2fe124a2bd1d70fb40243ba0e82 - arm-trusted-firmware/docs/plat/warp7.rst 3cefd2238957aeadfec4d578846bb38b56ca5c26 - arm-trusted-firmware/docs/plat/hikey960.rst 8b88e9d6cfe72a03efd7e226122d5cd33334fe66 - arm-trusted-firmware/docs/plat/ti-k3.rst 080191f60f9e441f7527257b977a2c8f6d8c5533 - arm-trusted-firmware/docs/plat/poplar.rst ed1a65471d042b402028616f2e38ed56b42dc891 - arm-trusted-firmware/docs/plat/qti-msm8916.rst a970558632482b93ee96aba756982061d20ea4e8 - arm-trusted-firmware/docs/plat/intel-agilex.rst 05664e895ce6375be6ad98e9576013d1209cb012 - arm-trusted-firmware/docs/plat/hikey.rst 01b97fb19ab7a8e8baa5a1a96d35f2cb5dc0a05c - arm-trusted-firmware/docs/plat/rpi4.rst 15d03048959cdd154b540a3b91f7aa6b48f7a7ef - arm-trusted-firmware/docs/plat/allwinner.rst ddffb1cc078fd2d3c58ed8cde2b32388ccd532c9 - arm-trusted-firmware/docs/plat/meson-gxl.rst de25efbc7acce27ba0385c2c51a59fbc0f7f7124 - arm-trusted-firmware/docs/plat/brcm-stingray.rst 763ed3b7f19f3755e4ab9d32e31712eea7a93e03 - arm-trusted-firmware/docs/plat/index.rst 9e85f6fbc5306c4b0604e98de5fcbddb385c4ce1 - arm-trusted-firmware/docs/plat/mt8192.rst 5e8683cb8a4bd212afefc2295ce7ebc01bf8a029 - arm-trusted-firmware/docs/plat/mt8188.rst f2bbe77ac618ba9be663de2bba3cee62eaf17f60 - arm-trusted-firmware/docs/plat/mt8186.rst 2ed0c805bd3cba59619101f0918aeac59d4e6fd3 - arm-trusted-firmware/docs/plat/rcar-gen3.rst df909307e45e07ec88f455e8ef27abedd18e3592 - arm-trusted-firmware/docs/plat/rockchip.rst 12b7c2db7722b49705438fabf8b96c0943d163bd - arm-trusted-firmware/docs/plat/meson-g12a.rst d0ad3f088b7307bd002023c2fcda2de07a36f40f - arm-trusted-firmware/docs/plat/synquacer.rst 53f0692ccc04d5d659e88ac1dc1080af6dcda94d - arm-trusted-firmware/docs/plat/qti.rst b54be1ac4f13d0a724629f301e245bbcc4379d44 - arm-trusted-firmware/docs/plat/nvidia-tegra.rst 661bb737bf5224a5d575864fc5e451ccae31bc37 - arm-trusted-firmware/docs/plat/xilinx-zynqmp.rst 1fb07134c685f21246757d77653a8c6bb12d949c - arm-trusted-firmware/docs/plat/socionext-uniphier.rst 241bdd87780a18be7b65da1cd4d2f486525a1023 - arm-trusted-firmware/docs/plat/xilinx-versal-net.rst 25ec8ee5167ea3d60afe26566de20782ee6aa44c - arm-trusted-firmware/docs/plat/qemu-sbsa.rst a6c4746123e21eba44253912da4e92f0fd31a6cc - arm-trusted-firmware/docs/plat/rz-g2.rst 9a8421091aa139e567a9d2716972e0169baf832a - arm-trusted-firmware/docs/plat/marvell/index.rst e9622121f101a843f70aaae2b455adfb3e2170b5 - arm-trusted-firmware/docs/plat/marvell/armada/build.rst 5315af3195d5a7c46ec750dccbf4f684c0df4e81 - arm-trusted-firmware/docs/plat/marvell/armada/porting.rst 011fd015be24cc6440f16c9224d4b7ebaf9c4e8f - arm-trusted-firmware/docs/plat/marvell/armada/uart-booting.rst bcb055e4f5b81eda0adb88f8b79f78b72b1332b9 - arm-trusted-firmware/docs/plat/marvell/armada/misc/mvebu-amb.rst 3b71f880342eddec219418df7f6e6034cce505b5 - arm-trusted-firmware/docs/plat/marvell/armada/misc/mvebu-ccu.rst 30afe5cabdcd30362317ee05e9fc4203912e1e30 - arm-trusted-firmware/docs/plat/marvell/armada/misc/mvebu-a8k-addr-map.rst 0af03a25bc9938840be478afe1f0c3375e852dc7 - arm-trusted-firmware/docs/plat/marvell/armada/misc/mvebu-iob.rst 4496a36f12db50b8075c93550ad2b7a23c24e490 - arm-trusted-firmware/docs/plat/marvell/armada/misc/mvebu-io-win.rst aa2be0dce19adf3702025c84d42587a8d1febeb0 - arm-trusted-firmware/docs/plat/arm/index.rst c72c6dbd6d6d3d814af8ac6d610aaac6f36a7e43 - arm-trusted-firmware/docs/plat/arm/arm-build-options.rst 839b91011a0ebdde7ac9b056ab0a3b087ef11114 - arm-trusted-firmware/docs/plat/arm/fvp-ve/index.rst f3d761746c24f650eb7ea60e9230cc57c34dc36f - arm-trusted-firmware/docs/plat/arm/juno/index.rst 46e0aef67518d4e85f7b3f9dc17b5e3a36fc9640 - arm-trusted-firmware/docs/plat/arm/morello/index.rst b10bad88c8647f9ecfe8b3bad163830573cfbdc0 - arm-trusted-firmware/docs/plat/arm/arm_fpga/index.rst a845be9736fc1cfcd3cefda5b6a0bde2419f9bc0 - arm-trusted-firmware/docs/plat/arm/fvp_r/index.rst 803add552f48a76b00b9383f4a7c9649096d3677 - arm-trusted-firmware/docs/plat/arm/fvp/index.rst dc03d6c732257847d92bd05db0e2b93163870fd7 - arm-trusted-firmware/docs/plat/arm/corstone1000/index.rst 0deb05883735117f3ea1e4e77cf354959dbf480a - arm-trusted-firmware/docs/plat/arm/tc/index.rst 5d7bd6f5908ace2c36015e0535f2deacac9a2956 - arm-trusted-firmware/docs/plat/nxp/index.rst ed3ec7c6e5baceda79c359ce661ac80dbf660d61 - arm-trusted-firmware/docs/plat/nxp/nxp-ls-tbbr.rst 231fc05a0b2de9270bfe513d92b37243b1cc9601 - arm-trusted-firmware/docs/plat/nxp/nxp-ls-fuse-prov.rst 7b3072f9759a1fe276a22dcb70d936006608d299 - arm-trusted-firmware/docs/plat/nxp/nxp-layerscape.rst b748a01e82c3ad35dacc68ae9295e4553d57beab - arm-trusted-firmware/docs/security_advisories/security-advisory-tfv-3.rst 939eb2b8d82c68d6c9a4e8c1271bd83151818553 - arm-trusted-firmware/docs/security_advisories/security-advisory-tfv-1.rst fab06483aeca0f68846039c9146a6d828ab12518 - arm-trusted-firmware/docs/security_advisories/security-advisory-tfv-7.rst 63e67342811855c2803be11bca43aa4c60543575 - arm-trusted-firmware/docs/security_advisories/security-advisory-tfv-8.rst e03dee87868096ffa7982026e20837ddfc9a6aa3 - arm-trusted-firmware/docs/security_advisories/security-advisory-tfv-4.rst baa4a5d45ad34ed640a9d885ca23ef3b9b71a895 - arm-trusted-firmware/docs/security_advisories/index.rst 5a8ee89be8b54261b0e207ca882fab66cb4db5b9 - arm-trusted-firmware/docs/security_advisories/security-advisory-tfv-2.rst a87b0ab171a6075141e159614c9bcb52f4e8ba58 - arm-trusted-firmware/docs/security_advisories/security-advisory-tfv-9.rst 266a8326bc618859a7a18572589b40f197ed1a82 - arm-trusted-firmware/docs/security_advisories/security-advisory-tfv-6.rst 1b8c8e49a1eac7ac65f01b730ef3d22dee6de50f - arm-trusted-firmware/docs/security_advisories/security-advisory-tfv-5.rst ead2c4aef238ecce539f8cc7d40bed271cecab63 - arm-trusted-firmware/docs/about/contact.rst 59188a229cb22f62c915c6615051abf66941512a - arm-trusted-firmware/docs/about/index.rst c199f39577c3b8a404c988f8328e38d731f4bdf7 - arm-trusted-firmware/docs/about/features.rst a71bf7430d4ed1cc4c2e0f1650b15d68c9ba74e9 - arm-trusted-firmware/docs/about/release-information.rst 3d4d6eeef77d8e11c9b5da38bf3008531d4cdff8 - arm-trusted-firmware/docs/about/acknowledgements.rst b545672f1415b20707cc26e3b09252c6b6e78cc4 - arm-trusted-firmware/docs/about/maintainers.rst 3e1557ac89eff3ea7cb96e090dcc6cd147117008 - arm-trusted-firmware/docs/perf/psci-performance-juno.rst 7dd6cda873ec6898dcb0060d0f9ad1c839a7a98b - arm-trusted-firmware/docs/perf/index.rst ff8ad4850057cbaba3caddae15b9429bb9c42b66 - arm-trusted-firmware/docs/perf/tsp.rst 840dcafe1996d0299a5922474d7980b6d2eb779c - arm-trusted-firmware/docs/perf/performance-monitoring-unit.rst 6fd5a13007e2c86b56b83ed08af9e4343890c44d - arm-trusted-firmware/docs/threat_model/threat_model_fvp_r.rst 0b2de3ce3ff9eb88a6a53c7ce6c8e2cb5f5770e9 - arm-trusted-firmware/docs/threat_model/index.rst 82bd4b2f6346ae7ceade3c10a81074f511a912d0 - arm-trusted-firmware/docs/threat_model/threat_model.rst 33eac087284d8339705c0376ae9a9c7653d6da62 - arm-trusted-firmware/docs/threat_model/threat_model_spm.rst 5020d1f2b31e9859c12467fbde12f5503d56f72a - arm-trusted-firmware/docs/threat_model/threat_model_el3_spm.rst ffda28459589a0ec22cacc12c5b92103ed64fbbc - arm-trusted-firmware/docs/design/auth-framework.rst a3f0b5a39e2120fdbcad8de599b7c1a18345cfcc - arm-trusted-firmware/docs/design/alt-boot-flows.rst b15afee5cbc5225a2ef2f709e9761fa2cd73d65e - arm-trusted-firmware/docs/design/psci-pd-tree.rst ac5a5e29221304cbf49e62fec636756672291630 - arm-trusted-firmware/docs/design/firmware-design.rst 7ad09b010b680585820d9507a30c3eb0abf05521 - arm-trusted-firmware/docs/design/trusted-board-boot-build.rst 8795f3e11e470aa0945c4c65f8e160672001edd1 - arm-trusted-firmware/docs/design/index.rst f880dd25cbf380065e9d345752376e40bc756664 - arm-trusted-firmware/docs/design/interrupt-framework-design.rst 6e60dedac282498dc34de3ebcecd6f0119e7348d - arm-trusted-firmware/docs/design/trusted-board-boot.rst 9e3383381d4184cf5d03540d6b53c1950b1c9214 - arm-trusted-firmware/docs/design/reset-design.rst c815977b5dd725f75f848ff21306de6e075ec9a5 - arm-trusted-firmware/docs/design/cpu-specific-build-macros.rst 1cf19041279928d9215bdd8c91a1559b37e426b4 - arm-trusted-firmware/docs/design_documents/measured_boot_poc.rst 3c9105f13eb03be1b0c0035eb88daafdd219f4a1 - arm-trusted-firmware/docs/design_documents/context_mgmt_rework.rst 6930f91b97e3940dc60b0cfa561a437027ec571e - arm-trusted-firmware/docs/design_documents/index.rst 9891ed85f2bc9de65aa8cf83cd460f2b88405633 - arm-trusted-firmware/docs/design_documents/drtm_poc.rst b5585102476dfaccde6a472ab5485236468a4d14 - arm-trusted-firmware/docs/design_documents/cmake_framework.rst add0156b84b7d9f7760db313170bf81a672a66a6 - arm-trusted-firmware/docs/resources/TrustedFirmware-Logo_standard-white.png 10d343a1dfde1e76a19cfc7a0f8a9ca28710ee17 - arm-trusted-firmware/docs/resources/diagrams/reset_code_no_cpu_check.png c05984305daded35b5f3a14ea3c5ac88319f4292 - arm-trusted-firmware/docs/resources/diagrams/romlib_design.dia 66f1f1fd09b5146cb2a5e1c538de29ea7f88ed7e - arm-trusted-firmware/docs/resources/diagrams/fwu_states.png 80b81639bb1aa78723d3635f0359764c595e38c8 - arm-trusted-firmware/docs/resources/diagrams/romlib_design.png b605edbecdbd0fe48f45856493d43740e3c060be - arm-trusted-firmware/docs/resources/diagrams/PSA-FWU.png 19e287ff6d7c25917fd56356da40bee3e5ef120e - arm-trusted-firmware/docs/resources/diagrams/sec-int-handling.png 77da82b847d9c9a0cecaa2e43e40dac166a66399 - arm-trusted-firmware/docs/resources/diagrams/cmake_framework_structure.png 24c61ef2cd5863d4313235af72b33307fdd2a08d - arm-trusted-firmware/docs/resources/diagrams/Makefile 40dca2e6d5cf7cdc88398bf5e2df39f3fce31bab - arm-trusted-firmware/docs/resources/diagrams/spm-threat-model-trust-boundaries.png 9bd9241452f165fcc7e5018bf8a24204767fa036 - arm-trusted-firmware/docs/resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png a68fd21bb442987ce7a67e0eb08d150b81bfe901 - arm-trusted-firmware/docs/resources/diagrams/secure_sw_stack_tos.png 2417a250f3f2552f5e881830e947024a92e55adf - arm-trusted-firmware/docs/resources/diagrams/arm-cca-software-arch.png b42c9e2672802e26c9137df29eff6a1c68652ea6 - arm-trusted-firmware/docs/resources/diagrams/context_mgmt_proposed.png ada526023821d5e57e3e1aa979b38d2c8708227e - arm-trusted-firmware/docs/resources/diagrams/ff-a-spm-sel2.png a0ca882a9a47bf5642759780b006f69f3c667fff - arm-trusted-firmware/docs/resources/diagrams/context_management_abs.png a6a4256584fddbb776f1e274748edeff4289cf4a - arm-trusted-firmware/docs/resources/diagrams/psci-suspend-sequence.png 77f9b835b00f7926f05f699362fefbecf98c649f - arm-trusted-firmware/docs/resources/diagrams/PSA-FWU.dia 4ab0332c836fdf5e5596c2b7ecc6ea4bccb62b8c - arm-trusted-firmware/docs/resources/diagrams/reset_code_no_checks.png d10eb3ff6f8cf071330205ec0d59126d79f939f4 - arm-trusted-firmware/docs/resources/diagrams/non-sec-int-handling.png 995f8620379e56790c9a95e7ad726868f0864d12 - arm-trusted-firmware/docs/resources/diagrams/rmm_el3_manifest_struct.png 84f99bb590f5c8748bc6e47f3e7bd4bf5890447d - arm-trusted-firmware/docs/resources/diagrams/xlat_align.png 4d2668ab5814fb9b799f65b69b427db29952658b - arm-trusted-firmware/docs/resources/diagrams/ffa-secure-interrupt-handling-nwd.png d2522911e613a4005eb1e10931779a1bb350a363 - arm-trusted-firmware/docs/resources/diagrams/FIP_in_a_GPT_image.png 04a65e98eceabb17ea534a6dea187021477a1fb2 - arm-trusted-firmware/docs/resources/diagrams/int_handling.dia 763017cfa85171acb7422b0f8ef1c40ba69443a3 - arm-trusted-firmware/docs/resources/diagrams/rt-svc-descs-layout.png 64d840596ae8dbdfb803bfdd471e3d4e7955ca82 - arm-trusted-firmware/docs/resources/diagrams/fwu_flow.png c194964eb3447a9c4baad661a58b201ca88c0e8f - arm-trusted-firmware/docs/resources/diagrams/partition-package.png fd3f89a0c0509273b1ad8532ee561ba5b112edac - arm-trusted-firmware/docs/resources/diagrams/rmm_cold_boot_generic.dia d5775195107610d6a67d5d7f8af6590e4e53e570 - arm-trusted-firmware/docs/resources/diagrams/default_reset_code.png c279d33545695cac4327bf14a8d84b4237dc8387 - arm-trusted-firmware/docs/resources/diagrams/MMU-600.png 08ebe00cb9823cd55d80c05b4aaaa64c103093ce - arm-trusted-firmware/docs/resources/diagrams/xlat_align.dia d9a6dc06e1a28c0235940539e527ac285c179342 - arm-trusted-firmware/docs/resources/diagrams/reset_code_no_boot_type_check.png d75be64656ad689f5ccb81b73dac7bc26b700618 - arm-trusted-firmware/docs/resources/diagrams/rmm_el3_manifest_struct.dia 961fd0fc52b27792b27c6cc8b9f210be8959e285 - arm-trusted-firmware/docs/resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png 7c4678ac4952c496df4536445b336d96139b0066 - arm-trusted-firmware/docs/resources/diagrams/ffa-secure-interrupt-handling-swd.png aacd72a3c084647a884d67147510a1b0c26d8359 - arm-trusted-firmware/docs/resources/diagrams/reset_code_flow.dia 1586bdc989b8698512851e436d39fed8ad375030 - arm-trusted-firmware/docs/resources/diagrams/romlib_wrapper.dia aa7462d2e5339e422146420f79d882671016b17b - arm-trusted-firmware/docs/resources/diagrams/rmm_cold_boot_generic.png 40ffa83fe202970879802b809b75c10ed360c7d4 - arm-trusted-firmware/docs/resources/diagrams/romlib_wrapper.png 02a0166ec0c907a8725efa2ff467ea4d5984a35c - arm-trusted-firmware/docs/resources/diagrams/secure_sw_stack_sp.png 17e11d01f23f073cec01fb44acaa3c976495e982 - arm-trusted-firmware/docs/resources/diagrams/cmake_framework_workflow.png 2e886fd02f6b39a545824f0819608260e0671c14 - arm-trusted-firmware/docs/resources/diagrams/context_mgmt_existing.png fdb07d57fc0ab62ee420a06287f1ebdc8c89f0fd - arm-trusted-firmware/docs/resources/diagrams/ff-a-spm-at-el3.png 5058f6e8c3278aeb9fcf6b27526000cd079a9d07 - arm-trusted-firmware/docs/resources/diagrams/ff-a-lsp-at-el3.png 2c5f1b895b01d75ebe2fd874d61f728fe18fca4a - arm-trusted-firmware/docs/resources/diagrams/draw.io/ras.xml ad73cbcd10b1b5e45ca3a01df6c435b345686322 - arm-trusted-firmware/docs/resources/diagrams/draw.io/ehf.svg a2eed4587b5987e97e3f8207a2c9783c5e322c90 - arm-trusted-firmware/docs/resources/diagrams/draw.io/ras.svg 4eb0b99548ee5cdbff9d0e01b3455c7c1e1af275 - arm-trusted-firmware/docs/resources/diagrams/draw.io/ehf.xml 89429fb35fc54ad81b4aab0c9d5860b228aab347 - arm-trusted-firmware/docs/resources/diagrams/plantuml/fconf_bl2_populate.puml 0cbedd3989e3d4fc11c3401d7b250d8b14411c50 - arm-trusted-firmware/docs/resources/diagrams/plantuml/sdei_explicit_dispatch.puml 7ca50157b91a940fdcd61fed7da54e93501b2c3e - arm-trusted-firmware/docs/resources/diagrams/plantuml/io_framework_usage_overview.puml cde708741ffdd39f92d8670aea4a93ef451cd611 - arm-trusted-firmware/docs/resources/diagrams/plantuml/spm_dfd.puml 9e7994a98a6d3531ff8f3c7e16b9e27ae0240805 - arm-trusted-firmware/docs/resources/diagrams/plantuml/io_arm_class_diagram.puml a431301dad1931dd6247cef4df049efa732cefe8 - arm-trusted-firmware/docs/resources/diagrams/plantuml/el3_spm_dfd.puml 7eb6ecf49d5ec8a975cccdc3aeb0d994e07362a0 - arm-trusted-firmware/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml 732ce8b12943c9ca218e89a1aa3eae1379952d12 - arm-trusted-firmware/docs/resources/diagrams/plantuml/fip-secure-partitions.puml 695a4bfc3f0c50586104d10e16a8527c37f3541f - arm-trusted-firmware/docs/resources/diagrams/plantuml/io_dev_registration.puml 853a892ccba3dedfcb4491b7ad449b46d6a4d47c - arm-trusted-firmware/docs/resources/diagrams/plantuml/sdei_general.puml 2c516abafcee77f3889360526590d0764a35d61c - arm-trusted-firmware/docs/resources/diagrams/plantuml/bl2-loading-sp.puml e357fbb8d83445182b61abea380d1885e484c4cb - arm-trusted-firmware/docs/resources/diagrams/plantuml/tfa_dfd.puml 0130e90e98cac66f9ac28a56d8fa17af801ead7a - arm-trusted-firmware/docs/resources/diagrams/plantuml/io_dev_init_and_check.puml 11335e71ce700055225b4223bb4218122db63853 - arm-trusted-firmware/include/bl2u/bl2u.h 061a6a5d58a19fa40602dcb1c9d1042a206ad73e - arm-trusted-firmware/include/drivers/spi_mem.h e52b9017a122dbf25d5764491104335c6a166dd2 - arm-trusted-firmware/include/drivers/usb_device.h 58d9040bd23a07f657047c01fbc92a62b9b04d45 - arm-trusted-firmware/include/drivers/clk.h 3fdd5f2bbd8585722f7176499884e963fcc1806f - arm-trusted-firmware/include/drivers/console.h 1e85ce64c0bc0c37f1c87dab8859540aadd4d842 - arm-trusted-firmware/include/drivers/raw_nand.h 32b681b12e18f054ea32d70a554e9c07ff59e4f5 - arm-trusted-firmware/include/drivers/spi_nor.h 18108c84fbcd74f0ea54a513ce5a2ab438e22e8f - arm-trusted-firmware/include/drivers/ufs.h beb3e629b953dd33bc44df27d3f0b251af4a75e5 - arm-trusted-firmware/include/drivers/scmi.h 3d13f3cbff61918c53bb0a76876155dc82337fe5 - arm-trusted-firmware/include/drivers/console_assertions.h 2c8fac425744348a8ae0d124f4784f930cb2c5d6 - arm-trusted-firmware/include/drivers/mmc.h 8709de3c5655138d78511772539fb29a8b660364 - arm-trusted-firmware/include/drivers/scmi-msg.h c8f57a02330fc21d063cbfa19b558cbd20de2787 - arm-trusted-firmware/include/drivers/generic_delay_timer.h c4429ee53ef448b397f7bb00549865cde71b807e - arm-trusted-firmware/include/drivers/nand.h b11f7ad45072a13e91bd01040adca94742f7cff1 - arm-trusted-firmware/include/drivers/gpio.h c6f581c377a1a1670d1dd54c360deded41593d6f - arm-trusted-firmware/include/drivers/delay_timer.h bb163896fcf9655f45d24b8676ea0a79a6c28272 - arm-trusted-firmware/include/drivers/dw_ufs.h 80ffbe42c480534b02989a02a37fe24a316746dc - arm-trusted-firmware/include/drivers/spi_nand.h bd4bb47e71397b065ce00f2af2e6c24b3a8e1d45 - arm-trusted-firmware/include/drivers/partition/efi.h a0cf43129d3b8d21348b212b8f1adaddb5c2258f - arm-trusted-firmware/include/drivers/partition/partition.h 53d9f7bd2b149b510835abe889d7520b7f40b916 - arm-trusted-firmware/include/drivers/partition/gpt.h 1c27aa6ecf64d9c63f2e200bb4b4f34c1493e6b4 - arm-trusted-firmware/include/drivers/partition/mbr.h 490bae640af8d15a10cc4a530a23cd51226ca709 - arm-trusted-firmware/include/drivers/mentor/mi2cv.h 8d5bb836b8836f486476f20753a83ca09d64567e - arm-trusted-firmware/include/drivers/coreboot/cbmem_console.h bd8eab4d0a2394ab277d17b70d1de2839a83ce04 - arm-trusted-firmware/include/drivers/fwu/fwu.h 89a898543325d24449f04f9b4f73ab80fe43615a - arm-trusted-firmware/include/drivers/fwu/fwu_metadata.h 79ff571f338c50e0dcfc74664868a91531295879 - arm-trusted-firmware/include/drivers/measured_boot/rss/rss_measured_boot.h 539e011d26794dcb08871f32e64aafbeaa1e8b04 - arm-trusted-firmware/include/drivers/measured_boot/event_log/event_log.h 4347dedb75a4a923fe512768084cc75d92ec9712 - arm-trusted-firmware/include/drivers/measured_boot/event_log/tcg.h 95f57bdb58eaa0c98d1495b69af4481368294101 - arm-trusted-firmware/include/drivers/synopsys/dw_mmc.h 7f1222ae6a5838bc830b1300ab199a3d42290790 - arm-trusted-firmware/include/drivers/marvell/addr_map.h 9b00b75ebe2ac0600a4eb5f6e9b76c2c77e19a94 - arm-trusted-firmware/include/drivers/marvell/ap807_clocks_init.h 69f49992d9c55ee0e777a11643d0b52001cb7622 - arm-trusted-firmware/include/drivers/marvell/aro.h 15475b1e40e5c5bddbfabed61f7f24162136b1f7 - arm-trusted-firmware/include/drivers/marvell/amb_adec.h 5c2e0ca868faae2060e6a9f3bf20896783564942 - arm-trusted-firmware/include/drivers/marvell/ccu.h 6fb4915c93922ffd80c2b7082f5219b13d64a4a9 - arm-trusted-firmware/include/drivers/marvell/iob.h 02710fe143b7937c1b4fad8c1e757146513ac135 - arm-trusted-firmware/include/drivers/marvell/io_win.h a3de98e4cc085d3cf7d5d52931b5b3623d0a619f - arm-trusted-firmware/include/drivers/marvell/mci.h d7bc8fa93e6253a8b9ef6c39613ea88489703b1f - arm-trusted-firmware/include/drivers/marvell/gwin.h 2a16f04ed2b2358e61aa3683ec3d1f2b3960dd2b - arm-trusted-firmware/include/drivers/marvell/cache_llc.h 000c88b50b95ab8b54fed58ab9f840b9bb69e06c - arm-trusted-firmware/include/drivers/marvell/i2c.h fd4a5e7af241c3b0572f5c9e81decf1868f17fb4 - arm-trusted-firmware/include/drivers/marvell/thermal.h 9fe146fde5aec71f5cc47d07590e1f76602bc9cc - arm-trusted-firmware/include/drivers/marvell/mochi/ap_setup.h 80057d817a90e75ad1e4eab0e4c81c6a62aa3911 - arm-trusted-firmware/include/drivers/marvell/mochi/cp110_setup.h 1bd923068f35229b4648825afdbe2d5ee74ba4fe - arm-trusted-firmware/include/drivers/marvell/uart/a3700_console.h c5bffc4b09ef56f6db52d14f27e4ba134a6cda11 - arm-trusted-firmware/include/drivers/io/io_storage.h 10532a6db736e62308718e7ed4602bcdad21e3e0 - arm-trusted-firmware/include/drivers/io/io_block.h 65ea10cb954a4eafbc5c1b0e1f4118cece4ff74b - arm-trusted-firmware/include/drivers/io/io_semihosting.h fe49b84f7431a3680d29420770e6c5a8e81abd5c - arm-trusted-firmware/include/drivers/io/io_encrypted.h d44cfbded1853f569ae63d99598504a959d6be61 - arm-trusted-firmware/include/drivers/io/io_fip.h 37187b6d387c4c5065ca5fcf7fb76e54527943c2 - arm-trusted-firmware/include/drivers/io/io_dummy.h f255bd6542ce1b5d70e6f1e8d795bf29367099a7 - arm-trusted-firmware/include/drivers/io/io_memmap.h ea2dcfb76c08ec6fec8d8a369642b152753b0780 - arm-trusted-firmware/include/drivers/io/io_driver.h e65ada86295c449ba40e5e0d4d1558b8c57e24c5 - arm-trusted-firmware/include/drivers/io/io_mtd.h d9fee9976962b8d9daffbf4d4cb1e7400e14c745 - arm-trusted-firmware/include/drivers/ti/uart/uart_16550.h 0601d762e1bfda8d93d085ea44202fdbff2d1ad9 - arm-trusted-firmware/include/drivers/allwinner/sunxi_rsb.h 1fad8ad24347aab9e6da6d46f5cf581f938d2ab8 - arm-trusted-firmware/include/drivers/allwinner/axp.h ddd09be972db2607bb424326a6c8fbb441dbfec2 - arm-trusted-firmware/include/drivers/rambus/trng_ip_76.h f18d30ed876fb854340d329c32144778921ba136 - arm-trusted-firmware/include/drivers/arm/tzc380.h e09b3a9f39d9785a8eb69e1d8ffb25ad70020002 - arm-trusted-firmware/include/drivers/arm/gicv3.h 9d3f8d8e035f50cdbbce90c33f419ebcd7641645 - arm-trusted-firmware/include/drivers/arm/smmu_v3.h 0282c52c2cf6a737b53c9bcebcd089c5bf35ab24 - arm-trusted-firmware/include/drivers/arm/tzc_dmc500.h 720d4bb282dee6b7e1e9b67b67fe1b83fa342188 - arm-trusted-firmware/include/drivers/arm/arm_gicv3_common.h c313d8aea2aa56300528293ebb42d4b35d46b18c - arm-trusted-firmware/include/drivers/arm/nic_400.h 94c17028c6397c87c565378f0d72da1e8e6ef222 - arm-trusted-firmware/include/drivers/arm/gic600ae_fmu.h 1f2f3ae5b2636732d8a2b76e04392deacdc51203 - arm-trusted-firmware/include/drivers/arm/ccn.h abaea50a4f3861dfaa3f55cba235dc00114b68f4 - arm-trusted-firmware/include/drivers/arm/sp805.h eb064e58fc5aaf99768b3c9f167e6a369c5d51b2 - arm-trusted-firmware/include/drivers/arm/pl011.h 7df6720ec26b2f7db5ecf69c6541afa8bd5cce16 - arm-trusted-firmware/include/drivers/arm/gicv2.h dcca36bec1c965c6413ab49729c23a771108058e - arm-trusted-firmware/include/drivers/arm/sbsa.h 2fa5a8cfd7f005b8d48960df0fa9dab5568d8059 - arm-trusted-firmware/include/drivers/arm/dcc.h cd54a5c35b74beeacb16c618204bb31eaa33126b - arm-trusted-firmware/include/drivers/arm/gic_common.h 3c63f525fa4ab772695c59df263364d15f606582 - arm-trusted-firmware/include/drivers/arm/sp804_delay_timer.h ea619e78dc1630857e7bca57a8fb64b7d45583ba - arm-trusted-firmware/include/drivers/arm/pl061_gpio.h f89cb135caa681130763fb120fd4660a0b2cec25 - arm-trusted-firmware/include/drivers/arm/ethosn.h 8d3c051e8ba42150549dab299eca67bf73caf21d - arm-trusted-firmware/include/drivers/arm/tzc_common.h be5093d8f8d48610060e70ed9a8ee5602ad6739b - arm-trusted-firmware/include/drivers/arm/tzc_dmc620.h 8971a6e6b857b7b1e6544d6c3c9a52ca567a9e11 - arm-trusted-firmware/include/drivers/arm/scu.h 781393d32ee895d4d1dbf5be1f50f038927329c1 - arm-trusted-firmware/include/drivers/arm/rss_comms.h ff57e2eeb8df1ea48a2e861c72cc1d2a6625dc97 - arm-trusted-firmware/include/drivers/arm/gic600_multichip.h 7ca64097543e0475ded88ff1b0c756ea3e68dce4 - arm-trusted-firmware/include/drivers/arm/tzc400.h dbd8416ff45616cedd618b5d04e9087cb853bfe6 - arm-trusted-firmware/include/drivers/arm/dsu.h 59b0744b90366dbe8e668e086e4b713ba9819b4d - arm-trusted-firmware/include/drivers/arm/mhu.h c269f40255323bed655d0c076e5fc771bee91550 - arm-trusted-firmware/include/drivers/arm/cci.h fdc34a2731639423ad5caeb5261f3207a4183cb1 - arm-trusted-firmware/include/drivers/arm/css/css_mhu.h c4e97cf187b8de349d494ab89ca4f5c1a83aadc7 - arm-trusted-firmware/include/drivers/arm/css/css_scpi.h 644885f6d536f0b9fecf9b19db5324cebdb1cd00 - arm-trusted-firmware/include/drivers/arm/css/scmi.h faa54f13bf1956078c447ae298b4696adc11ec16 - arm-trusted-firmware/include/drivers/arm/css/css_mhu_doorbell.h cb3a4608dbc689332bbeee2134f523d78ea6fcb8 - arm-trusted-firmware/include/drivers/arm/css/css_scp.h 2199dceebbe76121f35942566cde95a239340491 - arm-trusted-firmware/include/drivers/arm/css/sds.h 7d87f35690f4d41b9739eb995465900a8070b7d9 - arm-trusted-firmware/include/drivers/arm/cryptocell/cc_rotpk.h 3ffecadd4db08d4069780170baac205025ed7194 - arm-trusted-firmware/include/drivers/arm/cryptocell/712/rsa.h c55427770d64593e3cf15b3ed93e6488363b575d - arm-trusted-firmware/include/drivers/arm/cryptocell/712/cc_pal_types.h 10652996fa07e69877d9fb73449f7ab46d59ffa3 - arm-trusted-firmware/include/drivers/arm/cryptocell/712/util.h fc07b65f9cc014a0b1524b0068e8beccf88374cc - arm-trusted-firmware/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h d82ceff72eee2f6f805404b84357273d1eb09561 - arm-trusted-firmware/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h e610cb68e48f78caf111024d142af863b6398636 - arm-trusted-firmware/include/drivers/arm/cryptocell/712/crypto_driver.h e14a50e8d5c68b36920485b6db04f106817437e3 - arm-trusted-firmware/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h d73a1ca5bfea93a55e5c13b2b3f2051e3c0d7c12 - arm-trusted-firmware/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h 260990d658ffc91bafbece3081bb60c30618fa38 - arm-trusted-firmware/include/drivers/arm/cryptocell/712/nvm_otp.h 4639b7108f03bef1a92e980f8ee8eff03be1d869 - arm-trusted-firmware/include/drivers/arm/cryptocell/712/secureboot_base_func.h 49417191c51d1d9274572285c8ba5a8c8146e57f - arm-trusted-firmware/include/drivers/arm/cryptocell/712/nvm.h 5d04efda071e5940b11e2d270b3dae82a55dc93d - arm-trusted-firmware/include/drivers/arm/cryptocell/712/cc_sec_defs.h 6e4f8a88b84a4ce3b762b6c7f14ac5fec8744012 - arm-trusted-firmware/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h fb12a0265111fe6f1b941f06d20f54b9439c689a - arm-trusted-firmware/include/drivers/arm/cryptocell/713/bsv_error.h a9419e34fbc18ae5da0ef1566f5febc0cf829211 - arm-trusted-firmware/include/drivers/arm/cryptocell/713/cc_pal_types.h 13f5321936540bd85461ffa7ef611ca5d4082977 - arm-trusted-firmware/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h 5ff025817e96abd32dab9c26c2d10d5116b211f8 - arm-trusted-firmware/include/drivers/arm/cryptocell/713/bsv_crypto_api.h a182cb9bf34d396f46abd93062d06ce6ee8889c1 - arm-trusted-firmware/include/drivers/arm/cryptocell/713/cc_address_defs.h a8d2ea546937a35c7f822dd9e1a7e8eb3fd4438f - arm-trusted-firmware/include/drivers/arm/cryptocell/713/cc_boot_defs.h f48f4abf712cac68d01844cb146aa3c6e787e97c - arm-trusted-firmware/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h 513b5a19f2f0b580cf670eca60e57e793cac539f - arm-trusted-firmware/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h 93088698293330d0f56eaabb73e01615b19fed64 - arm-trusted-firmware/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h bf88a456fd40edb9bb68b2450d6251cda06f2465 - arm-trusted-firmware/include/drivers/arm/cryptocell/713/cc_sec_defs.h b69f3dd73cff9fd442b44ed25f2edbb0bc3baa5f - arm-trusted-firmware/include/drivers/arm/cryptocell/713/bsv_api.h 749ed7a2a602879315a2a407faa53d9fcc6f4242 - arm-trusted-firmware/include/drivers/arm/fvp/fvp_pwrc.h d3887ee8e4681e5e21d22c78756f8bb537359ef0 - arm-trusted-firmware/include/drivers/rpi3/sdhost/rpi3_sdhost.h 898f43097b2545ca29358b143d6e97761f1dbce4 - arm-trusted-firmware/include/drivers/rpi3/rng/rpi3_rng.h affa2c8404660a48bcd956f29a50e79120b1cc3b - arm-trusted-firmware/include/drivers/rpi3/gpio/rpi3_gpio.h 8865e3a5b086a9f57937f94373c1488796422a75 - arm-trusted-firmware/include/drivers/rpi3/mailbox/rpi3_mbox.h 04830d2bd9eaac4d5ab2cf414e66ae7439c3832d - arm-trusted-firmware/include/drivers/cfi/v2m_flash.h 6092827f0eb5f3c784b6a1da04df8d26918b01c5 - arm-trusted-firmware/include/drivers/renesas/rcar/console/console.h 1c35b8d1dd99e2556585b97e6c5f472b95565fd0 - arm-trusted-firmware/include/drivers/amlogic/meson_console.h 598adf21c9089a664c913fb3faf852fa36dddef8 - arm-trusted-firmware/include/drivers/amlogic/crypto/sha_dma.h 99694a5f2e9c541d163aa4fc3bae8f07cdd32b4c - arm-trusted-firmware/include/drivers/nxp/dcfg/dcfg.h 95b4d87dfcfc29bdf2b6cd0bbb06749112243507 - arm-trusted-firmware/include/drivers/nxp/dcfg/dcfg_lsch3.h 060901911b3564bae52c8476be0a91ea019b2283 - arm-trusted-firmware/include/drivers/nxp/dcfg/dcfg_lsch2.h e81281948e932f6635309e0cc817672144dd5cc1 - arm-trusted-firmware/include/drivers/nxp/dcfg/scfg.h f76687e9c42877c6684b9f0f42809be11e898f2e - arm-trusted-firmware/include/drivers/nxp/ddr/opts.h a38ba636dc7402ba5f0f12fac9db9813190a8c39 - arm-trusted-firmware/include/drivers/nxp/ddr/regs.h 3b20fa259fde3f160db7996e9571edfc5ab34bc5 - arm-trusted-firmware/include/drivers/nxp/ddr/ddr_io.h 90e8213c057c2449b5ba645b49e85458c0dc2e43 - arm-trusted-firmware/include/drivers/nxp/ddr/dimm.h d0fc8c7cc714365c4b36dc3b12083432b0173dd3 - arm-trusted-firmware/include/drivers/nxp/ddr/immap.h 190e1845f17fd2f9c9e7fdcb31f62f22735c2401 - arm-trusted-firmware/include/drivers/nxp/ddr/ddr.h 2b66abb34254db06ee8c88f5e0596c908b2d2026 - arm-trusted-firmware/include/drivers/nxp/ddr/utility.h d8d9fce57d178fdfd41f5be63879bfa85d2e2e15 - arm-trusted-firmware/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h 07aabe0c38fbe8ae82313542589e8b6013f0a704 - arm-trusted-firmware/include/drivers/nxp/qspi/qspi.h 46896393ac73e49d174031ad9db2b897a5a53cd5 - arm-trusted-firmware/include/drivers/nxp/timer/nxp_timer.h 56618eda200d872addc06447897a8b7ec619ffb8 - arm-trusted-firmware/include/drivers/nxp/pmu/pmu.h 225ffbb6a71c970da33f40390a7828768770c824 - arm-trusted-firmware/include/drivers/nxp/tzc/plat_tzc380.h b0e9643a90314ef89452944214806403f53b7b54 - arm-trusted-firmware/include/drivers/nxp/tzc/plat_tzc400.h 2388bdc4442c2695122e844d49738f95b18a84cf - arm-trusted-firmware/include/drivers/nxp/csu/csu.h 69289264b7a28a5ce23aa04ce828d8b4af255860 - arm-trusted-firmware/include/drivers/nxp/flexspi/xspi_error_codes.h ce837ddd809c0d8f381cefc82d212e9a1a20209b - arm-trusted-firmware/include/drivers/nxp/flexspi/flash_info.h 7989591e2a2162069486ebab7e2728208c51b5c2 - arm-trusted-firmware/include/drivers/nxp/flexspi/fspi_api.h be8a6b00a6db26fef151d90020cd12c856e4cacd - arm-trusted-firmware/include/drivers/nxp/i2c/i2c.h 3d4947f956585eb9cfe3b8245ad4c1749cdc72b1 - arm-trusted-firmware/include/drivers/nxp/sec_mon/snvs.h ccb0701fec1000c00375edbf0318bdce6617b109 - arm-trusted-firmware/include/drivers/nxp/smmu/nxp_smmu.h 7f0601b767be7522d2b3b053924b860224900737 - arm-trusted-firmware/include/drivers/nxp/ifc/ifc_nor.h cd9ce08e3ca357e9ac083fd384e2ffd154288032 - arm-trusted-firmware/include/drivers/nxp/ifc/ifc_nand.h f75c54f08edcc8069804184e40a6d8a74d3d1b42 - arm-trusted-firmware/include/drivers/nxp/sfp/sfp.h 3584254639e10b77ffd6ccf07f7a59923b337ffe - arm-trusted-firmware/include/drivers/nxp/sfp/sfp_error_codes.h b6baa4f2facaae8fcb1873db219796f86e62cbbf - arm-trusted-firmware/include/drivers/nxp/sfp/fuse_prov.h 460f93da77ff4c52f61d06eca41dc83c56a92b6d - arm-trusted-firmware/include/drivers/nxp/crypto/caam/rsa.h 2c95c38a7f65a3ef7eb3992c7136879ef75e4c7a - arm-trusted-firmware/include/drivers/nxp/crypto/caam/caam.h 66189a3d70ccfb57441e34458abfc9cd72c29d19 - arm-trusted-firmware/include/drivers/nxp/crypto/caam/sec_hw_specific.h bf836adf23266f3749b5e68af59a31d0ac0ea00a - arm-trusted-firmware/include/drivers/nxp/crypto/caam/jr_driver_config.h 8308e3c4607508799254cc82d52ec5d4aba905e2 - arm-trusted-firmware/include/drivers/nxp/crypto/caam/sec_jr_driver.h 91adf35b394ad394248624343b9c5b19fa0c2b09 - arm-trusted-firmware/include/drivers/nxp/crypto/caam/jobdesc.h 57d421cf90453e8aa05285508bc43ed0e325a7a7 - arm-trusted-firmware/include/drivers/nxp/crypto/caam/hash.h fc12ffe1d77603728f2c875a296218ae6cddb095 - arm-trusted-firmware/include/drivers/nxp/crypto/caam/caam_io.h 4229b536f33d8f4775076953d8c91ea47ad378a5 - arm-trusted-firmware/include/drivers/nxp/console/plat_console.h 26748e486ff05a3ed33d842cba65e4fecc362aae - arm-trusted-firmware/include/drivers/nxp/gpio/nxp_gpio.h aabedc9062342279b677c72861038190cfa65939 - arm-trusted-firmware/include/drivers/nxp/sd/sd_mmc.h ad1aee42247671abf00ceef8e5ddff7485a73431 - arm-trusted-firmware/include/drivers/nxp/gic/gicv3/plat_gic.h 141c6ec9750c86044338eb19ee622331b9a6c0d8 - arm-trusted-firmware/include/drivers/nxp/gic/gicv2/plat_gic.h eb200bcc06472d689f3a7419f0710c4c3d8ce0c5 - arm-trusted-firmware/include/drivers/nxp/interconnect/ls_interconnect.h 4453a2af06ed170ae6c69f42b415c69314fd3d9b - arm-trusted-firmware/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h 67ec9883d9b0ac3959b68dcf32dbf8d8fbc84bc8 - arm-trusted-firmware/include/drivers/brcm/scp.h 5632d0130d0787f77618a2ca64d09d7bc3d2433b - arm-trusted-firmware/include/drivers/brcm/usbh_xhci_regs.h 2dedb1c6a08bb98fab574fbb49becf23a0a40b3d - arm-trusted-firmware/include/drivers/brcm/dmu.h 3b8d411ed511e8d5f5cd285a04229eb0779c2609 - arm-trusted-firmware/include/drivers/brcm/iproc_gpio.h 04cc0e519d24a6729fbf6f89e981eaf992fe19d5 - arm-trusted-firmware/include/drivers/brcm/sf.h 2a62cccb75603f1abe573a211d9b149826e87356 - arm-trusted-firmware/include/drivers/brcm/chimp_nv_defs.h 542f2f80df9c9b264f0bfc9387e38e99ad2a9e7b - arm-trusted-firmware/include/drivers/brcm/spi_flash.h 8c4e00a589a41eac59a1e3f7743e362f874b80cd - arm-trusted-firmware/include/drivers/brcm/fru.h 5afc35a13cf962ad7cd0f15b0532bbe11c7ad17a - arm-trusted-firmware/include/drivers/brcm/ocotp.h f1e9babc3d5e854ba472c64f889f2fb01138cff0 - arm-trusted-firmware/include/drivers/brcm/chimp.h 907603dcc9f90f3393201ab4a2a5c8ce32f61543 - arm-trusted-firmware/include/drivers/brcm/sotp.h 823fbabdd578bbfbf92d8a2d68e8d7d2c3f652cd - arm-trusted-firmware/include/drivers/brcm/spi.h af14073522c90e3d69b0abc31fd3a2820dc54d47 - arm-trusted-firmware/include/drivers/brcm/emmc/bcm_emmc.h 40a4365490452d1db063c69f305c46be1d20e9f5 - arm-trusted-firmware/include/drivers/brcm/emmc/emmc_chal_sd.h 869edd881664c3e2332d5b2e6765e7dacbb0afb7 - arm-trusted-firmware/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h 5e1781b653944c224e65bec032fae482c1925591 - arm-trusted-firmware/include/drivers/brcm/emmc/emmc_csl_sdprot.h eafab2881a9d078ab544df13644c4b47b0670003 - arm-trusted-firmware/include/drivers/brcm/emmc/emmc_csl_sdcmd.h 38ad4c8652f178df916a5a1622fad23851187ba2 - arm-trusted-firmware/include/drivers/brcm/emmc/emmc_csl_sd.h d6123ce1d15ed92eb457d0e0d13d66841deb34ea - arm-trusted-firmware/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h c3be01e418a0c44f650529178aabc99c5fdbef33 - arm-trusted-firmware/include/drivers/brcm/emmc/emmc_api.h 5657b1337210a575a742026dfa31f3136b5bb625 - arm-trusted-firmware/include/drivers/brcm/emmc/emmc_chal_types.h 281ab6dc0343aa92cc689456d9b8b56e7e853961 - arm-trusted-firmware/include/drivers/brcm/mdio/mdio.h ba4c82c4f42cf7c6060c7266d23de675e741a191 - arm-trusted-firmware/include/drivers/brcm/i2c/i2c_regs.h 829056e15314b731c22b87d62a2c8606e72e1fb8 - arm-trusted-firmware/include/drivers/brcm/i2c/i2c.h f2ca7edf66b0d71fec9b893659707c7675f9d0a6 - arm-trusted-firmware/include/drivers/st/regulator_fixed.h e545051ef77d33ec66036fa94f2d53b51253d436 - arm-trusted-firmware/include/drivers/st/stm32mp1_ddr_helpers.h 156ba43b85065027d400a1287fa794a828df162b - arm-trusted-firmware/include/drivers/st/stm32mp1_clk.h eaf998cd31b2112d0a61198a5a7f14d484217251 - arm-trusted-firmware/include/drivers/st/regulator.h 6c00673ea5fb61808caf3b77e422043972ecafc7 - arm-trusted-firmware/include/drivers/st/stm32_qspi.h e6aa4130f95dc7da0f3a94482c2ee3325afdf0a0 - arm-trusted-firmware/include/drivers/st/stm32mp_ddr.h 16d36c74e72bc40e7ba15ea25ce38621a3dc3a9e - arm-trusted-firmware/include/drivers/st/stm32_console.h a832f792f5fc9564b02d96f85430f190c3f57417 - arm-trusted-firmware/include/drivers/st/stm32mp_clkfunc.h c13f39e45ffdff80cfe87c12423322a15b959794 - arm-trusted-firmware/include/drivers/st/stm32mp1_ddr_regs.h 967e02371bf07f76cf015635f5a50c0956176296 - arm-trusted-firmware/include/drivers/st/stm32mp1_usb.h b0e57331d216261ea6ec7814666ae64bd884dc05 - arm-trusted-firmware/include/drivers/st/io_mmc.h ff21abb6526ad91314e2f7cc58fa6fd6546c926f - arm-trusted-firmware/include/drivers/st/stm32_sdmmc2.h 86a1ad6cd3ce837f820ba6c1b9f6ee7182e74956 - arm-trusted-firmware/include/drivers/st/stm32_fmc2_nand.h 173981f3ca549df6d0e56fd0a16e4a055b9151eb - arm-trusted-firmware/include/drivers/st/stm32mp15_rcc.h 1b6f5d6f48fb0ceab8d15c6308e31e78e85bddba - arm-trusted-firmware/include/drivers/st/stm32_uart_regs.h 012bc14e697b26babd60ebc5e4d71cb855c093c5 - arm-trusted-firmware/include/drivers/st/stm32_saes.h bcfc65cd26c42c404b6482da16cdacf6e95c5733 - arm-trusted-firmware/include/drivers/st/stm32_iwdg.h 58a87d375953ce331a480d18ecbe92da88b221df - arm-trusted-firmware/include/drivers/st/bsec.h e86b4fde780cfae34213629b58ff8e1efd1eed73 - arm-trusted-firmware/include/drivers/st/stm32mp_ddrctrl_regs.h 7acaf13dfc8356f89ef051644b5a0453c01c9d81 - arm-trusted-firmware/include/drivers/st/stm32_pka.h cacf83dd6e129df0a9ffedbd38bfb757074d1240 - arm-trusted-firmware/include/drivers/st/etzpc.h ec0355e035856ac49891ebbbfb6b249439fe6bc2 - arm-trusted-firmware/include/drivers/st/stm32mp1_rcc.h 1735a240af4b99862e6cb202fc034231abeb53bd - arm-trusted-firmware/include/drivers/st/stm32mp_ddr_test.h 45a56579470aa4ad7e007373a068f3285f046de0 - arm-trusted-firmware/include/drivers/st/stpmic1.h e02eff807301ff7775369975495cad2a2082972f - arm-trusted-firmware/include/drivers/st/stm32mp13_rcc.h 51b50b86f5dea96ef59764df60f2d64a45d54bf1 - arm-trusted-firmware/include/drivers/st/stm32mp1_ddr.h 431e908bb797e10b7839fe28a0ace7d8a9e7bf99 - arm-trusted-firmware/include/drivers/st/stm32mp1_ram.h eae4fb4ef015039f57a757e732fbfa815bc9aeb1 - arm-trusted-firmware/include/drivers/st/bsec2_reg.h 6e705f58e33f92038f70bef6cfbe96e9c14a8d75 - arm-trusted-firmware/include/drivers/st/stm32_uart.h ae8d33f6e04e5baf46e8b00b1613dca79c462e1b - arm-trusted-firmware/include/drivers/st/stm32mp_pmic.h 4cdb146eb6fe5439dec2c5039a903ed5baee6aa6 - arm-trusted-firmware/include/drivers/st/stm32mp_reset.h 91bfb605e20bff6aead18279afab90eed7856ddd - arm-trusted-firmware/include/drivers/st/stm32mp1_pwr.h ac1cd6d311e2280721ba62f9e82c10322f6dad41 - arm-trusted-firmware/include/drivers/st/stm32mp_ram.h 7574c3687634e56e414a47e0fb3f5a5d7b1fc708 - arm-trusted-firmware/include/drivers/st/stm32_gpio.h b6eb16d19f62ff88852eab346d51d719944f14ed - arm-trusted-firmware/include/drivers/st/stm32_i2c.h 837212152227738be545a2d712a87729e35817de - arm-trusted-firmware/include/drivers/st/stm32_hash.h d688f9d156778709e953056a9145ea0e886a0212 - arm-trusted-firmware/include/drivers/st/stm32_rng.h c7235a5c0dc2db938ba5586b4a94294d0c1cef98 - arm-trusted-firmware/include/drivers/auth/img_parser_mod.h 125b1a75a3651ff04f7dd19ba665ccb6846f3a0b - arm-trusted-firmware/include/drivers/auth/auth_common.h 487e2e7025ad4207cb2dc1e52045c91796c5f00d - arm-trusted-firmware/include/drivers/auth/auth_mod.h 9dbd2762dc2015a7f3cd978b434bc1e073dd5f4e - arm-trusted-firmware/include/drivers/auth/crypto_mod.h 21f2b4221f273c0afed79420c75126131f6cbd5a - arm-trusted-firmware/include/drivers/auth/tbbr_cot_common.h 1295704504b1cd641f06e3789718d73f7995cd88 - arm-trusted-firmware/include/drivers/auth/mbedtls/mbedtls_config.h 8990234b68caadc3262242514364a5e4326b0c2f - arm-trusted-firmware/include/drivers/auth/mbedtls/mbedtls_common.h 41a9e785cff8ee17c58544900ad2cf351862fb31 - arm-trusted-firmware/include/drivers/cadence/cdns_uart.h 835fd8c82abcfae1bf3c5dceb1123a8b2bfd587d - arm-trusted-firmware/include/common/ep_info.h b0aadb059bd035c38b54ce8f2f7690b49b417e5a - arm-trusted-firmware/include/common/param_header.h 1fb3546ddcbbdb34f1bd8c5532fde531ed03e4fd - arm-trusted-firmware/include/common/runtime_svc.h 89063961a49fd394d2f83cb8bdf4b9dac1dba3c1 - arm-trusted-firmware/include/common/bl_common.ld.h cb99cbb9841e788adfe908cda31322399f53874a - arm-trusted-firmware/include/common/feat_detect.h a55024ef7fc69aa6ca1eb047f4af38d5c179bb16 - arm-trusted-firmware/include/common/bl_common.h ff9dcfa75dfbd082499e82016cf0b462fd635d8a - arm-trusted-firmware/include/common/fdt_fixup.h 4fc9a65c3b860622f142a8ce569d5919c1cb3160 - arm-trusted-firmware/include/common/fdt_wrappers.h f3ec87cdd303cc80ab1975ee4c970c1d72f2a1d9 - arm-trusted-firmware/include/common/desc_image_load.h 496c9494294abdf4875957c267086b10cf5a0c8c - arm-trusted-firmware/include/common/debug.h 5afd89832d7eb27979b6864884c4c5564a60279d - arm-trusted-firmware/include/common/romlib.h 9acd7a0a005acdb9eb6ee122677ee9528b36b6e0 - arm-trusted-firmware/include/common/nv_cntr_ids.h 3061ebcc5cc39e9b66461188d5eccd5bef4173d0 - arm-trusted-firmware/include/common/image_decompress.h b46a10bce55c312c93a16f506296f5642158a823 - arm-trusted-firmware/include/common/asm_macros_common.S 0adc1932137e9f09ebf8948f60d0bb0258ad0249 - arm-trusted-firmware/include/common/tf_crc32.h 2dd54092e4d1c788d0bbc6de650d021598d718f4 - arm-trusted-firmware/include/common/uuid.h 227245db4039eba1e0adf3fc9e0ef8e7ed8401a4 - arm-trusted-firmware/include/common/interrupt_props.h 22b063584c188624815fe5a57f199b9bde282c6a - arm-trusted-firmware/include/common/tbbr/tbbr_img_def.h b6ecc0e4dc99c28cefb717fd64a04cc4d11a5161 - arm-trusted-firmware/include/common/tbbr/cot_def.h 5027c09d49b1a717834fc13eec3e95b198226028 - arm-trusted-firmware/include/services/rmm_core_manifest.h f9e8e6beb1285dc1b188488dc9a217ba805b04e1 - arm-trusted-firmware/include/services/pci_svc.h d3bd4cf8e1c91ab4b8019456b7e19c3fd4675567 - arm-trusted-firmware/include/services/spm_mm_partition.h 37203234339e07aa2a107fa1570823a0970e8ee1 - arm-trusted-firmware/include/services/drtm_svc.h bd59ae9370224873185cfa4dfc1459db223f86d3 - arm-trusted-firmware/include/services/spm_core_manifest.h 55d7730a8a395727bfe396de26d51f8823e42b9a - arm-trusted-firmware/include/services/rmmd_svc.h 6b3525de0de5c707191677733b6c49dba80eed96 - arm-trusted-firmware/include/services/sdei_flags.h dea401b5fd2f174de5e57f9170ef8b02f491fc33 - arm-trusted-firmware/include/services/ffa_svc.h 5ec97fddcf40cdae74d90a9ac0389ac037f2f467 - arm-trusted-firmware/include/services/el3_spmc_ffa_memory.h 68410e63432d33f0661dc522bdffc99b13f92cd0 - arm-trusted-firmware/include/services/spmc_svc.h c322c63ec8512fae64ddf64b16f555410861459c - arm-trusted-firmware/include/services/sdei.h 5125f9c7ece259839fb0aa8436a45dac93c5a650 - arm-trusted-firmware/include/services/el3_spmc_logical_sp.h 583482e243ae52386041c084650c8579a1f113ab - arm-trusted-firmware/include/services/std_svc.h e7744d6577eca544cbed5801a58c554d3de82c3b - arm-trusted-firmware/include/services/trng_svc.h aa22fd8202b23470dcc741cf483f45edec3ea3bb - arm-trusted-firmware/include/services/spmd_svc.h 3b7a4c6d6c8ce3c42694e589dd7dd5d4ed7a4ced - arm-trusted-firmware/include/services/spm_mm_svc.h 53e733abf11ec08954e5e64474973896323d428b - arm-trusted-firmware/include/services/arm_arch_svc.h 44872a34c3f4a6ea08edc9cce511fc1f751a27a6 - arm-trusted-firmware/include/services/trp/platform_trp.h da36e4f102ab7a3b74920159b62a0bd87876f9cc - arm-trusted-firmware/include/services/trp/trp_helpers.h b296aa0c1c6575bc1a961fcbf21420aa5e6c0d3b - arm-trusted-firmware/include/bl31/bl31.h e53a01933d21a638975882b707f1db89c42dca54 - arm-trusted-firmware/include/bl31/sync_handle.h d71e9d9b24d7c7ced1c1c898952a38819c97c0a1 - arm-trusted-firmware/include/bl31/interrupt_mgmt.h 40a0dcdf3add2805bf312c4548d2ee377fc8e4db - arm-trusted-firmware/include/bl31/ehf.h 89971e627f1aaad3902b29c72eef83520766be40 - arm-trusted-firmware/include/bl31/ea_handle.h 618289fd2c98548dbc401a283df9d3c6386ce002 - arm-trusted-firmware/include/plat/marvell/armada/a3k/common/plat_marvell.h 71dfe89c5f0b7453c5e1af8a81c440aea8ecb34b - arm-trusted-firmware/include/plat/marvell/armada/a3k/common/board_marvell_def.h e6b0db0b8079bfb25c6c3257a0bc6403591a354f - arm-trusted-firmware/include/plat/marvell/armada/a3k/common/armada_common.h 98c1515593c3e784076edd107c7aa20f26d00900 - arm-trusted-firmware/include/plat/marvell/armada/a3k/common/marvell_def.h f1567dc5b7ad98ac1f602cf6a7ec37025de4b2b5 - arm-trusted-firmware/include/plat/marvell/armada/a8k/common/plat_marvell.h 79fec062b150f074e53c3a4b1987aea42e5a4eff - arm-trusted-firmware/include/plat/marvell/armada/a8k/common/board_marvell_def.h 5eb5b60a95f1d5821d119a38a870719cd6345ca8 - arm-trusted-firmware/include/plat/marvell/armada/a8k/common/armada_common.h 36e0657b50b40ad54b3ef6b8b6848377fa423ee2 - arm-trusted-firmware/include/plat/marvell/armada/a8k/common/marvell_def.h 48923d6fcb9d9e02790b158b5eaf6edb34db109d - arm-trusted-firmware/include/plat/marvell/armada/a8k/common/efuse_def.h 6e72bb219cdd7c32b97b3df3a2fd695dab5d6fc4 - arm-trusted-firmware/include/plat/marvell/armada/a8k/common/plat_pm_trace.h dc4318dff472842b4c63c7b87f23c3688def3c5a - arm-trusted-firmware/include/plat/marvell/armada/common/mvebu.h 8cdfa6f8ca1d681ba760da2fe49c8f365ef0dcbe - arm-trusted-firmware/include/plat/marvell/armada/common/marvell_plat_priv.h 9dd486928223e599a25bc6f13b414fc57c242b36 - arm-trusted-firmware/include/plat/marvell/armada/common/marvell_pm.h e2d034b7bbecdf28360fcf107159eae0bf87de48 - arm-trusted-firmware/include/plat/marvell/armada/common/aarch64/cci_macros.S b7faf2c71aa5d9ab793eadfeb28cd9effe284930 - arm-trusted-firmware/include/plat/marvell/armada/common/aarch64/marvell_macros.S 9cd1950e6a5ff8b2dcd0143c1dfe498c7804a1f0 - arm-trusted-firmware/include/plat/common/plat_trng.h ec1ba9f6e5e5199a8174963440c8673120fd65e0 - arm-trusted-firmware/include/plat/common/common_def.h c0d4235ef65c7a367e61417da13920825d2be61e - arm-trusted-firmware/include/plat/common/plat_drtm.h a400f7817b11c401e85ffb90776dea9b1011c6f2 - arm-trusted-firmware/include/plat/common/platform.h faf44d2a7589fe39f462d8b88f1d1283e1356a89 - arm-trusted-firmware/include/plat/arm/css/common/css_pm.h 0081d14a9dd87bdab5919da6391eb2275fa7e94a - arm-trusted-firmware/include/plat/arm/css/common/css_def.h 406bbb095f6bf7f140e7814e98b0ea99062ad767 - arm-trusted-firmware/include/plat/arm/css/common/aarch64/css_macros.S 85db4d68c709e11a4b63da0a434f5aeeef2aadec - arm-trusted-firmware/include/plat/arm/common/arm_fconf_io_storage.h 88fe915ca8ec7f1f3499a57f534e1396c6b7c98e - arm-trusted-firmware/include/plat/arm/common/smccc_def.h fdc727288dd453b4dcf18b744fc052a039bed405 - arm-trusted-firmware/include/plat/arm/common/arm_dyn_cfg_helpers.h 3e4bae22a7f832c776c0793b388068639b647bdc - arm-trusted-firmware/include/plat/arm/common/arm_def.h 441bc7cb069295fd0995018d47390e692c10513b - arm-trusted-firmware/include/plat/arm/common/plat_arm.h 3b7cf1ed6c9020d616700dd02676386d4684700d - arm-trusted-firmware/include/plat/arm/common/fconf_arm_sp_getter.h 36a2614776249ab76e9c86d1f08fd0057bab8263 - arm-trusted-firmware/include/plat/arm/common/arm_config.h 9437b8c5d8cf84ec02a69c03b1658cfe00ce9a70 - arm-trusted-firmware/include/plat/arm/common/arm_tzc_dram.ld.S cf73db69545d572b4f64aa05eefbbfd90153820f - arm-trusted-firmware/include/plat/arm/common/fconf_ethosn_getter.h 0afd9c0926d88821488dcd5686914fd1ccee3763 - arm-trusted-firmware/include/plat/arm/common/fconf_sdei_getter.h f0fb541bb623a169168129c94b788f2a409ffb5b - arm-trusted-firmware/include/plat/arm/common/fconf_sec_intr_config.h ff214af31c4e9b87c606562841632465464dfd77 - arm-trusted-firmware/include/plat/arm/common/arm_sip_svc.h eb2f94f2fc7e75343b6ebf27607b356ad90cdb7f - arm-trusted-firmware/include/plat/arm/common/arm_fconf_getter.h e578e001c2256e4085ed395b219161a17e2cdd9a - arm-trusted-firmware/include/plat/arm/common/arm_pas_def.h 44ce8058a0b197c5c89e419bcebc0ddcd8434c36 - arm-trusted-firmware/include/plat/arm/common/arm_spm_def.h 971368d067997c8cf7b990346646cedab7fb9189 - arm-trusted-firmware/include/plat/arm/common/fconf_nv_cntr_getter.h 2c4584c2c02301f10799d0e6b2616ff24a89b47d - arm-trusted-firmware/include/plat/arm/common/arm_reclaim_init.ld.S 3bb163e8411b70a5b6f5913631e64392b3154151 - arm-trusted-firmware/include/plat/arm/common/aarch64/arm_macros.S 657f1176fd4f82dc1155d86438b6fbf624d2747a - arm-trusted-firmware/include/plat/arm/common/aarch64/cci_macros.S a4c302b222e019205abf65fd01745d571d810ce7 - arm-trusted-firmware/include/plat/arm/soc/common/soc_css_def.h 64f1e7c2408515cbabe2321cf6584901213dcf2b - arm-trusted-firmware/include/plat/arm/soc/common/soc_css.h fe0efb2292b7b971908fcd44d634894276a51f1c - arm-trusted-firmware/include/plat/arm/board/common/v2m_def.h 81ed90e8c99ac6343426728d9299d8ad48305d39 - arm-trusted-firmware/include/plat/arm/board/common/board_css_def.h 40577c7bc2464cf873f1f2708e2db8112b51374f - arm-trusted-firmware/include/plat/arm/board/fvp_r/fvp_r_bl1.h d7f8e1c595627094eb1807e5f15cbb7674cb02d5 - arm-trusted-firmware/include/plat/brcm/common/bcm_console.h e639b2614ce8c77a52995ee2da45fe54fbb8dc2e - arm-trusted-firmware/include/plat/brcm/common/brcm_def.h 5d91bb2b767050d467d072d4e6d7036d8c71d06a - arm-trusted-firmware/include/plat/brcm/common/bcm_elog.h 0ad5bfa2837c10aafe72e696c238db4ebd82794f - arm-trusted-firmware/include/plat/brcm/common/plat_brcm.h b7307a0a106f93b2429fa105547d42bc65f8afc2 - arm-trusted-firmware/include/dt-bindings/reset/stm32mp15-resets.h 0ca59c4b41f2264bcc0d4b45550b8a587211aece - arm-trusted-firmware/include/dt-bindings/reset/stm32mp13-resets.h c5098c5b107f74cd689ca039a39721bc1ecb7523 - arm-trusted-firmware/include/dt-bindings/reset/stm32mp1-resets.h 5c7d53dffc9e4dbe1b29a7a3f2c66a36954dd32d - arm-trusted-firmware/include/dt-bindings/soc/stm32mp13-tzc400.h f237c837e7f3ca6eb78a837961cc378136eb56a4 - arm-trusted-firmware/include/dt-bindings/soc/stm32mp15-tzc400.h 4b89cad3c01b7767a5a3a13de49705b2cb3e7f9e - arm-trusted-firmware/include/dt-bindings/soc/st,stm32-etzpc.h 7efe8c0a3fbb4e9b29850fac16b475c45925c6e3 - arm-trusted-firmware/include/dt-bindings/pinctrl/stm32-pinfunc.h f28db646c8bdd11bb9593e0d241d924482a7d3ad - arm-trusted-firmware/include/dt-bindings/clock/stm32mp15-clks.h bd297c8c069baf4894e271462ecd0387ca142d2b - arm-trusted-firmware/include/dt-bindings/clock/stm32mp15-clksrc.h e0d1075d19bd35b9bf189dad00ef6b45991c1bf0 - arm-trusted-firmware/include/dt-bindings/clock/stm32mp1-clks.h 080c331a370bfcf9f9ce11ccdc89838ea7fd401c - arm-trusted-firmware/include/dt-bindings/clock/stm32mp1-clksrc.h fd1e043f322c708de5aa529250ef0ca7430cc508 - arm-trusted-firmware/include/dt-bindings/clock/stm32mp13-clksrc.h f8dfb28848429d1ddd93107a95f47d8c6701e359 - arm-trusted-firmware/include/dt-bindings/clock/stm32mp13-clks.h 56af3734637f9dcf2f75c88aad9614e515be1570 - arm-trusted-firmware/include/dt-bindings/interrupt-controller/arm-gic.h 3a4737826d5e90e262be765553886dc9b2cad966 - arm-trusted-firmware/include/dt-bindings/interrupt-controller/irq.h c8e4bf0f7dc18bfbfdfaa6261fb61aa8c47b18e7 - arm-trusted-firmware/include/bl32/pnc/pnc.h cb4a166015b83acf19a78617be8e774abc6e1798 - arm-trusted-firmware/include/bl32/payloads/tlk.h 2e44c81aaa54a5499ffaf341151168a669ea79cd - arm-trusted-firmware/include/bl32/sp_min/platform_sp_min.h dc1975b639c5dc6b8eee34ada66bffcbd10d3047 - arm-trusted-firmware/include/bl32/tsp/tsp.h 61531a0b7ca81943d7aebe7d3183f30c4b6b42b7 - arm-trusted-firmware/include/bl32/tsp/platform_tsp.h e1699b761cd12de148f701d78db5c24eb3aa7251 - arm-trusted-firmware/include/export/README 9367cefce0520648ccdaad1fe3a402422becdf55 - arm-trusted-firmware/include/export/drivers/gpio_exp.h 60669a2cabdf40b63773d538d47861c1a584f800 - arm-trusted-firmware/include/export/common/param_header_exp.h 45ecabce41da084db92b27dd88e6e89f30506036 - arm-trusted-firmware/include/export/common/ep_info_exp.h 9e9bd7336b20288fec4baabb6bf465e2848287e4 - arm-trusted-firmware/include/export/common/bl_common_exp.h 35aa4f2fe7e6e9e87f64206796a921e6888bf218 - arm-trusted-firmware/include/export/common/tbbr/tbbr_img_def_exp.h 9bb9fdc2ec0963a6cbbd0188ae70e368e67755f2 - arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h dcd0ca426668c19ab921df2fefbf2d83ca5afdd8 - arm-trusted-firmware/include/export/plat/rockchip/common/plat_params_exp.h 5091c9e14c49f9799bc9985442295e882a14d3b0 - arm-trusted-firmware/include/export/lib/utils_def_exp.h 72b925e2450734e1991799db8cc30f6a8609462a - arm-trusted-firmware/include/export/lib/bl_aux_params/bl_aux_params_exp.h 0b8f22e03d35106f8213bb63f81feeefe40d0675 - arm-trusted-firmware/include/lib/bakery_lock.h cf5f556d440245d73b0f784be4662e7cd634f39b - arm-trusted-firmware/include/lib/coreboot.h 90db5a8e9962b61142ef6eed7165cb5967d686be - arm-trusted-firmware/include/lib/optee_utils.h 7369ae279a5ff8285dcef7180be78415f46baf6b - arm-trusted-firmware/include/lib/smccc.h 06aee725316857addfb02415a55463647ed20701 - arm-trusted-firmware/include/lib/object_pool.h b1522d52a6103e87ea31e7207f54208dd2c5a6af - arm-trusted-firmware/include/lib/debugfs.h 7ffbca071dbd690b9d0ac30e6b388a848c55cc16 - arm-trusted-firmware/include/lib/semihosting.h 9637b2573e1df004bff5258027eee07e6d532cf9 - arm-trusted-firmware/include/lib/cassert.h 73dc3acb5868e207313dcdae4f6884d5c179faaa - arm-trusted-firmware/include/lib/utils.h de7b34ae4f5c2aa97efbb717d681f3f79f6b3a80 - arm-trusted-firmware/include/lib/mmio.h ed4976b8261e1ee44f4a2b7952563b6db8e63406 - arm-trusted-firmware/include/lib/spinlock.h 1f698e99c775d463461fd358a896217604420ef6 - arm-trusted-firmware/include/lib/runtime_instr.h 3d025e3103c56449f8cd85a563eb11936876c6de - arm-trusted-firmware/include/lib/utils_def.h c4a608146244624d7846ad9c2c37ed2d94bddecf - arm-trusted-firmware/include/lib/psci/psci_lib.h 1c0e9271a240a44ae26fe23c9d0bf4f2aefdbaa8 - arm-trusted-firmware/include/lib/psci/psci.h fad98eab51c54e641e9db5451eceb044f426276c - arm-trusted-firmware/include/lib/fconf/fconf_tbbr_getter.h 1cc2ff30d9d45589c3c7fa34a79ab141314e4974 - arm-trusted-firmware/include/lib/fconf/fconf_amu_getter.h 80dc3095cd932fed81c854b75676225204331fb2 - arm-trusted-firmware/include/lib/fconf/fconf_dyn_cfg_getter.h 531877858c00a04ba41ba7d211235fcad2bf2f77 - arm-trusted-firmware/include/lib/fconf/fconf_mpmm_getter.h 69c25267e6a696496c19ec6594d7cb73396cdce5 - arm-trusted-firmware/include/lib/fconf/fconf.h c90d25bb7b217171ad9437ee0bc8d4e0c5c7f4d3 - arm-trusted-firmware/include/lib/libfdt/libfdt_env.h 26e37a910f19c0fe0293821c838312e998579df1 - arm-trusted-firmware/include/lib/libfdt/fdt.h afe61379d0e4ab239cfab659325f01b81900eadc - arm-trusted-firmware/include/lib/libfdt/libfdt.h d0810db085b9b11a6ec8782407d9e662468892d3 - arm-trusted-firmware/include/lib/el3_runtime/context_mgmt.h db010d01a2298bde5d192dc8ca42d487ad8023ac - arm-trusted-firmware/include/lib/el3_runtime/pubsub.h 926a8f99c7871413aa6c48ee91bcacf8ea07e438 - arm-trusted-firmware/include/lib/el3_runtime/cpu_data.h 4d4c1ed6afee697c60bea690393d2827cb9036cf - arm-trusted-firmware/include/lib/el3_runtime/pubsub_events.h 9c3df6c4d9ecf03368ef7a5cd150157123c12ed1 - arm-trusted-firmware/include/lib/el3_runtime/aarch32/context.h 1f9a11d313ad81e786efda8e51243e4c829a2124 - arm-trusted-firmware/include/lib/el3_runtime/aarch64/context.h 0f9c6bddf555b127d0deea955abd911c85bc89b9 - arm-trusted-firmware/include/lib/mpmm/mpmm.h 64b082be684d2e9aac73592fc4658c81ded65fcc - arm-trusted-firmware/include/lib/xlat_tables/xlat_tables_defs.h a5b742f0a88671c56d4acb2c9f41a2859ccfe63c - arm-trusted-firmware/include/lib/xlat_tables/xlat_tables_v2_helpers.h 748f4763c6956e3a05b07a06f88394f925375806 - arm-trusted-firmware/include/lib/xlat_tables/xlat_tables_v2.h d096d2c939939ac7e3ce5358c63127a2e48fc66d - arm-trusted-firmware/include/lib/xlat_tables/xlat_tables_arch.h 0ea4285dd4504af01f2379c11c6b04292b5224d0 - arm-trusted-firmware/include/lib/xlat_tables/xlat_tables.h 147505a24c5c0680f8c21cd8b77aaa1ed3d9af0f - arm-trusted-firmware/include/lib/xlat_tables/xlat_mmu_helpers.h 6e06bd2959e9326e212bab4a1ef5d6d5f671b6ab - arm-trusted-firmware/include/lib/xlat_tables/xlat_tables_compat.h ef0a81e88f09c2c6ce252f01c0405fa13cf09822 - arm-trusted-firmware/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h 135853a26b41e70bb03df6feaa46157020f24f43 - arm-trusted-firmware/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h a9be03deeaf86090c4056f6844a1dafec0a14683 - arm-trusted-firmware/include/lib/xlat_mpu/xlat_mpu.h f8c54b786887634968bddeccab38c285d831d8a1 - arm-trusted-firmware/include/lib/psa/delegated_attestation.h eaa8691bcb32c78edbd5f3318787a76307addf9b - arm-trusted-firmware/include/lib/psa/measured_boot.h 6a0d32ef6eb88eb04926490a7a7e7e9e60ef2df2 - arm-trusted-firmware/include/lib/psa/psa_manifest/sid.h 9a50d9cc46ce725ec7feb0a606ab049a5d977e76 - arm-trusted-firmware/include/lib/psa/psa/client.h 9929d7145e068add1adeab78298ed4cc893eda3e - arm-trusted-firmware/include/lib/psa/psa/error.h 802b885838cc683c33d5bdf0db010936d1d60c40 - arm-trusted-firmware/include/lib/extensions/sys_reg_trace.h 49864e971e8571d9d0cb63bce06594f6c8b5d684 - arm-trusted-firmware/include/lib/extensions/mpam.h d9ddc757d1632d6d25a30937684cae6ef3ee6a50 - arm-trusted-firmware/include/lib/extensions/spe.h 84ebabfad9a6aea5b36eca181ecacd9f81feaf8b - arm-trusted-firmware/include/lib/extensions/sve.h 09511d96743a49bd6a8ce53a10a7a63f66fa69eb - arm-trusted-firmware/include/lib/extensions/ras.h a3c002de51adf7dd52647cf5c6e3f6e119634fc9 - arm-trusted-firmware/include/lib/extensions/pauth.h fcc42874d57314ab77ad7f2a2c1b2eb3862a576b - arm-trusted-firmware/include/lib/extensions/amu.h 13399de7c17424af3db66047381252029f9f9829 - arm-trusted-firmware/include/lib/extensions/brbe.h 660261bf21ef27aadbbab9d54b3c6300525e06d0 - arm-trusted-firmware/include/lib/extensions/ras_arch.h 08342ec02a973e05865c7a200258f0949f7e0948 - arm-trusted-firmware/include/lib/extensions/trbe.h cc7362066d33e226e7e9996002c683aeb7291017 - arm-trusted-firmware/include/lib/extensions/trf.h 5e43959b0322424d6c58374b9bf52ca3435e88c1 - arm-trusted-firmware/include/lib/extensions/sme.h 38027460aea214583844c4cb07db44077673acc5 - arm-trusted-firmware/include/lib/libc/string.h 0d835510f380ad8267995f98edca212d0c2d8f72 - arm-trusted-firmware/include/lib/libc/errno.h d0d4318e609c76661d8f0144b559d4c7e5c43cce - arm-trusted-firmware/include/lib/libc/limits.h 2f17e8f91531cbdb0dcb5638ffe35b4fc35169f4 - arm-trusted-firmware/include/lib/libc/endian.h 05293dcd9dcd66e6fbc14019807633a277c3a53f - arm-trusted-firmware/include/lib/libc/time.h b37dff6a9fa0fe100e6e204676f60358dfde29eb - arm-trusted-firmware/include/lib/libc/stdlib.h 167e84c7f69dda6dbee48fff38839436941dfe1c - arm-trusted-firmware/include/lib/libc/stddef.h 322120f3ba6d5668335ea4350891bff8dca36adf - arm-trusted-firmware/include/lib/libc/cdefs.h cd4aebb1eae6556c48cf70ab5616a71d15156892 - arm-trusted-firmware/include/lib/libc/assert.h 28d598da1ead2bf6ee9fd764635deb7d1a082fc9 - arm-trusted-firmware/include/lib/libc/stdbool.h fec91d22fe696952ba93c2d1ed6cedfa714a5a7e - arm-trusted-firmware/include/lib/libc/stdint.h 81c5f03ff17004354de01d3e369c0fbfa4826a03 - arm-trusted-firmware/include/lib/libc/inttypes.h 96064295890c1e484dfcf96039b0cf5c4babd361 - arm-trusted-firmware/include/lib/libc/setjmp.h 1f519accd161baa49f478a735728f1b81dd9a443 - arm-trusted-firmware/include/lib/libc/stdarg.h de263df3e964aac45b0a9be4096eb2a12c63d72b - arm-trusted-firmware/include/lib/libc/arm_acle.h 81fc18b0518ed12942398f24157b26767f2b5d58 - arm-trusted-firmware/include/lib/libc/stdio.h 99fb55bd4f7021bebc906bdfbf7f2e0a32e198f9 - arm-trusted-firmware/include/lib/libc/aarch32/stdint_.h 4ffa8f28ee204e4445f86ee9e68903c66fb5487d - arm-trusted-firmware/include/lib/libc/aarch32/stddef_.h 23c362318a90ff79c1855b9811de06b97efd7748 - arm-trusted-firmware/include/lib/libc/aarch32/float.h 1a74940543db527b4e1465a2fd1419f72b1e450d - arm-trusted-firmware/include/lib/libc/aarch32/inttypes_.h 5d60818c76a8f8d0645d40e13fb9c6bba183e2ac - arm-trusted-firmware/include/lib/libc/aarch32/endian_.h 8eaba3f90b7b124e01dd67a505f4e8dac6d42826 - arm-trusted-firmware/include/lib/libc/aarch32/stdio_.h c6119d73104bf3ae1d27bac47db49a0fbbdcd112 - arm-trusted-firmware/include/lib/libc/aarch32/limits_.h 945134d8abfd9b6f15d9b2d515cc7b78709591e9 - arm-trusted-firmware/include/lib/libc/sys/cdefs.h 81dc661e625cc7228b67c09aea60df34e729c283 - arm-trusted-firmware/include/lib/libc/aarch64/stdint_.h a0ec98e34e93c55ac6fc9241cbaed06bc372bb39 - arm-trusted-firmware/include/lib/libc/aarch64/stddef_.h 13cd0817f8e38f22995768011acff261a52b5351 - arm-trusted-firmware/include/lib/libc/aarch64/float.h fc3b05bccf27d1d12af0f292ef9321da22843643 - arm-trusted-firmware/include/lib/libc/aarch64/inttypes_.h 94f633f89b9ae70068fb70432456057bd04bb750 - arm-trusted-firmware/include/lib/libc/aarch64/endian_.h 8741dd9ddf232520a7e68bd21382fd53539b8c5b - arm-trusted-firmware/include/lib/libc/aarch64/stdio_.h e3ba7ed7d41ae3a8c9dd07d94f7bbef48adf165a - arm-trusted-firmware/include/lib/libc/aarch64/limits_.h c881950de56de06d14e10e06d219c0ad40613034 - arm-trusted-firmware/include/lib/libc/aarch64/setjmp_.h 84b28157b2cc81f5a9aa46c6edf2de6083f696bd - arm-trusted-firmware/include/lib/gpt_rme/gpt_rme.h d44192225758ac451b1c5bc5111f98c453327523 - arm-trusted-firmware/include/lib/cpus/wa_cve_2017_5715.h 58569d6f8289cc5c665cc6dd3455a31057e6209f - arm-trusted-firmware/include/lib/cpus/wa_cve_2018_3639.h 7a7b59a035c26b0ced83b40114b596358f1bd2c4 - arm-trusted-firmware/include/lib/cpus/errata_report.h 55da8ccc24cdd5cabba3e346f04694958ca9b84a - arm-trusted-firmware/include/lib/cpus/wa_cve_2022_23960.h ab3b500c80e0bf48a6fa1b8aa0cedb3451312f73 - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a53.h a90685421214c1862d537af563def9b63894e740 - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a32.h f05e12dd19967571232d263c83c6898dc9f9c9b1 - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a17.h 4f2016b0ee0a27a62e127a3e9e49889a8cb0d63e - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a57.h b4398b2cbe8c44396c14071dd547d3b4ae231f11 - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a15.h 7246c771a29d42ce8df39025143fedec1f1d22ea - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a12.h b28242a3c70922add954edac6ef6a6cc27eef33f - arm-trusted-firmware/include/lib/cpus/aarch32/cpu_macros.S 964ef94b44f29b27af9693592b55d5e045c68898 - arm-trusted-firmware/include/lib/cpus/aarch32/aem_generic.h bb26a1dad2c7e0bc860a422313a21fe96c5818e7 - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a7.h 7c549b2ab4e1d1d0e0a845e601e8778c8c5016d1 - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a72.h 4f8e78fb1d10bb5da1ae6792f2775a2e3d34e739 - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a5.h b3f572f2b6af62ea012727754cd52c72ab76a8cb - arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a9.h fe7e88bb537bded4caa68969291e0f7582e7abe1 - arm-trusted-firmware/include/lib/cpus/aarch64/qemu_max.h 316e8929890c4678843eeb9c9f055e3d7b37419b - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a53.h 3dd320abe3def927121347d7608fceb75ada00ec - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a77.h 0c6bcb7046600b3f3eb9304492262d44d10666bc - arm-trusted-firmware/include/lib/cpus/aarch64/dsu_def.h e935e9cfaae5f8493e694641b55553722a98f5cc - arm-trusted-firmware/include/lib/cpus/aarch64/a64fx.h ed260f8199efb4c6b1d32218c83039568c4ef425 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a65.h 44559a7bdfb73f25458f7ca2b0e8c8785ef8827f - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a35.h 70560b6cca33e37badb4f0e52e2781166227184c - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a55.h 38490302ff352b3d2135d055d89658db50f3caa7 - arm-trusted-firmware/include/lib/cpus/aarch64/neoverse_poseidon.h e762cbd4ef8859eb8d8ebd03899ec10c085ce1b5 - arm-trusted-firmware/include/lib/cpus/aarch64/cpuamu.h 9a1b5aa467e9d2d3b68dbfdc3d96397743562185 - arm-trusted-firmware/include/lib/cpus/aarch64/neoverse_e1.h e6acb51c8db67369002f21efe076d2f49d6972c8 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_hunter.h 4f1b3a7c5699c6ae409698b593edbc6ac8d2a861 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a73.h 7de432330be3e8f54c1e573f4ab59d51806e7365 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_hayes.h 483fe1017bc8ab108421aed0dbccf4272fb07ade - arm-trusted-firmware/include/lib/cpus/aarch64/neoverse_n2.h 84e558d38ecba4e5f4d2f894a9291c5037ce66ed - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a57.h 355fca18e54437b9380c7cd9a6fd192d525b97ad - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_makalu.h 67473e16bc81208a446d337e2e770d044eebb7e9 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_x3.h 6f80e2ceb55f9179c0e8b9d91d249e62d6b1face - arm-trusted-firmware/include/lib/cpus/aarch64/neoverse_n_common.h b3acab7f36dd2d0a55a63da670f4e69226d10be5 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h fee71b3ac82a2185c4d87e46ee0883cd51017f0f - arm-trusted-firmware/include/lib/cpus/aarch64/denver.h 739d930c4cafa0f19c99b5a754074eeb93969108 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_x2.h 9bd84f9c041c16e801d57bda8a1097007895b874 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a510.h efc8411aa80d03690795c5caab5213f739c3dae2 - arm-trusted-firmware/include/lib/cpus/aarch64/generic.h b9a6a19c148f0fb9ef9b3e03b113a48c319f50ed - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a78.h b5de08d6bad3b4fa6d103de5fdccbe1dd027b1e2 - arm-trusted-firmware/include/lib/cpus/aarch64/cpu_macros.S fb525a4bddf12d5307fdd7d77fe2c90783b76d85 - arm-trusted-firmware/include/lib/cpus/aarch64/aem_generic.h c28183e30f9dcc69c70f2b869675e702310293f8 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_x1.h 4f151b65fbed78d8f053cd42de22513a01d0eea4 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a78c.h e06ae7d94772d2e7df59aaed91759743f3614979 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a76.h eacf536256298aba714ab67057a26284f71e4999 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a78_ae.h 984197de644265b1fc25ee7a46feed54db865bd6 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a710.h 419eb76df58a410020e6b07ebdf44b31892e6bf7 - arm-trusted-firmware/include/lib/cpus/aarch64/neoverse_v1.h 309db7cc6a48f2dfc2fc82dad3300ad2825efae6 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a75.h 3f7b45d32e48e60ee32229b7e8f5860b6e67747e - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a72.h 03c06290a053bfb539077f235d6cbd00efa9839f - arm-trusted-firmware/include/lib/cpus/aarch64/neoverse_n1.h cecb6b77ddae233e9012f44da229b0f25904b481 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a65ae.h 26f966576d1ba5fe1e871578dea3ea004be5ee67 - arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a76ae.h b58c922be5d4bad0866dbb86570d6f9e94310f89 - arm-trusted-firmware/include/lib/cpus/aarch64/rainier.h 0423eaf099863f353d46fd75ecb52ac9b67b9d12 - arm-trusted-firmware/include/lib/cpus/aarch64/neoverse_v2.h bf81e2d1db65ed903ef83af8c902a2c570f7d8d7 - arm-trusted-firmware/include/lib/pmf/pmf_helpers.h 9b838f7bd9f2c4493efedef614f584d30c32546d - arm-trusted-firmware/include/lib/pmf/pmf.h be45471818b5fb856ed0fc1c303a3439ac749d6c - arm-trusted-firmware/include/lib/pmf/aarch32/pmf_asm_macros.S 2e8bf007844002145509b02185c1cfb380c086c7 - arm-trusted-firmware/include/lib/pmf/aarch64/pmf_asm_macros.S ff1f378cc136ea5bf58c5fe0df726e1d809c7efb - arm-trusted-firmware/include/lib/zlib/tf_gunzip.h 72f4645c807c6915c0628b0d200b18fba404f91c - arm-trusted-firmware/include/lib/bl_aux_params/bl_aux_params.h 76f24b5df32a33ff953257acc268f140bef007d8 - arm-trusted-firmware/include/bl2/bl2.h 673b0116566ca5b511cc79b1c712df419d18b06d - arm-trusted-firmware/include/arch/aarch32/arch.h 19edcf9b1fb1a08230c93e3bfa026e7b33cd3ac9 - arm-trusted-firmware/include/arch/aarch32/el3_common_macros.S 0e8c93e8e2069b7b80576b88757ad99a54dabc15 - arm-trusted-firmware/include/arch/aarch32/smccc_helpers.h 0da2d0fc0408fde90d3415fee2622185e5803ee1 - arm-trusted-firmware/include/arch/aarch32/arch_helpers.h c2be1c93cd54c4e39aaf2aaa3a0efde1a237ae5d - arm-trusted-firmware/include/arch/aarch32/asm_macros.S 1ac6bbd72fd5efcdea46d665f3b42539e55d19af - arm-trusted-firmware/include/arch/aarch32/smccc_macros.S 6a8e3ed67bce468bf878dee9e257722a13c705de - arm-trusted-firmware/include/arch/aarch32/arch_features.h 7473145f94c25355b413a071f083825a5bbf2ce8 - arm-trusted-firmware/include/arch/aarch32/assert_macros.S 707cddbbe6226e2efc883af7013f08afced5a708 - arm-trusted-firmware/include/arch/aarch32/console_macros.S 48339000786576a418a5e8426b0f8bc76914d4fe - arm-trusted-firmware/include/arch/aarch64/arch.h ad144423428ec92ff7791f7e65475d8179b74ef7 - arm-trusted-firmware/include/arch/aarch64/el3_common_macros.S 4982ef3fa6ca4800c1d698159a74398d4f15e089 - arm-trusted-firmware/include/arch/aarch64/smccc_helpers.h 729397d8e0647ebc70b4f600b1dcba110618faf2 - arm-trusted-firmware/include/arch/aarch64/arch_helpers.h d35ee46e0adae54b398a7fca1dfb048e883b5ad1 - arm-trusted-firmware/include/arch/aarch64/el2_common_macros.S e5fc82458985f16eb8fb07b3e2ae755e4536dd55 - arm-trusted-firmware/include/arch/aarch64/asm_macros.S 493f4e2675649eb8dc40d9acf46242e5725b6ec1 - arm-trusted-firmware/include/arch/aarch64/arch_features.h 04b3308044a6768acf0bad187fc2b69cb69a1fe4 - arm-trusted-firmware/include/arch/aarch64/assert_macros.S 82b34ecc6637bf3745fec6a4d1cbc29e06e8e19e - arm-trusted-firmware/include/arch/aarch64/console_macros.S b279cf845b5ea6ce93f6563029c2dfbe6f85a541 - arm-trusted-firmware/include/tools_share/firmware_encrypted.h 5b305602a0d789840e70ed10420e3322ad8d4079 - arm-trusted-firmware/include/tools_share/cca_oid.h b8ded722f2969756096f51971579a3ed97e61d8b - arm-trusted-firmware/include/tools_share/firmware_image_package.h 58d6bf8cd75f220139c010d1d5fb6e0a96d4564a - arm-trusted-firmware/include/tools_share/dualroot_oid.h 1fda7d8e566efd28aaedd2f5d1ae43b5bf4d2705 - arm-trusted-firmware/include/tools_share/tbbr_oid.h a628d4b48c67b17cc32449aacf6052a52eea1705 - arm-trusted-firmware/include/tools_share/uuid.h 2953c9cd650429f472333ef0f7cb9ab6c69488c0 - arm-trusted-firmware/include/bl1/bl1.h f3d565fadbf6176b3034b8359d22fa8c03772f95 - arm-trusted-firmware/include/bl1/tbbr/tbbr_img_desc.h f4efa0610d34dd7e2935e65e54d8226cf36f94ff - arm-trusted-firmware/common/desc_image_load.c b905f51e14e3f772087f538ddcd67d4944d39abc - arm-trusted-firmware/common/uuid.c 99dd5e80229e2a9877b9d9a00f77b5d744b7f726 - arm-trusted-firmware/common/fdt_wrappers.c 8208556a61b9a606af6a282954ce827a47ea6a45 - arm-trusted-firmware/common/feat_detect.c 54620aa80f910434a484672d917861106ecc2df1 - arm-trusted-firmware/common/runtime_svc.c 4e8e81d22968abbb440726d3094bc3a5bbab94c6 - arm-trusted-firmware/common/tf_crc32.c 3ccdb5028aa976066c06527a27303c4a0db57ead - arm-trusted-firmware/common/tf_log.c eccab296f9fda107bbf45a831feee6ce7db3fbde - arm-trusted-firmware/common/bl_common.c 91cec99e37b1e7e986e62eb3474f5b0d63516507 - arm-trusted-firmware/common/image_decompress.c b84e6a4906aaff1dfa517982829506cf8cd44ec9 - arm-trusted-firmware/common/fdt_fixup.c 63072c0e7844e01ace8f6ed240e0c3ca38383090 - arm-trusted-firmware/common/aarch32/debug.S 8f38a18a8b5d07fbff793edbd229c26ca793996e - arm-trusted-firmware/common/backtrace/backtrace.c b21d0924c4f52357b3815446ebd25cc4f58ad622 - arm-trusted-firmware/common/aarch64/early_exceptions.S c4f936595cbd7c8caccc3ba4bfdc1cded418aee2 - arm-trusted-firmware/common/aarch64/debug.S 349ffdc5116737cb6145e2fbf2ec946ae51e87b2 - arm-trusted-firmware/services/spd/pncd/pncd_common.c cda79b183e46a0edbeb54dbf2b6a4b94a78db8ad - arm-trusted-firmware/services/spd/pncd/pncd_main.c da74a3d01ff81faa8d4b11d5eb728cf282490890 - arm-trusted-firmware/services/spd/pncd/pncd_helpers.S 0fb6679b9728b7bf5f45e7f3f51e86605ab4b044 - arm-trusted-firmware/services/spd/pncd/pncd_private.h e6df3878f8d4759c9f52ea98cbd0d6303bd2983b - arm-trusted-firmware/services/spd/opteed/teesmc_opteed_macros.h 8887d0d62a1b5248423fbc54ee536be3e5131d91 - arm-trusted-firmware/services/spd/opteed/opteed_private.h 4577f90d8a829f8cb934271e6991bd34844e1854 - arm-trusted-firmware/services/spd/opteed/opteed_common.c b4e16e85997824311dd82861c4c22d6ed046b817 - arm-trusted-firmware/services/spd/opteed/opteed_main.c c7af1a7de6cb5d79bf42271e846f04a18df96b63 - arm-trusted-firmware/services/spd/opteed/opteed_pm.c c8ea87fefa1ecd86c162a85206e9427be8c93afb - arm-trusted-firmware/services/spd/opteed/opteed_helpers.S 04de846e914d22f5925ba665f709fd3b0793ea5c - arm-trusted-firmware/services/spd/opteed/teesmc_opteed.h 176e5bf39535fbb39c81b2deb17ee470cac87159 - arm-trusted-firmware/services/spd/tlkd/tlkd_pm.c e4543798b8feb237167dc8c495b7aeb079d1b290 - arm-trusted-firmware/services/spd/tlkd/tlkd_private.h c213fbde43c8075e8fe28297dd6934f2f7c5f6fa - arm-trusted-firmware/services/spd/tlkd/tlkd_common.c 61ff410fd8dae3d3ecffc63595125321444d53c7 - arm-trusted-firmware/services/spd/tlkd/tlkd_main.c 14bc8b1de264fc27498c195073dcf7c1dd736c4d - arm-trusted-firmware/services/spd/tlkd/tlkd_helpers.S ba437dffc2a576e12cd8b8b5e8331a43244754b0 - arm-trusted-firmware/services/spd/trusty/trusty_helpers.S 55c35f079c4fec17128f7c644425b13fd516f2e8 - arm-trusted-firmware/services/spd/trusty/smcall.h 2bbaae4a856f5eba1f98688458729049af38a448 - arm-trusted-firmware/services/spd/trusty/generic-arm64-smcall.h cb38cd65497ea7679a3c5ced33d2e833c2f82797 - arm-trusted-firmware/services/spd/trusty/trusty.c 912f672668f3beed13a6a55a3fab7666e147ea6c - arm-trusted-firmware/services/spd/trusty/sm_err.h 405a4e398e27192766391869719c952a77d4e789 - arm-trusted-firmware/services/spd/trusty/generic-arm64-smcall.c c41250dd18f5502066bab243f1a2f33acf9079f5 - arm-trusted-firmware/services/spd/tspd/tspd_private.h d68051c573aae1f65601f9c9307d095259f8de63 - arm-trusted-firmware/services/spd/tspd/tspd_pm.c f9cf95e919ab4903bc80205e402547ddebe078a8 - arm-trusted-firmware/services/spd/tspd/tspd_helpers.S 36db67e2b644b85662e0440abdf6bb464032dfb1 - arm-trusted-firmware/services/spd/tspd/tspd_main.c 45855bd72493c075e03c590cfade6075e5656654 - arm-trusted-firmware/services/spd/tspd/tspd_common.c 3a65202a9bf94d131767462a1eb31f0c56a5daf5 - arm-trusted-firmware/services/std_svc/std_svc_setup.c 250540ab4306221c494658c2239ffed65aa3fbd9 - arm-trusted-firmware/services/std_svc/pci_svc.c ccb5a8502e5983405a17241d9b4383f643461578 - arm-trusted-firmware/services/std_svc/spm/common/include/spm_common.h 1d78e66e35ecda90ea616a2e2c56d19e17b94c93 - arm-trusted-firmware/services/std_svc/spm/common/aarch64/spm_helpers.S 36a533c0f03ab263b5b62de3fe1557b8aebd16b0 - arm-trusted-firmware/services/std_svc/spm/el3_spmc/spmc_setup.c 586f59679745adddacc84ba8bb2da429eff1403b - arm-trusted-firmware/services/std_svc/spm/el3_spmc/logical_sp.c f95a2beac255a48f06c6d600526017ec36556fde - arm-trusted-firmware/services/std_svc/spm/el3_spmc/spmc_shared_mem.h c2bd81a96476ccee770ae29c59048936203a2347 - arm-trusted-firmware/services/std_svc/spm/el3_spmc/spmc_shared_mem.c 75b3dcb3e65f0542e0cf42b9aa0eaea07cd1581c - arm-trusted-firmware/services/std_svc/spm/el3_spmc/spmc.h 9e4dab11c6e58464591e0f106d3c13496af353dc - arm-trusted-firmware/services/std_svc/spm/el3_spmc/spmc_main.c 8ec297895b0680bf52b4f1fa1d512ed977be1db4 - arm-trusted-firmware/services/std_svc/spm/el3_spmc/spmc_pm.c f13aadd8b075a82277f5796277f6e3a3654c2293 - arm-trusted-firmware/services/std_svc/spm/spm_mm/spm_mm_shim_private.h a618d6ae3661380d93a81727202ea4276c1a3548 - arm-trusted-firmware/services/std_svc/spm/spm_mm/spm_mm_setup.c 0e01a87706eda52d18485da37a6df6cae99c53e4 - arm-trusted-firmware/services/std_svc/spm/spm_mm/spm_mm_private.h 22b299703158fe99c187cfe77aa01d86d71b1615 - arm-trusted-firmware/services/std_svc/spm/spm_mm/spm_mm_main.c 69d1e192cdbd3c680cfd4f7977d9a2ba5f880fe0 - arm-trusted-firmware/services/std_svc/spm/spm_mm/spm_mm_xlat.c 785ff37c2c59d92ad49861aab2dcf74eea24ac2e - arm-trusted-firmware/services/std_svc/spm/spm_mm/aarch64/spm_mm_shim_exceptions.S 26be0a6e880962cffc338be91ad0f344e8aee9ef - arm-trusted-firmware/services/std_svc/rmmd/rmmd_initial_context.h 0ee140a73378b09ce1db70b7ccede17d5b692b29 - arm-trusted-firmware/services/std_svc/rmmd/rmmd_main.c f40097e815dcad1dbf8becab4c3937ef4304091a - arm-trusted-firmware/services/std_svc/rmmd/rmmd_attest.c 61be680cf24f1cd6ed7af19a00b2547b7fba1d2e - arm-trusted-firmware/services/std_svc/rmmd/rmmd_private.h b8dab97e1d980a7236072f07cf660a0f7dc6037f - arm-trusted-firmware/services/std_svc/rmmd/trp/trp_main.c 4aa1cfc40693cf13c626c33e652a9c0e4fe09a50 - arm-trusted-firmware/services/std_svc/rmmd/trp/trp_private.h 531bf26f3430d8f6403d634beda58996dc24e22b - arm-trusted-firmware/services/std_svc/rmmd/trp/trp_entry.S ff0c111a2f42278dab1ef79a54691d48f1bcb9d8 - arm-trusted-firmware/services/std_svc/rmmd/trp/trp_helpers.c 6b1ef22efba95bff3270de056f0a4e2484528dee - arm-trusted-firmware/services/std_svc/rmmd/trp/linker.lds 51c4bc5d5a6c9b18e2f3f2c951d3f8abe0869ba2 - arm-trusted-firmware/services/std_svc/rmmd/aarch64/rmmd_helpers.S 55a731a97c5a74f2959119e9ab4874cf8072b0ab - arm-trusted-firmware/services/std_svc/spmd/spmd_private.h 97fd6240bc2e5ad14413967955abec486d7cc6c6 - arm-trusted-firmware/services/std_svc/spmd/spmd_pm.c 25c19e6d16ce3941d0e12dbec3b906eb9f6689c7 - arm-trusted-firmware/services/std_svc/spmd/spmd_main.c eb5c9e4113243964f83a249807ed07711dc6f145 - arm-trusted-firmware/services/std_svc/spmd/aarch64/spmd_helpers.S d3bfc986d76556c18127069d7171f912a650262f - arm-trusted-firmware/services/std_svc/drtm/drtm_remediation.h 7c0064a00ae5afe7e0056a585ae4569d30f93e14 - arm-trusted-firmware/services/std_svc/drtm/drtm_main.h 94a4dbebd05b5ac04ddc62f410c23978d1af5e79 - arm-trusted-firmware/services/std_svc/drtm/drtm_dma_prot.h 11f6d99892672b2a62ea499ded71fefff2d8d805 - arm-trusted-firmware/services/std_svc/drtm/drtm_remediation.c 7b11c94a3b7c10b67086dc68c9677849a8bc9f27 - arm-trusted-firmware/services/std_svc/drtm/drtm_measurements.c 3510e57e814a2ad8cc236670963d9b8179968c88 - arm-trusted-firmware/services/std_svc/drtm/drtm_dma_prot.c ef7031b55ae8ccff8614b097dab00ba1367d15ee - arm-trusted-firmware/services/std_svc/drtm/drtm_measurements.h f65d0ef1d69e16dbd7b0c9c18aec330d4aba748f - arm-trusted-firmware/services/std_svc/drtm/drtm_main.c a13fa14815a742133d25519d9616e0753aed9864 - arm-trusted-firmware/services/std_svc/drtm/drtm_res_address_map.c b8207b17922c0b2192565df4c3bc9e1e9e726afa - arm-trusted-firmware/services/std_svc/sdei/sdei_state.c e020a86b0568edbbb8e8a93f2cee43fc4812d475 - arm-trusted-firmware/services/std_svc/sdei/sdei_intr_mgmt.c c8a8e3febebccece37ca7976f39c7db13be5882c - arm-trusted-firmware/services/std_svc/sdei/sdei_event.c 36f054958b6c01f03eed070113b49903ce936a5d - arm-trusted-firmware/services/std_svc/sdei/sdei_private.h 0a593d9b9aca3739ab4d94c4aa2ecdf7481ad305 - arm-trusted-firmware/services/std_svc/sdei/sdei_main.c ed3a4e16186524a88ed19aa95176bc233b0928fe - arm-trusted-firmware/services/std_svc/sdei/sdei_dispatch.S 37b01eb1ed4da3bb42e9ba829719b6d771d1c8b4 - arm-trusted-firmware/services/std_svc/trng/trng_main.c c53e4b9cdb4eaee27196d9759c484c4faeaf7d06 - arm-trusted-firmware/services/std_svc/trng/trng_entropy_pool.h 6f50d5acbea1843b211e9064fb4d55a8687ba336 - arm-trusted-firmware/services/std_svc/trng/trng_entropy_pool.c 32f05b17684cd616a34fd51c98e75162d384217a - arm-trusted-firmware/services/arm_arch_svc/arm_arch_svc_setup.c 75c196ade8ef57a9775c286e3c2f88b52c492e67 - arm-trusted-firmware/bl31/bl31_context_mgmt.c cc44e2fa243d2b48575f0896f62dafb0a8a3f893 - arm-trusted-firmware/bl31/bl31.ld.S aff16dda38db2be9fd694ec17e83c6aeb84cf3e5 - arm-trusted-firmware/bl31/bl31_main.c ae44163001e4ade4c2e29f6afb43316e7584ee41 - arm-trusted-firmware/bl31/interrupt_mgmt.c 1e24f28e3ea18e28d03ff1be1d17a39ed84a20ab - arm-trusted-firmware/bl31/ehf.c 77af4fd72df52040aa9b967e5a6ef1aaeacb22a2 - arm-trusted-firmware/bl31/bl31_traps.c cd127daed96f6e9ba46db71649655534093c6ca9 - arm-trusted-firmware/bl31/aarch64/ea_delegate.S bc19019ea8f8942a074959edd36837982d35f12b - arm-trusted-firmware/bl31/aarch64/runtime_exceptions.S 7c846b0cc5af2d57b0a9ccac7bb940b95f682bce - arm-trusted-firmware/bl31/aarch64/crash_reporting.S ffb792493df46745086f05d8b8a44c8745cc6f0c - arm-trusted-firmware/bl31/aarch64/bl31_entrypoint.S a4208974e4c39b113510787cccd6c941971d46ee - arm-trusted-firmware/fdts/stm32mp15xx-dhcom-pdk2.dtsi c49dfbfab50db6d0014130e8d213b6a8113c9525 - arm-trusted-firmware/fdts/stm32mp153.dtsi a88bff2feebe3949acee8413241a06f4643f5419 - arm-trusted-firmware/fdts/n1sdp-multi-chip.dts 8a853676b7323e4490ffcf918d0061e70b9ab0d6 - arm-trusted-firmware/fdts/fvp-base-psci-common.dtsi 79d8f41f2a5afa474094fe763ef4ee39909d283b - arm-trusted-firmware/fdts/stm32mp157c-odyssey-fw-config.dts b6c1ef3fe03ee01cae9a90776cf4e18be5070804 - arm-trusted-firmware/fdts/rtsm_ve-motherboard.dtsi d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157d-ed1-fw-config.dts dbed6c5c0e011af658818b570feee9c093e65a26 - arm-trusted-firmware/fdts/stm32mp135f-dk-fw-config.dts 9ba3ae553db0be8969881ea12aba908298bee353 - arm-trusted-firmware/fdts/fvp-base-gicv3-psci.dts 910ac0ace6638b52d04843f12c3f0f521eb4f4e5 - arm-trusted-firmware/fdts/corstone700_fpga.dts 10bae29f18be4785b789ca4c08398643163c76be - arm-trusted-firmware/fdts/cot_descriptors.dtsi c8fd8ec89618a1cf2384c117aa86de6a6f748825 - arm-trusted-firmware/fdts/stm32mp13-fw-config.dtsi 8a70c913e436a192e4ec040bfdc235e56eb6bd74 - arm-trusted-firmware/fdts/stm32mp15xx-osd32.dtsi d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157a-avenger96-fw-config.dts 39ca5b339d21ea4068206120199d10ab11b3a92e - arm-trusted-firmware/fdts/stm32mp15-pinctrl.dtsi bbe441adbb4706bbc2d792a33b888f441d489177 - arm-trusted-firmware/fdts/juno.dts abbe0e5a7c63995c207b1995649e3a6ed6b4221a - arm-trusted-firmware/fdts/stm32mp15xc.dtsi dc880b2cbd39cde08860e8ebf3cb4b92bbb21748 - arm-trusted-firmware/fdts/stm32mp15xxab-pinctrl.dtsi 195376b3fa6a4af6db8e90af65ae62d649d506c1 - arm-trusted-firmware/fdts/fvp-defs-dynamiq.dtsi ee1bb06de6ee0eba0fe695f5c7f9dbc12abb6f3e - arm-trusted-firmware/fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157a-ed1-fw-config.dts 4fa3b6d4bddfb09bf8b8ac8f78bc5806a1063cf6 - arm-trusted-firmware/fdts/stm32mp157c-dk2.dts 775896f2dacd473d7e9aeae79154270439d15e7b - arm-trusted-firmware/fdts/fvp-ve-Cortex-A7x1.dts 4e388ba63ace4d4df9d1abc9e400e0588da4b439 - arm-trusted-firmware/fdts/stm32mp157c-ed1.dts 2f05be7afa52d4db4c62e213a91e5efc3908193a - arm-trusted-firmware/fdts/stm32mp157c-lxa-mc1.dts 9b3b205955072832ef708f17e0263101865c13c1 - arm-trusted-firmware/fdts/stm32mp15-bl32.dtsi f7ba40a101d1f02c70445a0d783a347ed212cf03 - arm-trusted-firmware/fdts/stm32mp157d-dk1-fw-config.dts 0203c56a6aaec146dfc7e5851db0142b2d9edc04 - arm-trusted-firmware/fdts/stm32mp157c-odyssey-som.dtsi 4d121467e71a4bd15241201c1c23fbb169901959 - arm-trusted-firmware/fdts/a5ds.dts a120c4c89b1562f49a4d3533b3f500e946f46224 - arm-trusted-firmware/fdts/tc.dts f7ba40a101d1f02c70445a0d783a347ed212cf03 - arm-trusted-firmware/fdts/stm32mp157a-dk1-fw-config.dts e5866956ed22d66798a7ed86b2f223ef2ed59054 - arm-trusted-firmware/fdts/stm32mp131.dtsi 9ca89fcc131c223dc7f257c86f5677ae3b6dae7d - arm-trusted-firmware/fdts/morello-soc.dts 33afbee5fd7bbf5c15449c00db2a57cd4ba0634e - arm-trusted-firmware/fdts/fvp-ve-Cortex-A5x1.dts c028d02d6d68dfd3c16c8ea9c6e247c72a911abc - arm-trusted-firmware/fdts/fvp-foundation-motherboard.dtsi f92cb32ea29e10232721e9d596972e82444c21d2 - arm-trusted-firmware/fdts/stm32mp15xxad-pinctrl.dtsi d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157a-ev1-fw-config.dts 5d5ddb74e5499f300b5d1800520a4651078d347b - arm-trusted-firmware/fdts/fvp-foundation-gicv3-psci.dts 79d8f41f2a5afa474094fe763ef4ee39909d283b - arm-trusted-firmware/fdts/stm32mp157c-lxa-mc1-fw-config.dts d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157f-ed1-fw-config.dts a2179d252faf4859c7a7e68d3ba75a0955f53d37 - arm-trusted-firmware/fdts/stm32mp157c-odyssey.dts d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157c-ev1-fw-config.dts 0fec14d4dc8c75bbdea73be1457f5ed47458cb9a - arm-trusted-firmware/fdts/fvp-foundation-gicv2-psci.dts 266d21043cd7cb1e457def745a1a90b859ba0be7 - arm-trusted-firmware/fdts/fvp-defs.dtsi 84f2fbf7e3f43a269b2ec65171b627dfab1ebffe - arm-trusted-firmware/fdts/stm32mp133.dtsi 8693e118ad32484388e5072264c6544a4c7e69f3 - arm-trusted-firmware/fdts/stm32mp13-bl2.dtsi 08e1154998efab771552e2671de34b775b2ca963 - arm-trusted-firmware/fdts/stm32mp157a-avenger96.dts 5ab2cb4f026f883cf11454d7ca2822c99bcf65ce - arm-trusted-firmware/fdts/stm32mp135f-dk.dts a6ef63af22c25465b4276c77535b30d8baaa1ea4 - arm-trusted-firmware/fdts/arm_fpga.dts 2975b8960cae049843178f072921ce9c826e8822 - arm-trusted-firmware/fdts/stm32mp135.dtsi 07dea9d014bf6f86c5ceed73c6656d32a583cd5e - arm-trusted-firmware/fdts/fvp-base-gicv2-psci.dts 561d58d7c0fe33f9ab8972df13dd6343378a5023 - arm-trusted-firmware/fdts/stm32mp13xc.dtsi 9c409a5e63830a8252f05627060449b59408b7b6 - arm-trusted-firmware/fdts/stm32mp13xf.dtsi 992348633a6518e2d0464e4afe90c22c87a617a6 - arm-trusted-firmware/fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157f-ev1-fw-config.dts ca1bb28fb60b80437e687827d9c6459d97e36ee7 - arm-trusted-firmware/fdts/morello.dtsi 59f777f521b3de55f482d1b9623951a1dc5c0046 - arm-trusted-firmware/fdts/stm32mp157c-ev1.dts c078bf1220e11a54b0ae9d20bf948f1f4cb30d37 - arm-trusted-firmware/fdts/stm32mp15-ddr.dtsi f0f10a0dcdd4cf762612a46effc427b39f801fc6 - arm-trusted-firmware/fdts/juno-ethosn.dtsi bc6c22a9eb6a331b29f27c4c829076992d321463 - arm-trusted-firmware/fdts/fvp-base-gicv3-psci-1t.dts d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157c-ed1-fw-config.dts 6b86a9e9c6c06841937a884fcc7b91e67ce3b81c - arm-trusted-firmware/fdts/stm32mp13xd.dtsi a035ecb2738ee727c5cce5cde80d6a9225206fdf - arm-trusted-firmware/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts 180b7b537e0272e8e8ce9e631259c8bb1c9a7bb6 - arm-trusted-firmware/fdts/stm32mp15xx-dhcor-io1v8.dtsi 2d9983ae7b41417977f671f99eec7d6c8f5a99be - arm-trusted-firmware/fdts/stm32mp15xxaa-pinctrl.dtsi d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157d-ev1-fw-config.dts a50dec7e2783a8212860dc362ed39193bd7980e6 - arm-trusted-firmware/fdts/fvp-base-gicv3-psci-dynamiq.dts ebdd8c67e9833bb5ed3c45b38112dff58af15403 - arm-trusted-firmware/fdts/stm32mp15-fw-config.dtsi 6b86a9e9c6c06841937a884fcc7b91e67ce3b81c - arm-trusted-firmware/fdts/stm32mp13xa.dtsi 1eec69a2fb20f914f15b04407b66d3758c2b48e8 - arm-trusted-firmware/fdts/stm32mp15xx-dhcor-avenger96.dtsi ca71563d0fa28538f143c0ae69e1f638dfb82942 - arm-trusted-firmware/fdts/stm32mp157c-dhcom-pdk2.dts e89eb8adf0cc60e3d4860de6e443eab803fe34ec - arm-trusted-firmware/fdts/stm32mp15xx-dkx.dtsi d0ca311ee090d9d69c82273e0e6f4d65bb330554 - arm-trusted-firmware/fdts/stm32mp157a-dhcor-avenger96-fw-config.dts fafc1a46bd195774df21a32f1e87a087f14e2c67 - arm-trusted-firmware/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi bbadcb3a4067c694d778aa897c37cfbf52dbb796 - arm-trusted-firmware/fdts/stm32mp15xx-dhcom-som.dtsi 0406f39f568a59a508af277447007c21f12a6dd7 - arm-trusted-firmware/fdts/stm32mp151.dtsi 79f46e10c0482b6f495a6a16f4e3721ec6ad5d0f - arm-trusted-firmware/fdts/stm32mp15xx-dhcor-som.dtsi f7ba40a101d1f02c70445a0d783a347ed212cf03 - arm-trusted-firmware/fdts/stm32mp157c-dk2-fw-config.dts ddb3d9266ce77ac3e0746820b562a07f35eafb01 - arm-trusted-firmware/fdts/n1sdp.dtsi 7b7f266b622d5c0683632221803d79a1f5f80e32 - arm-trusted-firmware/fdts/morello-fvp.dts 122430dfffc3d549a6991bc3154850d76b80c2bb - arm-trusted-firmware/fdts/stm32mp157a-dk1.dts 390a6cef77d9095a9c98b9abe19eaaa6eedbdb73 - arm-trusted-firmware/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi f7ba40a101d1f02c70445a0d783a347ed212cf03 - arm-trusted-firmware/fdts/stm32mp157f-dk2-fw-config.dts f99071420aca4da5f493b73afa3d3777206e23d7 - arm-trusted-firmware/fdts/n1sdp-single-chip.dts ca0ac09e5eb628e7c9a43b6fb0e1e24ce5c836e6 - arm-trusted-firmware/fdts/stm32mp157a-dhcor-avenger96.dts ac548bc11fadca6cc0c3eb4d0a551c4f1917fb4b - arm-trusted-firmware/fdts/fvp-base-gicv2.dtsi b97ef7b89b0064ff2dcadf45495d02f7a2a5aa07 - arm-trusted-firmware/fdts/stm32mp157c-dhcom-pdk2-fw-config.dts 094f752c659ba4c70dae4bfdd3041ffdc45d6451 - arm-trusted-firmware/fdts/corstone700.dtsi fdc05334cd630b63cf2fd11add62d6580489d832 - arm-trusted-firmware/fdts/stm32mp13-ddr.dtsi 4ae95220b0fb426eaa4f25852ab261389c875af5 - arm-trusted-firmware/fdts/stm32mp1-cot-descriptors.dtsi c1d24ce6492d52d78484c4b3cf9d2466dbf9c0b0 - arm-trusted-firmware/fdts/stm32mp157.dtsi b61926af906ac72d7ffe15c3a30ce22c0ecce8ae - arm-trusted-firmware/fdts/fvp-base-gicv3.dtsi 8a029ef453949855d4148edd185ebf88c64e67f9 - arm-trusted-firmware/fdts/stm32mp13-pinctrl.dtsi 3b21b710cc058aa0493ac54f0e9fbc7b2547734f - arm-trusted-firmware/fdts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi a61a77e18f14a9ba0916b5d0c1d4c7b0e07d1441 - arm-trusted-firmware/fdts/stm32mp15xxac-pinctrl.dtsi 20769b04e4fa588ef10d7460a5b4a9061c70ebfa - arm-trusted-firmware/fdts/corstone700_fvp.dts e46dda91eeaf889c50bf363cdc9fcf0017c45fdc - arm-trusted-firmware/fdts/stm32mp15-bl2.dtsi ce8e6c97e3af86cafccb6b9ffe857b9c1ec62598 - arm-trusted-firmware/plat/qti/sc7180/inc/qti_secure_io_cfg.h 19c93a98e1f08d21eaa65898889b3f74f7fca312 - arm-trusted-firmware/plat/qti/sc7180/inc/platform_def.h 576c57f662c322a2eac3565e848ea0179d7290a1 - arm-trusted-firmware/plat/qti/sc7180/inc/qti_rng_io.h 25ffc66bfd8596789ed4e6ec3329a46ce29927d6 - arm-trusted-firmware/plat/qti/sc7180/inc/qti_map_chipinfo.h d99874d76998c7025371fc6e19def1521bfacc2d - arm-trusted-firmware/plat/qti/sc7280/inc/qti_secure_io_cfg.h db1632b3d9b656b70c43049ed9e7ff1859e2ca1d - arm-trusted-firmware/plat/qti/sc7280/inc/platform_def.h 8b0399819af138f97f2f4270408c66b5d23b6052 - arm-trusted-firmware/plat/qti/sc7280/inc/qti_rng_io.h 9e0b31305ede1a8540fd77a9083d96cc98db3f47 - arm-trusted-firmware/plat/qti/sc7280/inc/qti_map_chipinfo.h f12c8a79f6141094db1aac3d48ac6ea34800ff6d - arm-trusted-firmware/plat/qti/common/src/qti_stack_protector.c aeecda36338ac151632b50ce13795833a9f6ce3b - arm-trusted-firmware/plat/qti/common/src/pm_ps_hold.c f3b7fa7c62db7248cf8b50316244b8239596f267 - arm-trusted-firmware/plat/qti/common/src/qti_rng.c 825f74a7f38dc32847afc499110e74db3937935f - arm-trusted-firmware/plat/qti/common/src/qti_syscall.c fcc252758f191a6ca9bc59db1e5ea226fa79d1ea - arm-trusted-firmware/plat/qti/common/src/qti_bl31_setup.c 3fc5e394e0d8ea8b2367dec56d27e29444d67bfb - arm-trusted-firmware/plat/qti/common/src/qti_common.c 26a9cbddd8b9a236e5d0f3550807554e23563f18 - arm-trusted-firmware/plat/qti/common/src/qti_gic_v3.c accf2747a7781193d7806b7d3d6b6de2a7c9d5e8 - arm-trusted-firmware/plat/qti/common/src/qti_interrupt_svc.c bea1c249fdc7e365ba7e5d773a7e312de9345fb8 - arm-trusted-firmware/plat/qti/common/src/spmi_arb.c ac89500a8d77a91b9b24a426b3394744bf74efb5 - arm-trusted-firmware/plat/qti/common/src/qti_topology.c 7fc1d5b81ce41fbda7e5fda0ba2e22acdf4d5934 - arm-trusted-firmware/plat/qti/common/src/qti_pm.c e1c323c2517fcdcdc4c19a1be62b15dcf31174ae - arm-trusted-firmware/plat/qti/common/src/aarch64/qti_helpers.S 7547a5ef92ec4ac40eed5a73041ef25902042bf2 - arm-trusted-firmware/plat/qti/common/src/aarch64/qti_uart_console.S a015f785f3a8598abf893b7534677029f8d88010 - arm-trusted-firmware/plat/qti/common/src/aarch64/qti_kryo4_gold.S 0a334ecdfcaa10aaf8316d9a9824e5b72a5a2beb - arm-trusted-firmware/plat/qti/common/src/aarch64/qti_kryo6_gold.S e613029e9a1503a47ce38fb17df6f5002f8f1919 - arm-trusted-firmware/plat/qti/common/src/aarch64/qti_kryo4_silver.S 54e64bbb0d58ddc5eb65cf980f9355513e861265 - arm-trusted-firmware/plat/qti/common/src/aarch64/qti_kryo6_silver.S a492ca7a1a6a0dc9b988c09a6838be72f3a00cc3 - arm-trusted-firmware/plat/qti/common/inc/qti_board_def.h 7bc95caff2b0700d04cc28cec44bcae1965e8b73 - arm-trusted-firmware/plat/qti/common/inc/qti_plat.h 0b01452153b97f032c89b81698730bd0211ee4cf - arm-trusted-firmware/plat/qti/common/inc/qti_rng.h af87d6c46e8e3304b92c90ed0111bb3066bac8e1 - arm-trusted-firmware/plat/qti/common/inc/qti_interrupt_svc.h f00660ee7d40d5826515fe5266e50d2172c12bc1 - arm-trusted-firmware/plat/qti/common/inc/spmi_arb.h 1d172cb4df58b173035b99b5855545b25fd764be - arm-trusted-firmware/plat/qti/common/inc/qti_uart_console.h 2c7d5721030a2353cd649ad2cf4da49242ed3195 - arm-trusted-firmware/plat/qti/common/inc/qti_cpu.h 5901fe33e7d63a4a03e1b95469b48c8299d178f6 - arm-trusted-firmware/plat/qti/common/inc/aarch64/plat_macros.S 1a6c92af22149cf7ac8cccac367bfc9610d45ab3 - arm-trusted-firmware/plat/qti/qtiseclib/src/qtiseclib_interface_stub.c 4e66aa575523181fefb5720d798a257e98a26003 - arm-trusted-firmware/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c 5db76531814dda261416dc016b511d807c3a4ba5 - arm-trusted-firmware/plat/qti/qtiseclib/inc/qtiseclib_defs.h a28527a439c34c2ff37a3bd1ace46fb9ddb4f357 - arm-trusted-firmware/plat/qti/qtiseclib/inc/qtiseclib_cb_interface.h 186065ea9c6a4a2d16c200d4d07466514f5a1c29 - arm-trusted-firmware/plat/qti/qtiseclib/inc/qtiseclib_interface.h 885aa0bbda57cb30366ac8f9ea09f3f8e7ad31da - arm-trusted-firmware/plat/qti/qtiseclib/inc/sc7180/qtiseclib_defs_plat.h 3e4d34962a59227a5d8d494f35e80b77fdf8d61e - arm-trusted-firmware/plat/qti/qtiseclib/inc/sc7280/qtiseclib_defs_plat.h 6e7e984a8e5dfab7008759c759d8244470f3dae2 - arm-trusted-firmware/plat/qti/msm8916/msm8916_cpu_boot.c 2cfbd336aca6ffd917aac7811b326bc53c734d1c - arm-trusted-firmware/plat/qti/msm8916/msm8916_bl31_setup.c e08f230adb59004c64e07444599554c275f1643a - arm-trusted-firmware/plat/qti/msm8916/msm8916_pm.h 3b21be43300990b373aae5fc9fe86650293e6465 - arm-trusted-firmware/plat/qti/msm8916/msm8916_gicv2.h 455f78881f3e452bc906dd8e2dd74d7e668f33dd - arm-trusted-firmware/plat/qti/msm8916/msm8916_gicv2.c ec2741df6c60880f2d8d7c157dcda59d0c50eacd - arm-trusted-firmware/plat/qti/msm8916/msm8916_pm.c 180bf4b2deb975b6753f7b845e0055ea91a2aa13 - arm-trusted-firmware/plat/qti/msm8916/msm8916_topology.c 07c3221b9d62d08349ed7bc9f4f1e779f524ec32 - arm-trusted-firmware/plat/qti/msm8916/include/msm8916_mmap.h 8150ca146a9314d5192e1e394975bb932029bd0b - arm-trusted-firmware/plat/qti/msm8916/include/uartdm_console.h d2d25cc01ae69fbf7368f681a6be32083570007e - arm-trusted-firmware/plat/qti/msm8916/include/platform_def.h e1247a97415e84032dab91e8daa6df51645413ac - arm-trusted-firmware/plat/qti/msm8916/include/plat_macros.S 91be000247752e30dfd222eef60029b13936f320 - arm-trusted-firmware/plat/qti/msm8916/aarch64/msm8916_helpers.S fd14d1c817b69bd4a42046e3a208b999bffc7e36 - arm-trusted-firmware/plat/qti/msm8916/aarch64/uartdm_console.S 1ea7a5c813a861814cb6a9635ab2899599b1f14e - arm-trusted-firmware/plat/intel/soc/stratix10/bl31_plat_setup.c 8598eec66d15027434f5e31ce76936d555fb60f0 - arm-trusted-firmware/plat/intel/soc/stratix10/bl2_plat_setup.c db28b2738f48c2d2751af6dee5456298ec578706 - arm-trusted-firmware/plat/intel/soc/stratix10/include/s10_memory_controller.h 0ecc6c7913824d78deaeaa2c01ec8b40e2bacbc6 - arm-trusted-firmware/plat/intel/soc/stratix10/include/socfpga_plat_def.h fbf4ab727479f904a0ae30ca600e339277fc9c11 - arm-trusted-firmware/plat/intel/soc/stratix10/include/s10_pinmux.h 6569c6244a923e1aa7f5ce62d1edef532b9c61e2 - arm-trusted-firmware/plat/intel/soc/stratix10/include/s10_mmc.h 78da5bc74c17e2a2fc3eeb3eec9ac39a6b54684c - arm-trusted-firmware/plat/intel/soc/stratix10/include/s10_clock_manager.h 70667783807950b851233233349f9cadef62b70d - arm-trusted-firmware/plat/intel/soc/stratix10/soc/s10_memory_controller.c 87dc55fea317913960f41df594ea406bd410da89 - arm-trusted-firmware/plat/intel/soc/stratix10/soc/s10_mmc.c 165df3d4e79eedab33c9012f09d6e960f68d4ce3 - arm-trusted-firmware/plat/intel/soc/stratix10/soc/s10_clock_manager.c 5a527e1803e29b659091fe8cf586adaf527a55dd - arm-trusted-firmware/plat/intel/soc/stratix10/soc/s10_pinmux.c 744622161f66d8947e1701aedf45d2e4c911d98f - arm-trusted-firmware/plat/intel/soc/common/socfpga_sip_svc.c 0c8169624b733658b1eee7afa553ac38e2f2660d - arm-trusted-firmware/plat/intel/soc/common/socfpga_storage.c 3e96caf672e37f83d553d90424f092bd1e55c0e8 - arm-trusted-firmware/plat/intel/soc/common/socfpga_sip_svc_v2.c 98e7e0c1e8b661cfd05aacfbfc969aea710cf145 - arm-trusted-firmware/plat/intel/soc/common/socfpga_psci.c 659bce34ee85d1001adb313d9a639d66d3a89deb - arm-trusted-firmware/plat/intel/soc/common/socfpga_image_load.c ecfa5e68e1c5043d25b54cab656ce201d1bab865 - arm-trusted-firmware/plat/intel/soc/common/socfpga_delay_timer.c cc4b0a911ae0f00cfc94310c6a9d60716e9a1064 - arm-trusted-firmware/plat/intel/soc/common/socfpga_topology.c 9c1ab97bc7e1b8a4c4fdbdc721a1ad1605842cd3 - arm-trusted-firmware/plat/intel/soc/common/bl2_plat_mem_params_desc.c c9354b6d74c4a24fae2207b5b999882056d88e91 - arm-trusted-firmware/plat/intel/soc/common/drivers/qspi/cadence_qspi.h 41479908d06f853d367898b86dda07763652f4c7 - arm-trusted-firmware/plat/intel/soc/common/drivers/qspi/cadence_qspi.c c72a5bba918c6067f6a77a639c42bc477c71de2c - arm-trusted-firmware/plat/intel/soc/common/drivers/wdt/watchdog.c 5c64677609f95ebafb78a49847ca9c07c1a3aa87 - arm-trusted-firmware/plat/intel/soc/common/drivers/wdt/watchdog.h 40a8cdcc9de34b1816ae44611e3eb25846bdce83 - arm-trusted-firmware/plat/intel/soc/common/drivers/ccu/ncore_ccu.c 5e8868245cddc9cd3bff4ded0c90d2f8b356920d - arm-trusted-firmware/plat/intel/soc/common/drivers/ccu/ncore_ccu.h 152aac97afc14f46701c2c6191022a02a8bf6c8b - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_reset_manager.h 41d7e3ea3d55787ad71372ec8b0bf6ba1b7f7eef - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_system_manager.h 970f387d2b06ae8e286bce0ae31cce567cfbc9f4 - arm-trusted-firmware/plat/intel/soc/common/include/platform_def.h ffac73fe826ff46223b2ddaebd9e7206528dfe33 - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_emac.h b1757fca7c0b4611f05ff58ccf57fd05a1cdce19 - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_fcs.h 4dd7031ad5db9e76642ee94035b1dc3209a508bb - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_private.h 3eb20b0d72778ce95cdd02e0732ff2485fdcbe49 - arm-trusted-firmware/plat/intel/soc/common/include/plat_macros.S 00f501d1e338fcfdee5a84ea4618b4800bb66b13 - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_noc.h c23a6bade313d779668249feebdf126a3bebf3e0 - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_mailbox.h 386b0fdaa7ee713193bb54beb3607996260be346 - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_sip_svc.h 0e535605a23a91a4da7cb7a80263fb88f42d5b03 - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_f2sdram_manager.h 3886a4a113d64631d91373640cc1e9d6ad0f9de5 - arm-trusted-firmware/plat/intel/soc/common/include/socfpga_handoff.h 23d9dff6e9c23385b4ccea7791e18d709f29f6d0 - arm-trusted-firmware/plat/intel/soc/common/soc/socfpga_handoff.c e574f0019a7633a4bdd77aca757ca8eb9578b909 - arm-trusted-firmware/plat/intel/soc/common/soc/socfpga_reset_manager.c 05cf124f63ca2ad812cdaf29b4c53a36bd5772c0 - arm-trusted-firmware/plat/intel/soc/common/soc/socfpga_mailbox.c ab30d05818b8bad26af22d404704a8359dc1b6aa - arm-trusted-firmware/plat/intel/soc/common/soc/socfpga_firewall.c dbb5c27c52afd2347aa5d78b423a051d694a5c1e - arm-trusted-firmware/plat/intel/soc/common/soc/socfpga_emac.c 35147be6f6f43142d92f8f49026c79d220570691 - arm-trusted-firmware/plat/intel/soc/common/sip/socfpga_sip_fcs.c 8b1c7bd1975b587b7b972a8471ba45698080074c - arm-trusted-firmware/plat/intel/soc/common/sip/socfpga_sip_ecc.c c93b1e05180647b1752b51838d7b935bf554e073 - arm-trusted-firmware/plat/intel/soc/common/aarch64/platform_common.c d7e8f58ba8eb1fbdee758371be39f1e404609ad4 - arm-trusted-firmware/plat/intel/soc/common/aarch64/plat_helpers.S 0b122983293e62477b54bc9dc2db6ae570a37866 - arm-trusted-firmware/plat/intel/soc/agilex/bl31_plat_setup.c e4cbd01cb86ec050c9290b57cdf1c95485e99e9f - arm-trusted-firmware/plat/intel/soc/agilex/bl2_plat_setup.c e61cd2fc029895773c3e7781028ff30b7d863cb7 - arm-trusted-firmware/plat/intel/soc/agilex/include/agilex_pinmux.h 2cbef8a830bfec6a533910d7a00ca01de32629c3 - arm-trusted-firmware/plat/intel/soc/agilex/include/agilex_mmc.h be1098914558f70eba583d6ff1cbae6da84aefe7 - arm-trusted-firmware/plat/intel/soc/agilex/include/socfpga_plat_def.h 83dddfbc36bd0b0d2132cb5fdce3a0c4e4a546e0 - arm-trusted-firmware/plat/intel/soc/agilex/include/agilex_clock_manager.h a86635994a276adad357b7b9a9408af38860c61c - arm-trusted-firmware/plat/intel/soc/agilex/include/agilex_memory_controller.h f28f931b63cba463d5ec189bc42550444729edad - arm-trusted-firmware/plat/intel/soc/agilex/soc/agilex_pinmux.c 0701baf6d3a2c6d67485a189fa41e9c33fd20ca4 - arm-trusted-firmware/plat/intel/soc/agilex/soc/agilex_memory_controller.c 3c317104013baa1af66596ba8f1eef175f48843d - arm-trusted-firmware/plat/intel/soc/agilex/soc/agilex_mmc.c 92d9e49e6c214fc90bb4c35e673bc023e1c15880 - arm-trusted-firmware/plat/intel/soc/agilex/soc/agilex_clock_manager.c 16fa99d266e68db425dc073b83184b96d58bd140 - arm-trusted-firmware/plat/intel/soc/n5x/bl31_plat_setup.c 886bf1383cdc15c386329821d32302b814036a6c - arm-trusted-firmware/plat/intel/soc/n5x/include/socfpga_plat_def.h 40c2d9f804ed183a8befa38d61bdd2164d711b34 - arm-trusted-firmware/plat/marvell/armada/a3k/common/plat_pm.c 5ce8b4638274f9c66287b2f3662bb0bfcfc00074 - arm-trusted-firmware/plat/marvell/armada/a3k/common/a3700_ea.c d00c0cf869839d6cd370b5b6c58e8d066705e2e1 - arm-trusted-firmware/plat/marvell/armada/a3k/common/marvell_plat_config.c 344f94187e37e08b2f532eb66281e7e28e7702c5 - arm-trusted-firmware/plat/marvell/armada/a3k/common/io_addr_dec.c 1b64a7198143a5ec5cbe075762bfc0f47e7eded0 - arm-trusted-firmware/plat/marvell/armada/a3k/common/cm3_system_reset.c a8ca841fb42e9bb5a9c071732f25138003b82d96 - arm-trusted-firmware/plat/marvell/armada/a3k/common/plat_cci.c 4e66aa51fabafab21b8e01fa4f3d49fc8fe6a97e - arm-trusted-firmware/plat/marvell/armada/a3k/common/a3700_sip_svc.c f0aaac82be8c1b465622b1b82d8514de62c2e937 - arm-trusted-firmware/plat/marvell/armada/a3k/common/dram_win.c 6a269296c2d98fb8f6f4c1736696c4e6081cbc88 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/a3700_pm.h 6c89be0e3e7e102687ce8d216227785edce4db33 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/ddr_info.h 61ab3a7cf4de99459f74b40ee4aa7c4c063f92ab - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/platform_def.h 71cc1316bcad08255d76ad0ad858f47d681be60d - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/a3700_plat_def.h 0e8b8f431e24f28a92fcd4fb9d46eb87a1113db4 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/io_addr_dec.h 12bd9050e1d74b888a3866cf8ff79d17103fd0f2 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/plat_macros.S 58c7ff47a2230af870313a655dcab4f22dd64957 - arm-trusted-firmware/plat/marvell/armada/a3k/common/include/dram_win.h 6a97369a4a693cf002e5f5f6ece32516e5978068 - arm-trusted-firmware/plat/marvell/armada/a3k/common/aarch64/a3700_common.c 80f0ae31f4c2b57b330b01be44b293f6aa2cef72 - arm-trusted-firmware/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S 965bc32da1f0ff9aa830bcede48eaca19cbe3b29 - arm-trusted-firmware/plat/marvell/armada/a3k/common/aarch64/plat_helpers.S 716620282caf3210c15f6795e996035311a8ddd8 - arm-trusted-firmware/plat/marvell/armada/a3k/a3700/plat_bl31_setup.c 2cecd73b6df5a49196420939a6810672640ce165 - arm-trusted-firmware/plat/marvell/armada/a3k/a3700/mvebu_def.h 8f4af50a0df849dd31970be55e943ee4302b0472 - arm-trusted-firmware/plat/marvell/armada/a3k/a3700/board/pm_src.c 9a52294343831155772b4411f11af6c989dbd182 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0/mvebu_def.h c0c43ed673f4f38bd78a3d145c4ff0f553bf3032 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0/board/dram_port.c 027eab15e763f75779fca4721b6612e1cef0f74a - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c 80de920eee6f0214b1cfb2cf104cd6d295bb478b - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h c7d9738b5d030b72c12bb9649d2dfb58e180b5b8 - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0_amc/mvebu_def.h eecb4e28621a6ea2bbe58371406ef5f58590424c - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0_amc/board/dram_port.c 8eca9aa01df9af91fe07386e941d7557eae7d0ce - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c b79710e67347483f51ba3aa8fcb25a7f7dbb5083 - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0/mvebu_def.h e0382b98cbf2ae3613453ec924646d5af8b1f11e - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0/board/dram_port.c a3184b54f314a3880b11bd80e9ace2a825e4e251 - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c 9a52294343831155772b4411f11af6c989dbd182 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_puzzle/mvebu_def.h 4d33d263a3f05c3d8f3400a45afc2dd7f1792669 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c f1c6500edd19c1540f562c4ea2dba8443a7cd419 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_puzzle/board/marvell_plat_config.c 7bdf0ea1da45eaab8f21dca700b29582ccc57d0a - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c 266ed9c2a714504a190f6bdd10db0d40815a428a - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_pm.c f1e7a83b618d37eb2df8dcc4cff814b934a4ab74 - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_thermal.c c96d4c2fac061ca1e3be3600ee8748de11d20ed0 - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_pm_trace.c bc3edb20ef2a7baebacce2c631f800cb6d206bbc - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_bl1_setup.c 3f6403fd39850e34f4c3bd674ccf8170f74af43d - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_bl31_setup.c 4f7afd096359c9aad1f7852029a643db033fe7c7 - arm-trusted-firmware/plat/marvell/armada/a8k/common/plat_ble_setup.c 8d8ccf9d72fb421744052b95f2dc698844542a67 - arm-trusted-firmware/plat/marvell/armada/a8k/common/ble/ble_mem.S 29b7013d6e080d93a60b3780f10310e29aaa6bbb - arm-trusted-firmware/plat/marvell/armada/a8k/common/ble/ble_main.c 04e2455b39d088cb56ccb73dac9c842fb6f6b7eb - arm-trusted-firmware/plat/marvell/armada/a8k/common/ble/ble.ld.S 9fe71c8db281a9fc253c959e2bf8d7ed5b59f658 - arm-trusted-firmware/plat/marvell/armada/a8k/common/include/ddr_info.h 0f1625972d53fdedca61514318bdfd1ca806ac51 - arm-trusted-firmware/plat/marvell/armada/a8k/common/include/a8k_plat_def.h eb840b0d5bb6e8cbd42b1ab32b72baec165926e7 - arm-trusted-firmware/plat/marvell/armada/a8k/common/include/platform_def.h 86c5d3b710ba9b63aaf82c0f9dc1606c22176f45 - arm-trusted-firmware/plat/marvell/armada/a8k/common/include/plat_macros.S 3145664e80460f27bc2fd8cda127e916e518678f - arm-trusted-firmware/plat/marvell/armada/a8k/common/include/mentor_i2c_plat.h 97ae958df0c9d8f54ff36a7803fe0ba27434e45c - arm-trusted-firmware/plat/marvell/armada/a8k/common/mss/mss_pm_ipc.h 9acdf9fa5a506b13c376584f49b42a4f437af6c5 - arm-trusted-firmware/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c cc11d9f29f29d9c9366f3e6c66183d38e3031ab7 - arm-trusted-firmware/plat/marvell/armada/a8k/common/mss/mss_pm_ipc.c 392f1834ac5b4679e9ae724c7cf1f3a20c0e566a - arm-trusted-firmware/plat/marvell/armada/a8k/common/mss/mss_bl31_setup.c f83bec0cc962f915447a4582455414387713f7ac - arm-trusted-firmware/plat/marvell/armada/a8k/common/mss/mss_defs.h 4b2131b48e6b858b49e7e4d819172c5bc729f213 - arm-trusted-firmware/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c 01f390bd22a88039e1fc5f2d062ca126dae34478 - arm-trusted-firmware/plat/marvell/armada/a8k/common/aarch64/a8k_common.c 919f5232edc5f6c3ec1670dedf5bf25fbb59356f - arm-trusted-firmware/plat/marvell/armada/a8k/common/aarch64/plat_helpers.S 29e2e91f84a20d0c2f220e0eba6c447909e5aab4 - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0_mochabin/mvebu_def.h 8211399dfbf7994faafa28d85d5d232265c000fe - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0_mochabin/board/dram_port.c e26cc9cf2cffd853101d24b0e6cade82ff5f5cbe - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0_mochabin/board/marvell_plat_config.c 99aea1bcabb4f6d0d7452ad42116629d21bb2b61 - arm-trusted-firmware/plat/marvell/armada/a8k/a70x0_mochabin/board/phy-porting-layer.h 9a52294343831155772b4411f11af6c989dbd182 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_mcbin/mvebu_def.h 25524fffee705cfc27dd670e05523c5de9ef0ed6 - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_mcbin/board/dram_port.c 586996360a2bcce38bf90fa0b1b7a20a45c6e26b - arm-trusted-firmware/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c 1a879218f61e83b5068e40a2b093fdb4ab851a4d - arm-trusted-firmware/plat/marvell/armada/common/marvell_ddr_info.c db23baf6374a79472a4b930f1fd68144d4f314a1 - arm-trusted-firmware/plat/marvell/armada/common/marvell_bl2_setup.c c6e2fab47d050265fe94d5ce57fd1a3a684da2c9 - arm-trusted-firmware/plat/marvell/armada/common/marvell_topology.c 2c689ed8bfb3abf1dc9ea37ffaa8aa9479649eac - arm-trusted-firmware/plat/marvell/armada/common/marvell_bl31_setup.c 5f97ccaef3ab26b2710ad26fb0fdbd9facfd0b7d - arm-trusted-firmware/plat/marvell/armada/common/marvell_gicv3.c e8797c2639ec349e76fc1946c984275c010e4cc0 - arm-trusted-firmware/plat/marvell/armada/common/marvell_console.c 6ea11f2ef3d7978e714cdf621aeb7c8719c7edf3 - arm-trusted-firmware/plat/marvell/armada/common/marvell_bl1_setup.c 59510c739cc2d9619a9a5c21e1cbf1bb05094867 - arm-trusted-firmware/plat/marvell/armada/common/marvell_pm.c c785e8c07a0fa5d01b9ecf8eee873f7a18697e3a - arm-trusted-firmware/plat/marvell/armada/common/mrvl_sip_svc.c 79f7407103c1059afb212382689fff9c6a4f4350 - arm-trusted-firmware/plat/marvell/armada/common/marvell_io_storage.c 0ff28a152c1c0997120e1e3a5fe654f1ae19ac60 - arm-trusted-firmware/plat/marvell/armada/common/marvell_cci.c 69ee13cde36accbde0f355f89f9cc2b5d1aa2cb9 - arm-trusted-firmware/plat/marvell/armada/common/marvell_image_load.c 9fa0f4b8209945eb39ccee90bcc305efbe10f211 - arm-trusted-firmware/plat/marvell/armada/common/marvell_gicv2.c ea896d0f1d011e14c4411020d73d083c22eac783 - arm-trusted-firmware/plat/marvell/armada/common/plat_delay_timer.c 42d2fb2461687118d1f9e79ed2ae2a274cc91c45 - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_ipc_drv.h 44573513efade3da9aa2ca94c3d4069a8af646fd - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_mem.h 56e5fda520a793a37c7e8daa1ecfe2354b26e99e - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_ipc_drv.c 872e517062b5b548f6de42424dfb8290309f6773 - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_scp_bootloader.h 5cecfb1042c66b79c4c4c9bc5961fd91b34c880f - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_scp_bl2_format.h 0bb02e303d4c696fe34379bc2d5dd9f2fe16229d - arm-trusted-firmware/plat/marvell/armada/common/mss/mss_scp_bootloader.c a71cc21b90eb5b1d29b125e9c98c3e50f9a145bc - arm-trusted-firmware/plat/marvell/armada/common/aarch64/marvell_helpers.S 0842c4cae12a7c22367b83357a2c824d060dee67 - arm-trusted-firmware/plat/marvell/armada/common/aarch64/marvell_common.c c990f5d612bc8d238855b21005f4771531af3124 - arm-trusted-firmware/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c 65b77a7dbb8e28f892af2bf3b76eff17c87a9cbd - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130/mvebu_def.h a1f884a99e9e14ac83551e73429b0cf7a2c5aa0d - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c 147f2e7e737cb6a5eb1dd98a0deed8c0462d2041 - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c 2311f962795291fdd649a3acb3d3fcee85e19d11 - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h 60baba93a9e38f989d8f3fdfb045849d1edc2d69 - arm-trusted-firmware/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/marvell_plat_config.c d25ef41e434700921c3427ff0dac7aba4b81e1ba - arm-trusted-firmware/plat/xilinx/versal/versal_ipi.c 7a7cc273f02a2bb687d9cbdb064ea628cf8ae499 - arm-trusted-firmware/plat/xilinx/versal/plat_topology.c a72274d6a08a1768eebe97dcee5b711d1d1ea691 - arm-trusted-firmware/plat/xilinx/versal/bl31_versal_setup.c 359fecdbc2aea1f92150901c3b69081173688574 - arm-trusted-firmware/plat/xilinx/versal/plat_versal.c ae93ab3d9073a13aaab98c76cbff9539cb6b8402 - arm-trusted-firmware/plat/xilinx/versal/plat_psci.c f241ecfc0ce4c6677cbaca2991578232a4c20ad7 - arm-trusted-firmware/plat/xilinx/versal/sip_svc_setup.c b32dca9e82fc194265815e96dc44c232f292898f - arm-trusted-firmware/plat/xilinx/versal/versal_gicv3.c 3ee0b3ebf248c8195e9dea15b7601482c3fb9c9d - arm-trusted-firmware/plat/xilinx/versal/include/versal_def.h 5126174019498cc7fe5c93b70f586b64eb2f6761 - arm-trusted-firmware/plat/xilinx/versal/include/plat_private.h 1a5dc34056175e8444f3545c0f174dff3dcb536b - arm-trusted-firmware/plat/xilinx/versal/include/plat_pm_common.h 734b58fe20a10f52da076fc2667f0bf5bd8c8d39 - arm-trusted-firmware/plat/xilinx/versal/include/platform_def.h 50268618a09434af24c4a339c20a1b7b4a2e4901 - arm-trusted-firmware/plat/xilinx/versal/include/plat_ipi.h d43cd481e9d0acc960fc0f51fbeb274b0ec28712 - arm-trusted-firmware/plat/xilinx/versal/include/plat_macros.S 9dbd3610b2589c93fc91024ed8d39f4e5725d8ec - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_defs.h 67797b5d7b79d4fe75c894faa289f6d4deac5929 - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_node.h 7725db323b24ae5a9fadf6a242bc50d82835b86b - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_api_sys.h 95df6ca84bc196e5f5b6e22cce245ae78217a107 - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_api_sys.c 4248e970a1ba169aa4892274e272df8e52df5e00 - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_client.c a3cd953fef7447b80fc303931cdb6e6e0a9cb0da - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_svc_main.h 984dedbce16b4eb8de9a934f61b48768753b7d7a - arm-trusted-firmware/plat/xilinx/versal/pm_service/pm_svc_main.c 6b87bc415258116316a3b89d124ff4be9d5fd944 - arm-trusted-firmware/plat/xilinx/versal/aarch64/versal_helpers.S 17c00132a2d1c14af4ec8aac0677c8cec6838112 - arm-trusted-firmware/plat/xilinx/versal/aarch64/versal_common.c 4cc25fc42bd45d2db2be80b630d57a12fc244ab4 - arm-trusted-firmware/plat/xilinx/zynqmp/bl31_zynqmp_setup.c 9eafad8129f35d9d02d9cc93d60e653c41e3b321 - arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_ehf.c e3f68c1d366163959ee86ecdeed4a1400a451117 - arm-trusted-firmware/plat/xilinx/zynqmp/plat_topology.c 4018dd905c37ab4e205c88450ef0d6b0a1d45041 - arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_sdei.c ea6d37faa54c270b3c68586b921a880ead5d06fd - arm-trusted-firmware/plat/xilinx/zynqmp/plat_psci.c 06c4f927cc1972bc5c9da0d5a445bd2e617e9e23 - arm-trusted-firmware/plat/xilinx/zynqmp/plat_zynqmp.c a56515dee5e536d653d6f81080b25c90afbcd220 - arm-trusted-firmware/plat/xilinx/zynqmp/sip_svc_setup.c 3c9875ea4481fc73b7478362a4d3fb716a56ce1c - arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_ipi.c 51f1c62f9ff5f61f509efbd45107c18e9d199569 - arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_private.h fcc8c8052c715326e932fd7e210fe0beefa2d175 - arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_pm_common.h 804ff5cf868ee33695565baa638b234a4fb88f0d - arm-trusted-firmware/plat/xilinx/zynqmp/include/platform_def.h ece26f9de6cb348c48126562b55e4a6b7e3275ed - arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_ipi.h 8ede155c56692751835019579474fd5fbda5ba26 - arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_macros.S 3126b7881aa02ce6b3375b4c5fc63b612a49d311 - arm-trusted-firmware/plat/xilinx/zynqmp/include/zynqmp_def.h 19fc437eb2fad50da7e96ada0f240279ec999548 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_defs.h 15cd9e7e290094d6002d1934f0e3c8c9fc024fa8 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_clock.h 0f260822c28ad7d167b9e6518455595189f44d56 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c 53dfba6afcea5d904e8bc0154b54bb40dc2e373d - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.h 6595a97b0d15954b0fdf5ce2a0dab9eee0f95cf6 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c 1f232985388dd1bc7f786370a7d5262c0022ed0a - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h a2440b2db19c0d9b8afd5de045b6af7197f9d1c9 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.c 17c2b51fe84ffb00f831d2dc387700fd9ec3df71 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_client.c 86a5a63e53f6e9e9369f277e88db5ddf8947f749 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.h b6ef82c65316f3bfd6fa3fbd79088a652c04c455 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h 493682fea368bdb72b7efa045ae43eaead367f65 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.c 5cc1b6fa9d7c8c883304ec32fd2fb3268abce7d9 - arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_clock.c f82a0ba91d921f8782dbacd326cf93f93d406ff3 - arm-trusted-firmware/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c 625ae1615d3ffcf7e9729014864cef8550139b20 - arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_common.c bca57ae928a46e00c62d44205c7238c103d89723 - arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S 052bcf3e3faadeecd571f842f4acddd8e5ebc9c9 - arm-trusted-firmware/plat/xilinx/versal_net/bl31_versal_net_setup.c bd2f98d5580345c25ebef9aa23a21577aad582a7 - arm-trusted-firmware/plat/xilinx/versal_net/versal_net_ipi.c 0bd5915515d8c23e7e331b6086287b2219e72329 - arm-trusted-firmware/plat/xilinx/versal_net/plat_psci_pm.c 5027c913c3c05768e6940b33572c26060600dda8 - arm-trusted-firmware/plat/xilinx/versal_net/plat_topology.c 041003fe9f65969fe198a0fa296c5f55d19e467d - arm-trusted-firmware/plat/xilinx/versal_net/plat_psci.c 7d4dffbd821b16f6280da0d85589e54112af561b - arm-trusted-firmware/plat/xilinx/versal_net/sip_svc_setup.c 5a179f8f1e79815b3b2ff741d750d8e30edf887c - arm-trusted-firmware/plat/xilinx/versal_net/versal_net_gicv3.c 1a77c8bcca937be5c1bd35a38bb5b7ccea0086a1 - arm-trusted-firmware/plat/xilinx/versal_net/include/plat_private.h 263a46ff8b559789752c4a6407d8baea90978bd2 - arm-trusted-firmware/plat/xilinx/versal_net/include/plat_pm_common.h b983f677eb7e6502b569fda58d4bc74f2c278106 - arm-trusted-firmware/plat/xilinx/versal_net/include/platform_def.h 7c7e0815080db04ce31603877d4a391ffbe8c937 - arm-trusted-firmware/plat/xilinx/versal_net/include/plat_ipi.h 843bf8581070f83c6ed1cecc93eb4358f0a18877 - arm-trusted-firmware/plat/xilinx/versal_net/include/versal_net_def.h 75b5f8d16b2af5b0f7bda432ba1d2dec2cfd56ff - arm-trusted-firmware/plat/xilinx/versal_net/include/plat_macros.S 02b48cd3c217599176d86b00b98acf959a42b990 - arm-trusted-firmware/plat/xilinx/versal_net/pm_service/pm_client.c f8acccd8f94d785953e24d764a4a12a6cd86393f - arm-trusted-firmware/plat/xilinx/versal_net/aarch64/versal_net_common.c 9f621e3103cc6252e44148714e3a20d4d3f79781 - arm-trusted-firmware/plat/xilinx/versal_net/aarch64/versal_net_helpers.S 70a3081ce068629c8ad7e61e96d23da774a4dac5 - arm-trusted-firmware/plat/xilinx/common/ipi.c 76d25750fdd11451198c4f9e0850aa537a773df6 - arm-trusted-firmware/plat/xilinx/common/plat_startup.c 127d5b6672e9e114dfed723d5cd61b804def4b5f - arm-trusted-firmware/plat/xilinx/common/include/ipi.h 60cc821ff7abe1f421c5e66630717c6e30154c10 - arm-trusted-firmware/plat/xilinx/common/include/plat_startup.h ab5c0545a54fbd173cbecbb576dddfc7238419af - arm-trusted-firmware/plat/xilinx/common/include/pm_common.h d9b73bfa7792124a294a3c3f64980e36dd06c458 - arm-trusted-firmware/plat/xilinx/common/include/pm_ipi.h 88bc86a89827430321362f9dcaa7bc3d8e023059 - arm-trusted-firmware/plat/xilinx/common/include/pm_client.h 6e4f82021a75a4172004be07c575351283307cea - arm-trusted-firmware/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c 4862191b3291da0974839d79ccc335c03151a333 - arm-trusted-firmware/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h 010c7e9ea00c3336aa39f3a0ec508f771614e097 - arm-trusted-firmware/plat/xilinx/common/pm_service/pm_ipi.c 33ec06e0674715932071745b37498c738414ee8f - arm-trusted-firmware/plat/ti/k3/include/platform_def.h f2111ae0b834107dddf37cb4846a7065472db0fe - arm-trusted-firmware/plat/ti/k3/include/k3_console.h 734674f35450e45ca0c58c9036e71a978ef8407d - arm-trusted-firmware/plat/ti/k3/include/k3_gicv3.h da89ff4506058f3e90a127f4e7d79a7d86057bfd - arm-trusted-firmware/plat/ti/k3/include/plat_macros.S 96d874b239805cfedc0fadfd9f07eed0e423a919 - arm-trusted-firmware/plat/ti/k3/common/k3_helpers.S 170634ac25c995303394743ee26ab4f2265800ca - arm-trusted-firmware/plat/ti/k3/common/k3_topology.c 4677f1e48833ef10dc9d9ed492dfe849c8466b05 - arm-trusted-firmware/plat/ti/k3/common/k3_console.c 17f32476111c7a6c8fbb1903c6f09ddcd7a2188a - arm-trusted-firmware/plat/ti/k3/common/k3_psci.c fd1bbe596ff44d2104431c2924e172d0ef4c5b34 - arm-trusted-firmware/plat/ti/k3/common/k3_bl31_setup.c e7af4119b7b224d4db963739334e05efc40352c9 - arm-trusted-firmware/plat/ti/k3/common/k3_gicv3.c 27b2ba24623a62aa30daea138411571e17aeb579 - arm-trusted-firmware/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h d3624f3dc097829d1b9f6b277bd1aebe77963d97 - arm-trusted-firmware/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c 2318551075aa817413a9db54c0d7e55dbfbf6e86 - arm-trusted-firmware/plat/ti/k3/common/drivers/ti_sci/ti_sci.c 64ac58ae7f73656cb094306caf6259d8ad0adf65 - arm-trusted-firmware/plat/ti/k3/common/drivers/ti_sci/ti_sci.h 7a2e0003d64b5e2bc3e218d124a90dc529ac69eb - arm-trusted-firmware/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h c7ddd4760ae395c7e0e845a27777a73fdcbdf6ed - arm-trusted-firmware/plat/ti/k3/board/lite/include/board_def.h 571ddc2a22b19054342209337c7bbaa4bca47f54 - arm-trusted-firmware/plat/ti/k3/board/j784s4/include/board_def.h 85bfc710f2f6c79b7c0e025f6f6e653d16f39bb7 - arm-trusted-firmware/plat/ti/k3/board/generic/include/board_def.h f5a23e3802d2c1d7b94a9fb3c62e5b43cf3283ac - arm-trusted-firmware/plat/allwinner/sun50i_r329/sunxi_idle_states.c 3fa3a563994fcf2710324634950265fc8f9d7850 - arm-trusted-firmware/plat/allwinner/sun50i_r329/sunxi_power.c 2870bd5728ae0e5857fadde22b048a6fcf6ee2d3 - arm-trusted-firmware/plat/allwinner/sun50i_r329/include/sunxi_ccu.h d430caf710295e9e77a240b785740fdde6705e26 - arm-trusted-firmware/plat/allwinner/sun50i_r329/include/sunxi_mmap.h 1acbdb220cff8edffa7cc7fd4808f71574b90966 - arm-trusted-firmware/plat/allwinner/sun50i_r329/include/sunxi_spc.h f8fae43c9902bbf818480c6633e05fc6b751aabd - arm-trusted-firmware/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h f5a23e3802d2c1d7b94a9fb3c62e5b43cf3283ac - arm-trusted-firmware/plat/allwinner/sun50i_h616/sunxi_idle_states.c 786942614a650ccd6930f2bd19bb42b2b539e1f9 - arm-trusted-firmware/plat/allwinner/sun50i_h616/sunxi_power.c 1590f260f1febbedf931a1596cea2d2e437ea92b - arm-trusted-firmware/plat/allwinner/sun50i_h616/include/sunxi_ccu.h 2b80f35aa1746d608c2eac4eec351c292e0298f0 - arm-trusted-firmware/plat/allwinner/sun50i_h616/include/sunxi_mmap.h 3dde76eb498c889851714b3d8e6749211c62bbec - arm-trusted-firmware/plat/allwinner/sun50i_h616/include/sunxi_spc.h 0ba24eb82465b3d3ad4e293692984b972663d57c - arm-trusted-firmware/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h 7c04eab85ab52983fe11df7e0b2bd05d9500729d - arm-trusted-firmware/plat/allwinner/common/sunxi_common.c 704da3ea1b61d5106a6172712ecf6a80b1528bf0 - arm-trusted-firmware/plat/allwinner/common/arisc_off.S a35cee830ec32f0b3aadec9d5859cc0edde18ca0 - arm-trusted-firmware/plat/allwinner/common/sunxi_pm.c f2bc1957fa87b9880744d070c964b7803c7bf295 - arm-trusted-firmware/plat/allwinner/common/sunxi_topology.c 1475b73e29f2726ff49707c2527361e6a4b1e9d2 - arm-trusted-firmware/plat/allwinner/common/sunxi_scpi_pm.c b832fd1c1d7bc307d2c3698bf00ee15b93de8cb8 - arm-trusted-firmware/plat/allwinner/common/sunxi_cpu_ops.c e602a60b0fabfe8e91ecf654c16701712b20c3f1 - arm-trusted-firmware/plat/allwinner/common/sunxi_native_pm.c 522a372bd9aee035e1cde2200f2e599f19d6a040 - arm-trusted-firmware/plat/allwinner/common/sunxi_bl31_setup.c a44feb979fffb71189cf9943a6d99946305122e2 - arm-trusted-firmware/plat/allwinner/common/sunxi_security.c 0ded87657ff47f0fe5896f1ab1d6d2f9b34f0429 - arm-trusted-firmware/plat/allwinner/common/plat_helpers.S 9aaf3008124ddaf584b655e91f5e7f77af6762c0 - arm-trusted-firmware/plat/allwinner/common/sunxi_prepare_dtb.c d582e96cda9b2a3c482ce41d9a67c7954ec620af - arm-trusted-firmware/plat/allwinner/common/include/sunxi_def.h 882b0a00bd44fa0f716f94c278beb28761d0e229 - arm-trusted-firmware/plat/allwinner/common/include/sunxi_private.h 31a7e9055463700ee8fc1104f79949816de6f944 - arm-trusted-firmware/plat/allwinner/common/include/platform_def.h 7d746a44b6a3bbaa1c3e923de0abdfc40393712e - arm-trusted-firmware/plat/allwinner/common/include/plat_macros.S 77455765d6d80bf4a48d7744bf6f4770b7369215 - arm-trusted-firmware/plat/allwinner/common/include/mentor_i2c_plat.h f5a23e3802d2c1d7b94a9fb3c62e5b43cf3283ac - arm-trusted-firmware/plat/allwinner/sun50i_h6/sunxi_idle_states.c c2785b4c0937862f1abb7251642a4028a913504d - arm-trusted-firmware/plat/allwinner/sun50i_h6/sunxi_power.c 1590f260f1febbedf931a1596cea2d2e437ea92b - arm-trusted-firmware/plat/allwinner/sun50i_h6/include/sunxi_ccu.h 2514153e63bbcc5513712db8766fd278fa3b0d44 - arm-trusted-firmware/plat/allwinner/sun50i_h6/include/sunxi_mmap.h 3dde76eb498c889851714b3d8e6749211c62bbec - arm-trusted-firmware/plat/allwinner/sun50i_h6/include/sunxi_spc.h 0b8b7ce5f06e24ad7b853125e17507934dfc45e5 - arm-trusted-firmware/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h c8e9b163151610444afe368cd3525dc165595d51 - arm-trusted-firmware/plat/allwinner/sun50i_a64/sunxi_idle_states.c a38730b258e2c37f114fdb3c923369bade8e7a1a - arm-trusted-firmware/plat/allwinner/sun50i_a64/sunxi_power.c 65eec287284371a887adc4c9aa1952c26be66df7 - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/sunxi_ccu.h 3f4f908a2f0a6a7660d40d79215077ee248f740e - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/sunxi_mmap.h 2c5ad97e48086e62d1d58d1d8289ac4ab3153179 - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/sunxi_spc.h a462f612d127344fc711a68e3751b31b2b7ce938 - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h 54ee3b911a552e2cd6e3802820f5cf3e09575a01 - arm-trusted-firmware/plat/allwinner/sun50i_a64/include/core_off_arisc.h c7afb73f40f0759cd775aec59723f92f7dd54435 - arm-trusted-firmware/plat/common/plat_bl1_common.c 9a2a266c43747a7efa24c0b5dcc1f8cd7affd77d - arm-trusted-firmware/plat/common/plat_gicv3.c 8020a28923a271101b29516f4997bb7a1b8a6708 - arm-trusted-firmware/plat/common/plat_spmd_manifest.c dd38f3a1079a17328d48c8cb719713d4de7361a6 - arm-trusted-firmware/plat/common/ubsan.c 195d9f6a57eaa5525666a31bad43c24c5b6f8cc7 - arm-trusted-firmware/plat/common/plat_gicv2.c ca3750949173b2315d20907e7c6da4a66f32a5cf - arm-trusted-firmware/plat/common/plat_bl_common.c ec9195d2ba3b66b6f4258c18a36b14a5cf41ac55 - arm-trusted-firmware/plat/common/plat_psci_common.c 5e22516412e81af7bbc52e0e460447cf2d1d63f3 - arm-trusted-firmware/plat/common/plat_log_common.c 36144ebe1637da9185e2256593f8aa7307d0cccb - arm-trusted-firmware/plat/common/tbbr/plat_tbbr.c f742befce701fed79ec16b324c92409b36838226 - arm-trusted-firmware/plat/common/aarch32/plat_sp_min_common.c 2f11ce1b9cf6e69ec84aaca831735fcb77ab9bc8 - arm-trusted-firmware/plat/common/aarch32/platform_helpers.S 79f7a0e7df796600cfad4b11f4bf7dbafb65a4ea - arm-trusted-firmware/plat/common/aarch32/platform_up_stack.S 578b46ce0ccf74ba18ce1747df871537294d4ddf - arm-trusted-firmware/plat/common/aarch32/platform_mp_stack.S 05ebeff6ee2416ab2697799fb338367a03b0ba75 - arm-trusted-firmware/plat/common/aarch32/plat_common.c c8eab49f9d5326ffc974d2ba7c05bd411df90eb1 - arm-trusted-firmware/plat/common/aarch32/crash_console_helpers.S 53568d8d4a43005d8a1be8a379cf0f4b7ddc5637 - arm-trusted-firmware/plat/common/aarch64/platform_helpers.S 1fe60996e262523b671b678aa41a510a2cfa2ce9 - arm-trusted-firmware/plat/common/aarch64/platform_up_stack.S 785a7be686f124f8b30c5f96bbdc9670988f49c2 - arm-trusted-firmware/plat/common/aarch64/platform_mp_stack.S ebd158bd333d7179cda2ea7ec89f06269458ddd6 - arm-trusted-firmware/plat/common/aarch64/plat_common.c 8bf3a22931bb5a18034f1275429068834943cb9e - arm-trusted-firmware/plat/common/aarch64/plat_ehf.c 8be9392135f6389b22910a9e22011c2e5abc6708 - arm-trusted-firmware/plat/common/aarch64/crash_console_helpers.S da446db6b40b974a31d66ba55f23047f28d3f748 - arm-trusted-firmware/plat/arm/css/sgi/sgi_interconnect.c c6341f0f666b8a901520e32310b18a323af9f925 - arm-trusted-firmware/plat/arm/css/sgi/sgi_topology.c c94b450df6acdbadb362a07e171bda21eeebc43f - arm-trusted-firmware/plat/arm/css/sgi/sgi_plat_v2.c a12ad9fe2e578f1c9186976a41033a398307aba6 - arm-trusted-firmware/plat/arm/css/sgi/sgi_ras.c a0d413ba6f916898703d3e92672a47e884f0a460 - arm-trusted-firmware/plat/arm/css/sgi/sgi_plat.c 11d8cfb6e0edafbb6ddbc2ea973d521e8a6cbeb6 - arm-trusted-firmware/plat/arm/css/sgi/sgi_image_load.c 76bbec9213c7d768e35fc8eb3833867643da0627 - arm-trusted-firmware/plat/arm/css/sgi/sgi_bl31_setup.c 138c1bc36bb3c91d2b2d9f5ac1702aa0975c850c - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h f340bb1f1f4dcfde1ab65f3d67e26a33025f37a6 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_sdei.h 94d80de987f2ce932b0ca41f2b48f540a342b0a0 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_soc_css_def.h 39df7df7edfc75c87a8874267d8a593a05b50fd6 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_variant.h 81b2886ee53d898274e18c14f6f466511d2c6dda - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_base_platform_def.h 5972e7acb9e93b201406ff9cf0cbab522f942eb3 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_ras.h 27f76e3e4eb310e1d6262b27f27f55010b9ffda0 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b45c063aa1fdf9280c52020500ae6e83d71244c5 - arm-trusted-firmware/plat/arm/css/sgi/include/plat_macros.S 42a0e02948578c19827684fd1870be1821b76c66 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_soc_platform_def.h c388d0822e5ef0bf97db4c66ab46d4088421f0e6 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h b30c67527c7802085733426c8c113a7ab2492ce8 - arm-trusted-firmware/plat/arm/css/sgi/include/sgi_plat.h aeb8a1b51452a7c1b9088cd2cc5f0c6ab2590b45 - arm-trusted-firmware/plat/arm/css/sgi/aarch64/sgi_helper.S f00b456e46701cc6a1e2b31fdd93091805ab0809 - arm-trusted-firmware/plat/arm/css/common/css_bl1_setup.c 75cc05419580aa9e613157ed0cacf5e0447c7d7b - arm-trusted-firmware/plat/arm/css/common/css_bl2u_setup.c 3bc7caa521ce87bd672c20940f330d81613afdc1 - arm-trusted-firmware/plat/arm/css/common/css_topology.c e35946648a3f4e38af67096b19e7cbe49324a3e2 - arm-trusted-firmware/plat/arm/css/common/css_bl2_setup.c 24eb9c67fbb392767ee5be52c7e73641f4c74abd - arm-trusted-firmware/plat/arm/css/common/css_pm.c 29476751ce928c5170b93c840f4fd925619fb9f9 - arm-trusted-firmware/plat/arm/css/common/aarch32/css_helpers.S 3ddcf64aa2f7a53edf4016ea4d4c636a371f4516 - arm-trusted-firmware/plat/arm/css/common/aarch64/css_helpers.S bb20b499eb4fed681f076d21eeabaaf686b1c7fe - arm-trusted-firmware/plat/arm/common/arm_bl2_setup.c 60e57974dbb765f8039eca7d2d1eb2d1c984b6f1 - arm-trusted-firmware/plat/arm/common/arm_bl1_setup.c c3c969f538ef3f3853d867a2c9c020723e5adc66 - arm-trusted-firmware/plat/arm/common/arm_tzc_dmc500.c 9ac215f26148ab94b630463319c086d3e8b88c31 - arm-trusted-firmware/plat/arm/common/arm_bl2_el3_setup.c 5f8fb896e304dbb204531641566de21b2e53a426 - arm-trusted-firmware/plat/arm/common/arm_tzc400.c dd2c481628c54d07d905a85f08e527943473d31b - arm-trusted-firmware/plat/arm/common/arm_nor_psci_mem_protect.c f2f3b9e0893c37d6ecae1332b3df925e9ab4d30f - arm-trusted-firmware/plat/arm/common/arm_console.c 53d385569ada7ff06030853184930078d8a2e4d8 - arm-trusted-firmware/plat/arm/common/arm_cci.c 000e2caa19a9821e0bb2e5c0a9ee102f7e0d8d99 - arm-trusted-firmware/plat/arm/common/arm_dyn_cfg_helpers.c f156559b1bbad3210329982534bb9f8f47d3bd0a - arm-trusted-firmware/plat/arm/common/arm_bl31_setup.c 8d5a41b0cad025e83538d4508b8de54c96dd6be8 - arm-trusted-firmware/plat/arm/common/arm_pm.c cd95670c369591d9f552605b6c7a3eb62882da7a - arm-trusted-firmware/plat/arm/common/arm_common.c abdb20c16e5bae6df0e447b4a356eb5b9ed3eda0 - arm-trusted-firmware/plat/arm/common/arm_bl1_fwu.c 61b4b6215ec4cf4e050d7a14359bfdc2b64e2d8e - arm-trusted-firmware/plat/arm/common/arm_sip_svc.c c568af7da3024b7d6747f5fb2b560fea22018e31 - arm-trusted-firmware/plat/arm/common/arm_dyn_cfg.c d663fd87f45498acaee1a4325d0e44e561dd102a - arm-trusted-firmware/plat/arm/common/arm_image_load.c 70afb2dd0a66c2a2b6eb5bfaf16df448d90e029d - arm-trusted-firmware/plat/arm/common/arm_io_storage.c fde62327d83289a093f9126cd1fbd07a704e63b2 - arm-trusted-firmware/plat/arm/common/arm_err.c 842368bd1a44c1ece633a1254dc3cdaa4983c6ae - arm-trusted-firmware/plat/arm/common/arm_topology.c 758c96ae68613d1d656825a271d08c5c7f4ee780 - arm-trusted-firmware/plat/arm/common/arm_gicv3.c 3b628c17fd98697338a0997a380df8a81c7d2e66 - arm-trusted-firmware/plat/arm/common/arm_bl2u_setup.c 9b812991736d46b06d462799a31eb49ffae96260 - arm-trusted-firmware/plat/arm/common/arm_gicv2.c 667de698f76e8d0b6d6f1b85f8012f3bed27e925 - arm-trusted-firmware/plat/arm/common/arm_ccn.c 9e473b6458e0a41a90cfd20021aa925abeeb0a49 - arm-trusted-firmware/plat/arm/common/trp/arm_trp_setup.c 361186531a919bdc7825945fec639bf0db44800f - arm-trusted-firmware/plat/arm/common/fconf/fconf_nv_cntr_getter.c c67f1c965e03e1e11a2032a79f3592845f4eb1d8 - arm-trusted-firmware/plat/arm/common/fconf/arm_fconf_io.c dce55e77a6a4b9da7a42be37f5bba717d0c353e0 - arm-trusted-firmware/plat/arm/common/fconf/fconf_sdei_getter.c ec085ad0ac3025f41f02161b77f8c4ee60775114 - arm-trusted-firmware/plat/arm/common/fconf/fconf_ethosn_getter.c 3ddfbb8ae3448f315371d7a3a814bea1d055cd3a - arm-trusted-firmware/plat/arm/common/fconf/arm_fconf_sp.c ac62b3ab6e132e1747dbd2ffd6f40a72b4270235 - arm-trusted-firmware/plat/arm/common/fconf/fconf_sec_intr_config.c 8c6171b381cfc6eca906ce2f7e2e6658895380ca - arm-trusted-firmware/plat/arm/common/aarch32/arm_helpers.S 2147b3c541e549d0bc01f00aed57c924d90d6003 - arm-trusted-firmware/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c 3237cf84bb44f0cc5b45b74d69d2934525543135 - arm-trusted-firmware/plat/arm/common/sp_min/arm_sp_min_setup.c cacda44b3716b65a5c30eedd17ed5a1335b8597b - arm-trusted-firmware/plat/arm/common/tsp/arm_tsp_setup.c a60fe2bc76c9c5a5a3a4e04918884fd7983a6c8e - arm-trusted-firmware/plat/arm/common/aarch64/execution_state_switch.c cc6a2551546758984d250e491c5c077149044f98 - arm-trusted-firmware/plat/arm/common/aarch64/arm_helpers.S 3fc67b6c1c162e05c28e1ac8a50d8a35ec97eb2c - arm-trusted-firmware/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c 1177013eddcf476b6a6d1f3367ae319363663450 - arm-trusted-firmware/plat/arm/common/aarch64/arm_pauth.c 8543903cea745c6c6709fd524622d3d5d3fd8df2 - arm-trusted-firmware/plat/arm/common/aarch64/arm_sdei.c 08fffa1ca580eaca04a26cfc974edd901c2997b1 - arm-trusted-firmware/plat/arm/soc/common/soc_css_security.c 87d9fc22d1228a7faf0c17443f9d5afd194e4334 - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_err.c 103c2c1d17da9dfaab63bca2f61e6bd21aa82c19 - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c b0261bd454617bc33a79aa98dcfa987149992300 - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_bl1_setup.c 4a175994a02eeb79a8ccc76f0b3be5ac2d45771d - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_private.h af1f8d5af2ee91ba0dd180c42a7b8f73b7543474 - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_security.c 6733f3383940d86208b8239c1d08d9221c2c2929 - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_common.c b370460e14d8e464d9f852b0e3f18cf2dca4950b - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_pm.c a924444b8053fdd6d907961d26d25ef0d3a207f7 - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_topology.c 300e69aa5df2f362bc3ddf1c430fe3fab03f11da - arm-trusted-firmware/plat/arm/board/fvp_ve/fvp_ve_def.h 2ff5ebca71b32318bae21e3dbb7699236b9cbe61 - arm-trusted-firmware/plat/arm/board/fvp_ve/aarch32/fvp_ve_helpers.S d56cac77b62eee0ed50166d2264e0a00c8fe4ffa - arm-trusted-firmware/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c 19f1b6fffc9b7e4d8a55730d5dc6740b06415c71 - arm-trusted-firmware/plat/arm/board/fvp_ve/include/platform_def.h 996afef966d673534a7502180616ba362cdb0d9c - arm-trusted-firmware/plat/arm/board/fvp_ve/fdts/fvp_ve_tb_fw_config.dts a857b4f74c6a05502271795dcd7a71f24a024b41 - arm-trusted-firmware/plat/arm/board/fvp_ve/fdts/fvp_ve_fw_config.dts 0b886935846ab1d278829932851b6cc492f106cc - arm-trusted-firmware/plat/arm/board/juno/juno_bl31_setup.c 50963e02933b9165b4b2c2a4b8ce7f8cc758df7d - arm-trusted-firmware/plat/arm/board/juno/juno_trusted_boot.c bef868e2dcb239da5ba7d1787c2f790e1f31d33a - arm-trusted-firmware/plat/arm/board/juno/juno_err.c 8a5716ff7852804effaf5810a335e69d3a788a50 - arm-trusted-firmware/plat/arm/board/juno/juno_trng.c b9b538be910b8f73b7432358e0f07f30e602b2cb - arm-trusted-firmware/plat/arm/board/juno/jmptbl.i ebbb9c3ccbc5ea001a213d0ba5a9b7744bd561dc - arm-trusted-firmware/plat/arm/board/juno/juno_tzmp1_def.h 07f098d234d16533d40b505e91dbb1aae1712650 - arm-trusted-firmware/plat/arm/board/juno/juno_security.c 905aac590f6fdf10096fd3e0f4bb661a2953acfb - arm-trusted-firmware/plat/arm/board/juno/juno_bl1_setup.c 0ff3d7a6c51d9752cc2a86bb19e800a94245eea2 - arm-trusted-firmware/plat/arm/board/juno/juno_stack_protector.c 419b6382a2607911be10024a6287e69289234326 - arm-trusted-firmware/plat/arm/board/juno/juno_topology.c 17d854b860806d6ad8af6ee63952524a3bcbd9e9 - arm-trusted-firmware/plat/arm/board/juno/juno_pm.c 53c5a79a63bf1f5551016da97e29bf8702e32ad3 - arm-trusted-firmware/plat/arm/board/juno/juno_def.h 6cea3743018f1d02cac51c8d78a92561ea46ce14 - arm-trusted-firmware/plat/arm/board/juno/juno_bl2_setup.c d784833f267d4a24f2a529767e8892a4aa11df9d - arm-trusted-firmware/plat/arm/board/juno/juno_common.c 319dfb0515299119770970eb5953825ab7abd95c - arm-trusted-firmware/plat/arm/board/juno/aarch32/juno_helpers.S 9bc7c91b290d19799c80d9254b6d86d7dcbf3e94 - arm-trusted-firmware/plat/arm/board/juno/include/platform_def.h 53f8c45c8436fb9bb4378cd8782a0b7d8037e5d2 - arm-trusted-firmware/plat/arm/board/juno/include/plat_macros.S 805360ecd38e071b1f2e9b60704130be813557e2 - arm-trusted-firmware/plat/arm/board/juno/fdts/juno_tb_fw_config.dts dfc9edcda0daf49b40451e94c30405aa901ef204 - arm-trusted-firmware/plat/arm/board/juno/fdts/juno_fw_config.dts 4780ddabb988fa673f07503011a00242d2ea9faa - arm-trusted-firmware/plat/arm/board/juno/aarch64/juno_helpers.S d2cf1d7868d3a048734caa91b018fb43f56c36dd - arm-trusted-firmware/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c 8908fa02b1140f0d45e9bdcc3d5552190eb3af41 - arm-trusted-firmware/plat/arm/board/corstone700/common/corstone700_security.c 9351efb35af5c14748c7b05d814c8176be5b8716 - arm-trusted-firmware/plat/arm/board/corstone700/common/corstone700_plat.c df9742f665da99900fe4a3fdc0b6fbcc02209a0f - arm-trusted-firmware/plat/arm/board/corstone700/common/corstone700_pm.c 5f0ac09b373c85fd1d635fb4f06ea45011389b19 - arm-trusted-firmware/plat/arm/board/corstone700/common/corstone700_topology.c 3d1a55d785180dd11beb8473207268d04543695a - arm-trusted-firmware/plat/arm/board/corstone700/common/corstone700_helpers.S ed51f976efc9644368dd64840ed3d158c086650e - arm-trusted-firmware/plat/arm/board/corstone700/common/corstone700_stack_protector.c c7a771e05849f4d7b946b8b3c32ba774fbff39dd - arm-trusted-firmware/plat/arm/board/corstone700/common/drivers/mhu/corstone700_mhu.c a3a970e3ac6e7d75b9c190fb16599a2ab423f3db - arm-trusted-firmware/plat/arm/board/corstone700/common/drivers/mhu/corstone700_mhu.h 3c1fd619c9a1da90f7af84b9c6e1b8eceb5e7a20 - arm-trusted-firmware/plat/arm/board/corstone700/common/include/platform_def.h cdf2af8fe7e5ba8b9ff36e04a33ebff2cf20f79b - arm-trusted-firmware/plat/arm/board/a5ds/a5ds_bl2_setup.c 7d714f8f2b3f7274c9d2e73eaa5d46215c7d3911 - arm-trusted-firmware/plat/arm/board/a5ds/a5ds_err.c be0cd4f5f48b5eb3a64885536643645036173809 - arm-trusted-firmware/plat/arm/board/a5ds/a5ds_common.c f2a71185ac9189cbe4310e27a7ead8d40c23c377 - arm-trusted-firmware/plat/arm/board/a5ds/a5ds_pm.c 007839db0f0e5c02b3362ce770b02771a47faa27 - arm-trusted-firmware/plat/arm/board/a5ds/a5ds_topology.c fabc6650d0d7860d4d615e5e997c72bed71aecb3 - arm-trusted-firmware/plat/arm/board/a5ds/a5ds_bl1_setup.c c6fdde231ff1fe0ddb8f585bd3fead2a7f2f0f46 - arm-trusted-firmware/plat/arm/board/a5ds/a5ds_security.c c8bea252a67bd4f3ad0910e3dadd0b76dc62c7f3 - arm-trusted-firmware/plat/arm/board/a5ds/a5ds_private.h 142d4bce7860550461e2498ba8c9f4ebb17d902d - arm-trusted-firmware/plat/arm/board/a5ds/aarch32/a5ds_helpers.S a8eb0724c2056ed80453ea31aa3ebc822e93ffa2 - arm-trusted-firmware/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c 189ef1e9d436f631711b2a4bd2e75efb635a322a - arm-trusted-firmware/plat/arm/board/a5ds/include/platform_def.h 996afef966d673534a7502180616ba362cdb0d9c - arm-trusted-firmware/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts adc821bdac8aebcefb26e3f8cd54497b3b8dfab4 - arm-trusted-firmware/plat/arm/board/a5ds/fdts/a5ds_fw_config.dts 866a21334d0661b2dde96c9ea5c2e2c99e649ab3 - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_trusted_boot.c 851570d1add4283d5a01ff4893f1558decb2d6e9 - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_topology.c 1d0b4260fe8a6c2a5d54c62bf8f386935c28968b - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_plat.c 561594e99d3e16d7826006d518e141e9a58eadec - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_security.c 7d37a6f29bbe666c9db7538d4d7a123d1ab40b17 - arm-trusted-firmware/plat/arm/board/rdn1edge/rdn1edge_err.c 432792585d2507e4ec5aa343420eb1a274a819c2 - arm-trusted-firmware/plat/arm/board/rdn1edge/include/platform_def.h 5d0744ed59fc75ba7204d9d0083fbc0cd64e74d6 - arm-trusted-firmware/plat/arm/board/rdn1edge/fdts/rdn1edge_fw_config.dts 869fa43b401d5d394651f9d1bd9eb784b7ebb14d - arm-trusted-firmware/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts a87583e95c695a2bf6af550cd6fbbffb3eae3961 - arm-trusted-firmware/plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts da7cdbbeb9c965719cb254b7e1d2167fe50b88b8 - arm-trusted-firmware/plat/arm/board/common/board_arm_trusted_boot.c f06e3bb0c501f8c6d86fc8db78e724dcf47cb291 - arm-trusted-firmware/plat/arm/board/common/swd_rotpk/arm_swd_rotpk_rsa_sha256.bin 80a8b20bcc3bcbf794bc78499c52841c807ec68e - arm-trusted-firmware/plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S 4907b4eaa1230000b1db585d555d4fd41be655b8 - arm-trusted-firmware/plat/arm/board/common/swd_rotpk/README ee231e4311e32bd023dc5df9d23a580c2109fe2a - arm-trusted-firmware/plat/arm/board/common/swd_rotpk/arm_swd_rotprivk_rsa.pem d7941a7e9ec8fa11c4dd7580b57e1543e335d61b - arm-trusted-firmware/plat/arm/board/common/aarch32/board_arm_helpers.S f63762c7a16038a4bc3a046a89d815cf9ae9089b - arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem 99b2edcf01ed68e8e25f2687d31ef61f0531f26f - arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotpk_rsa.der b48500f3591ea941f29e3cb482855cd947d886c3 - arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotpk_ecdsa_sha256.bin 2b0cf90adf32af769b93e85764f195737286be65 - arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotpk_rsa_sha256.bin 64194de14ee2424df1ca72d388c407f3d0c16184 - arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem b22a3e04b7c492d96f48978250bd02b1de04304b - arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotpk_ecdsa.der c4cd605f9796351468c8e3427ec60a3ab5966a93 - arm-trusted-firmware/plat/arm/board/common/rotpk/arm_dev_rotpk.S a819075a49fd85dede74b56ddededf2f4c046f07 - arm-trusted-firmware/plat/arm/board/common/protpk/arm_protprivk_rsa.pem cdb90754cb9118d6571aad9c3846b2c410f708d1 - arm-trusted-firmware/plat/arm/board/common/protpk/arm_protpk_rsa_sha256.bin aa5febfe9cf8a923785e2509c54c7e03032167e7 - arm-trusted-firmware/plat/arm/board/common/protpk/README ce90ae54534188e8ed455e84da4ee7656807dc45 - arm-trusted-firmware/plat/arm/board/common/protpk/arm_dev_protpk.S 885dbc360b97a82697b2978ae8f5665ba4878080 - arm-trusted-firmware/plat/arm/board/common/aarch64/board_arm_helpers.S bbb015479be8a51c7ec691d5a9283657dd1b6de1 - arm-trusted-firmware/plat/arm/board/morello/morello_plat.c 275ff8fd1cb66a02cc8ca9b9494035d3aa7f8ebf - arm-trusted-firmware/plat/arm/board/morello/morello_image_load.c 846d7f92ffe6c368d0d0b85ffa36409b0dd04caf - arm-trusted-firmware/plat/arm/board/morello/morello_trusted_boot.c d115cd145587e366c9c6d02d47cc7ea610f7791f - arm-trusted-firmware/plat/arm/board/morello/morello_security.c 03a2e96479894138f50468a179aa59836db7df08 - arm-trusted-firmware/plat/arm/board/morello/morello_bl2_setup.c c855687b5adb537f1a56e37496a708864bd72650 - arm-trusted-firmware/plat/arm/board/morello/morello_bl1_setup.c 4f730b658c4d20887e0c7d6293b90f37cf62fa26 - arm-trusted-firmware/plat/arm/board/morello/morello_bl31_setup.c 0105670429d8a205bc698cf69de09044501a55a1 - arm-trusted-firmware/plat/arm/board/morello/morello_topology.c 710e4ce5fe08ed123d1977361a4bbf49dff07ba9 - arm-trusted-firmware/plat/arm/board/morello/morello_def.h 59b5177c9b302f117bea58642d758d747224eaed - arm-trusted-firmware/plat/arm/board/morello/morello_interconnect.c 021dca0ec2928f72c45e98a602338d8a2bb08cc2 - arm-trusted-firmware/plat/arm/board/morello/morello_err.c e1eb7e2194a62fcfa63e0d92da3567386d98a24d - arm-trusted-firmware/plat/arm/board/morello/include/platform_def.h 5361abb465b0253014c38facafec374dd284699a - arm-trusted-firmware/plat/arm/board/morello/include/plat_macros.S bf30791c97940cf78bee90bb458a53b2480a4154 - arm-trusted-firmware/plat/arm/board/morello/fdts/morello_nt_fw_config.dts a95b1476c52a6213400f2402811d15e5d82d7d83 - arm-trusted-firmware/plat/arm/board/morello/fdts/morello_tb_fw_config.dts 9c4c899115425303ba08c836c2a6ca740418160b - arm-trusted-firmware/plat/arm/board/morello/fdts/morello_fw_config.dts 1c3ff5d4d35a2aa211380dea2b252236f3dae0b1 - arm-trusted-firmware/plat/arm/board/morello/aarch64/morello_helper.S 70fd1afdd7b31d55ddd95d7018ba66095315083e - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_topology.c 89a8aeb02e2a9467d783383e96d830647443b99d - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_bl31_setup.c 0ca4a4d2749cd227831e57d361b8c16ee0f3cf03 - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_gicv3.c 15269f87cab6dfa65ce9cbaacbb13ee9cf2af583 - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_pm.c fe445cbd11196fc3c69cdcbc6be5cdbc4354026b - arm-trusted-firmware/plat/arm/board/arm_fpga/build_axf.ld.S 1cfbd3237d5138875eda5a3f57ebd08f452c4992 - arm-trusted-firmware/plat/arm/board/arm_fpga/kernel_trampoline.S bdf16498e248d1d87d012aca5001940fb8328395 - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_private.h 78391ad4c170cb70d2db6ad5639108f4f6020dc6 - arm-trusted-firmware/plat/arm/board/arm_fpga/rom_trampoline.S ef779e5f985f2ebef6d66a83442695603c463465 - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_def.h 86553039cac69d2003776608e4a3172af5f6263d - arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_console.c 6631f2221faec011381242d2e2011d9eda3e9780 - arm-trusted-firmware/plat/arm/board/arm_fpga/include/platform_def.h 87820ef2083d1576c3d29546b46fb922eafa3737 - arm-trusted-firmware/plat/arm/board/arm_fpga/include/plat_macros.S 205b5febc22c83179a2fc6c9005499ef61e8f347 - arm-trusted-firmware/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S 866a21334d0661b2dde96c9ea5c2e2c99e649ab3 - arm-trusted-firmware/plat/arm/board/sgi575/sgi575_trusted_boot.c e717578fd539b138146efa385134192a8aa4055c - arm-trusted-firmware/plat/arm/board/sgi575/sgi575_plat.c 95aa905a5aa0734b8993eaf65aa91924c6ba1ccd - arm-trusted-firmware/plat/arm/board/sgi575/sgi575_topology.c 3aff6d693c63d2b2dc58205e075552c4f14e24c2 - arm-trusted-firmware/plat/arm/board/sgi575/sgi575_security.c 4bcbaa1f0a092433b2d017ed4941be94943fa552 - arm-trusted-firmware/plat/arm/board/sgi575/sgi575_err.c bcfd1ed6049c78b3929107750fd430051ca8245c - arm-trusted-firmware/plat/arm/board/sgi575/include/platform_def.h a19b040188761f8bccb0937f9f397e3b191c143e - arm-trusted-firmware/plat/arm/board/sgi575/fdts/sgi575_nt_fw_config.dts 77c37592e064ebc47319196a2468d4a75a6ff7de - arm-trusted-firmware/plat/arm/board/sgi575/fdts/sgi575_tb_fw_config.dts 9f8fd7d90d63ffe6d71473664ec09b7aa4cdf607 - arm-trusted-firmware/plat/arm/board/sgi575/fdts/sgi575_fw_config.dts 1f85fcf3a3d2c0bd5a8c5e848a4841400b54f9fe - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_private.h b1777d180724d85711393cf136ad5b34e80ce86a - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_def.h 2ce9cd0a5ef399a537316089ff1451da165bdd42 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S 2b7e3adfdb026d5ab4fa54d23c6ff105d9d5e633 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_bl1_setup.c e985480b9d1aa1426a500f3c4869a1f32bb8b422 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_io_storage.c b5fe2445bbd4cfd3d360d2d930d9358c4eed5555 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_trusted_boot.c 61fa6bbfd2f41f1cc6fe1c4caacb1fa09461692c - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_helpers.S 5f78d5ae0c4547371279bfc19196f01fb454e3b6 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c deb3a6a31fba479e597c0ae722532692996e2372 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_common.c 860f2b3b1633322a3865add4e226f457c1a7237d - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S 181e66fa9c41732917a323ee0fe465da3b5ce36d - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_stack_protector.c efd5139ee502cdc5570d9ec338ee84b3410067fd - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_misc_helpers.S 8e7bab3de835fbccc87f8d20b8acecc011d4fcaa - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_debug.S 486d3021b7aeeb557efb82cafa7337d3d3041fb7 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_bl1_main.c db240cab0da9aaf6298ede4c8418abd28744a258 - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_err.c b20640f66687a9edf5c361b2cf32bf1244777ecd - arm-trusted-firmware/plat/arm/board/fvp_r/fvp_r_context_mgmt.c e9c7e8c62f6a1ac8f4b8f79ebb080765f9244fbe - arm-trusted-firmware/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h 5356ccdf1172f23b213522e8c204e511fd9b8841 - arm-trusted-firmware/plat/arm/board/fvp_r/include/platform_def.h 866a21334d0661b2dde96c9ea5c2e2c99e649ab3 - arm-trusted-firmware/plat/arm/board/rdn2/rdn2_trusted_boot.c 73d0e620495671f0ffa9cfdd536e8f3c97f6e384 - arm-trusted-firmware/plat/arm/board/rdn2/rdn2_err.c c39970cf01913b1983d5d5de5df9f0594aa17080 - arm-trusted-firmware/plat/arm/board/rdn2/rdn2_plat.c 3693a7e757b2541552b2c91c91a0dba2d6a0a8de - arm-trusted-firmware/plat/arm/board/rdn2/rdn2_security.c 795d97596b09631253539c8a66fa49d5d422d01d - arm-trusted-firmware/plat/arm/board/rdn2/rdn2_topology.c 23cb4b07e11224d3835380c29ff7e97799593ef7 - arm-trusted-firmware/plat/arm/board/rdn2/include/platform_def.h 77c37592e064ebc47319196a2468d4a75a6ff7de - arm-trusted-firmware/plat/arm/board/rdn2/fdts/rdn2_tb_fw_config.dts a4ba16614c6a505745db29fa4630d16be498fa22 - arm-trusted-firmware/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts 3fa6109549ac24e3e9727ec6cfc9c34111cf53c9 - arm-trusted-firmware/plat/arm/board/rdn2/fdts/rdn2_fw_config.dts 79e40d92dcde7f9d17195a4a63d0608730af9c4b - arm-trusted-firmware/plat/arm/board/rde1edge/rde1edge_topology.c 4e3d6ef9cbb8925d20f8946cbf6f998ea3c4eb8f - arm-trusted-firmware/plat/arm/board/rde1edge/rde1edge_err.c aa3d4b5a511124fc6ae5cd9244633af5ae0ab4a9 - arm-trusted-firmware/plat/arm/board/rde1edge/rde1edge_security.c bb5bde77d451942a4effe8cd36463c1dfc1df462 - arm-trusted-firmware/plat/arm/board/rde1edge/rde1edge_plat.c 866a21334d0661b2dde96c9ea5c2e2c99e649ab3 - arm-trusted-firmware/plat/arm/board/rde1edge/rde1edge_trusted_boot.c a313f9d9379f97d4d9972ba55afd1183c324e96f - arm-trusted-firmware/plat/arm/board/rde1edge/include/platform_def.h e5b638c1ab3d0ee37ca9b8702ee4262358c3559b - arm-trusted-firmware/plat/arm/board/rde1edge/fdts/rde1edge_fw_config.dts 1477905828689906107808c1098cccb0a22dc73b - arm-trusted-firmware/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts 0397a242841f6193faacaba41c8326032a1e7729 - arm-trusted-firmware/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts fe8cc2e85b4f542f5e3598a28a47287a535b24fc - arm-trusted-firmware/plat/arm/board/fvp/fvp_gicv3.c d38a95d1f5ad91c3e864092385cc54e8e8ef7cce - arm-trusted-firmware/plat/arm/board/fvp/fvp_common_measured_boot.c 0c9d3267229403366a43f37306593c660c95628b - arm-trusted-firmware/plat/arm/board/fvp/fvp_drtm_measurement.c 08b0026f4dffa89a42ad4c11149acce9a60fa627 - arm-trusted-firmware/plat/arm/board/fvp/fvp_err.c 79c69d8696ab8e4e4dd7f7dae5b7c797399173c3 - arm-trusted-firmware/plat/arm/board/fvp/jmptbl.i 18f3aa0aff6bb4d6f611db9497d43afc72362199 - arm-trusted-firmware/plat/arm/board/fvp/fvp_sync_traps.c 87220bf30d58a155c2f10f38418d094db212e5b6 - arm-trusted-firmware/plat/arm/board/fvp/fvp_private.h 79412e695ecbb03e3a0547e5f21f2bd1e40eb3a9 - arm-trusted-firmware/plat/arm/board/fvp/fvp_drtm_dma_prot.c a8b81a81c625a2d7a9ca4bfdfb0cdb99bc06225d - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl31_setup.c fc4f78f936a0a2bdad7090f496539847de766227 - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2_measured_boot.c 9becd5a35328d19646bc14bdbf52f66571aad713 - arm-trusted-firmware/plat/arm/board/fvp/fvp_el3_spmc_logical_sp.c 98977adb2cf0024fd193291f2990442bf4e58776 - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl1_measured_boot.c fa75b4ccee6e6d8604b819da30a1ed892db70b15 - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl1_setup.c 1570105ddfc280d36e64641b556bc2da9a0529dc - arm-trusted-firmware/plat/arm/board/fvp/fvp_security.c 86c2465abfadc0a5dfe9b561b0f5675db8fee013 - arm-trusted-firmware/plat/arm/board/fvp/fvp_stack_protector.c 71418933f8bb76fa971723d4cb9bc6748a009f33 - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2_el3_setup.c 10c7154aeb64129154f13657841ad8f9aee6af85 - arm-trusted-firmware/plat/arm/board/fvp/fvp_trusted_boot.c 19591a34444effbe25bc3245bb68e6462bda0024 - arm-trusted-firmware/plat/arm/board/fvp/fvp_pm.c 0cd688de833f2a18c6d772bd627a60f6ada7351b - arm-trusted-firmware/plat/arm/board/fvp/fvp_drtm_stub.c 9fc1159cfd38294a716a80afd2da3ca690fcb25b - arm-trusted-firmware/plat/arm/board/fvp/fvp_realm_attest_key.c aed35e7aa732be73eef26face244c3acdee67640 - arm-trusted-firmware/plat/arm/board/fvp/fvp_console.c 06847bf81aa287adc738ca7e18e792f817de2227 - arm-trusted-firmware/plat/arm/board/fvp/fvp_plat_attest_token.c 20e8179e5c61147fc2d627dbb503babac430603c - arm-trusted-firmware/plat/arm/board/fvp/fvp_def.h f6099efde790e929572be29c9d98bcfa1864e8e4 - arm-trusted-firmware/plat/arm/board/fvp/fvp_el3_spmc.c 82ed42473643f46d039c3fed625bfc4c52a73ea9 - arm-trusted-firmware/plat/arm/board/fvp/fvp_drtm_addr.c 1f4bd385163a4d08851a30681746396352c6d77b - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2_setup.c df0b10a5b65cf57a485f5eb846e0cfa7e64c429b - arm-trusted-firmware/plat/arm/board/fvp/fvp_io_storage.c 2394ce186fe1fd2d76b8a728058bf8c779d8495e - arm-trusted-firmware/plat/arm/board/fvp/fvp_drtm_err.c 6f76c4d8ae1abb640a62785bfc535bcb485f9511 - arm-trusted-firmware/plat/arm/board/fvp/fvp_topology.c ef9c5a0fb7265f1ba0f41a24b4aefa35781372dd - arm-trusted-firmware/plat/arm/board/fvp/fvp_common.c 1924351967826f1ad9898254b30419ba2e7fb9cc - arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2u_setup.c 83e404fdd5bc4dda0b68b92d365d6e9b047f13d3 - arm-trusted-firmware/plat/arm/board/fvp/fconf/fconf_nt_config_getter.c 10fc5531e7b7d5ac9ffba191f525b64179843eae - arm-trusted-firmware/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 2c7ccf1e47b4fdac9dc7745e506f4194cce2e498 - arm-trusted-firmware/plat/arm/board/fvp/aarch32/fvp_helpers.S e4fcdd5d1b362e5247f4877f39ac24a55a02619f - arm-trusted-firmware/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c c6b81accb44678a523485111e3a272cfda2337aa - arm-trusted-firmware/plat/arm/board/fvp/include/fvp_critical_data.h 7ae5efc596f9378d386e60bc5f50985eb9cb361d - arm-trusted-firmware/plat/arm/board/fvp/include/platform_def.h aaff5cd1241ce58ab9627da89fb4860390a0864b - arm-trusted-firmware/plat/arm/board/fvp/include/fconf_nt_config_getter.h aed581dcf8acf86f277ecf028cc1eec4f0c081fc - arm-trusted-firmware/plat/arm/board/fvp/include/plat_macros.S 84180022623ad574044b9436e62202ee5635c6ae - arm-trusted-firmware/plat/arm/board/fvp/include/fconf_hw_config_getter.h 1f6772f1b9358e6acc890bc4475a57f68cebc72d - arm-trusted-firmware/plat/arm/board/fvp/include/plat.ld.S 5601a00daf6c8ba481f1addc03652d97efe84a3c - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_soc_fw_config.dts aba68daa32f394274fa0c7b3ebb2d77514e105da - arm-trusted-firmware/plat/arm/board/fvp/fdts/event_log.dtsi 9ad16d4008c6be1847f6efb82008607aff0ebaf3 - arm-trusted-firmware/plat/arm/board/fvp/fdts/optee_sp_manifest.dts e4d213d66811bdfc6375016599a2f2a901043fe5 - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_fw_config.dts 6d68ca2eec213a5065a5f8754f9544fa16682719 - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts df9f20c998402fb612824aeec7d618e97e023cb8 - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts 33a1a8c0c5e1f8f806d0dbe69adab509f55301be - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_nt_fw_config.dts 56e13f4a58600986e9375220ad5ff2f9c55cb305 - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts 26761d08528feec31bb15a854b65dd46629135fe - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_tsp_fw_config.dts fa01aa43bab7bb9524735734f410da8758264bdd - arm-trusted-firmware/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b59b8589b390aaea5c26a9621713fe3d78e47e8b - arm-trusted-firmware/plat/arm/board/fvp/tsp/fvp_tsp_setup.c d5a6187ffa8ab68518e9d896c2d50bbf600d68cd - arm-trusted-firmware/plat/arm/board/fvp/aarch64/fvp_helpers.S 3f4bcd29ccbf7cd09dfe8275846469b38db62e2f - arm-trusted-firmware/plat/arm/board/fvp/aarch64/fvp_ras.c 70913ecf05a6e846d99d63213b643de746a371e8 - arm-trusted-firmware/plat/arm/board/corstone1000/include/plat_macros.S 5562bd387d6506e0db4a62fe23b24cd1c5046754 - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c 665dd624982ad98f765987aa9abfb2a29f195e2d - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c c10b97a1764fe4c02c0a7ae81b0a75313edeed05 - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_helpers.S 1e7fe4ccc25d366dfe5f6a14851dab68001bdb13 - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_topology.c fbb932100f4228bb8fe153a58d84898837188f8b - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_err.c b9f80852b169e9c137876fadebe0782792162fe4 - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_security.c b8986dac246e932ea1ba7ee38e8e8ede263e1b24 - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c 22a37f39d795371d274a9f3846b68a893966da33 - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_pm.c ec5c4655dfd1f5f6c9cde2f1dea202506c0ea6b8 - arm-trusted-firmware/plat/arm/board/corstone1000/common/corstone1000_plat.c 35364097d95fff4d6dcac3d39086e9bd15167caf - arm-trusted-firmware/plat/arm/board/corstone1000/common/include/platform_def.h 16e3686521725b2e8cf355c2d990811fc260a02c - arm-trusted-firmware/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts 07a42e98f0211f264decd0d40369a5a22999a7a4 - arm-trusted-firmware/plat/arm/board/rdv1/rdv1_err.c daecdf40f28b13596b217b424164a59b35baa192 - arm-trusted-firmware/plat/arm/board/rdv1/rdv1_plat.c 1c209493074be7ae85b1aafe237784f10e2b7093 - arm-trusted-firmware/plat/arm/board/rdv1/rdv1_topology.c 866a21334d0661b2dde96c9ea5c2e2c99e649ab3 - arm-trusted-firmware/plat/arm/board/rdv1/rdv1_trusted_boot.c 39dd88b06678aa7f03906487a206a758c69bb621 - arm-trusted-firmware/plat/arm/board/rdv1/rdv1_security.c eb03bd37d9fe5130c83a90a8f6b4ae6ec5a70c9f - arm-trusted-firmware/plat/arm/board/rdv1/include/platform_def.h 3fa6109549ac24e3e9727ec6cfc9c34111cf53c9 - arm-trusted-firmware/plat/arm/board/rdv1/fdts/rdv1_fw_config.dts 77c37592e064ebc47319196a2468d4a75a6ff7de - arm-trusted-firmware/plat/arm/board/rdv1/fdts/rdv1_tb_fw_config.dts 4eee465e298e33cc2776504ed671b987022fb333 - arm-trusted-firmware/plat/arm/board/rdv1/fdts/rdv1_nt_fw_config.dts 04538cf26382d09d8e2c07c0b46f13a5b099236a - arm-trusted-firmware/plat/arm/board/rdv1mc/rdv1mc_topology.c 584cb4b05aeec673c6c04da7c3885037b079afa4 - arm-trusted-firmware/plat/arm/board/rdv1mc/rdv1mc_err.c b53ded92528c275e65fc5654ce2f65a96096309b - arm-trusted-firmware/plat/arm/board/rdv1mc/rdv1mc_plat.c 866a21334d0661b2dde96c9ea5c2e2c99e649ab3 - arm-trusted-firmware/plat/arm/board/rdv1mc/rdv1mc_trusted_boot.c 3f70fab8ee8fcd7926df2c977d9380f53cbbb9f6 - arm-trusted-firmware/plat/arm/board/rdv1mc/rdv1mc_security.c d44f2f7e1a20469a2ffaccbde28906fdcc5a60e6 - arm-trusted-firmware/plat/arm/board/rdv1mc/include/platform_def.h 3fa6109549ac24e3e9727ec6cfc9c34111cf53c9 - arm-trusted-firmware/plat/arm/board/rdv1mc/fdts/rdv1mc_fw_config.dts 77c37592e064ebc47319196a2468d4a75a6ff7de - arm-trusted-firmware/plat/arm/board/rdv1mc/fdts/rdv1mc_tb_fw_config.dts c139b0b044ff0f3122d7f6e5b65703bc3fbee8d2 - arm-trusted-firmware/plat/arm/board/rdv1mc/fdts/rdv1mc_nt_fw_config.dts 1f68f4b41cf660f6aecbd9c91cffd25b5da791a9 - arm-trusted-firmware/plat/arm/board/tc/tc_err.c e359fea3cdefe52d1384eaf4e3657d1a8639ce5c - arm-trusted-firmware/plat/arm/board/tc/tc_trusted_boot.c 4820529d3f2dd58d5a256494c687006b2eff63ad - arm-trusted-firmware/plat/arm/board/tc/tc_bl2_measured_boot.c c14c384694fa6f799c7df9925a9afa420147bc48 - arm-trusted-firmware/plat/arm/board/tc/tc_plat.c 89a5e32d31fb4109758d8eab72df17a1e36004e9 - arm-trusted-firmware/plat/arm/board/tc/tc_common_measured_boot.c 28488a6123a3f6e963e45167297c24b033c4ea20 - arm-trusted-firmware/plat/arm/board/tc/tc_bl31_setup.c e12be214b71705c426b59f867e2c1e12d74eb660 - arm-trusted-firmware/plat/arm/board/tc/tc_topology.c ded1714043a17b1985c18754683ddcc8a2954d2a - arm-trusted-firmware/plat/arm/board/tc/tc_bl2_setup.c 4335b9a6f68fb49824b223397621a29f3d1030c9 - arm-trusted-firmware/plat/arm/board/tc/tc_interconnect.c fc718361b3f42b952f8b5b107ca5aeacc22f9dc5 - arm-trusted-firmware/plat/arm/board/tc/tc_bl1_measured_boot.c ae19b2b5534ecfc11125374e36d9e8f859a89eda - arm-trusted-firmware/plat/arm/board/tc/tc_security.c 519d8a1e3c1a9b5ad5b03d86b69451ba3ac67a95 - arm-trusted-firmware/plat/arm/board/tc/include/platform_def.h 12e15891d91866e073604872dd843da7a55ab1ca - arm-trusted-firmware/plat/arm/board/tc/include/plat_macros.S 8ad72d03b3ba43d1683a1303fee28ea1c7be281d - arm-trusted-firmware/plat/arm/board/tc/include/tc_helpers.S 9660ea0d565256c4b8a124a3b15c393be1d5f9b0 - arm-trusted-firmware/plat/arm/board/tc/include/tc_plat.h b6a0718fcdad5e07263ed41c89641a47d843eb14 - arm-trusted-firmware/plat/arm/board/tc/fdts/tc_tb_fw_config.dts 46c4eb5b1105e6fcf9a5ebc8bb219b4f6250ef79 - arm-trusted-firmware/plat/arm/board/tc/fdts/tc_fw_config.dts 6d8e682b0e92f3c4b0317af9db0cf378942f0637 - arm-trusted-firmware/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts dd7dfe59caab52d2698deda4e52c6508f481ea7a - arm-trusted-firmware/plat/arm/board/tc/fdts/tc_spmc_manifest.dts 4b2fa306464372689007dbc453675d5ea6a5783d - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_def.h e50d2dd98343b489f7e7c65c66462d77e358058e - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_plat.c 31f172efc8e16bf86bc5a0266155410faa98e56d - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_trusted_boot.c 7104250da7bca258ddb0bf081570d32f8900092b - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_interconnect.c 65f4dae233a8130318848bb4b108b07c4580d531 - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_image_load.c 17cc0bef584ee2a5b4315f60a6c07b461b64cdbd - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_bl31_setup.c 7d80d6700188f44364662e46113af9036afedcbc - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_topology.c 8bb93dc2fa4e107a6a9b7eaa82259298199588b3 - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_bl2_setup.c 4497a7586471f072a94ff5a066931c86dcb6fd2d - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_security.c c0478746f7abb1567136588aa75b9ec5142ebcea - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_bl1_setup.c c12269118b21e6143b6706a81b90cf54740d000e - arm-trusted-firmware/plat/arm/board/n1sdp/n1sdp_err.c cd7e3d3de668bb687ba56bcc08c15894451c4181 - arm-trusted-firmware/plat/arm/board/n1sdp/include/platform_def.h b45c063aa1fdf9280c52020500ae6e83d71244c5 - arm-trusted-firmware/plat/arm/board/n1sdp/include/plat_macros.S 138fe343329f375a545d7daa55144c70b2cbddb8 - arm-trusted-firmware/plat/arm/board/n1sdp/fdts/n1sdp_tb_fw_config.dts 85ebc38bf15e709a94617d0e22454746189c93a0 - arm-trusted-firmware/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts 7f1a7e1c53ebc90c5254e41517a96e05072b6af6 - arm-trusted-firmware/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts 9da6c3964d40da13feef13c16d595d7266ce7e68 - arm-trusted-firmware/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts 4b16feb977654bc82a89a104dc5b31b167bf17d1 - arm-trusted-firmware/plat/arm/board/n1sdp/aarch64/n1sdp_helper.S 1690035b8b9571d77eafa8b4dc7d1b5145635c1a - arm-trusted-firmware/plat/qemu/common/qemu_common.c 16002a1a28f7ec581aae95aba10964655f89c5dc - arm-trusted-firmware/plat/qemu/common/qemu_pm.c 00fcc8b29bf97f9ede1c2dfbe40db7ef83c72695 - arm-trusted-firmware/plat/qemu/common/qemu_spmd_manifest.c 16be159c4a5d2a3878237098afe450cac07536d1 - arm-trusted-firmware/plat/qemu/common/qemu_trusted_boot.c c154631e1880ac14882cbb7ec28846bcac331126 - arm-trusted-firmware/plat/qemu/common/qemu_bl31_setup.c fcbaa96813c363c3db4933b80039d532e1252dc7 - arm-trusted-firmware/plat/qemu/common/qemu_io_storage.c 21efcb8ca3eeadb04af0ad8b5dbff0a548221482 - arm-trusted-firmware/plat/qemu/common/qemu_bl2_setup.c 8ebb840a06cb6dddf6c0fd5fe4a612f832842576 - arm-trusted-firmware/plat/qemu/common/qemu_bl2_mem_params_desc.c 2085009221c46e8e62ac297e819084f4b6087615 - arm-trusted-firmware/plat/qemu/common/qemu_rotpk.S d78bd11a3e46b66140586c01d9f834a788316251 - arm-trusted-firmware/plat/qemu/common/qemu_gicv2.c a58c658f18083c55761b946dd01b034df662dada - arm-trusted-firmware/plat/qemu/common/topology.c 930aace47c80c680938c0b2934fc56ba412930da - arm-trusted-firmware/plat/qemu/common/qemu_private.h 95a9e39672a85b16243df6db511e352e068b90ee - arm-trusted-firmware/plat/qemu/common/qemu_bl1_setup.c ec654aff1a7a4e282bbbe2dc13b2042b9534eb61 - arm-trusted-firmware/plat/qemu/common/qemu_gicv3.c 3ca3d10548276087940fd7af8f274b1b68378322 - arm-trusted-firmware/plat/qemu/common/qemu_stack_protector.c ce499ea5552f0a580d2d730cd86b20a544fb4759 - arm-trusted-firmware/plat/qemu/common/qemu_console.c 51d8305f79f4736a224811e549fd92ffee6e2134 - arm-trusted-firmware/plat/qemu/common/qemu_spm.c 854064daf74a72113baf3004985576f30ed85540 - arm-trusted-firmware/plat/qemu/common/qemu_image_load.c 674a4514924db14c06277e39651b46250347d7a4 - arm-trusted-firmware/plat/qemu/common/aarch32/plat_helpers.S 553cd30299445b034280689989176963a39f2b4d - arm-trusted-firmware/plat/qemu/common/sp_min/sp_min_setup.c f58716f140fa8f450f8073fca6f98a8eda79bbc2 - arm-trusted-firmware/plat/qemu/common/include/plat_macros.S fe635c884df368ae689c259f9ac0787b17064bb4 - arm-trusted-firmware/plat/qemu/common/aarch64/plat_helpers.S a1a54b73ef6817449b27e96c2b447c7d42812d47 - arm-trusted-firmware/plat/qemu/qemu/qemu_measured_boot.c 550744a18b4aa7236d084b7faa39941e6e0fea6f - arm-trusted-firmware/plat/qemu/qemu/qemu_helpers.c a1a12a4a2a7978cb4f20160ecc843dc94ea76cf2 - arm-trusted-firmware/plat/qemu/qemu/qemu_bl1_measured_boot.c 5c21f6d26dfbcc5e7fefe1ca8e7bc4deeef4eb32 - arm-trusted-firmware/plat/qemu/qemu/qemu_common_measured_boot.c 25a1420f59573a9a4daa0ba527157db311b5df67 - arm-trusted-firmware/plat/qemu/qemu/include/platform_def.h a3366d3ea9b4a5a823b365b0a4fe16dd24af7388 - arm-trusted-firmware/plat/qemu/qemu_sbsa/sbsa_private.h f2efe87ffe7cd41bf5ac442c75b40fb2593a8fbb - arm-trusted-firmware/plat/qemu/qemu_sbsa/sbsa_topology.c 151cea63605746875bff4fceaa296485033aa280 - arm-trusted-firmware/plat/qemu/qemu_sbsa/sbsa_pm.c 46b611bd4d5b4370f104fdcc62cf5da040ec7970 - arm-trusted-firmware/plat/qemu/qemu_sbsa/include/platform_def.h e3aeb1fcc3d0ea558495c190263daaff95f76f64 - arm-trusted-firmware/plat/renesas/rcar/bl2_plat_setup.c 716e1c7c79baa403b9c5d0ef120f23d8cac8e802 - arm-trusted-firmware/plat/renesas/common/plat_pm.c 514484b073de3f03a0c25885d1947529d0863273 - arm-trusted-firmware/plat/renesas/common/bl2_secure_setting.c 12b42e58567a9ecd3d1d63318cb5ec7011a41573 - arm-trusted-firmware/plat/renesas/common/plat_storage.c a977937122b0a3096d2974c21e1d01713d54ef5b - arm-trusted-firmware/plat/renesas/common/plat_topology.c ffd1e457886f1089d9c344f701ec17dc97f8f074 - arm-trusted-firmware/plat/renesas/common/rcar_common.c 5f9406be82d4cf619e442556228de3e2d1283e39 - arm-trusted-firmware/plat/renesas/common/plat_image_load.c d414d4d769295e5a493cf3e77c9c51626ee0e6fb - arm-trusted-firmware/plat/renesas/common/bl2_interrupt_error.c ae71ad3a55f0e9c013697f9775e6c12c0ff7bd74 - arm-trusted-firmware/plat/renesas/common/bl2_cpg_init.c 9e2b414041c35052396135ebdc28539af32c2593 - arm-trusted-firmware/plat/renesas/common/bl31_plat_setup.c ea086669ab75f559b2e65b291fea3af158c18bd2 - arm-trusted-firmware/plat/renesas/common/bl2_plat_mem_params_desc.c aa601d2e26e65cab57efac1579ef07d5a4966f23 - arm-trusted-firmware/plat/renesas/common/include/rcar_version.h 2f021b7dce5115d413267052dd5b471ceff900cf - arm-trusted-firmware/plat/renesas/common/include/rcar_private.h 939b904cc911a51e5bfd33fc817d5c5b22e55400 - arm-trusted-firmware/plat/renesas/common/include/platform_def.h 72226e12e556432cb547181aa73e0d55c5c8777f - arm-trusted-firmware/plat/renesas/common/include/plat_macros.S f4aa97332efbbc8e20e48e338443fd3b9c208830 - arm-trusted-firmware/plat/renesas/common/include/plat.ld.S f99514b828a7a7fe6f0063a291c023d74a2c9bd2 - arm-trusted-firmware/plat/renesas/common/include/rcar_def.h 64ef91e2bf3528ac94c8eb79c5c3f80113257721 - arm-trusted-firmware/plat/renesas/common/include/registers/lifec_registers.h f773e9cbe28c8c27bd7013b66cd612cd63f790fc - arm-trusted-firmware/plat/renesas/common/include/registers/axi_registers.h f5943232ea7fe8a4717cdaa5d1f371ec634c8074 - arm-trusted-firmware/plat/renesas/common/include/registers/cpg_registers.h 3c4b66c3e0e2ea740399f2ac87b9c61af5c45031 - arm-trusted-firmware/plat/renesas/common/aarch64/platform_common.c 2b4770445484da2ea7c1061c5e772905f5f9eda9 - arm-trusted-firmware/plat/renesas/common/aarch64/plat_helpers.S d9c373f0351531965e8097178bbc13ede3af7485 - arm-trusted-firmware/plat/renesas/rzg/bl2_plat_setup.c 4dbec584881036aa37e59b66185d958a695a455d - arm-trusted-firmware/plat/nvidia/tegra/drivers/memctrl/memctrl_v1.c 164348d605c323efb61920d24f91b3e8067e2cff - arm-trusted-firmware/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c 4d04fd613146842b18904061da84f5958c44b16b - arm-trusted-firmware/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c fb218e655fd6a3d77f969fce9cd6cb5dd0a6c5b2 - arm-trusted-firmware/plat/nvidia/tegra/drivers/gpcdma/gpcdma.c d25c56f572cf7b3618f7567d502c1ee11dec2bae - arm-trusted-firmware/plat/nvidia/tegra/drivers/smmu/smmu.c 58fc3b165ee7a61397eef3e9f2065858876ce9de - arm-trusted-firmware/plat/nvidia/tegra/drivers/spe/shared_console.S 6f1dca2fba8be7758cfe4395226b2e4be820e3f1 - arm-trusted-firmware/plat/nvidia/tegra/drivers/pmc/pmc.c 8d9b8ebe2f8407dfc849bee6942b55d0a9c76d41 - arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp/bpmp.c 2a6016cc527d04ca332373c0d14542d5176aebf8 - arm-trusted-firmware/plat/nvidia/tegra/drivers/psc/psc_mailbox.c 8724a95f2af055e28a26a7fa510e1e2312dbb435 - arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp_ipc/ivc.h 29b42ced515a2a6ab925492a74ebb472d35665a9 - arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp_ipc/intf.h ea44439d01bb9f52d710121f37d71ecec4d7de36 - arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp_ipc/intf.c ecf2d932f335bc64d226c7d6502806590af552b6 - arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp_ipc/ivc.c ce1df43aa2a9700b9c00f14be842646284b3ee3d - arm-trusted-firmware/plat/nvidia/tegra/scat/bl31.scat 61343b0647173b58eec236e5f6781f95ee64f5d2 - arm-trusted-firmware/plat/nvidia/tegra/include/tegra_platform.h a5e64180eefbbe8a53719e8e53546a55a7466dcd - arm-trusted-firmware/plat/nvidia/tegra/include/platform_def.h 33618152dc9d927ecdc5b8542c2131cf6b9e0488 - arm-trusted-firmware/plat/nvidia/tegra/include/tegra_private.h 949736009adf4b730b592ef786e3d66eaf769d8c - arm-trusted-firmware/plat/nvidia/tegra/include/plat_macros.S 00ba4a09814b790749853248a68f57c1bf5d8a77 - arm-trusted-firmware/plat/nvidia/tegra/include/t186/tegra_def.h 80ba76cba14e63964ee35830536886c24581020c - arm-trusted-firmware/plat/nvidia/tegra/include/t186/tegra_mc_def.h 68ec103aabc7cf1ba96e9f802589f232bf63e8fb - arm-trusted-firmware/plat/nvidia/tegra/include/t186/tegra186_private.h ecb6bb2512f5f946927baadc3238cacaf9e9c42f - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/flowctrl.h b01b1d6699848ec430ef6c7ff1fa536c611ac8d8 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/bpmp.h 0005633528a5228ce544a5fe3fc8b984d26eff95 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/gpcdma.h dd094069cb1a5bb53cf55c4e87b2364925c1e25c - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/mce.h 7eee98bf96c4e615e71244fad2270fe3ac7bca96 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/spe.h e4e77bfcd8d045ecce243b060298bf229cbf3941 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/security_engine.h 97366374236e04da0a203c6df1ed7e93325e40f5 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/memctrl.h 6d07e5af0ce90657c3fa05b05110cc06037b6648 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/bpmp_ipc.h 1ad3acb2c35dab529632e51cfd8a1977d0a3e495 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/pmc.h eccbd7dbdb2b149abd38a48ddd5f6b0f292373b7 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/memctrl_v2.h fa073698981deb8685410d390184a2fea2477d8d - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/smmu.h 2693485a6a4c24984696bab65e09494c4af953a6 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/psc_mailbox.h 28825a53871fc7fdbdc73c536a3aecd05e9eb80d - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/tegra_gic.h d6acbb5f1eb851fbab413c7209bfba21509b4d31 - arm-trusted-firmware/plat/nvidia/tegra/include/drivers/memctrl_v1.h e2ee66cf2f19643997f9bd21f182be19a82c1f71 - arm-trusted-firmware/plat/nvidia/tegra/include/t234/tegra_def.h b76d085fd8bf62b29b2651fb2baafb167bbb3f37 - arm-trusted-firmware/plat/nvidia/tegra/include/t234/tegra_mc_def.h 81ea9f15588c258ecbc3f05e477af82433321620 - arm-trusted-firmware/plat/nvidia/tegra/include/t234/tegra234_ras_private.h 06b78efa72c2fd24fec6849056456faa9678a613 - arm-trusted-firmware/plat/nvidia/tegra/include/t234/tegra234_private.h fc8ce0bab3e269ab289babbc37c5ffea6c1105c1 - arm-trusted-firmware/plat/nvidia/tegra/include/lib/profiler.h 249831518e8554837fb8750d200cb4b786c2d683 - arm-trusted-firmware/plat/nvidia/tegra/include/t194/tegra_def.h 65dcb16996ba6f5480b25b088c00618a8401e2b0 - arm-trusted-firmware/plat/nvidia/tegra/include/t194/tegra194_ras_private.h 0770b19832587bf494cdf6a16cf0af55ef4e3eba - arm-trusted-firmware/plat/nvidia/tegra/include/t194/tegra194_private.h 8617ceef396a9a7f9b5e9e1a4866cede187f6ba6 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_sdei.c 7832f9e627bdeb224b72a22840b7b4cd3354b962 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_stack_protector.c 3ec4772e3564c951724bc646a368912365c2070a - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_platform.c bbb547cc93729fd63ae5da22480a94dc84ad6fbf - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_sip_calls.c 348ad39495b7209e9858421f7bd1a02f9712a410 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_pauth.c c7104ef4a0ccb4a2ceb01951a0c8442349cf4ca7 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_delay_timer.c f6b990f82323d07ea2950b6ce6ff8db7724dc1d9 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_bl31_setup.c c97649b9bd33d9e7f4268f6ddc79d603a3a317f2 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_fiq_glue.c fa85e2dbd21318c0c3aeb697b4dfc2d7a5a07e6f - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_pm.c b3f5f7ac2563ba78dea104674a6dd9403ad6206b - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gicv3.c 0c5a65d7362595eff6d472ba23ccde7af61d9ce8 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_io_storage.c 55b938cb527f31dfe8ec3b11bd74470694eec560 - arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gicv2.c c00b9f5780cdfda81db3419b659966b43f39373f - arm-trusted-firmware/plat/nvidia/tegra/common/aarch64/tegra_helpers.S bf02f90c1795b9e26f314ab310c0ba4e389257e4 - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/plat_secondary.c 0dd6e3b7ed73b5e77f6ebc89320058cde70900c2 - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/plat_trampoline.S 8ed0428c2133d5bcc570a67baa3ebdd5208cc7bd - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/plat_setup.c 106e68f73e09c8f51c620c0dd840b42ea6dbd67f - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/plat_sip_calls.c 5b9c61a07970be31ce559c1b2c78acc41d5223e3 - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/plat_smmu.c c7611d91a504dd3fe52ee769f9fa2d4f469010a8 - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/plat_memctrl.c a94f3bf95a41f47e1aae597082786cb5b8978350 - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c 34309aaec4559a7c2094873802490b96b9cf9dc1 - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h 34e8d1c4e060805a3f55969aabbd211dc6b08fbd - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h d96974438f18123824bf23413d2d0d75452fb4da - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/se/se_private.h 326d37fa1c2f92a2e56baf3391479c3dd1365396 - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/se/se.c 4588d011d8dbc1073379954dcdfb1c437cf9d4ce - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c cde1d7e2f8c3e1513d4828b37df69223bfb780be - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c 0a76eef9a0cb2d3c1fffc2a886eab6fdabb34997 - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c 015badf34dbdf2955bc1dc9f4b22627bde8f9f9c - arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/mce/aarch64/nvg_helpers.S c2cd522ab9668274cd7bf26fde63e9dbc9a94f28 - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/plat_secondary.c 653b68f60890691683fdca0db20bfd0b107308f5 - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/plat_setup.c e6ee29b4c786d6d279e82a4066d13703168bd28e - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/plat_sip_calls.c 3d01d365783ad5b2ce0f76df72a4a10db3d9a10d - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/plat_memctrl.c 5539d4b4adbd8a16367417d468bc7c27a07fa94a - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/plat_ras.c ddd85e1d0b1de3e76efb8ac87a71e7d4441b2795 - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/plat_psci_handlers.c 2a8ad3b4a69807fdca8231ae7fe2b8ecb8409a2e - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/plat_errata.c ce88b9f9a752b57b5a9b852374cefa3c2476672a - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/drivers/include/t234_ari.h 08aec0d0be276f69ddac5a77363f59f1ef42d88b - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/drivers/include/se.h 97be2d05021abe3f3efae84ce56f37d1597701c3 - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/drivers/include/mce_private.h 7641a42485d020517c692c523a29fe5be4136651 - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/drivers/se/se_private.h b445bacb5c4d8f02da2e408d0e5e7382b69c7108 - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/drivers/se/se.c 83d9b00e44be4758c0c5171072545bcc0d7feb8b - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/drivers/mce/ari.c 2cbef431f380eae34ec9bf1e4f71c37df3219721 - arm-trusted-firmware/plat/nvidia/tegra/soc/t234/drivers/mce/mce.c e17a699cecafbd3bdb8d61ca87a15bf611962a09 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/plat_secondary.c d893793283c93ce6c488a51940c01574780f7333 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/plat_trampoline.S a715ba2ed80e34193ccdccc4e3f808e07c3ef1a8 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/plat_setup.c d5aef4c8d30794a496c1c3bd18d000991bbae988 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/plat_sip_calls.c ba0a312824b0782a438e265e86a6e9d7638032db - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/plat_smmu.c 595bafd552b05d81a25e9916fe91779e18beddda - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/plat_memctrl.c c55c5c502ca4117b327d32cc3fef8203d3c64731 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/plat_ras.c 169df2b969afbaebb2dd262359264090342f12e5 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c ee3f4b7a69c6c3dd475a88c55076077415fc76b7 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h 298abb9097e851023b914f09fe36c8cdaf367e22 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/drivers/include/se.h 8cec2a63b748c24a5fab3c7c47f114b8147894c4 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h fa7909d4e0ccdeee6f0765cf68a95899ac8aec1f - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h ee99b21f1c4746989c94c7e3a6a28309b2cb7929 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/drivers/se/se.c 0cdfadd153db5ee7d515adb01dd35d62e546226a - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c ccebfe25a0f4bc54b5d08685ce74082118f713e4 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c 99d5d980ae032fa2dfb6e9da5fe48dd600b2a896 - arm-trusted-firmware/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S fbecdf95d5fb90503336b712a6955a36a635aac0 - arm-trusted-firmware/plat/nvidia/tegra/lib/debug/profiler.c 2321fbf75d8e96d90a1b6f6a14160c91b949cabc - arm-trusted-firmware/plat/amlogic/common/aml_scpi.c 1c810633809eed169ef7ae47da01b6326b111a64 - arm-trusted-firmware/plat/amlogic/common/aml_console.c f1168dcf0c90f4d7a3456d82b909e287a16875ed - arm-trusted-firmware/plat/amlogic/common/aml_topology.c 22fc306f5f9b6613312023233481baaf99493614 - arm-trusted-firmware/plat/amlogic/common/aml_sip_svc.c 887d16c962bbfdec5ddb366c33ffec0ad5697447 - arm-trusted-firmware/plat/amlogic/common/aml_thermal.c fa91c2d51bbe34be89ba41e055f4e78eba6ac67e - arm-trusted-firmware/plat/amlogic/common/aml_efuse.c 1b86970e6e211ba1548f3469a4682db7c31577f1 - arm-trusted-firmware/plat/amlogic/common/aml_mhu.c 74bc476713af13ff5ee94c7bdad6c5763f99e9af - arm-trusted-firmware/plat/amlogic/common/include/plat_macros.S 5240bdc42061a821a089cae1eeca3fb799e6aa1c - arm-trusted-firmware/plat/amlogic/common/include/aml_private.h 61752908966c74b637938d2fa11e73c5d5373d9d - arm-trusted-firmware/plat/amlogic/common/aarch64/aml_helpers.S 3667781fa0058dcdd1cff5587b45c798978c7966 - arm-trusted-firmware/plat/amlogic/axg/axg_bl31_setup.c 7fdb79ffddbe1ee7f1b2c543a1eaa07f2671a2ca - arm-trusted-firmware/plat/amlogic/axg/axg_pm.c c60f26b9eb14d703065a758062f9c76e4e70f8ed - arm-trusted-firmware/plat/amlogic/axg/axg_def.h d3c822e681ab6d5016ae06adb88ca9aeb6073aba - arm-trusted-firmware/plat/amlogic/axg/axg_common.c faf31bdcea206b83c40fbe2d878c14fa8327a37a - arm-trusted-firmware/plat/amlogic/axg/include/platform_def.h 28726387d3750ce4724f9147e5e173131ee7164f - arm-trusted-firmware/plat/amlogic/g12a/g12a_common.c 03a70925292deabd473bf5ffcd0d0d95dd70456e - arm-trusted-firmware/plat/amlogic/g12a/g12a_pm.c fe8712d8d4a3787c6c2456ffcc2cc468b12bfd7e - arm-trusted-firmware/plat/amlogic/g12a/g12a_bl31_setup.c 495f096204283e82b03abed56414e3d1a29f9b6f - arm-trusted-firmware/plat/amlogic/g12a/g12a_def.h 8e1154709ae343cd8d783739b29005ea2b9a7c7f - arm-trusted-firmware/plat/amlogic/g12a/include/platform_def.h 25d4db1b1e385a2e45f4ffea43edbfc8bf4fef89 - arm-trusted-firmware/plat/amlogic/gxbb/gxbb_common.c 704885551348b4b44d9b7b092aafc3c54533b7e0 - arm-trusted-firmware/plat/amlogic/gxbb/gxbb_bl31_setup.c 80fbc4757d8f389dc885b90a5eef8c0c4f6e23c2 - arm-trusted-firmware/plat/amlogic/gxbb/gxbb_pm.c 3389361e87f5cd5e4f7e606599032c3aa3a41b72 - arm-trusted-firmware/plat/amlogic/gxbb/gxbb_def.h d558f98c64955249d21b9227149b68808cb3e358 - arm-trusted-firmware/plat/amlogic/gxbb/include/platform_def.h 550ec6753c2e8a5f41a920ea9bfffec47ae78dc8 - arm-trusted-firmware/plat/amlogic/gxl/gxl_bl31_setup.c 68a18488494ea52a108462ec30b6833447e75e62 - arm-trusted-firmware/plat/amlogic/gxl/gxl_def.h 5ce07f2865d514a3a8979c638337a338fa110f74 - arm-trusted-firmware/plat/amlogic/gxl/gxl_pm.c 8b93edbe34b51b737299797607de4e6ff0003917 - arm-trusted-firmware/plat/amlogic/gxl/gxl_common.c 22603b51918b7c1f721eee33d26629b16cff6683 - arm-trusted-firmware/plat/amlogic/gxl/include/platform_def.h f2d39611e277f7dd7865f658ae5966d635ed6ede - arm-trusted-firmware/plat/mediatek/drivers/iommu/mtk_iommu_priv.h 7760486a7b1b2262c2648d0acce4cac108084e85 - arm-trusted-firmware/plat/mediatek/drivers/iommu/mtk_iommu_smc.c 3ac3ac8822c26d2a036acd7be2c989f1962eedfc - arm-trusted-firmware/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c 48679afeaf5a52a3c862c57d1684d07ed5e2b502 - arm-trusted-firmware/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h bb9905d3ca82a3d6dfa57699b19611f4867577ac - arm-trusted-firmware/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v2.c 2a10904482493ddeae18582fba23ff8f9181bf75 - arm-trusted-firmware/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h eb7915fed5f701e9926022ff49c0a65788171ee7 - arm-trusted-firmware/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init.c c7f5e857fc70c5ce4f9dcaa96f337af61105ace8 - arm-trusted-firmware/plat/mediatek/drivers/pmic_wrap/mt8188/pmic_wrap_init.h 1f18015e4a91fbc2f6f458600c406f2460034d01 - arm-trusted-firmware/plat/mediatek/drivers/timer/mt_timer.c 1dd137b3f01e2411cbb14572a975e1b3f4105830 - arm-trusted-firmware/plat/mediatek/drivers/timer/mt_timer.h 69f1fae59df7524be33d4147b2a092c6e51ef8e9 - arm-trusted-firmware/plat/mediatek/drivers/dcm/mtk_dcm.c 95dafe420ae67f2efd1510f1092a4779616c29f5 - arm-trusted-firmware/plat/mediatek/drivers/dcm/mtk_dcm.h 89c6cdceb30d5175973c272aa2357dc7aa1a3543 - arm-trusted-firmware/plat/mediatek/drivers/dcm/mt8188/mtk_dcm_utils.c df145329af783d50890626c102e62382f51887ce - arm-trusted-firmware/plat/mediatek/drivers/dcm/mt8188/mtk_dcm_utils.h d9bded336f634453e481841c74413768ad395834 - arm-trusted-firmware/plat/mediatek/drivers/dfd/dfd.h a0b0b3baf65bc8806a395dc788a2b106c02f3949 - arm-trusted-firmware/plat/mediatek/drivers/dfd/dfd.c 6abded7e1568631f71e2d6557c3332d3847ea188 - arm-trusted-firmware/plat/mediatek/drivers/dfd/mt8188/plat_dfd.c 261cf35d5384041d1dbb855b554e68ea39a1664c - arm-trusted-firmware/plat/mediatek/drivers/dfd/mt8188/plat_dfd.h ee1c1bf9c78b5c46f7772dc45f77f687953b93fe - arm-trusted-firmware/plat/mediatek/drivers/msdc/mt_msdc.c 156cac9afbdde89449a6d21df46d0c5a1bf37071 - arm-trusted-firmware/plat/mediatek/drivers/msdc/mt_msdc.h 8f1cfa9df72c598247cff91a97b5a830e3569cc9 - arm-trusted-firmware/plat/mediatek/drivers/msdc/mt8186/mt_msdc_priv.h 7f192da248ec23c019cb333f4caafc278271f676 - arm-trusted-firmware/plat/mediatek/drivers/mcusys/mcusys.c aee672e423696b65c1630801b16273e8e495a149 - arm-trusted-firmware/plat/mediatek/drivers/mcusys/v1/mcucfg.h 134fbe21ac0f2c1854b10e7eef89ee12b020fe20 - arm-trusted-firmware/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_mbox.c 9b4ecc667dc11af294dbd507e43cab0314e2dd11 - arm-trusted-firmware/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_mbox.h 0b7f2e5711c02061341a8dad767bd48e81ed38d7 - arm-trusted-firmware/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.h e3cec46ff910a44ee5ea099c67fcd1a9118aadd8 - arm-trusted-firmware/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h 1684070d09d29ebffbd8554091fc33e886e3e2ee - arm-trusted-firmware/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_cpc.h 0711d9c3c743a3380f9dede1b38165296fce1778 - arm-trusted-firmware/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_cpc.c c898216aa5b8f9fe89997d856427e3778ef12d5d - arm-trusted-firmware/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.c 3e492f0e007c2b3f2bb272091ab2a691ae0ca23f - arm-trusted-firmware/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c 99f0022ad9e87c24e1887747d2c9884d00178733 - arm-trusted-firmware/plat/mediatek/drivers/cirq/mt_cirq.h 0285366adb4935f641e32567eb7f77904837f281 - arm-trusted-firmware/plat/mediatek/drivers/cirq/mt_cirq.c 930f766565bf0d229b59529e45f88732759a7231 - arm-trusted-firmware/plat/mediatek/drivers/uart/8250_console.S bdb3af368e931968e90077cf992a6651daac9391 - arm-trusted-firmware/plat/mediatek/drivers/uart/uart.c 98496e45e45833386917e41a5a20706c54c620e0 - arm-trusted-firmware/plat/mediatek/drivers/uart/uart.h ec8068037d563767633d21d9e3b1f5baea14858e - arm-trusted-firmware/plat/mediatek/drivers/uart/uart8250.h 77e9f93ff781a1987a0a63caa4c149bdaa1252a0 - arm-trusted-firmware/plat/mediatek/drivers/audio/audio.c 7a6ca16f381f362b101117ec84ac8c0911cf8861 - arm-trusted-firmware/plat/mediatek/drivers/audio/audio.h da5af19c7dc77d5deda15f6e2a5b62f584a72556 - arm-trusted-firmware/plat/mediatek/drivers/audio/mt8188/mt_audio_private.h 24c24026f60ea4f0f096ff1c721dd6b8916c733f - arm-trusted-firmware/plat/mediatek/drivers/audio/mt8188/audio_domain.c 57196037d33fe489f4e50ea7bfb8648048ad869a - arm-trusted-firmware/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c 78fd2deca88fa22b733b9155ca6148caa6108f40 - arm-trusted-firmware/plat/mediatek/drivers/emi_mpu/emi_mpu.h b63c6b7304e5a2a7c914fdce47dc0d3c1a50bd4d - arm-trusted-firmware/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c 937baf1160c2bc760a12977fa3f2735f77fb5ea3 - arm-trusted-firmware/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h b6c9e8ee30ac8f5f0ac0b9bb03694eeb4a7f155a - arm-trusted-firmware/plat/mediatek/drivers/rtc/rtc_mt6359p.h f0c7283e2441d12480c08faab3da2308d913f99b - arm-trusted-firmware/plat/mediatek/drivers/rtc/rtc_mt6359p.c 03e4798e0ab038392164d015a29e788781517dce - arm-trusted-firmware/plat/mediatek/drivers/rtc/rtc_common.c c2355cf6efda6f81bd7a9c35e7752d27980b28a9 - arm-trusted-firmware/plat/mediatek/drivers/rtc/mt8188/rtc.h 16462f5d17a1157411af721102b9276f82abeaeb - arm-trusted-firmware/plat/mediatek/drivers/gic600/mt_gic_v3.h 2244e999237d16423c20b9bfe3d7669970012fdf - arm-trusted-firmware/plat/mediatek/drivers/gic600/mt_gic_v3.c 6e8328bde0c302e5e4a920571add2cb941bd94bd - arm-trusted-firmware/plat/mediatek/drivers/ptp3/ptp3_common.h 04c6c2bf26c5aebf15755019eb1ecb9e65ce69b6 - arm-trusted-firmware/plat/mediatek/drivers/ptp3/ptp3_common.c 8496c537b7b48853a0cb2708741487f8a36ffe6a - arm-trusted-firmware/plat/mediatek/drivers/ptp3/mt8188/ptp3_plat.h 126809c50663fcf6c39cfc9d13e7e92ca3c5fb6f - arm-trusted-firmware/plat/mediatek/drivers/dp/mt_dp.h 532fa3e763874411f39bbd85ad681e402e90f231 - arm-trusted-firmware/plat/mediatek/drivers/dp/mt_dp.c ad4b615259a210c00456d992b513086733bcb9c7 - arm-trusted-firmware/plat/mediatek/drivers/gpio/mtgpio_common.h 490fcf180d98bb8cb8e2efc29f9d5501848afd7d - arm-trusted-firmware/plat/mediatek/drivers/gpio/mtgpio_common.c a84237a9b3216421db5d1231f196ac9c22aa66d0 - arm-trusted-firmware/plat/mediatek/drivers/gpio/mt8188/mtgpio.h 1d48befec54e9fa19cfb6946d74529810512043c - arm-trusted-firmware/plat/mediatek/drivers/gpio/mt8188/mtgpio.c 522b63231b909ee04c701b3cfc83f0e36837b43c - arm-trusted-firmware/plat/mediatek/helpers/armv8_2/arch_helpers.S f080b060c3a7a6d1c5f4ffa322865258db95bd1f - arm-trusted-firmware/plat/mediatek/topology/armv8_2/topology.c 2036b11036478a7316c8fd022436bf0c5c86fcb1 - arm-trusted-firmware/plat/mediatek/mt8188/plat_mmap.c b575c7b1b11043054b52711aa20bc1563b674ba3 - arm-trusted-firmware/plat/mediatek/mt8188/include/plat_helpers.h edf168931ae63b6f50119f11a6c30332f17b221b - arm-trusted-firmware/plat/mediatek/mt8188/include/plat_private.h f1b2ba201219ae790d2471a44d438295c54cd208 - arm-trusted-firmware/plat/mediatek/mt8188/include/platform_def.h 6c02313dd3c36357c07071c1b1e8c6541d7fac3d - arm-trusted-firmware/plat/mediatek/mt8188/include/plat_macros.S fe92777b57e50f9794d099db02b51f77dc6ba550 - arm-trusted-firmware/plat/mediatek/mt8188/include/spm_reg.h e90649554240f75d20e82bcaf1d5fc7f72308d84 - arm-trusted-firmware/plat/mediatek/mt8173/plat_pm.c 6a2d3a421c077dcc608a94317ecf55a80c640d76 - arm-trusted-firmware/plat/mediatek/mt8173/plat_mt_gic.c 9b148285683f9f62babcdd92b4cbb3edf8d47275 - arm-trusted-firmware/plat/mediatek/mt8173/scu.c 322049a08a3981e4c34fb6991314537e02662946 - arm-trusted-firmware/plat/mediatek/mt8173/plat_topology.c 5b0d461df0d4936d87d5a3b87846da17b5bffdcd - arm-trusted-firmware/plat/mediatek/mt8173/power_tracer.c abe0c66165b32a2f3dee830062f153c3c29738ce - arm-trusted-firmware/plat/mediatek/mt8173/plat_sip_calls.c b49fda8c23d477e92d842bb950e93962c77a82cd - arm-trusted-firmware/plat/mediatek/mt8173/bl31_plat_setup.c bb6c45f6edb308171b205123bd682e3db84ec58f - arm-trusted-firmware/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.h d86950fce5e4e2f48f1efc48472289033367e47e - arm-trusted-firmware/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.c 0f38df7cc1b225ffb568e7df5c4981b0d29ee7ae - arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm.h 9623b67d4f2dfac8dcc78ed711172fcb5f85511d - arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.h d73f4f2080ec7098103c5209a4c302f80535dc77 - arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c 4398c8e27acb0bc2b28771ed5c1a0689971fac4f - arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c b18c4af2e0471a0d5de267ac5c1e4a52b1c94ea6 - arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c 8ffb063b98ca22c66f9f96260216a31b1de20519 - arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.h f3ba2dabf2cabb2644ae09476c62fee2023d6abc - arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm.c f6fe2ef42009b0fa69b3957d63488b6192072275 - arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.h 9e687cd54be9aa08265355e1079ba5f6cd2a93cc - arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.h 4af6a675f41b6d5566fcc13863c1507f5fe28f7f - arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c 3160163c493937b3bb0298d50d918627d0d0e4e4 - arm-trusted-firmware/plat/mediatek/mt8173/drivers/wdt/wdt.h 27287e7e69b6a6be66a87cf9e294f25a682e92fe - arm-trusted-firmware/plat/mediatek/mt8173/drivers/wdt/wdt.c 27cbf1f064da3e18b5cd7c0e83fb1c9da349e00e - arm-trusted-firmware/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h 42adaa32fd22643561c090086db64c635fd6d686 - arm-trusted-firmware/plat/mediatek/mt8173/drivers/rtc/rtc.h b7e2ebfeb39fa655c846358a6439c708fba4b6d5 - arm-trusted-firmware/plat/mediatek/mt8173/drivers/rtc/rtc.c 4535129d635202f3bf1b447e411bd1c7eda5f7db - arm-trusted-firmware/plat/mediatek/mt8173/drivers/crypt/crypt.h 0f16bd582feb0391ddd3b4685fab51a7e11667ca - arm-trusted-firmware/plat/mediatek/mt8173/drivers/crypt/crypt.c 12c0bb5878f5671aeb4bc9ea733ddd80cdb960da - arm-trusted-firmware/plat/mediatek/mt8173/include/plat_sip_calls.h 755906af584459bc7964059a3022e624d4743b62 - arm-trusted-firmware/plat/mediatek/mt8173/include/mt8173_def.h 3d43facf8bc958241dcaddfa4cd6f9e61362c87e - arm-trusted-firmware/plat/mediatek/mt8173/include/plat_private.h fb0128ee719cdbc40fa546319e2635e3e19f1e11 - arm-trusted-firmware/plat/mediatek/mt8173/include/power_tracer.h 2bd6a37616bcda8ee48aa9917c65801ceeea804e - arm-trusted-firmware/plat/mediatek/mt8173/include/platform_def.h 95875d234df9d7f7a86bfda389367f298611eb38 - arm-trusted-firmware/plat/mediatek/mt8173/include/plat_macros.S 89bb4015a4309bd60ed5dc2f32033dd0a4f603cc - arm-trusted-firmware/plat/mediatek/mt8173/include/scu.h 7848197b715dc7fd355b6bc2d2232123facb9994 - arm-trusted-firmware/plat/mediatek/mt8173/include/mcucfg.h 314689d0bbe7b2567ccd667c6f70815679729e1f - arm-trusted-firmware/plat/mediatek/mt8173/aarch64/platform_common.c fefea9a047dc27fa97fc660c62bc2a4b68539b35 - arm-trusted-firmware/plat/mediatek/mt8173/aarch64/plat_helpers.S 50be946eb9555627f53bac17f5e9c5f0f1d76f19 - arm-trusted-firmware/plat/mediatek/include/plat.ld.rodata.inc 224ae9c18657e9641adf9757e552301efe8f5959 - arm-trusted-firmware/plat/mediatek/include/mtk_sip_svc.h 4f5f60f494b7c5e54c5fcc61e93c22948842bd50 - arm-trusted-firmware/plat/mediatek/include/vendor_pubsub_events.h 9be29b085a8e415dd0a0755207108112b034341d - arm-trusted-firmware/plat/mediatek/include/mtk_sip_def.h 730fc794ca6543e8ce9f5fbf3106440fdd972a88 - arm-trusted-firmware/plat/mediatek/include/mtk_mmap_pool.h 2f24ac043a34f33be26778e4bcef73be1d2560de - arm-trusted-firmware/plat/mediatek/include/armv8_2/arch_def.h f430f1fc1cb4e9869f5188a8a2e41fe2388d6337 - arm-trusted-firmware/plat/mediatek/include/lib/mtk_init/mtk_init.h 1ebe4b764d469b2138366b316a32f9aa69e86930 - arm-trusted-firmware/plat/mediatek/include/lib/mtk_init/mtk_init_def.h 9b3a7047c79a6db7a90592284ff1383a9562706f - arm-trusted-firmware/plat/mediatek/common/mtk_smc_handlers.c 8b0adf6f37fac4a221d543c6307ba999c9272fe3 - arm-trusted-firmware/plat/mediatek/common/mtk_plat_common.c 078e8353bd2d5d9a24dc7b0eb02885c17df8a41b - arm-trusted-firmware/plat/mediatek/common/mtk_plat_common.h ffdbbcc522937a13b7f658754005673d0257f6dc - arm-trusted-firmware/plat/mediatek/common/mtk_sip_svc.c 4f1e69980b6fa0691ac24f320f777fa5f690c987 - arm-trusted-firmware/plat/mediatek/common/params_setup.c 7858c40d5378047a8869189376fb70d934ed6f9b - arm-trusted-firmware/plat/mediatek/common/plat_params.h 0e20220bdc9fa89c61ef332d8150d693e92a43d6 - arm-trusted-firmware/plat/mediatek/common/mtk_bl31_setup.c b824bad57c9119d6dbc7dd2998f333efbfcc9f53 - arm-trusted-firmware/plat/mediatek/common/lpm/mt_lp_rm.c 6ce70a527ab5b3fffd16f7aaf8af5b2a7a94aba9 - arm-trusted-firmware/plat/mediatek/common/lpm/mt_lp_rm.h 8274c219bcba2090fe7e6e628abe65c7c3780d33 - arm-trusted-firmware/plat/mediatek/mt8183/plat_pm.c e9bb8f5dfe42b8cfdd770db2301155ad00d93617 - arm-trusted-firmware/plat/mediatek/mt8183/plat_mt_gic.c 7a7fbf6ac91e6e9ff86ac7350e8de64f834b5997 - arm-trusted-firmware/plat/mediatek/mt8183/plat_dcm.c 2f1976dda894f28a35f0cc50623e070a354d044c - arm-trusted-firmware/plat/mediatek/mt8183/scu.c 03b9e95dd87fe5cdd436743fb8f5f59d4b2f2de3 - arm-trusted-firmware/plat/mediatek/mt8183/plat_topology.c 3cb5ee19a3d0915879c602a240e4affb4a0d7c94 - arm-trusted-firmware/plat/mediatek/mt8183/plat_debug.c 9065f62c97422538ddfd15c89806f2869ffb98c5 - arm-trusted-firmware/plat/mediatek/mt8183/bl31_plat_setup.c 51b89484342a85c2ee1e944fbbfc08a8bc663f63 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/mcsi/mcsi.h 4ab8cc9c4d3ff197639f9b78f7b860ebb8879967 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/mcsi/mcsi.c 23040542c3bf819fe42a45ea51427b1a39edfab5 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/timer/mt_timer.c 1f21078b5dce77d5939c39ae046fcf15cf1bcc4d - arm-trusted-firmware/plat/mediatek/mt8183/drivers/timer/mt_timer.h 96ac9c853839aff7b9c19b8ce2bdd09ffee2c87d - arm-trusted-firmware/plat/mediatek/mt8183/drivers/spmc/mtspmc_private.h 2e1849b9de23cbd064f9e90e4c83cd761e284e18 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/spmc/mtspmc.c 316277d91acd7098ec6ac153e95c932aca46d3c5 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/spmc/mtspmc.h b26d910796c32c24b2519666922a9991a16d3562 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.c e92a0c648e09b96cd906a5e008c418d7d61fd577 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/spm.h f1a812bc872a1ac1c695c5485fba1a135307986c - arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/spm_suspend.h fe16bd5deb42a8c0e902c3a7547e11d7d5afa0bd - arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/spm_suspend.c fdbc0bcded1a96ceeb994c74a3a48eec3af06df3 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/spm.c 8156e8c4b7f219c9590cfcb2338d845c2b0c71b6 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/spm_pmic_wrap.h 264db153102d726c6a9455244b40d552d0960af2 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/devapc/devapc.h ed39e8ba2090c26070e12def3287c0ff46721987 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/devapc/devapc.c 62325eff3c956aa9ca90b298e958e8ed5941a8a4 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c 88c148094b3fac4149258b8fe4786fe4ac3f8f3a - arm-trusted-firmware/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h 214f922545d6899c3e5621df156f1712ebb3c009 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h 1d535ab7f8d2fb5131a0ce0e6a7b11c4a188a009 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/pmic/pmic.c ddd6d454dc5e0a1dead801b5cb856c7f27a8065e - arm-trusted-firmware/plat/mediatek/mt8183/drivers/pmic/pmic.h fb3c91bb75b7fe6fff5323ead8dc73efc07f1289 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/sspm/sspm.c 645f76b92e2714b452ae24edcd6a40cfa879ea61 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/sspm/sspm.h edd71b3e0aaea146cfadebca131cd7e6ee13d303 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/rtc/rtc.h 888e5c6480da8cc9f0dd6d5febc12f7d0a8a16fd - arm-trusted-firmware/plat/mediatek/mt8183/drivers/rtc/rtc.c 3a86fc89605145b3faa5aa385e8f7a11851b424a - arm-trusted-firmware/plat/mediatek/mt8183/drivers/gpio/mtgpio.h 346960934a0779649e0412ae87abde963086ff8a - arm-trusted-firmware/plat/mediatek/mt8183/drivers/gpio/mtgpio.c 94b038f0c7b76069f4f85185a375d4d2aa61a74f - arm-trusted-firmware/plat/mediatek/mt8183/drivers/gpio/mtgpio_cfg.h 7ac4fd4d1072962002d4b4a7439a7fc6fea85b48 - arm-trusted-firmware/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.c 0bae9ef296eeb3bf9ed2342aa58b2d505dc8f04f - arm-trusted-firmware/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h a4d241e1fe6a38acfd38a895dc29d0d3762c185f - arm-trusted-firmware/plat/mediatek/mt8183/include/plat_private.h 447f690a22efc00539cd931fc1d9aba592997a19 - arm-trusted-firmware/plat/mediatek/mt8183/include/plat_dcm.h 01e8de6953d79923463ea639e7d8e218ecdbc8e6 - arm-trusted-firmware/plat/mediatek/mt8183/include/power_tracer.h 387e06d0f2e4f36818ebd660cd1c4d429222a6fa - arm-trusted-firmware/plat/mediatek/mt8183/include/platform_def.h 97a99a4b4542d549efbe9122362e0ee8fcac89fa - arm-trusted-firmware/plat/mediatek/mt8183/include/mt_gic_v3.h 58b0e33d4a7460c72049a50f5cb8e8af5a5260d9 - arm-trusted-firmware/plat/mediatek/mt8183/include/plat_debug.h f7b9354cce893182c4203079dc774a9b048d05d7 - arm-trusted-firmware/plat/mediatek/mt8183/include/plat_macros.S 9ff5bdd1f6610dc5e442304399c97ab95361e3a3 - arm-trusted-firmware/plat/mediatek/mt8183/include/scu.h 16b7a7f8d62f9bc9d06c01d5e72b2ef5653e7455 - arm-trusted-firmware/plat/mediatek/mt8183/include/mcucfg.h a52a6337e1e29bc64b0d301f31d88c42981a1105 - arm-trusted-firmware/plat/mediatek/mt8183/include/sspm_reg.h c7ae3ce6e37f4d27b8733d9c3b1bafa8add40a8b - arm-trusted-firmware/plat/mediatek/mt8183/aarch64/platform_common.c c5295d987eeadbc7fa82ddedb5266f20e7dd3cec - arm-trusted-firmware/plat/mediatek/mt8183/aarch64/plat_helpers.S 6311b185f7f7c8af501aa62696276641763e1810 - arm-trusted-firmware/plat/mediatek/lib/system_reset/reset_cros.c d9cf3a5339c9b4f70641e25b6acbf16e49cf61dc - arm-trusted-firmware/plat/mediatek/lib/mtk_init/mtk_init.c 0836a904278842a9ddbdfe4c73ff81b9c1d56d85 - arm-trusted-firmware/plat/mediatek/lib/mtk_init/mtk_mmap_init.c 813385e82fabd06d5d9692ffd200a4f727c11fad - arm-trusted-firmware/plat/mediatek/lib/pm/mtk_pm.h 4ba889b4d34e8b0d77d2e96be7443670fc8c51b4 - arm-trusted-firmware/plat/mediatek/lib/pm/mtk_pm.c 6c7a6b0f1a8f8bb9669f4da479574579c42cc692 - arm-trusted-firmware/plat/mediatek/lib/pm/armv8_2/pwr_ctrl.c 3d4c7bca1a506e4803a73126897ce1d6a95d97a8 - arm-trusted-firmware/plat/mediatek/mt8195/plat_pm.c 02f0daaeeb8c59d391a631dd2f7624e598748e99 - arm-trusted-firmware/plat/mediatek/mt8195/plat_topology.c e38d78c0178f1220a1c667dad257e8efbc88de4e - arm-trusted-firmware/plat/mediatek/mt8195/plat_sip_calls.c f6cbc785839b2fde5bb8c3d87190641b45997d2b - arm-trusted-firmware/plat/mediatek/mt8195/bl31_plat_setup.c 79890abe09ae9210d94ce3c0f27c8e1d61ed6fae - arm-trusted-firmware/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.c b6ba63645f7269f8d27b087a36b742340630864b - arm-trusted-firmware/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.c d83f926ab5ef0f16323281a34f12b358f3af50be - arm-trusted-firmware/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.h b1174b8477d0e126d9a35147161079391bf09ab0 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.h 17199f9bb411ca8735cf2bc4b22e8baa7bc2d152 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/dfd/plat_dfd.c 4168e0d14bbe98c0b575d2e572fdb4b73586f8c7 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/dfd/plat_dfd.h 5785dfb24000631b8d3ec2c8363f0de46908d763 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/apusys/apupll.c dace58b25824fbc880b58670389d47358981547f - arm-trusted-firmware/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.h 98090ad034ce904969ba1583467f8e5ef565d2d8 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/apusys/apupwr_clkctl.c e37292ff38e07fc925308e8d725c49e48fa0a085 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/apusys/apupwr_clkctl_def.h fb86370251784e4a48a2bfe74baf2d7c56f3701b - arm-trusted-firmware/plat/mediatek/mt8195/drivers/apusys/apupwr_clkctl.h c925ae2549008a58fda62b34de221dd620c70d96 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/apusys/mtk_apusys.c f70563982bec81cd15b17e693da41e7d1f469c6d - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h cb6cde28e9dcb269b456216c0e1b8d55c8ea996f - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spmc/mtspmc.c e1b4cce4c465228019f6128073e4634dce0d2986 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spmc/mtspmc.h d21496a22308580c07df11ebe7adf41f274bfd59 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.h d655b93e0b18efc8d5ac80ceae4a282c70d79c8a - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h 1c5969bf63da110696877497bf7bb035238af2c3 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_resource_req.h a2ab35d6915d2ac73d85c1068d973a0d3514da41 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.h 6ef0f4493d19b357c77df1b5cd49696a5263d102 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.c 2516c5016c27a7706bfb86cea698a6741d845eef - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.c 618680bf1155ee1bdf7f67df15cfeefeded70e66 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.h 0a4ed6a9c901c1bc5b75371aa26917fe6d9b243e - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_vcorefs.h 709be723f3bb2b8be34dabc19ffec007a928b060 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/sleep_def.h 1e9fb5aa9c1bd6bfedf0be53b9f529290a141a9e - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.h c5542e49f5d3326418606d161d9490c9dc3c7bcf - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_reg.h 33b92edafecacba8aed5f6b12c0b051740d4aa8e - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.c f438fe8befd240fc23c7cc48c7e77e1e1a3cc0c8 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm.c 416b58dbb44fb50ec9cbdda2b4af6cc04bd48d20 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm.h c13822b4c2268325ef4398fbd0d28eacdfb59602 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.c 1209a457ffc9d4ceeebf3f3e24300146fecbd276 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_constraint.h 3e3b62df98d3d83eb2016c9d8dd1f67a641e95e4 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.h 28a7ecc5d35653b1b3e42ad19c1d1526f8b4ba13 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c 445db7752ab6359cd4ddfebded67f1dc59603220 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/pcm_def.h c997c26d9a441b3b550fa191f122a33d669d38b4 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.c b24e7e4ca2cd9b25fdbad93fed94631f347b78f8 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.c 85497a05edddd868fbe7322a3621d2b7c88c9814 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_notifier.c 73de5db2e94313670371f83a648fe95de097e7f7 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_intc.h e3e6596065738a8b19bfde088f92c7a4bf51b851 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_notifier.h a3456911635f8af4f989688a8a1ae80de5256fb3 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_syspll.c 9cad31dffedae7113515acf396b47ad67db95e65 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c c24f82eb4ee80d7945922eac27dac514db2a49ac - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_dram.c 98f55522313c18575ac3b999f71ef98dd128d004 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_internal.h 872b3910dfca5bff8749f70e72fba760cf6289c7 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c 1a8e74d1db7ceb847a8217c94620d6a73c28e8ba - arm-trusted-firmware/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c 35dc8ecb34f8b16c7fc40797709568394bfa2700 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.h 9b146c3beb02a68ede21f883f70b46fd4239d784 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h 0bcb38d8c8e61fff34a01235e370ae936b49f149 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/ptp3/ptp3_plat.h cd5607156fa9256dbf860561db48d3e74c800295 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/gpio/mtgpio.h 49758ae69918fd8c1b52c54bc298f1f3e80fe1b9 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/gpio/mtgpio.c 670e89ed3e54a8fcab5f9bdc69b0710229d556a7 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.h 73a75da66496e41636460ff121095c03a41ba9a7 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h 77b795f3ba595013340ed1473935df13b18992f0 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c 45cc9c21a8808b71ae0f1ed548228c543b03809a - arm-trusted-firmware/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c f8540b0d0f9d75dd733f6683d68945b2408cb0be - arm-trusted-firmware/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h 368d6d264c555843d3708e20700f8851e215df63 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c c4e2a5509c4bbef64807d58ddfea984f66031f26 - arm-trusted-firmware/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c 89839e3156f8231e002ce636b3025d34e9f4e407 - arm-trusted-firmware/plat/mediatek/mt8195/include/plat_sip_calls.h 5fdb5614708d12a66d8b58741f2e38c49b7690aa - arm-trusted-firmware/plat/mediatek/mt8195/include/rtc.h cfc60d518acd24b2043bf29a48105110ad3068aa - arm-trusted-firmware/plat/mediatek/mt8195/include/plat_pm.h 9ba9b4651c7e04ead5846597f6564fab10d8de4a - arm-trusted-firmware/plat/mediatek/mt8195/include/plat_helpers.h d923270912bbaad8959a73f39f933db6c98a49ce - arm-trusted-firmware/plat/mediatek/mt8195/include/plat_private.h aac0409410547bbc2e6658bbb739314494aa28ed - arm-trusted-firmware/plat/mediatek/mt8195/include/platform_def.h 4b7558ac17d450a33285d28478f8d8596edbb1b5 - arm-trusted-firmware/plat/mediatek/mt8195/include/plat_macros.S af49cf4a43c7cf77fcfa20fe09d7197390bf3969 - arm-trusted-firmware/plat/mediatek/mt8195/include/mcucfg.h 1244ea062e485744ad8d59bf66ba3a455bec7f13 - arm-trusted-firmware/plat/mediatek/mt8195/include/plat_mtk_lpm.h cf12b1cf99214c2d6e1e4c31e66bc9aa981037b2 - arm-trusted-firmware/plat/mediatek/mt8195/aarch64/platform_common.c 1e5bead24560b23256aa9e306e5a4ece724bd6af - arm-trusted-firmware/plat/mediatek/mt8195/aarch64/plat_helpers.S 98b250fb48fc293e489948124f342093ba6dd423 - arm-trusted-firmware/plat/mediatek/mt8186/plat_pm.c 02f0daaeeb8c59d391a631dd2f7624e598748e99 - arm-trusted-firmware/plat/mediatek/mt8186/plat_topology.c 8fcd8c6da6a5b779050aba77c3a1d180e1fcf42b - arm-trusted-firmware/plat/mediatek/mt8186/plat_sip_calls.c e30b233c6a0d10cb0d058f63a7d68bced2033d08 - arm-trusted-firmware/plat/mediatek/mt8186/bl31_plat_setup.c 26687de903046dca0b5e9750e8a59b9355a29ec0 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/dcm/mtk_dcm_utils.c 3880fbedb01ad739666ead858ff32c11692d7ab0 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/dcm/mtk_dcm.c 982ba0c3e5b8772dbcb65fe9ec04f07cd66c03e3 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/dcm/mtk_dcm_utils.h 8836e6535eaf80d79c28bc7e61f796c61f019c9a - arm-trusted-firmware/plat/mediatek/mt8186/drivers/dcm/mtk_dcm.h d2b7ae5854f6cb1abfe5c55f52385c86fe6752f0 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/dfd/plat_dfd.c f0e1185e7fac539c5d2edbf5893678d2ca131f70 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/dfd/plat_dfd.h acd408521525ea61a78ab71ab790b33f6c8835a5 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spmc/mtspmc_private.h 97a67051462aa2dc020abb4c615ec1b8d55798dc - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spmc/mtspmc.c 514a984bcec8f805fbc3fc8b0213b8603009b717 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spmc/mtspmc.h 0c0e64bb4e502f8b06cddf4f5701a2004dae88bb - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.h 23822f16c7741b8a82e6c1b2bf37723c9b661d23 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h c493de6825dedbe205476271578675f186aad0a2 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_resource_req.h 714e06306174609b86f6dfecb362e5d307815984 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.h 8e4cded7b48b70c4d63171d01619ea77582a15d8 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.c b196a520bf04181913710fa0ad6c7e98df814be6 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.c c3913ece4d63b48d8aaa43aaaa4f7c5927073b30 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.h 6fad70943b4e7bc9042ec608eca4905531b622d8 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.h 302fea6e0fc2351dbc6ccda1ed9190941f2c0250 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/sleep_def.h 2915d56fef4019217f23aeab0ebcf0ff98b2818d - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h 85a883d9102bcbda2f8b172b3428fa270a259858 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_reg.h 14bc032be258ef049809f2d64758d7861d5e5ac2 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c c6cd4eccdc73fc94fe1d36f9c0d24adf82f6b762 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm.c 9842a9ba9c2a948191518a1dcac7efa316141dd3 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm.h ed2f1e43ce8ff9065b95a274256a78d34d08b184 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.c d252e68c77c34429d934422da1ce46e64553c23d - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_constraint.h ff8ca308a59e802f869d16233f792ae0e6d19a52 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.h 2f14e2189e22b58a7f814523923a82b761565793 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.c 6afbc58701e19d1e4b949615eca0a6fee5c0eec7 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c 8d4291524d054f1b355580fb4254843ee94015f3 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.h 1b4a0d65fcaaccb28afc897aef9a76972b99b9f2 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/pcm_def.h be59b0efd4cc9ca4eb6570a3a2fe1d3f0f812fc6 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.c a6cfe8969863b9001520ec912315467a2b1213e8 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c b0f17b327e8e440edfd9723c0c1af4418672b99d - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c ec1e10ba1585046d426fcca0c8d6a0452015786a - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_intc.h 3b25bdf185a1377c793c31e212d50a0027fda91d - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_notifier.h 6dd95a8f29a4eb734a92736d768d92a35ce910f8 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_syspll.c b0b7d71eae5d9658f4318b8d609630ce8baa600f - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c d7be908565309c39ef0e37d464011c7340c16d6d - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_dram.c 6dea64a1dcb62407a4021b892e2da1cdc50af221 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_internal.h 97b36bd56cf9603b43fd2acace9ae94457d14776 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c df5d6cd84cc2ebf2e1a29b946cfbfe1742c01b79 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/emi_mpu/emi_mpu.c 35dc8ecb34f8b16c7fc40797709568394bfa2700 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/emi_mpu/emi_mpu.h fae5279d3f23c61cc28aef0666b48296099ed71c - arm-trusted-firmware/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h 8fdeee52467e248a082f45d92512e951f2611360 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/pmic/pmic.c 60b16e786121e9076be12c5a78ec91c7e33801be - arm-trusted-firmware/plat/mediatek/mt8186/drivers/pmic/pmic.h 9114133093483da052525a109b5ca5242a14cdc7 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/rtc/rtc.h 0bf3be2cc82c84d28437a838ec18ee32b52448a2 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/rtc/rtc.c 175403c002e2bae8b4b5f15356300cbbf3a37aac - arm-trusted-firmware/plat/mediatek/mt8186/drivers/gpio/mtgpio.h 1cd2b844b96d5646b2f021f2b7a50358af7908a1 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/gpio/mtgpio.c 680305a5142d3cda1b9ccc1bba0d1ca8dbf42b0e - arm-trusted-firmware/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.h 391c8bd0413603fab7961273368ae142ef2e605d - arm-trusted-firmware/plat/mediatek/mt8186/drivers/mcdi/mt_mcdi.h 0950b022f226cf400c633b938956424ef62156a9 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/mcdi/mt_mcdi.c 63d1221a97ab18b30010ef6dd666592c84488052 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.h b25eb762ade9feade7265b6836091ffda16eb118 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c 68d0d1df925010bde7b53a36dd82ab05a0cc23dc - arm-trusted-firmware/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm_cpc.h 3de0a5c82b6c6679381b6c8887a23b11e1ee49e5 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm_cpc.c 63bd27946e361d2e05b681e47abfc894e0b23e88 - arm-trusted-firmware/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.c 80f29d1cc6d6673486836b7eb69a41f7a95ba4a7 - arm-trusted-firmware/plat/mediatek/mt8186/include/plat_sip_calls.h 85515b62d8aa7cf44ac7f0b5a705f9507bc7da21 - arm-trusted-firmware/plat/mediatek/mt8186/include/mt_spm_resource_req.h c02f1fbfaf33a5bbf3351dff53710e6e70a59e74 - arm-trusted-firmware/plat/mediatek/mt8186/include/plat_pm.h 9ba9b4651c7e04ead5846597f6564fab10d8de4a - arm-trusted-firmware/plat/mediatek/mt8186/include/plat_helpers.h d923270912bbaad8959a73f39f933db6c98a49ce - arm-trusted-firmware/plat/mediatek/mt8186/include/plat_private.h 9d9e1a21208cd3b5491a40bacb421776e8c1b680 - arm-trusted-firmware/plat/mediatek/mt8186/include/plat_uart.h 81581d815a00bd82cc4ed5ecd31f9cf483855e6f - arm-trusted-firmware/plat/mediatek/mt8186/include/platform_def.h 4b7558ac17d450a33285d28478f8d8596edbb1b5 - arm-trusted-firmware/plat/mediatek/mt8186/include/plat_macros.S f3091cf7bfc468b69812a8ad31b9b5d768775e88 - arm-trusted-firmware/plat/mediatek/mt8186/include/mcucfg.h 80a7b771023f421a796b8da96a4d42a7672cb817 - arm-trusted-firmware/plat/mediatek/mt8186/include/plat_mtk_lpm.h b220ab62195da381290e15b4cfd22942786b4eb1 - arm-trusted-firmware/plat/mediatek/mt8186/include/sspm_reg.h e55a87f7c47f362fafe9a61204603c0aacd71ab9 - arm-trusted-firmware/plat/mediatek/mt8186/aarch64/platform_common.c 2c9ea17eea925548d393c14f7f51d8bc2fbccdcf - arm-trusted-firmware/plat/mediatek/mt8186/aarch64/plat_helpers.S e1863524c093ea2e6d043b9f6c7dc1e219f08467 - arm-trusted-firmware/plat/mediatek/mt8192/plat_pm.c 653b82370d0b1ad6cebef8b6d7072051e934caa0 - arm-trusted-firmware/plat/mediatek/mt8192/plat_topology.c 56805f883f3c9325a69cdc97e327ca7c80bce78e - arm-trusted-firmware/plat/mediatek/mt8192/plat_sip_calls.c 5d84153e66efa37728948b5b1fe281913f5ea657 - arm-trusted-firmware/plat/mediatek/mt8192/bl31_plat_setup.c 51222b809151abb01db2556abfba262c93f7f0e1 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c 0652a5c416f4dd969f772d9774e55501993af032 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c 6710f6e1dfa15b331f9d813a5003b5198af81c04 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h a84fa1ee247e2005166d9018df2bcc75e63deaab - arm-trusted-firmware/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h 9b42c233c5ba1e6b8a384b28424da455c27a53a6 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/dfd/plat_dfd.c 89fce0253e363a84cec3e3957ac8d951a80ebe74 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/dfd/plat_dfd.h 45377afc42584fa85f873fca2cd0e157c1a16b37 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h f7c1784f7532b244fe2bbca846d710d03061bed6 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h f5cfe3883759a648f72458b1bd84bf01d3bb1657 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c cb930a7db51e4c8871ab7fcfa242466c2a8b36df - arm-trusted-firmware/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h 1b68266c3c155960dc03cba027a4d430c74473bf - arm-trusted-firmware/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c d42c9ba8c699033bed7f64376149e25aaf0ba27b - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spmc/mtspmc_private.h cc63207972ae473d6a68bc41f3aa23093730183f - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spmc/mtspmc.c b434a3c4454f2c705b0f3b7c565d85e147e7a7dc - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spmc/mtspmc.h ec2b85d104ef0ad52faf88881e864e93c37e0ffa - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.h e3a261adfa46ae2657a455b7d25b7af56bb62a37 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h 6c9c6446695fbbb9ef086f4f783aae57f24ff6af - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_resource_req.h 0f8fcf83ec923d192f61376370dd90635259a378 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.h 9858935fcdc71e5145d69b0d6b65410dfc4c6dd0 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.c ab677ba0b11817e784f6008456b3501b7438cfbf - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.c c7e5e4cde0a05fa756e3fc6cd32654be3343cecb - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.h e5e46ff7c9820b84c61e6bf2afdad854e42c6985 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.h 9479c40f7955d1b8da21fece7877b3f970886a62 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/sleep_def.h 905a72478cd919c732be2d3f3c066d27f34b489e - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.h aa2819aa55d76d63f05809805f6ebf6f84fb8f71 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_reg.h b2f984f7c8707ce9470fc25ae8af0f7a041f1602 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.c 4b3e251e2f0c0e4796105e6d25927067e14a2a6f - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm.c dd32e9eb6d0e8f5083df2bf5abfe28fcaf6f2c5c - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm.h 9bd59c04a5dabacf5a9ce010eefebd393e814115 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.c a65ccd601ba3861f13ec19d1ec6cc79d4295961d - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_constraint.h 1f598d0b85f3b211c05adb41726664e4a2bbddc5 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.h bb750dd896f8785a87ba62867b0e862dbb4199c2 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c 26edcaa081665198f705a5d6e4a606c0b4e00689 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/pcm_def.h 1637cf9d86b35aef31283240a30095022c0476cf - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.c 9fc0480b22dccdbb2dad940666ba124a785ed285 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.c ca56b6a499c7e44f09c1f020859f9e7d51b014a3 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_notifier.c d2d41012d692a8857c6f842bcf2eb065142a90c2 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_intc.h 067d8c516f8ce37edb7c8228d9d7fc4ba15ad7ed - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_notifier.h 1e038ef0b716c1ba013366f2d656026ff4bacd71 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c 92c5f85bd201557dbc4e1e49474793a5152f5bd9 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c 345b11fdc0c85e312ed8e6a8643339d691fadf6f - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c b656247e4733dfab4d7db4f7361cd1b15a0c14bf - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h eefb0e4293a309d3eae668a9f4fff6b9d45d3597 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c 31d2ee83370c6c53704ab1a6ef9b905297491333 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/devapc/devapc.h f1eb5fa4f4de22b769d0667ea9bea00613216cf9 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/devapc/devapc.c 7494ace1b19166bbf26931bbcce0c574629ee2ab - arm-trusted-firmware/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c a0c85124251b9cdae75734966ce95891397ca477 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.h ee295aa348b00745e28bd430f83fcf77824b88d4 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h 2dd99ac3ceb6063e89c9c016bf2e965abd2636c0 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_common.h 30341bebf59f92502ed0e0f772ffd6ff3f4691aa - arm-trusted-firmware/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c 319ec69ebc8189c0b9500805069cb9eab1288242 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/gpio/mtgpio.h fa7a5c1599cac3c19ca4cd64215b1938313806c5 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/gpio/mtgpio.c 6158a4631af76550355215276ddfb61772f11c91 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.h 73a75da66496e41636460ff121095c03a41ba9a7 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.h 965dec0900511bac7618f812c33f95620e3b1068 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c ba494a785110e76f1ca2c3a0f49371ab768f7d58 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c f8540b0d0f9d75dd733f6683d68945b2408cb0be - arm-trusted-firmware/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.h 368d6d264c555843d3708e20700f8851e215df63 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.c c42e69a4b160aed3d646987f867de63fd6542f09 - arm-trusted-firmware/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c 9a55085dd16d8fb1643981ea5bd79a7009ebc8e4 - arm-trusted-firmware/plat/mediatek/mt8192/include/plat_sip_calls.h 5fdb5614708d12a66d8b58741f2e38c49b7690aa - arm-trusted-firmware/plat/mediatek/mt8192/include/rtc.h cfc60d518acd24b2043bf29a48105110ad3068aa - arm-trusted-firmware/plat/mediatek/mt8192/include/plat_pm.h d3155938568a3ee3a31e1df08de79e5bf68dc877 - arm-trusted-firmware/plat/mediatek/mt8192/include/plat_helpers.h a6ce0baf4ebd3c81556e0945c2649f2efae6c879 - arm-trusted-firmware/plat/mediatek/mt8192/include/plat_private.h 555f92b188335e740adcafa8f411f751f8aa9102 - arm-trusted-firmware/plat/mediatek/mt8192/include/platform_def.h 166890efce4ba83ab0783f4b56821c8576731a31 - arm-trusted-firmware/plat/mediatek/mt8192/include/plat_macros.S af49cf4a43c7cf77fcfa20fe09d7197390bf3969 - arm-trusted-firmware/plat/mediatek/mt8192/include/mcucfg.h c080e0d9285c2d3fd252d1b5d80f857f7b5f7ca5 - arm-trusted-firmware/plat/mediatek/mt8192/include/plat_mtk_lpm.h 5c6677206ac7ea4573dbb96868e106a55445d4f9 - arm-trusted-firmware/plat/mediatek/mt8192/aarch64/platform_common.c 4a2ec93e8013a56c39ca18d0e283fc9cccb43b1c - arm-trusted-firmware/plat/mediatek/mt8192/aarch64/plat_helpers.S 8539e94b825c242859fa5c4a3c03901703c386f0 - arm-trusted-firmware/plat/nxp/soc-ls1046a/soc.c 1e814209bd02d7457755dcf4493b05a3794c811c - arm-trusted-firmware/plat/nxp/soc-ls1046a/soc.def 0f38703d163bd042c7827eaddb04ea092b30a478 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/platform_def.h 5da46b775851344c65928890c699d7ff047606b2 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/platform.c 39ce8f1f0afc76a2d1a98e86df076ef84d185da3 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/plat_def.h 0fb5432862f668e38f9bbce3af181371cdecf0cd - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/policy.h dc2f8422b34c58988a9114726e339491a2ed999a - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c 9ed3d544ff5ab2cfa0ea13d1fb3b59534eb90e14 - arm-trusted-firmware/plat/nxp/soc-ls1046a/include/soc.h bfdacfdea0aa10e1ece5ae2925625ce34328672a - arm-trusted-firmware/plat/nxp/soc-ls1046a/include/ns_access.h 0f38703d163bd042c7827eaddb04ea092b30a478 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046afrwy/platform_def.h 5da46b775851344c65928890c699d7ff047606b2 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046afrwy/platform.c dc407d2ead98e6d20e59ac0b6c5e75116a82ddd3 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046afrwy/plat_def.h 0fb5432862f668e38f9bbce3af181371cdecf0cd - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046afrwy/policy.h 945ec23ee2ba0c79a5e6140d043290e9afde9b2c - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046afrwy/ddr_init.c 0f38703d163bd042c7827eaddb04ea092b30a478 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046ardb/platform_def.h 5da46b775851344c65928890c699d7ff047606b2 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046ardb/platform.c 686ad098c68cbf424bb3e89e451ab64b8183a91c - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046ardb/plat_def.h 0fb5432862f668e38f9bbce3af181371cdecf0cd - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046ardb/policy.h 2ea7db20f6633e1dbecd9a70ed4cac89d97c2a76 - arm-trusted-firmware/plat/nxp/soc-ls1046a/ls1046ardb/ddr_init.c 06d4dda248389e306ea0cf1688bc9944d1511d03 - arm-trusted-firmware/plat/nxp/soc-ls1046a/aarch64/ls1046a_helpers.S 8cc150d9e1c9199572b24d0af559c82e4db71320 - arm-trusted-firmware/plat/nxp/soc-ls1046a/aarch64/ls1046a.S 0b417a1d9881a05757a25db89aa6739867cc6cff - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_a009660.c 2e0e20e6baddb412ce97b52be66cd32d6f8f367f - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_a010539.c 254c94ec21e9680a13a88c1c24d884bfb8b9479c - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_a008850.c 5f62419793539e6fbda55df6e2b3fa9e0b21b776 - arm-trusted-firmware/plat/nxp/common/soc_errata/errata.h f925bc09cf5f24b92110d8e7eb81b6948bc855b7 - arm-trusted-firmware/plat/nxp/common/soc_errata/errata.c 492965693fd60a384d16d12de2ecd89c7f522702 - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_list.h c693c689d519e4697e033a4df6e7da75ecaca5b7 - arm-trusted-firmware/plat/nxp/common/soc_errata/errata_a050426.c 5898658243b0a5f981f4c051061be8d7f7ff3a7f - arm-trusted-firmware/plat/nxp/common/fip_handler/common/plat_def_fip_uuid.h fc286a6d896799156121d56095076ee1765cdd18 - arm-trusted-firmware/plat/nxp/common/fip_handler/common/plat_tbbr_img_def.h 9670a30b894318a795c85e5ee63edbe979b023b6 - arm-trusted-firmware/plat/nxp/common/fip_handler/common/platform_oid.h 96bd522ef14fb5ff8a4247a028501ef7c4367f3a - arm-trusted-firmware/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.h 97667263a954ff77c695a93ec98b767bccf035cd - arm-trusted-firmware/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.c e41af019a383e1c29f6cfe79b98e6812ee9e71e8 - arm-trusted-firmware/plat/nxp/common/fip_handler/fuse_fip/fuse_io_storage.c 0f0ae89b60dfac27f5f00ac6c76a3c1fbbf30e8c - arm-trusted-firmware/plat/nxp/common/fip_handler/fuse_fip/fuse_io.h 3a09baff31a554c63552bd51f6adea91aa05d3c1 - arm-trusted-firmware/plat/nxp/common/nv_storage/plat_nv_storage.h ceb1d9520145856651363de47761abc466dd38a8 - arm-trusted-firmware/plat/nxp/common/nv_storage/plat_nv_storage.c 3b5918338beab36f0f06c2b7e82c7f49a7b351bf - arm-trusted-firmware/plat/nxp/common/psci/plat_psci.c 187a0bff6625818b129b5ab42039158f8126ddb3 - arm-trusted-firmware/plat/nxp/common/psci/include/plat_psci.h 11b25502ea937dd88b3986d358aad3eff9f39c71 - arm-trusted-firmware/plat/nxp/common/psci/aarch64/psci_utils.S 48b1c6e031a18037fbc338e8d3f6d0efbe6c0eca - arm-trusted-firmware/plat/nxp/common/warm_reset/plat_warm_rst.h f71b1c56189f5904469d9e69c7b5206a4bd12454 - arm-trusted-firmware/plat/nxp/common/warm_reset/plat_warm_reset.c 003b4e0c6ab04fb9bd51037a2c976e8e9a1e90dc - arm-trusted-firmware/plat/nxp/common/tbbr/nxp_rotpk.S 9b61ef7f7b42a7a2448ff56ef3a4dde77d0a3c6a - arm-trusted-firmware/plat/nxp/common/tbbr/csf_tbbr.c 99de11a8e1d6aa0d67bff400dc27222a3f67bda3 - arm-trusted-firmware/plat/nxp/common/tbbr/x509_tbbr.c 6edca4ab32d5c19db4706b176997f9bc4f085702 - arm-trusted-firmware/plat/nxp/common/img_loadr/load_img.h 29f392d59518df56b682fde92d9adb7b7e97112c - arm-trusted-firmware/plat/nxp/common/img_loadr/load_img.c dcfd794664af1da07e241e7f44705b02a86955bb - arm-trusted-firmware/plat/nxp/common/include/default/plat_default_def.h 962eb919fbdac8edf23f3cca5303772adc4690b0 - arm-trusted-firmware/plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h 1c0daba5be7bb7055a56df067ffc86d62af94382 - arm-trusted-firmware/plat/nxp/common/include/default/ch_3_2/soc_default_base_addr.h 9fecb13f267ce5c792719b3969ef19e96064d75a - arm-trusted-firmware/plat/nxp/common/include/default/ch_3/soc_default_helper_macros.h 3b4e4e380dbab1bf4ad037c20f705b6e42b5d992 - arm-trusted-firmware/plat/nxp/common/include/default/ch_3/soc_default_base_addr.h 764ceec06291ed492b81348c85ad37e77f32eb3a - arm-trusted-firmware/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h 2941f6674d8de1d2b22c22b91db3b63996c45d80 - arm-trusted-firmware/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h de50adad02cc0f2c2f34b32e9f3ba2aafe28571c - arm-trusted-firmware/plat/nxp/common/setup/ls_common.c e0dfec4c8847e15aeb7a774844188ab382bdd027 - arm-trusted-firmware/plat/nxp/common/setup/ls_stack_protector.c cb4accb6830f44fe050021fd6e32cca1a8acf7ee - arm-trusted-firmware/plat/nxp/common/setup/ls_bl31_setup.c 475644583f7d46ef814913dcdcfddfa706f9f9bb - arm-trusted-firmware/plat/nxp/common/setup/ls_io_storage.c d736c2075e7e15a400e61a1db310a4d1b43bffd2 - arm-trusted-firmware/plat/nxp/common/setup/ls_image_load.c 7159132c839b1d3568d7b7b03da30f6d03e5336e - arm-trusted-firmware/plat/nxp/common/setup/ls_interrupt_mgmt.c 98e57da5931c557522da93cce9fe3bfb911d2cb0 - arm-trusted-firmware/plat/nxp/common/setup/ls_err.c 6694d9cc9520a800f00a344d9cc1c534b6e88d91 - arm-trusted-firmware/plat/nxp/common/setup/ls_bl2_el3_setup.c 9e4c6090807eed8550b5e6acaf048f870d04011b - arm-trusted-firmware/plat/nxp/common/setup/include/bl31_data.h 7deb5f8e4cedbb8f2f2faed66426dac4607d7f04 - arm-trusted-firmware/plat/nxp/common/setup/include/ls_interrupt_mgmt.h 4f9b26944e2ce37da586a62bdec3d03549edca60 - arm-trusted-firmware/plat/nxp/common/setup/include/mmu_def.h c8d60b0a7cea607dac9dc88673f41a4be9285d2e - arm-trusted-firmware/plat/nxp/common/setup/include/plat_macros.S 52c5991d0ead354cd375910f00aefc81953d5681 - arm-trusted-firmware/plat/nxp/common/setup/include/plat_common.h 8094976b2b7aa5bbc113bbc852215f8e0513c202 - arm-trusted-firmware/plat/nxp/common/setup/aarch64/ls_bl2_mem_params_desc.c 9c72b3ecd5d5982e63db876f7dfefb7cbac10bea - arm-trusted-firmware/plat/nxp/common/sip_svc/sip_svc.c 27f86d14fd5ce72d0aaa417b4c893049acc97e1c - arm-trusted-firmware/plat/nxp/common/sip_svc/include/sipsvc.h be62a5510efe4bb10130935015fc6c12d3b02ed4 - arm-trusted-firmware/plat/nxp/common/sip_svc/aarch64/sipsvc.S 2c5220969ad934f5e3904f8b72774332826fb89d - arm-trusted-firmware/plat/nxp/common/aarch64/ls_helpers.S fdb986fc3069c5b8c185c58c199bc5e56a6d1655 - arm-trusted-firmware/plat/nxp/common/aarch64/bl31_data.S 08360ed6a8b3d051a5cad1cb6e001cf1600b7ac8 - arm-trusted-firmware/plat/nxp/common/ocram/ocram.h 5e45989256d4cb803eb129882666969d3d952ac6 - arm-trusted-firmware/plat/nxp/common/ocram/aarch64/ocram.S 1fc45a1f2166ae38c534bcf389857b89c441c5af - arm-trusted-firmware/plat/nxp/soc-ls1088a/soc.c 0f6a22f1e28fcb385608a72a297b0cbd67935113 - arm-trusted-firmware/plat/nxp/soc-ls1088a/soc.def 11e2d32b094714041c63cf972054b12b7c0db04e - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/platform_def.h 344959df5ba88c1bf9ce847e6735395045c1253c - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/platform.c 9c8add03dd402a33b546ebe338030483a6e30892 - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/plat_def.h 992637daa6e8a443c6f0a176079ce731d593f699 - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/policy.h 30d19335e7872d98487de84b2cc1cfad32bc26ad - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c 11e2d32b094714041c63cf972054b12b7c0db04e - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/platform_def.h 344959df5ba88c1bf9ce847e6735395045c1253c - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/platform.c 3328578a5401038f068eded4991d6a403c5276b7 - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/plat_def.h a7f75b9047c373fb59a317bd6d2995d70aa0aefa - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/policy.h e9f8a604d5a2d30bd7a467c0b5624df132c867ee - arm-trusted-firmware/plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c d1bd24409a0956382d617f97af627e582ec04d5c - arm-trusted-firmware/plat/nxp/soc-ls1088a/include/soc.h 764c8c04a6189e6992612672f9e41abde5000248 - arm-trusted-firmware/plat/nxp/soc-ls1088a/aarch64/ls1088a_helpers.S 492d3f0900343c093e718ba1816eb94bfc3931e9 - arm-trusted-firmware/plat/nxp/soc-ls1088a/aarch64/ls1088a.S b971fa529d2080fd471b3ef7ec4466a972529aee - arm-trusted-firmware/plat/nxp/soc-lx2160a/soc.c 189fa51ba04371ccab55ac105b7dfe77c07f3552 - arm-trusted-firmware/plat/nxp/soc-lx2160a/soc.def c515220a4c8200d4212a8d951e49a9022e7bef2f - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160aqds/platform_def.h b52ff38c67c39f3dc4731b38d094152cb31b4ccd - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160aqds/platform.c 2881529cc073176412af0c380690bab77add20c5 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160aqds/plat_def.h 353f72fa699efe7dc63602a04a220dd43adb85ba - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160aqds/policy.h d07e54f7cdb54922dac5c758dd79b5adb4d9e93f - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160aqds/ddr_init.c f856b32032e096e20ae0a454ad54d4fd64dfca0c - arm-trusted-firmware/plat/nxp/soc-lx2160a/include/soc.h 0fe0002fb83ef9fcbbed68caa9cea3b775bfc529 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160ardb/platform_def.h b52ff38c67c39f3dc4731b38d094152cb31b4ccd - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160ardb/platform.c f53ad9b2677286b07fdbc25c8c257e4891f15607 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160ardb/plat_def.h e7b379eaa610c82050a0e57c194b10a794f23d91 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160ardb/policy.h 764850c7f4814c83fc8b48d4a353c5ae2836edf6 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2160ardb/ddr_init.c c515220a4c8200d4212a8d951e49a9022e7bef2f - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2162aqds/platform_def.h 85eb1ecc310643c5e3edb3761897745f5f4eaa6a - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2162aqds/platform.c 6701efe4878d9b4a7d1035d7d747426951d04e8b - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2162aqds/plat_def.h ab191a3fce41d791a52ed732c81fa4c127537b13 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2162aqds/policy.h e8ecd59dc257f4918515a132b0c4787bc1890021 - arm-trusted-firmware/plat/nxp/soc-lx2160a/lx2162aqds/ddr_init.c 63c93614b627d3a013d8176aa4248010115eecf0 - arm-trusted-firmware/plat/nxp/soc-lx2160a/aarch64/lx2160a_warm_rst.S 3e9660b08500144943aee803a37816f45307d66b - arm-trusted-firmware/plat/nxp/soc-lx2160a/aarch64/lx2160a.S ed1f52b1a3d4ce48135556f32d8667c7367494d8 - arm-trusted-firmware/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S 07fb6c57566e19aa44ef34559874dfd995b582b6 - arm-trusted-firmware/plat/nxp/soc-ls1043a/soc.c 059b1c4ea6e6b540b7b01bdeb7153b4dfcacdb1b - arm-trusted-firmware/plat/nxp/soc-ls1043a/soc.def 9b815992ca7df805a51a7cdece2e7c074a0958fb - arm-trusted-firmware/plat/nxp/soc-ls1043a/include/soc.h 69427e6f64ce96dfa6842364a758359b8fa821c6 - arm-trusted-firmware/plat/nxp/soc-ls1043a/include/ns_access.h 802c1d23237eb5cc83388950a75fa13d076b0dbf - arm-trusted-firmware/plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h 859878633110369cd34a10f6683227f6b49d0006 - arm-trusted-firmware/plat/nxp/soc-ls1043a/ls1043ardb/platform.c 60033abedd63947cfda10bf00d77951046e244c2 - arm-trusted-firmware/plat/nxp/soc-ls1043a/ls1043ardb/plat_def.h 2e5c9db35f0a8446aa2a2a08f75f1488255df745 - arm-trusted-firmware/plat/nxp/soc-ls1043a/ls1043ardb/policy.h f9f0fbba1b0d27332355fe6c4e06137ca772597b - arm-trusted-firmware/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c b132e33ac02b41bfdd0b2ba27b1e5432e0f7ef08 - arm-trusted-firmware/plat/nxp/soc-ls1043a/aarch64/ls1043a_helpers.S 18db50ef3d11821179318d84b45c532d3b107226 - arm-trusted-firmware/plat/nxp/soc-ls1043a/aarch64/ls1043a.S 7101b940d392636f546086caa2626d9a940d9eac - arm-trusted-firmware/plat/nxp/soc-ls1028a/soc.c 490b7dbb3b819d5251283d9069f177092c665489 - arm-trusted-firmware/plat/nxp/soc-ls1028a/soc.def d78024dda44030bb2c60a6c6f0f31b0cdf79c510 - arm-trusted-firmware/plat/nxp/soc-ls1028a/include/soc.h daffee032773c1420ec3c8da52a5bc9db4610aaa - arm-trusted-firmware/plat/nxp/soc-ls1028a/ls1028ardb/platform_def.h 859878633110369cd34a10f6683227f6b49d0006 - arm-trusted-firmware/plat/nxp/soc-ls1028a/ls1028ardb/platform.c 264c5f8c566b8945850048aceba967dd8fd1e72b - arm-trusted-firmware/plat/nxp/soc-ls1028a/ls1028ardb/plat_def.h b435bed7113e72930be88bfe8f61e7da61994418 - arm-trusted-firmware/plat/nxp/soc-ls1028a/ls1028ardb/policy.h 3268f346c7eb1578007b13a160c4c3d08efe2c0b - arm-trusted-firmware/plat/nxp/soc-ls1028a/ls1028ardb/ddr_init.c 033fd89d203e44c446aba6134e51e46a7d9cf324 - arm-trusted-firmware/plat/nxp/soc-ls1028a/aarch64/ls1028a_helpers.S e436d0bfcc7b7c83db0242b6ffefad0a2985a81e - arm-trusted-firmware/plat/nxp/soc-ls1028a/aarch64/ls1028a.S 5fa3e198d6ad7a764cb058e6e88fa12a0d8ffe85 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_nand.c b445ddffd2167b6758d19874673ec99f3f2a1d30 - arm-trusted-firmware/plat/socionext/uniphier/uniphier.h 456820f5853d3f1676ee19bf63b9c360ed9a80a8 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_io_storage.c 21ef9559c64415fef54f3373f28fde4fa86d92d3 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_topology.c 05b8fac4f5d6b8cee9465b541e992f27f071fe8f - arm-trusted-firmware/plat/socionext/uniphier/uniphier_console.S eca523ec19dc113ddd19b9427a6651cd6ebe6bb3 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_soc_info.c ab09cd5d8d3222857a607791bee8b31359314aa9 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_bl31_setup.c 91e3ef5fbfd42b725b57f2608d1934a5c717de3b - arm-trusted-firmware/plat/socionext/uniphier/uniphier_tbbr.c 2b022afd58ed2221e8abc99099867eab0c42c326 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_emmc.c 7cb14fc4ccfe79fe8ffb080b91337e263775111d - arm-trusted-firmware/plat/socionext/uniphier/uniphier_syscnt.c d342acec84b75ea4f64204404f0a54b4158920e1 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_usb.c d94b79f813abf374eef409d04968fce943a3ef84 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_boot_device.c 7518b6009c736b543504a3f84be4cbd20e8d9f0c - arm-trusted-firmware/plat/socionext/uniphier/uniphier_scp.c 69a2371870f65a855d9ff7c728f2e9c32882aa2c - arm-trusted-firmware/plat/socionext/uniphier/uniphier_bl2_setup.c e4e4584414cea9a632b613da62b76c3999974c0c - arm-trusted-firmware/plat/socionext/uniphier/uniphier_console.h ad344a675d5f4bf3287a6e32451b462c3ea7d29c - arm-trusted-firmware/plat/socionext/uniphier/uniphier_rotpk.S 98c1438c270db5db7bd6f971cb928420df53c1b7 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_image_desc.c 516680ab29649a33ea07ffa922f3b18448e61e55 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_psci.c 26621302eaceca62d3b0e8224c6c14d5ea08df38 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_xlat_setup.c 006db753e22b1119a67d4f76bd213bf3de08be09 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_gicv3.c 8a0a08bd7b9292bd5b334bc91ad422838eb83118 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_cci.c 30db57b3d947cfae86d4cb1fbd7d79f7365fe01d - arm-trusted-firmware/plat/socionext/uniphier/uniphier_smp.S 30d16489f342eed522b276128737ad41acb82ba9 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_helpers.S dd16d7be9af0988718096ec4af552732207ad390 - arm-trusted-firmware/plat/socionext/uniphier/uniphier_console_setup.c e35ee40c042c15de97496be4f1d9c81b960cc3da - arm-trusted-firmware/plat/socionext/uniphier/include/platform_def.h 8bea3f2da202b83b97d9b86e32cb50d5c17cae7e - arm-trusted-firmware/plat/socionext/uniphier/include/plat_macros.S d181839ef722d36e8a51c126deb67a2eae64c527 - arm-trusted-firmware/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c f43a62ef3a99346a097b8813441539c5354436fc - arm-trusted-firmware/plat/socionext/synquacer/sq_ccn.c a8796cf9a2847c8c6d4851d911b9bd0622450b48 - arm-trusted-firmware/plat/socionext/synquacer/sq_io_storage.c a11d578ee6af8315da34f383d53ad866c3acb944 - arm-trusted-firmware/plat/socionext/synquacer/sq_image_desc.c a32f17d7db01cfb7a14811a914ba2066581d29a1 - arm-trusted-firmware/plat/socionext/synquacer/sq_spm.c fabaf9f847297853dc77c6577d5049ea4ab77809 - arm-trusted-firmware/plat/socionext/synquacer/sq_bl2_setup.c b60ee8850906f76ada82b2db19c8656ed9c12d9a - arm-trusted-firmware/plat/socionext/synquacer/sq_gicv3.c 94f1c76a8b066bc8d833c5c6d9d83cc9d34c7f6a - arm-trusted-firmware/plat/socionext/synquacer/sq_helpers.S 9b1262ca8c6950227a294b789fb3e53dfa2086b1 - arm-trusted-firmware/plat/socionext/synquacer/sq_topology.c 77fff6026c1390b1ee72fb8b325459f621ba78e3 - arm-trusted-firmware/plat/socionext/synquacer/sq_psci.c 8286dff95425dddb9a5b25ffda50460831781793 - arm-trusted-firmware/plat/socionext/synquacer/sq_xlat_setup.c 572ea5edf4e0c46c76fdc9b6eb08197c585be8b5 - arm-trusted-firmware/plat/socionext/synquacer/sq_rotpk.S 46f95ebc32523d9f1cccec7e9619f41394a601cf - arm-trusted-firmware/plat/socionext/synquacer/sq_bl31_setup.c b8adf13173155303a49ce111d0e2bf30bae8a3c8 - arm-trusted-firmware/plat/socionext/synquacer/sq_tbbr.c 961c660b9e7a5641523d5d23b5396c2a2a67746e - arm-trusted-firmware/plat/socionext/synquacer/drivers/mhu/sq_mhu.c ebfc7926ca7e342e5cec3fed564e68be76a80fdd - arm-trusted-firmware/plat/socionext/synquacer/drivers/mhu/sq_mhu.h b6784404cec981a185e6f44ef689f28b7d9513e3 - arm-trusted-firmware/plat/socionext/synquacer/drivers/scpi/sq_scpi.c f8fe95fbe1e35e8c328ec5a197b76c329feda4bd - arm-trusted-firmware/plat/socionext/synquacer/drivers/scpi/sq_scpi.h e431465e90b8b68ce2922ff400c2e6953eaeea9d - arm-trusted-firmware/plat/socionext/synquacer/drivers/scp/sq_scmi.c f57f50699d6a8f3902d4673f01ec3ff0d6931d29 - arm-trusted-firmware/plat/socionext/synquacer/drivers/scp/sq_scp.c 3feac02c8c7ca9aa51ae9f96e7c204d43856d111 - arm-trusted-firmware/plat/socionext/synquacer/include/platform_def.h 71b4d3a8866abd87734eafad2ffcf269d273af25 - arm-trusted-firmware/plat/socionext/synquacer/include/sq_common.h 9f24e8fcbc08c61f43c8041c0464cae65fe01ce8 - arm-trusted-firmware/plat/socionext/synquacer/include/plat_macros.S ef74e9cda94f07bf3061b037195287d609c0c6b4 - arm-trusted-firmware/plat/socionext/synquacer/include/plat.ld.S 43da4a7bd6435c6cc7d733e6363a59cacabb9ef5 - arm-trusted-firmware/plat/brcm/common/brcm_mhu.c 02ea7c4006c2910720bf4a85c3766c293d4cb8e5 - arm-trusted-firmware/plat/brcm/common/brcm_mhu.h c02bbae941528cbae0665016d62e54bfffb74444 - arm-trusted-firmware/plat/brcm/common/brcm_bl2_setup.c bc616aa281d726780f6a73b3986accbe986e780f - arm-trusted-firmware/plat/brcm/common/brcm_bl2_mem_params_desc.c 9b8db7387e47af68fc183fe909d3060d65438cb2 - arm-trusted-firmware/plat/brcm/common/brcm_io_storage.c 43088754fcc9a1fcbb6308988d79eca0c2771d5a - arm-trusted-firmware/plat/brcm/common/brcm_ccn.c 389238486613bb86c6032f788a4605c782e7475c - arm-trusted-firmware/plat/brcm/common/brcm_gicv3.c d083c67e189d3cd3712a827a23e28d0aaf2964d1 - arm-trusted-firmware/plat/brcm/common/brcm_bl31_setup.c 303c81103a6ebbdf9e4afc16b17d17195a5b9238 - arm-trusted-firmware/plat/brcm/common/brcm_scpi.h 6d6865834cfc5ce82506bf1ef6df2e3cb196e028 - arm-trusted-firmware/plat/brcm/common/brcm_scpi.c 48faf64df1848d8493a3f273494ea883a4aafb0c - arm-trusted-firmware/plat/brcm/common/brcm_common.c 2ef6d891873792dd5af17cc1091f369c0865c70d - arm-trusted-firmware/plat/brcm/common/brcm_image_load.c 1dea9a2af71a56fe60929b854a2c73220603d2be - arm-trusted-firmware/plat/brcm/board/stingray/include/timer_sync.h 2817bede11ad2da4d5612a155f5a76e30b62de62 - arm-trusted-firmware/plat/brcm/board/stingray/include/paxc.h 2c4acf78dfd7c25c281471b6717273ff7920fea8 - arm-trusted-firmware/plat/brcm/board/stingray/include/ncsi.h 4bc4735b9e7c2a5eab8ae91a28d110dd24a42d75 - arm-trusted-firmware/plat/brcm/board/stingray/include/sdio.h 2ef5c016a1130291e30fb58c1e1b397bb15a531c - arm-trusted-firmware/plat/brcm/board/stingray/include/platform_sotp.h 1e67ee0873eb29816b418096b514d39c3aeb7d27 - arm-trusted-firmware/plat/brcm/board/stingray/include/swreg.h cc26d153c04427651e12bf00d19497e5bd8cb7a3 - arm-trusted-firmware/plat/brcm/board/stingray/include/platform_usb.h a6bea74c09e847241ba6a156aff89b12670cc98b - arm-trusted-firmware/plat/brcm/board/stingray/include/scp_cmd.h d823df9c59408673229302e557a65ad1c404e047 - arm-trusted-firmware/plat/brcm/board/stingray/include/platform_def.h bbaec5f331d8cf8f24898a8d172190c5f7940b6a - arm-trusted-firmware/plat/brcm/board/stingray/include/ihost_pm.h 90c98d478915f89433c419b06613a52965aeeef6 - arm-trusted-firmware/plat/brcm/board/stingray/include/sr_utils.h bd25c5d9d7605649bc1d1dee9a734ccb130101c3 - arm-trusted-firmware/plat/brcm/board/stingray/include/fsx.h 10104d7d5d9eeeb545dea9ac306deb2c5cf46036 - arm-trusted-firmware/plat/brcm/board/stingray/include/plat_macros.S 0228e24fbe8ff775ac7a709f272d375a8e7aa3bf - arm-trusted-firmware/plat/brcm/board/stingray/include/scp_utils.h eeabf0e8e4cda99b503b2ea41298aff2d87e1278 - arm-trusted-firmware/plat/brcm/board/stingray/include/ddr_init.h 8c57e437d9f4b2b49f005f899624af9b47121102 - arm-trusted-firmware/plat/brcm/board/stingray/include/crmu_def.h 0ef862af40a95d70feda6b8367e6e7452e90099b - arm-trusted-firmware/plat/brcm/board/stingray/include/board_info.h b0a1c672d4d7095f6e7ec5305e084cb3a29a790e - arm-trusted-firmware/plat/brcm/board/stingray/include/bl33_info.h 76dbcdb10f12f01d94b3c70d2f8562b0cc8b233a - arm-trusted-firmware/plat/brcm/board/stingray/include/paxb.h 491a5116f054df365b530dc8b09613f1178c2d8a - arm-trusted-firmware/plat/brcm/board/stingray/include/sr_def.h 9765542d155d4fc37ee167eda672c6a33030ca8c - arm-trusted-firmware/plat/brcm/board/stingray/include/iommu.h e7629876236e444ee69e40c96440f3f24b16fefe - arm-trusted-firmware/plat/brcm/board/stingray/include/usb_phy.h d15b82eea2aaa023805036e829ee46cd08ea72ed - arm-trusted-firmware/plat/brcm/board/stingray/src/iommu.c 52a5e5247c12940390abe486ab490a1d8929feb4 - arm-trusted-firmware/plat/brcm/board/stingray/src/paxb.c 0283858faf5651d4db16f0e4b8bcaadd40bcabe1 - arm-trusted-firmware/plat/brcm/board/stingray/src/scp_cmd.c f89deabe82fe9129f1dde3fb24e57c940e008913 - arm-trusted-firmware/plat/brcm/board/stingray/src/bl2_setup.c c01d8b9f9c48a1185129c492ab1f8ce1134ed892 - arm-trusted-firmware/plat/brcm/board/stingray/src/scp_utils.c e9f5650def0bf0c03c50ad69056cf6ff9d71a715 - arm-trusted-firmware/plat/brcm/board/stingray/src/tz_sec.c 78d2915d5c3a6c4b75eb97c897cd4e58b4d5b962 - arm-trusted-firmware/plat/brcm/board/stingray/src/topology.c 085cb8e4f6dd01efc01f633680e7db315718c304 - arm-trusted-firmware/plat/brcm/board/stingray/src/ihost_pm.c 062b1d173f23bc015ebb5c790f890e5f2a6934e1 - arm-trusted-firmware/plat/brcm/board/stingray/src/paxc.c 1fd2e7122a0c63a14a64215ae5750097f050841b - arm-trusted-firmware/plat/brcm/board/stingray/src/brcm_pm_ops.c 9b0afdae90ec3159bd428d4b9f586d84a0cb55b3 - arm-trusted-firmware/plat/brcm/board/stingray/src/sdio.c d746f7070f366ac250b3766606d2de76a6192436 - arm-trusted-firmware/plat/brcm/board/stingray/src/fsx.c 77916c4c9e55da373b1b66dba19dfed0034cde48 - arm-trusted-firmware/plat/brcm/board/stingray/src/bl31_setup.c 863c6f32899af28cd9a60fb273bdc02a29100114 - arm-trusted-firmware/plat/brcm/board/stingray/src/sr_paxb_phy.c 75de08bf7cc548fc88463a459efa719ce9dae276 - arm-trusted-firmware/plat/brcm/board/stingray/src/pm.c 072e5bc5c72a860c50c3413898b60dd18931b100 - arm-trusted-firmware/plat/brcm/board/stingray/src/ncsi.c 1071f5589a11aaf7354868d034e149b27d48adc6 - arm-trusted-firmware/plat/brcm/board/stingray/driver/swreg.c 13bbb4dc261e840997a59d4e914f071835d33fab - arm-trusted-firmware/plat/brcm/board/stingray/driver/usb_phy.c 7cc68c731d1d4e967a6b258c94afef74800e2c27 - arm-trusted-firmware/plat/brcm/board/stingray/driver/usb.c b4637f982a40118b9d83d3908d0b189d3524bce0 - arm-trusted-firmware/plat/brcm/board/stingray/driver/plat_emmc.c 483849480279e54ca28e4177fea05d6bd3cd36d7 - arm-trusted-firmware/plat/brcm/board/stingray/driver/ihost_pll_config.c 4573848f39ea4bfceb55e0932f0494af8b890d1d - arm-trusted-firmware/plat/brcm/board/stingray/driver/sr_usb.h eed068af90592502021f8e15b556ae302cd8db87 - arm-trusted-firmware/plat/brcm/board/stingray/driver/ddr/soc/include/board_family.h d0dacd8fc79f78cee10bd8513550abf93624afe2 - arm-trusted-firmware/plat/brcm/board/stingray/driver/ext_sram_init/ext_sram_init.c 46e832c20411ea4d2bcbcf1cc8968149375047f4 - arm-trusted-firmware/plat/brcm/board/stingray/driver/ext_sram_init/ext_sram_init.h ac2b64132debec3b54ae614c64dac69067b39291 - arm-trusted-firmware/plat/brcm/board/stingray/aarch64/plat_helpers.S 9635661f5e56e9ab172dcec943257465bf36e634 - arm-trusted-firmware/plat/brcm/board/common/bcm_elog.c e1b5c755e9973d3e41e6f8dd620990a0dd5ba5e6 - arm-trusted-firmware/plat/brcm/board/common/cmn_plat_def.h 9eda9f547bdfb6e83ef3c8d82d849e1e4cb68252 - arm-trusted-firmware/plat/brcm/board/common/brcm_mbedtls.c 5f45cc70d813bf16880f4f1f4a246ad6114fbb78 - arm-trusted-firmware/plat/brcm/board/common/cmn_plat_util.h eca89f1edcb0c3fc702ac123a55821cde16106bb - arm-trusted-firmware/plat/brcm/board/common/err.c 2d3a08ac4729a455bffd5c4c70365350fec69e23 - arm-trusted-firmware/plat/brcm/board/common/bcm_elog_ddr.h dfc2e7fae9dd66b664758412e1f4c06762246ed6 - arm-trusted-firmware/plat/brcm/board/common/cmn_sec.c 2cf7d5accbb22d89a3c89c768604f667a23bef52 - arm-trusted-firmware/plat/brcm/board/common/sbl_util.h 500e36754a0240001fe7b400bf8d4806a06de6ee - arm-trusted-firmware/plat/brcm/board/common/timer_sync.c c0ecc823e4de1814edd6bf48321b6317c448b16d - arm-trusted-firmware/plat/brcm/board/common/sbl_util.c a731b4badf1cf5a90a0ab197b39a2723e4c85dd9 - arm-trusted-firmware/plat/brcm/board/common/platform_common.c b2a5352558dc92001c80e614a9b293a1eb19573a - arm-trusted-firmware/plat/brcm/board/common/plat_setup.c a794cd95a890c951acc5192426abc008b4213a8f - arm-trusted-firmware/plat/brcm/board/common/chip_id.h 801bb1cdab4baf3440ac23728e6190881af4264f - arm-trusted-firmware/plat/brcm/board/common/bcm_elog_ddr.c c124ba5ec6d9fc3e8f1f0b72d3852473ab67e998 - arm-trusted-firmware/plat/brcm/board/common/board_common.c 515e3aecc5237dcc8197e4e8ed7fd7d15765d808 - arm-trusted-firmware/plat/brcm/board/common/bcm_console.c eeff346a4c2b6893ad0fa417570e747058627c11 - arm-trusted-firmware/plat/brcm/board/common/cmn_sec.h 779be799404c9562032c8c586f3a3b23835ad722 - arm-trusted-firmware/plat/brcm/board/common/board_arm_trusted_boot.c d2d1fd0fffc8a200fd42f1b74c8c7d54c483f219 - arm-trusted-firmware/plat/rpi/common/rpi3_trusted_boot.c 41feb9d914df818ac88209ee1569e1701d794248 - arm-trusted-firmware/plat/rpi/common/rpi3_common.c 854bc00d3c5fce60726920c1e5b1b7cd9352568a - arm-trusted-firmware/plat/rpi/common/rpi3_io_storage.c e7c5c53de7054042af3cf0941787805fcbbc77fd - arm-trusted-firmware/plat/rpi/common/rpi3_pm.c 11c87bf8a084123bf9a431cc289a66e23112bade - arm-trusted-firmware/plat/rpi/common/rpi3_rotpk.S 46c13e3cff3d9c29a733d01629589bd31b37eb5e - arm-trusted-firmware/plat/rpi/common/rpi3_stack_protector.c e621f46501a2d1856f297145947d1c8d89d5f990 - arm-trusted-firmware/plat/rpi/common/rpi3_image_load.c dc79372e77a81c53ff2886832f206db2f63873b7 - arm-trusted-firmware/plat/rpi/common/rpi3_topology.c c3a79cfd4e400e0a2dfa7ee5e27e50f1bcd8464b - arm-trusted-firmware/plat/rpi/common/include/rpi_shared.h d2456dd752e5376ca6049639fe93ef04bd5aa04f - arm-trusted-firmware/plat/rpi/common/aarch64/plat_helpers.S 20b2e08539e950f86d86538ed688408f90574454 - arm-trusted-firmware/plat/rpi/rpi3/rpi3_bl2_setup.c 052815ff6a9d47f47e57d320313a74f10c8a34d3 - arm-trusted-firmware/plat/rpi/rpi3/rpi3_bl31_setup.c fd5000ab9d2eac8341e267b879e1ef29eaebf5d7 - arm-trusted-firmware/plat/rpi/rpi3/rpi_mbox_board.c d9b070fbdda2cab75cc45e6dddd9a31f84baf594 - arm-trusted-firmware/plat/rpi/rpi3/rpi3_bl1_setup.c 94001fd4bfa1b8e08f4d51f437c7b006362f24fd - arm-trusted-firmware/plat/rpi/rpi3/include/rpi_hw.h 7aeb3415e697151619997c1c184f380eb310be78 - arm-trusted-firmware/plat/rpi/rpi3/include/platform_def.h 64987d2484ce3d48cc4431fee2de9e375235bb5a - arm-trusted-firmware/plat/rpi/rpi3/include/plat_macros.S 5a79ec05194636d3850044f358b4673a3f0b9fa0 - arm-trusted-firmware/plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c 54eb696ef592336053f52bc556f47122b4e94fdc - arm-trusted-firmware/plat/rpi/rpi4/rpi4_pci_svc.c 793e163b5e60486c53f3ff36c98ab1c8f144a1bd - arm-trusted-firmware/plat/rpi/rpi4/rpi4_bl31_setup.c e2412e3cbdcc8daaecfab85f295ee3456cf1f98d - arm-trusted-firmware/plat/rpi/rpi4/include/rpi_hw.h 6a73f5496572d65332bbf4a50c3c9d4faa9af438 - arm-trusted-firmware/plat/rpi/rpi4/include/platform_def.h b1c50f058d68ea165b6dd5f45af97d2b1dd33e64 - arm-trusted-firmware/plat/rpi/rpi4/include/plat_macros.S 4d8d91a23a19a15ff7c18f8e6e523c26cd453f2f - arm-trusted-firmware/plat/rpi/rpi4/include/plat.ld.S 5e76d520f8ea85f6710a605e2c9a4db0d1a66640 - arm-trusted-firmware/plat/rpi/rpi4/aarch64/armstub8_header.S eaa5486b6bf2e6ae1fa166ea8faf069982cafc3e - arm-trusted-firmware/plat/st/common/stm32mp_common.c c0fcb84a94921b5ff081822dea1f4054a0733389 - arm-trusted-firmware/plat/st/common/stm32cubeprogrammer_usb.c 04e1f5b8785d5e9cc7a97feca82d6cc1ecbefe14 - arm-trusted-firmware/plat/st/common/stm32cubeprogrammer_uart.c 74fbe0f984451420cfc011a7d13cc3b0fc5f6336 - arm-trusted-firmware/plat/st/common/stm32mp_fconf_io.c e87c6273c39e0415537fb0bc256a937bc1f48bbc - arm-trusted-firmware/plat/st/common/bl2_io_storage.c 39406ac1da20e5a2872807c5677512999c03c4d9 - arm-trusted-firmware/plat/st/common/stm32mp_trusted_boot.c 3844d67d29936a57d4c37fb4ffdd41d212121420 - arm-trusted-firmware/plat/st/common/stm32mp_dt.c a055271fe9c247011994ab1513d2fd32c6d82009 - arm-trusted-firmware/plat/st/common/stm32mp_crypto_lib.c 356f823bccc7081e026233c6fb511c0602208101 - arm-trusted-firmware/plat/st/common/usb_dfu.c a48402444da4bcb7bce60d2e3f9972f07bebc8a4 - arm-trusted-firmware/plat/st/common/include/stm32mp_dt.h 8bb1550cf77c8680e05ba46ad44ab77ff26bb8f3 - arm-trusted-firmware/plat/st/common/include/usb_dfu.h b270dbb723f5c002dbf393eb752ccb946afc5baf - arm-trusted-firmware/plat/st/common/include/stm32mp_shared_resources.h 4ca9fb0296b649411cecd45263ecadb41540d6e4 - arm-trusted-firmware/plat/st/common/include/stm32mp_fconf_getter.h a36884221e8b5d12d086eaf6864ac84cddb76454 - arm-trusted-firmware/plat/st/common/include/stm32mp_common.h 1125720a4a5573b7f8197d2dabdf308f51407896 - arm-trusted-firmware/plat/st/common/include/stm32mp_efi.h dd7ae18098736e737a0482a59de65f64d5edd503 - arm-trusted-firmware/plat/st/common/include/stm32cubeprogrammer.h 8f929216bedbfc6324814103b9ff902713ed14cf - arm-trusted-firmware/plat/st/common/include/stm32mp_io_storage.h 5219346badc88996294b1e6304843c005a6bc3e2 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_tbb_cert.c 24a80504eaab8e742fc6d02a0234cd3712d28e30 - arm-trusted-firmware/plat/st/stm32mp1/plat_def_uuid_config.c 43753b990fdb953ffc38ef29474ef4af453444b7 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_stack_protector.c 008b02c65cede29f0ab582356d6d4400ace3914b - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_private.c 58a5d9c283fcb21c6328e65dda44190d07fe6bb2 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_syscfg.c 155e11b39243b6257695dfe51258e330e378e1b8 - arm-trusted-firmware/plat/st/stm32mp1/plat_bl2_mem_params_desc.c 7b00ed042c247bac94b4766cb42dddc0e21764fc - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_scmi.c 0f0baced38fb65393cd300bdc024b68e707f5f4b - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_topology.c f171c1cd88d3ea2070a747ca519f7d6b9e8257f5 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_usb_dfu.c d3e90d44407a4707ef8edd3a8bf03d39015f4b3d - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_def.h b900c2f6ef836a0f77c00c851815a09220d8c5e3 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_fconf_firewall.c 355c64575394ac01f1861e0f9e3a5787e66fa3ed - arm-trusted-firmware/plat/st/stm32mp1/plat_image_load.c 494b344c5c893bd8e9e3ab32c16acc57ebd39f73 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_boot_device.c 77c94644e0ef95316e08e0a339fb16a856ae5d97 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_dbgmcu.c 168a3e80fa38489428f2b6ee242c480adee12b73 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1.ld.S 3139c2b0c93ae17696224f59b5486f65e1649dc7 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_gic.c ab223932eb6ce18395dd58bd90e047532d3644c8 - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_fip_def.h 4768b03bc74bbab9e5cff7a9d7dbd20e4f25decb - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_pm.c d5b0e2699695505579def8552759c7d668a0b3eb - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1.S e9bf2a255a3615d1939e4f6d7ac9ef0b19052a2b - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_helper.S ec9fe0a8eec79fee1d3dd34bf1a969b8f0b93f4a - arm-trusted-firmware/plat/st/stm32mp1/stm32mp1_shared_resources.c 9f1c3deb238c6eec4aa10af2edf07f90deb8f5ba - arm-trusted-firmware/plat/st/stm32mp1/bl2_plat_setup.c d3b6a6e439aa3550128eac0599ad9ac7024c43a4 - arm-trusted-firmware/plat/st/stm32mp1/sp_min/sp_min_setup.c 8386333a75dca31e05ab9b598b8dd745d166e129 - arm-trusted-firmware/plat/st/stm32mp1/include/plat_def_fip_uuid.h c8836682d54efbf71217e171f7181151c66fca07 - arm-trusted-firmware/plat/st/stm32mp1/include/stm32mp1_mbedtls_config.h 08483c5e8b122913b20ea045dbb185897d5bccf1 - arm-trusted-firmware/plat/st/stm32mp1/include/plat_tbbr_img_def.h 037c15f669a9751a6f762da3b2951007624902ef - arm-trusted-firmware/plat/st/stm32mp1/include/platform_def.h 7eaf59b974175885a0dfccf0b42c774580444f92 - arm-trusted-firmware/plat/st/stm32mp1/include/stm32mp1_smc.h 6d6391c62306978263be31d559221680ed9b6025 - arm-trusted-firmware/plat/st/stm32mp1/include/stm32mp1_shared_resources.h 2b0ef70f72efdd3be6c6218b5b2251c6ec57b831 - arm-trusted-firmware/plat/st/stm32mp1/include/stm32mp1_private.h d12872b893bf8db2b51b7243dd638bf34e9d6cfa - arm-trusted-firmware/plat/st/stm32mp1/include/stm32mp1_dbgmcu.h 96b4835eb47121c77e236ef5f06041eabf4b9df1 - arm-trusted-firmware/plat/st/stm32mp1/include/boot_api.h 3634a2a5153ce08df9ec6873bf13d67cfbe72002 - arm-trusted-firmware/plat/st/stm32mp1/include/tbbr/stm32mp1_tbb_cert.h 406790007d4d597b108faf9871360acfa7cdcf23 - arm-trusted-firmware/plat/st/stm32mp1/services/stm32mp1_svc_setup.c 89ab811529f632c51fa5e732be395bac1ea89887 - arm-trusted-firmware/plat/st/stm32mp1/services/bsec_svc.c 3b882920ab056c9bbc38be63b2715e1d796109c4 - arm-trusted-firmware/plat/st/stm32mp1/services/bsec_svc.h 09dd0d32acc68693a9cc4e6edda975b30b997a7d - arm-trusted-firmware/plat/hisilicon/poplar/plat_pm.c 706af98521027fbfb3cb50742e9203904186ccfb - arm-trusted-firmware/plat/hisilicon/poplar/poplar_gicv2.c 43b6cb88b4528db3610c0591b417afee9f8e086f - arm-trusted-firmware/plat/hisilicon/poplar/plat_storage.c 942f440e430db3a0fb9bafcb2877fa0f2b2b2206 - arm-trusted-firmware/plat/hisilicon/poplar/plat_topology.c 5366b77beffc310cab412735a4e4f43185e171c6 - arm-trusted-firmware/plat/hisilicon/poplar/poplar_image_load.c 166469bcfd5bac8ca50e33d23d40607d532f7a9f - arm-trusted-firmware/plat/hisilicon/poplar/bl1_plat_setup.c 575e7801ee2435ca3d3bc588117235189cba8fa2 - arm-trusted-firmware/plat/hisilicon/poplar/bl31_plat_setup.c efef809ad6abb1c1388bcc0ffa92d502ca075b96 - arm-trusted-firmware/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c 4df6d997a517a03b7120733e3ff6f1a2634caa47 - arm-trusted-firmware/plat/hisilicon/poplar/bl2_plat_setup.c 54bc2fcf8fb31777a2eee36c5b61246cc0fa0a17 - arm-trusted-firmware/plat/hisilicon/poplar/include/poplar_layout.h 2bc481728aac66acbe669f76aa6dd84c3f4e88a7 - arm-trusted-firmware/plat/hisilicon/poplar/include/plat_private.h e8d837174e3274ddbcd923af88d3e19e1af8c06a - arm-trusted-firmware/plat/hisilicon/poplar/include/platform_def.h 7309b02ef23609fb839b029b295bffaf714cdc1a - arm-trusted-firmware/plat/hisilicon/poplar/include/plat_macros.S 5333986fb9d6df5ca3e50aad616e8c1422eafdd2 - arm-trusted-firmware/plat/hisilicon/poplar/include/hi3798cv200.h 5b726e62a784d7660009ac2235ebf2d76dc809ad - arm-trusted-firmware/plat/hisilicon/poplar/aarch64/poplar_helpers.S ef034cd3245b78dec24c714d8ffbb7e9b490427c - arm-trusted-firmware/plat/hisilicon/poplar/aarch64/platform_common.c 19471da73d6d6e0316b89091e8034b65252676ea - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl1_setup.c e521b7127c97a6dc50d62a6fb23613467dfa5c91 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_boardid.c 3b43870e172a97e6682dc9e7adeb7ee54b219ce1 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_mcu_load.c bbe8476c612a414078e7e0577543027250b3be7c - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_private.h fc3d37d2191841fe6bab5841f4be4e364cf919b1 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_io_storage.c b4ec4794171dff334edac55b287dbba42365301a - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl_common.c e7130fd49b764ab203b1f70d8c04929b17c338a1 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_tbbr.c df960717d8f3e8b3111b85c464d02214767ffe67 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_rotpk.S 00000d9a64ab9fc946dd3055da2fa43094bc324f - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c e5d1ee45233d19ae915b7dcde9d177ac30ff3c59 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_pm.c 6fa5580d26b86920efd2c1e07b6a3f6a14561af8 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl31_setup.c 0f1a35cf03c46fa57303de1b14fd3ec9d83d2e72 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_bl2_setup.c 0cd271eb1db1372ebacbc89a1ab7e6b858522177 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_topology.c 9becd5a35328d19646bc14bdbf52f66571aad713 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_el3_spmc_logical_sp.c dd51fbc51f374c1d5e6292885a8f0058321bb5cc - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_image_load.c 58fdfe0ccfcc2206b61f2c7148ae45a7e7b5c061 - arm-trusted-firmware/plat/hisilicon/hikey960/hikey960_def.h 4a0475ff7dac46ea547e623a9a83071f69b5a4b7 - arm-trusted-firmware/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.h 168bc920b2828c8478a977c1e6b9e597791c0e45 - arm-trusted-firmware/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c 4abee183dc860ea0fe600bb9b19e3c4a0a3d6773 - arm-trusted-firmware/plat/hisilicon/hikey960/drivers/ipc/hisi_ipc.c 9b6172a308464c71e87f1f420cb1df10ceb7bfb4 - arm-trusted-firmware/plat/hisilicon/hikey960/include/hisi_ipc.h d8da79f1ebd9b100b4d3dc915552f3d086d5eda9 - arm-trusted-firmware/plat/hisilicon/hikey960/include/hi3660_mem_map.h 98cbcb7b00b84ca35f3855f0fed8a0bcc35044b6 - arm-trusted-firmware/plat/hisilicon/hikey960/include/platform_def.h 390e28e24c8915a9f956b1a1de0cafa7306bf9ed - arm-trusted-firmware/plat/hisilicon/hikey960/include/hi3660.h 201bc8884be1cfb9b4f87f3fcc6ccf3aeec268d8 - arm-trusted-firmware/plat/hisilicon/hikey960/include/hi3660_hkadc.h b1be891afebf5d255da6f6dcb865725241f566b9 - arm-trusted-firmware/plat/hisilicon/hikey960/include/hi3660_crg.h 930c77f84c5ef2c7971e52015e58fd9c314fbba5 - arm-trusted-firmware/plat/hisilicon/hikey960/include/plat_macros.S 77e4539abdf67b163741920f231c1ecefc072c27 - arm-trusted-firmware/plat/hisilicon/hikey960/include/plat.ld.S 14bf1952f6bf5592c70b43aff34b3984bb9079a7 - arm-trusted-firmware/plat/hisilicon/hikey960/aarch64/hikey960_common.c 33e4f92c8882961c556666d4e463a0cd932589bb - arm-trusted-firmware/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S 0472150350a0f6a23e8750e0fe14991d176d1a04 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl1_setup.c e5479e33302a43e627013dbe10bbcca8ccdbf8b5 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl31_setup.c 8b11d0569d254ee10c03b8e7dfaebf823b7b1746 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl_common.c 132b89dc419b19bfabb3eb2450a5e74317faea11 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_io_storage.c 8d152d6cc7fa809e64664b6fda9d33b121b05eaa - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c 1dc25162c504805b378176ceb2a1fac39b8fa3e2 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_ddr.c 33f9c2d61b7aa3242f22100ba2694ba2709f7a1b - arm-trusted-firmware/plat/hisilicon/hikey/hikey_topology.c 0071214b6af7f5e24aa92d4e7849c79c3818ed05 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_bl2_setup.c b8ddcea3e66690f3932ae009921566fe249feccd - arm-trusted-firmware/plat/hisilicon/hikey/hisi_pwrc_sram.S cfc7af573fbb40bb702a616d8f0bf02b017a3e0b - arm-trusted-firmware/plat/hisilicon/hikey/hisi_dvfs.c b0603f49d7b1252e6774be83ed95232695f1f263 - arm-trusted-firmware/plat/hisilicon/hikey/hisi_ipc.c a68989337ee4c06cf76f89d69cfc5c3aca210b00 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_private.h bca37120bec0db88310c0e711220bd8301c8b932 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_pm.c e90b7c0a59b785560e233605f2968b642d26fcdb - arm-trusted-firmware/plat/hisilicon/hikey/hisi_sip_svc.c 3f90b73f27ba47848db784621dd350e6a5ec54d9 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_tbbr.c 1975a45f73616d0ceb03dab4a9397cbabc1e66ce - arm-trusted-firmware/plat/hisilicon/hikey/hisi_pwrc.c 5366b77beffc310cab412735a4e4f43185e171c6 - arm-trusted-firmware/plat/hisilicon/hikey/hikey_image_load.c 126933334b9ebdde11859016f3bbcc6ac9bbef88 - arm-trusted-firmware/plat/hisilicon/hikey/hisi_mcu.c 1b333e35df79afc9319c45ded87fe22b1e5547fc - arm-trusted-firmware/plat/hisilicon/hikey/hikey_security.c 0aace28e8f75168d13d7274d81f1f906cc1b2cae - arm-trusted-firmware/plat/hisilicon/hikey/hikey_rotpk.S e2fd2bbe14a506ac8ab6eb8f4c65dd34827b33a8 - arm-trusted-firmware/plat/hisilicon/hikey/include/hikey_def.h 31f012031e8dec3fe5dab7afc9ab89deffb7fe7c - arm-trusted-firmware/plat/hisilicon/hikey/include/hi6220_regs_pmctrl.h 95b6af34fbda29b2cef5ecaa3ecf9deb1f7a48cb - arm-trusted-firmware/plat/hisilicon/hikey/include/hisi_mcu.h 659dfae8f25d18bef4e2ac3c9b2cc07bbd255dd4 - arm-trusted-firmware/plat/hisilicon/hikey/include/hi6220_regs_acpu.h ee2004c34a377b43d61f3fde4201ea86e1834fc7 - arm-trusted-firmware/plat/hisilicon/hikey/include/hisi_pwrc.h fff863e589a15845fe768ee9bd16a482d5946db7 - arm-trusted-firmware/plat/hisilicon/hikey/include/hi6220_regs_ao.h 379cc0fd2c6486a2bfc850d19190835961783f16 - arm-trusted-firmware/plat/hisilicon/hikey/include/hisi_sram_map.h 79f261b3e512eb92ef04e1b172276ba95108b6ac - arm-trusted-firmware/plat/hisilicon/hikey/include/hisi_ipc.h 42137e1b1e1f31a2b92b351765982cc8bcf28601 - arm-trusted-firmware/plat/hisilicon/hikey/include/hi6220_regs_peri.h 5da379773f07f291d897ea36a13ac008c78bbbe4 - arm-trusted-firmware/plat/hisilicon/hikey/include/hi6220_regs_pin.h eb1ee8f26e0a9e1d174893e2a80e0ea2be070df3 - arm-trusted-firmware/plat/hisilicon/hikey/include/platform_def.h b9c87b1b0f989e816c65163d00ead7cd68b4b6bc - arm-trusted-firmware/plat/hisilicon/hikey/include/hi6553.h e0f40190a4d2a13086e9b7c951d5301f744dd767 - arm-trusted-firmware/plat/hisilicon/hikey/include/hi6220.h 4619ff482dfa91c976c3d58153ac694dd92a0abf - arm-trusted-firmware/plat/hisilicon/hikey/include/plat_macros.S 98509207554ab836b38f580d203793668061ce40 - arm-trusted-firmware/plat/hisilicon/hikey/include/hisi_sip_svc.h c54b714045ab12cfcff4363f00ce94952a40e2d6 - arm-trusted-firmware/plat/hisilicon/hikey/include/hikey_layout.h f4fe9f99f519b213b8d23015c37b2e4013ebb066 - arm-trusted-firmware/plat/hisilicon/hikey/aarch64/hikey_helpers.S f3431f5300aefc0065b1e6ad9f3e996878027bff - arm-trusted-firmware/plat/hisilicon/hikey/aarch64/hikey_common.c 524ab6d6a8a79e76857af71a8c36886929a16243 - arm-trusted-firmware/plat/rockchip/rk3288/plat_sip_calls.c 7d9851bfe1b3a6bff1b3fe3a5a42152bdbbdd641 - arm-trusted-firmware/plat/rockchip/rk3288/rk3288_def.h 53d9e3936b39e758560745d492d1473ac9c98278 - arm-trusted-firmware/plat/rockchip/rk3288/drivers/pmu/pmu.h db1ef060ee221e9b61acbb781c42ed42e926b26e - arm-trusted-firmware/plat/rockchip/rk3288/drivers/pmu/plat_pmu_macros.S bcf5a24d5d284bc2b87c3b5299a9f548df4bc95f - arm-trusted-firmware/plat/rockchip/rk3288/drivers/pmu/pmu.c 00a800ecdcad577d80ed2968cfee8abc2ff260d0 - arm-trusted-firmware/plat/rockchip/rk3288/drivers/soc/soc.h 408d92dc22d97bff7148a2338e91746328b4bb4f - arm-trusted-firmware/plat/rockchip/rk3288/drivers/soc/soc.c 70ecc34e2c4236edbd52a088d6dc72300d1038e0 - arm-trusted-firmware/plat/rockchip/rk3288/drivers/secure/secure.h 90e4b5914845f3238bde4617bcf04acabfc52406 - arm-trusted-firmware/plat/rockchip/rk3288/drivers/secure/secure.c 0454e2aefd623a64760090a825f3cb0c26b0a3ca - arm-trusted-firmware/plat/rockchip/rk3288/include/plat_sip_calls.h 58f0ccc10fae70932566781c7c34457a239e027c - arm-trusted-firmware/plat/rockchip/rk3288/include/plat_sp_min.ld.S 0a2a001f434d83ab306c453b6d60f886a0b59a96 - arm-trusted-firmware/plat/rockchip/rk3288/include/platform_def.h 1321792bce42c44c3fed91fea86cceca52486ffa - arm-trusted-firmware/plat/rockchip/rk3288/include/shared/bl32_param.h 524ab6d6a8a79e76857af71a8c36886929a16243 - arm-trusted-firmware/plat/rockchip/rk3368/plat_sip_calls.c 0b8ef1037611c38ba89966b1da4ef153e47b4fb4 - arm-trusted-firmware/plat/rockchip/rk3368/rk3368_def.h a4fe0b238351912e5a3b7e1de16ea4b470dbcfe0 - arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h 7a2d810a3f11780033972a9b1f3f2eb09adddfc5 - arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin edac1a959247a82db5f820097a9f8ded6c4665b4 - arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c 985e72c79b58499d32fbf6ef6f46a741c6356e9d - arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/pmu.h 0ea97dd2ed72ec48826e4668463b1067b1e3e91a - arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/plat_pmu_macros.S 859692a896bf24f76093c6cc1a923f3bd7f06c49 - arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/pmu.c cb622b7fdee1e5387ed783d371b6cfdd0400df92 - arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/soc.h 22974ca90d72fb96f260417ace863c692dad5cdc - arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/soc.c 0454e2aefd623a64760090a825f3cb0c26b0a3ca - arm-trusted-firmware/plat/rockchip/rk3368/include/plat_sip_calls.h 5817c26932930a69f20037fcfd33b6f700e518a0 - arm-trusted-firmware/plat/rockchip/rk3368/include/platform_def.h c03dbe37ab69ed71bbbc9100b47ff77d3c1f19e9 - arm-trusted-firmware/plat/rockchip/rk3368/include/plat.ld.S 85d08d7cf74717daed56a0770f3c79bca90280dc - arm-trusted-firmware/plat/rockchip/common/plat_pm.c 91be87581dcd25681be045b39eb7934ec59a6fa9 - arm-trusted-firmware/plat/rockchip/common/sp_min_plat_setup.c 3bb10820f3cac4793d72ccd0dbaa9513b9945d80 - arm-trusted-firmware/plat/rockchip/common/rockchip_gicv3.c 32f9de1c486103a42cf6a9d291f42989b42a98e4 - arm-trusted-firmware/plat/rockchip/common/plat_topology.c 4a1355d1645ef943a89aa54999041bd5a970c764 - arm-trusted-firmware/plat/rockchip/common/rockchip_stack_protector.c 2047ecc940bb80f5a0b484df48d3c24d285820e9 - arm-trusted-firmware/plat/rockchip/common/params_setup.c 9213c21ad6f4d071ef85303d7f16f295b02bc212 - arm-trusted-firmware/plat/rockchip/common/rockchip_gicv2.c 1f63c15382d48351f3d1c1709e7428545ce2cb72 - arm-trusted-firmware/plat/rockchip/common/rockchip_sip_svc.c d30876af46d1b3b1d2c18f43fa7894f8fda3c5f8 - arm-trusted-firmware/plat/rockchip/common/bl31_plat_setup.c 5c96dda447934109fef22dbfc20108fea56100fe - arm-trusted-firmware/plat/rockchip/common/drivers/parameter/ddr_parameter.c e40967392bea64496e752401f887b55eae946bf3 - arm-trusted-firmware/plat/rockchip/common/drivers/parameter/ddr_parameter.h 5b690165e56aee2f4e71841059154598362ce876 - arm-trusted-firmware/plat/rockchip/common/drivers/pmu/pmu_com.h 505eeb07bdc39ad3e19a4f6676774af764d3c300 - arm-trusted-firmware/plat/rockchip/common/aarch32/platform_common.c ba0fb41c4b6e827fc3092feb1e41d096daa7e77c - arm-trusted-firmware/plat/rockchip/common/aarch32/pmu_sram_cpus_on.S 63a3ba51a470fe12e6026880ee67d6de178f8590 - arm-trusted-firmware/plat/rockchip/common/aarch32/plat_helpers.S c08e0dba86277197d207590daf335b7a863f4f32 - arm-trusted-firmware/plat/rockchip/common/include/rockchip_sip_svc.h 5c6218088ea95aa4cdcffbabdfabcf2054405b9a - arm-trusted-firmware/plat/rockchip/common/include/plat_private.h e0b9109d2e15ba78290c67b35d231cc82990137e - arm-trusted-firmware/plat/rockchip/common/include/plat_params.h 2360baef8c09eed0a7d7ca2b2f97f9405c9bfd92 - arm-trusted-firmware/plat/rockchip/common/include/plat_macros.S 1b33ae60df43cf398d1a8b472866e811981ad1c4 - arm-trusted-firmware/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h 4db0b70aecaf5352c4deda76075a44c7ed772f91 - arm-trusted-firmware/plat/rockchip/common/pmusram/cpus_on_fixed_addr.S 47fca1d947e59a046afce81911f7f552c72c6ab5 - arm-trusted-firmware/plat/rockchip/common/aarch64/platform_common.c 258f177b9b9412883f714cff3406818288eca04f - arm-trusted-firmware/plat/rockchip/common/aarch64/pmu_sram_cpus_on.S aceb5792fbe22f18f421f2a754469db4f6f62cac - arm-trusted-firmware/plat/rockchip/common/aarch64/plat_helpers.S ef5a8ce281d95041b91f8f165ef782642d022de2 - arm-trusted-firmware/plat/rockchip/px30/px30_def.h 6fd13eff5a2d17a6f2e651b3eba6211a93d3522f - arm-trusted-firmware/plat/rockchip/px30/plat_sip_calls.c 6940e4242af969ec608caab6d93dd03364b78580 - arm-trusted-firmware/plat/rockchip/px30/drivers/pmu/pmu.h 4661321c301694bb1cfb029693c60d50387885d6 - arm-trusted-firmware/plat/rockchip/px30/drivers/pmu/plat_pmu_macros.S 338871ee4d601414cf6ab0c718cb19938c37c7b5 - arm-trusted-firmware/plat/rockchip/px30/drivers/pmu/pmu.c dbc0dd67905cb60b55ff82d4f1d8bf96a7ec2514 - arm-trusted-firmware/plat/rockchip/px30/drivers/soc/soc.h 288f8f52c9a5423576d1fd403f776da8e5906395 - arm-trusted-firmware/plat/rockchip/px30/drivers/soc/soc.c 7129bd0759914b2bdbe0af12743e79277b990a3d - arm-trusted-firmware/plat/rockchip/px30/drivers/secure/secure.h e5df7e7476f59e23d9c3c1097c64bad93fb273ca - arm-trusted-firmware/plat/rockchip/px30/drivers/secure/secure.c 4abb3f49d90cc7242ff9d366432f9423ed190c44 - arm-trusted-firmware/plat/rockchip/px30/include/plat_sip_calls.h 8b1c4b26a5cf109ec97a2bd711e46dc76c20891c - arm-trusted-firmware/plat/rockchip/px30/include/platform_def.h be822c3b60a3f8f4215925d9c6aa8ff3d90ab56b - arm-trusted-firmware/plat/rockchip/px30/include/plat.ld.S 80988c6b4c1d5c128f556b4704d2a13dca1b94ac - arm-trusted-firmware/plat/rockchip/rk3399/plat_sip_calls.c 07fcff2e4785739f2818730be2df2798395d6dd0 - arm-trusted-firmware/plat/rockchip/rk3399/rk3399_def.h fdf96b7b34ebbd88b6c053c20c493dfcd5d2eec6 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h 8080df60a96f3ccb59e64a8c4468c29298a40160 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c a203f9155033bc4a154799d63ebe669baadb7c82 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c 26f96f6bfc5d8cd2811341eaa144693019daa5cf - arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.h 4f34aa4fe829a116338b7c8cb363091b98b1df1c - arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S 21c19d18b927a98e453d2dd32fa075e1556c8d10 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c d6f6a92953b02dda92949d05699b4a8c09ec1ab6 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/soc.h f10fc723b4f781fa92f52d189e12ab2599f2be33 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/soc.c 91fa17de464bf17060f5d782d3addc2d250f2bcf - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dfs.h d4edbc276d8a41ceabeabd135ee44750077267fb - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h 455f3ca45423a7d3a17a25fa9a199ee6f33accdf - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/suspend.c 341cf7780e76c0eed9bb587ced84821148eaeba4 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c cc96ce897ce3dfd398d571f73d60df020e312a7f - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram.h 1a0ef7b5013eea98c8892cc73f9acf7aadc6542b - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram.c 8bb28c62f323cba1149703071fa6c9cd723e7681 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/suspend.h fde45271c5e9a03975a13a19aa58f7ce1627247b - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dfs.c 2f72933afb37b859ea9a98d233ab11f81301c9db - arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/Makefile 98a096aced18ab4c9a4b3ab325773ed273acd4cd - arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/include/addressmap.h 222366fd88fa37c34896b96be4724020febaf122 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h 249a2bba707f4aae60e76e4d2ca07180426f3657 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/stopwatch.c c651d2e10f915a285792aa7e66836e66a3fb3b68 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/startup.c 15ccafa1fb201c2bdc50eb32beb4d9331e95424b - arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/suspend.c 9cfa6b80558dac90724c830c7c2b792099232962 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld.S 3832f35bf0192ab6299ed6f72d97ea798c64ec01 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/dram.c 34cef331645617d77f27ee050065b2678b021605 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/secure/secure.h 12d0e498bcf7645b6d17eda0b6c88f9c68345720 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/secure/secure.c 8af098c906ff4222b7fb1b8a8e528a842931e11a - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dp/cdn_dp.c e4ba052fe71c1dbb0fd712a9e23751995fa17236 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dp/hdcp.bin 0e0164a1fd25ccd71404f643551fc197b6d3545f - arm-trusted-firmware/plat/rockchip/rk3399/drivers/dp/cdn_dp.h 1761d34cf2fa35e5eaf8e4707cde5f3fec7345ce - arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c 912b3ac53149ee0912cdc571503cbe6f5d9e5e31 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/pwm.h 81bb90565c30ebb1d2a2074e665099c5df4b3f16 - arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/pwm.c 0454e2aefd623a64760090a825f3cb0c26b0a3ca - arm-trusted-firmware/plat/rockchip/rk3399/include/plat_sip_calls.h 735db5fedc39c83875dd50d345431e840a75ce95 - arm-trusted-firmware/plat/rockchip/rk3399/include/addressmap.h d037385198294976c392eaac15722c2bc43171e6 - arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h 33691c33d59c3cbf5321efb5e9cf1ce6f908b1b3 - arm-trusted-firmware/plat/rockchip/rk3399/include/plat.ld.S f61d8134dfdbc2de01b130177e3623bfc96e582b - arm-trusted-firmware/plat/rockchip/rk3399/include/shared/dram_regs.h e27f9ab0eb7cc700bac4af81ef063675ddea3d16 - arm-trusted-firmware/plat/rockchip/rk3399/include/shared/pmu_regs.h dffb716056a5cfe4289bde5769bacd0a9c517467 - arm-trusted-firmware/plat/rockchip/rk3399/include/shared/bl31_param.h a3ec096942a7038a658d2de2da28c8d7772e2601 - arm-trusted-firmware/plat/rockchip/rk3399/include/shared/pmu_bits.h d3a8c566b07530d947493f642a829c2173e7eb3c - arm-trusted-firmware/plat/rockchip/rk3399/include/shared/addressmap_shared.h 37de06dae36b2c9133dfa3db58b9403eca97534e - arm-trusted-firmware/plat/rockchip/rk3399/include/shared/m0_param.h 514bb50a35bc277734414a501833d9cf9103b613 - arm-trusted-firmware/plat/rockchip/rk3399/include/shared/misc_regs.h 9eb41f0b086d93dd52f10cd88c871e9f872da485 - arm-trusted-firmware/plat/rockchip/rk3328/rk3328_def.h 75d3fb351c1418d28d1be951921dde7cac623d53 - arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/pmu.h 74e69a5d06c7c10f8fd04052bfd92c89a6b685c2 - arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/plat_pmu_macros.S d6fb6002e2f08bc736d1fbcfef5f7d518331e24a - arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/pmu.c 888b9ca7b2dca798b061df341269bb1bf0cdc6a2 - arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/soc.h aa37703bdb16d2d93c4cb6a1c3f5740f10400717 - arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/soc.c d0cf327dcd15f8fc85f2c3c93e82fd6199973f0b - arm-trusted-firmware/plat/rockchip/rk3328/include/platform_def.h c03dbe37ab69ed71bbbc9100b47ff77d3c1f19e9 - arm-trusted-firmware/plat/rockchip/rk3328/include/plat.ld.S d4e968db5e699bc36032dfe35d7fada27142c699 - arm-trusted-firmware/plat/imx/imx7/include/imx_hab_arch.h 1027e5173d316fd6d9dd6588b9666b53ed9d1116 - arm-trusted-firmware/plat/imx/imx7/include/imx_regs.h 10003f2e608d5073c076ab1a446f4ba07c06086d - arm-trusted-firmware/plat/imx/imx7/include/imx7_def.h 81ea2015e04bbc53b7d42589a21821a183fc1c8a - arm-trusted-firmware/plat/imx/imx7/common/imx7_bl2_el3_common.c bffe5bd7851f8d028c92d9d68dba7806be5bd662 - arm-trusted-firmware/plat/imx/imx7/common/imx7_image_load.c 3bba3282b340c9896990c2ffcbf10d5bfb0070b2 - arm-trusted-firmware/plat/imx/imx7/common/imx7_rotpk.S 7b5d73ec9d9c7e14fd48653c6e018d432654101d - arm-trusted-firmware/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c 8403135be33e11a4b696e90b5b253465b6838682 - arm-trusted-firmware/plat/imx/imx7/common/imx7_helpers.S 4d406209e8b278e9730968baee57f5106d424aef - arm-trusted-firmware/plat/imx/imx7/common/imx7_trusted_boot.c 1e1f92bc6f801c91fde3bbe4ce99b62beb0eb7d2 - arm-trusted-firmware/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c 42143dbacac34a118b7b86673774e843e7e84fd8 - arm-trusted-firmware/plat/imx/imx7/warp7/include/platform_def.h 1e876f487cd25f4a6cd08d0a21926f5405676a07 - arm-trusted-firmware/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c 1b13f9e313e75353b45d6528629485488b180345 - arm-trusted-firmware/plat/imx/imx7/picopi/include/platform_def.h 7bd8d4e39f1f3905630b08a16be851097fa5ab67 - arm-trusted-firmware/plat/imx/imx8m/imx_rdc.c d08ec11462c38ed056bd8ce300169c64d976b21d - arm-trusted-firmware/plat/imx/imx8m/imx8m_csu.c 6253f7542bd4e5a6244779068845d717f8eca3f6 - arm-trusted-firmware/plat/imx/imx8m/imx8m_measured_boot.c 20f064bee50b84b4f3ec957cd09aad9e647b84f1 - arm-trusted-firmware/plat/imx/imx8m/imx8m_psci_common.c 6db7c9804f412b76babb45883d6ae2cf83dbd139 - arm-trusted-firmware/plat/imx/imx8m/gpc_common.c 1ccbc8b82968361279d02b4c1cf10c91215a3e19 - arm-trusted-firmware/plat/imx/imx8m/imx8m_caam.c 10fb6753c1ece21522f45f372d0cbf3b416b5190 - arm-trusted-firmware/plat/imx/imx8m/imx_aipstz.c 27b7f5cd3416b96295c70624ef4970c56913b2dd - arm-trusted-firmware/plat/imx/imx8m/imx_hab.c 996e00079997c54373e5acb4a6f39bfe8cbe346e - arm-trusted-firmware/plat/imx/imx8m/imx8m_image_load.c e345520494aee2764cb14af7ae66ab0293c32ea8 - arm-trusted-firmware/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c b163641b5e9a43abd2579b2b6bfb9b0bc2160b6c - arm-trusted-firmware/plat/imx/imx8m/ddr/lpddr4_dvfs.c d4df8831fbb6c08572840739b41989da51232a80 - arm-trusted-firmware/plat/imx/imx8m/ddr/ddr4_dvfs.c 439ff0fd34804282a6c62a21bf3c37d6d6def362 - arm-trusted-firmware/plat/imx/imx8m/ddr/dram.c 138a9f0052b0bf51298edd4844ee390e9930d174 - arm-trusted-firmware/plat/imx/imx8m/ddr/dram_retention.c 1bba6b6b8117430fecdbc1fd53e0cc854e41705b - arm-trusted-firmware/plat/imx/imx8m/ddr/clock.c 0efee336c964d1973fec201980455aee08396081 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_trusted_boot.c 9a2fbd0bf6a37c0a14dc2fceacbca9de09cd6731 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c 169ab98f3d4cd7620ffef0d78f7c2329be9c1586 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_psci.c 4fe2987f9c2e076b0f22ddae51289cc8c0194a9e - arm-trusted-firmware/plat/imx/imx8m/imx8mp/gpc.c 97a556f1fc780240a2ad81127c295bd39a0c6512 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_rotpk.S be1935709a939c0480bc4cc27058482508f2596b - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_bl2_mem_params_desc.c 3d38c99169530f67aeba8526bd7cd4559981a349 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/imx8mp_bl2_el3_setup.c df0e3b50430ac47d2263ca8e0a4b83d46c8c0193 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/include/gpc_reg.h b3f6e6c8e01fe656ab452f5e739393958e63dc6e - arm-trusted-firmware/plat/imx/imx8m/imx8mp/include/imx_sec_def.h 48df7eeefd8913a2f04fac1fd8be28ba629dfa14 - arm-trusted-firmware/plat/imx/imx8m/imx8mp/include/platform_def.h c65d55a5e1a73f615b9fe213427e4605f4b3806c - arm-trusted-firmware/plat/imx/imx8m/imx8mp/include/imx8mp_private.h 4bc0eb69bf40f2ac07200a788f79ad6e9ec8b3f2 - arm-trusted-firmware/plat/imx/imx8m/include/imx8m_psci.h 5eac3f0d57b86e7c5a80ef9b695586701ae316cf - arm-trusted-firmware/plat/imx/imx8m/include/ddrc.h 47de7cdf356158f2b651bafb8659187db3a13e65 - arm-trusted-firmware/plat/imx/imx8m/include/imx8m_measured_boot.h e736eb11303455b8c0cbc82a8de2427020c2494a - arm-trusted-firmware/plat/imx/imx8m/include/imx_rdc.h a5788395393205a482a59b20966c9082905875b0 - arm-trusted-firmware/plat/imx/imx8m/include/dram.h 3bc736f072705dfa2d00383fe60d8497b3676fcc - arm-trusted-firmware/plat/imx/imx8m/include/imx8m_caam.h 5ec5413514abe79264b0bed81c75f811d2621d46 - arm-trusted-firmware/plat/imx/imx8m/include/imx_aipstz.h a2949dca5beb711e3ee904e2a31c8887df22bdc8 - arm-trusted-firmware/plat/imx/imx8m/include/imx8m_csu.h 8747c056d1b3007701d58eb1db52fde1db54a9b0 - arm-trusted-firmware/plat/imx/imx8m/include/gpc.h a2af87335b959f57d6de74f40740b48de27a802e - arm-trusted-firmware/plat/imx/imx8m/imx8mq/imx8mq_psci.c 423539360c2f1638f2f1606b67eabf4533b0acd4 - arm-trusted-firmware/plat/imx/imx8m/imx8mq/gpc.c 64914d9666ef5bb8c8063dd32aaf9fbc8f83703e - arm-trusted-firmware/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c d1fa70b45e2971a3e4103d0b2ff864ec706c5af5 - arm-trusted-firmware/plat/imx/imx8m/imx8mq/include/gpc_reg.h 6b72ec3d8edc7fc323fd768161812a0b5e5b7105 - arm-trusted-firmware/plat/imx/imx8m/imx8mq/include/imx_sec_def.h 33992acf1aa341055320009de8bd607d2ba2c8d7 - arm-trusted-firmware/plat/imx/imx8m/imx8mq/include/platform_def.h 060756d07ff95fa2e15ef2cab742c6f6fdfdc5e3 - arm-trusted-firmware/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S f9007785b7de40f327bd11a83c710c297b45e4ab - arm-trusted-firmware/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c ccad568808449da2db9bbf955065a017f9d4092c - arm-trusted-firmware/plat/imx/imx8m/imx8mm/gpc.c 3fcc366713e1667476479363fd2d0fb74144e491 - arm-trusted-firmware/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c 5e7971c14f77e2f2450badad4a156ca33a9eb89f - arm-trusted-firmware/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c 0e0933de6793e323f4c77e12a89455776a0dfe57 - arm-trusted-firmware/plat/imx/imx8m/imx8mm/imx8mm_psci.c 75a249b8b3a7fb6bbaa75ab69f98a6aa95e31d0c - arm-trusted-firmware/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c 4a704d5f5cc4958ad509fe9771d30d6632cb1a0a - arm-trusted-firmware/plat/imx/imx8m/imx8mm/include/gpc_reg.h 630860627b72fcc588880f6db00488e9e3493a24 - arm-trusted-firmware/plat/imx/imx8m/imx8mm/include/imx_sec_def.h fccec02276027ff921840bfbd9c5afef599192b5 - arm-trusted-firmware/plat/imx/imx8m/imx8mm/include/platform_def.h 0f9e1a9d6497a3ad4e415d483905f2ef16aaa423 - arm-trusted-firmware/plat/imx/imx8m/imx8mm/include/imx8mm_private.h e7ded5d1571dcf2246b5480dea7517bbc0e45a87 - arm-trusted-firmware/plat/imx/imx8m/imx8mn/imx8mn_psci.c 556bc132ee9c3d6e9c409ca686544b48a2be227b - arm-trusted-firmware/plat/imx/imx8m/imx8mn/gpc.c 8e8f859c9cf8ff904fb614ad296e664a23674041 - arm-trusted-firmware/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c 82259d3c2b7d974ad94a42c37f37e0a8f0ce576f - arm-trusted-firmware/plat/imx/imx8m/imx8mn/include/gpc_reg.h 3396e16e3b097202dc246e4cb3e23073ec5a0ea3 - arm-trusted-firmware/plat/imx/imx8m/imx8mn/include/imx_sec_def.h cb5e88c5d23518d2ea454fa4d9c3b5dcd64b2693 - arm-trusted-firmware/plat/imx/imx8m/imx8mn/include/platform_def.h 83187f1c90615deae51e2febc0506394e8d4d444 - arm-trusted-firmware/plat/imx/common/imx_sip_handler.c b26cdffd75a0ba04b4a312520443d0c77b388242 - arm-trusted-firmware/plat/imx/common/imx8_topology.c da4b81f475ec53f2578ba031cd1f30f759bc5dde - arm-trusted-firmware/plat/imx/common/imx_snvs.c 9026b30dd1244e0fa2416dac0e9f2b92c11bc83e - arm-trusted-firmware/plat/imx/common/lpuart_console.S c014188b6f4a48f9dc6d6fed678081f02f8d8e86 - arm-trusted-firmware/plat/imx/common/plat_imx8_gic.c 5225b741c941cba9f489d347aae2707d99896d7d - arm-trusted-firmware/plat/imx/common/imx_csu.c e7ef15bdf83a7d4e3ca78dd0d0e9daf56414e55e - arm-trusted-firmware/plat/imx/common/imx_caam.c 03ff82e03dc9eb60e02c6e23f0c199fdd1753c9c - arm-trusted-firmware/plat/imx/common/imx_aips.c d93d2cf3c9aafc65833374f51376f03bc2387ecd - arm-trusted-firmware/plat/imx/common/imx_uart_console.S 6ac985911e7e26d13c75d48a04457fbcb209b62f - arm-trusted-firmware/plat/imx/common/imx_sdei.c 97029bcef11b7a8598834c9717cec7a5655b895a - arm-trusted-firmware/plat/imx/common/imx8_helpers.S ac923dd7af0d3485eceae86115ea73150575ac4f - arm-trusted-firmware/plat/imx/common/imx_wdog.c 561b0822ac98206dceac588b536d745fc70829d9 - arm-trusted-firmware/plat/imx/common/imx_ehf.c ad339798ed1c81b2dfda72cc1cefaae7acb622d9 - arm-trusted-firmware/plat/imx/common/imx_io_storage.c f30799014ffd50a32b0d021473b50cf5c4a28634 - arm-trusted-firmware/plat/imx/common/imx_clock.c 1901b0c4a5e19926a9e1b5ae437ebbeb0dc0d181 - arm-trusted-firmware/plat/imx/common/imx7_clock.c e03b60801f58711597b0bb457ecf6e3e84c9f44e - arm-trusted-firmware/plat/imx/common/imx8_psci.c 1b219401b9b5eb5bd8c83fa92fc68c591d48a3da - arm-trusted-firmware/plat/imx/common/imx_io_mux.c 8e4f08d6803ac3e0274858a4408149fd675066d8 - arm-trusted-firmware/plat/imx/common/imx_sip_svc.c 8c98c79db7801610b0bf01e1ea680ec8347be4f2 - arm-trusted-firmware/plat/imx/common/sci/ipc.c f2ab11050d68bdc711e7c18f9437fba728ab77bb - arm-trusted-firmware/plat/imx/common/sci/imx8_mu.h 985fca791927ad8088399ab8840bcbcfb8277a6e - arm-trusted-firmware/plat/imx/common/sci/imx8_mu.c 3f381087336a847b53323f6828aa61478b46a2cc - arm-trusted-firmware/plat/imx/common/sci/svc/timer/sci_timer_rpc.h 30cf1dfdd48ef57921bbd93789aaedbebd754c55 - arm-trusted-firmware/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c fdc0fc24ee38df2fd92f2f039664af39724513e7 - arm-trusted-firmware/plat/imx/common/sci/svc/rm/rm_rpc_clnt.c 9162637c3ad8ef97f19a264c504c58d5886f9d7c - arm-trusted-firmware/plat/imx/common/sci/svc/rm/sci_rm_rpc.h ada89ab08a1bfb90ad5b0e5ffb325268ddbc837e - arm-trusted-firmware/plat/imx/common/sci/svc/pm/pm_rpc_clnt.c 99d10095088dddbbe81826dbf7827bdc9c6bffb8 - arm-trusted-firmware/plat/imx/common/sci/svc/pm/sci_pm_rpc.h a593348ba8dcf5a3577bb48cd9d9ab7fe88c6df7 - arm-trusted-firmware/plat/imx/common/sci/svc/pad/pad_rpc_clnt.c 53b961e268ec00956cf3635d8561601e5c5bf70b - arm-trusted-firmware/plat/imx/common/sci/svc/pad/sci_pad_rpc.h 1dc0e610322825b6f58ac08670b99a4598bc01f1 - arm-trusted-firmware/plat/imx/common/sci/svc/misc/sci_misc_rpc.h 65f1e12aab1c7815ccb98973525d32d30e635a1d - arm-trusted-firmware/plat/imx/common/sci/svc/misc/misc_rpc_clnt.c 8169135849017c45a81b2c0447e940e3e5396145 - arm-trusted-firmware/plat/imx/common/aarch32/imx_uart_console.S b9d688fac07189d434ac636324a632e9bf78825c - arm-trusted-firmware/plat/imx/common/include/imx_clock.h bddfe7c6dc079e9f45c4a41601888d27f5d29c48 - arm-trusted-firmware/plat/imx/common/include/imx_csu.h 24f8d34fd7865c2235d12e87791c7ae77d55d281 - arm-trusted-firmware/plat/imx/common/include/imx_io_mux.h 816bfc02478ff083b5f3557753a4d0d4f2f32c9e - arm-trusted-firmware/plat/imx/common/include/imx8_lpuart.h 8830c18819f942388c5badcb2c19eaea2ae058dd - arm-trusted-firmware/plat/imx/common/include/imx_caam.h a5fcaffa0e69f234b0620f32d3556bf79ace50f1 - arm-trusted-firmware/plat/imx/common/include/imx8_iomux.h 0b633d6b19c3fd7cb43c433d74b84ede423bab4f - arm-trusted-firmware/plat/imx/common/include/imx_hab.h 28b31b74552131c2ba5875fb7db44b22ca16b722 - arm-trusted-firmware/plat/imx/common/include/imx8qx_pads.h a3a14f38cbc846da3bc2498cf8e07b62479aa62a - arm-trusted-firmware/plat/imx/common/include/imx_snvs.h f5724b26de0d68b4b37e1d580c6e30842eacd6c0 - arm-trusted-firmware/plat/imx/common/include/plat_imx8.h 8ae002187ace1e1358c7af1e06ef7957179939f5 - arm-trusted-firmware/plat/imx/common/include/plat_macros.S 36d5f07566aad340b6ec06b01cfbe631023ca7f5 - arm-trusted-firmware/plat/imx/common/include/imx_wdog.h 2e84528c7d6b12beb2c64505a14d73bcfb03ef87 - arm-trusted-firmware/plat/imx/common/include/imx_aips.h e7321f13995ca121a697a5c20da4d3819b0949e5 - arm-trusted-firmware/plat/imx/common/include/imx_sip_svc.h 6f89a14dc12ddacabad367a7e69d8bf469274ec4 - arm-trusted-firmware/plat/imx/common/include/imx_uart.h 1d847530cd83143e4a50b94c5499ee8c11f9d3e1 - arm-trusted-firmware/plat/imx/common/include/imx8qm_pads.h 19674e70669fa3f7fb7e509377e445f7fd4c7be4 - arm-trusted-firmware/plat/imx/common/include/sci/sci.h cc9366b07e946d7946bdfeae628f8a6c7ac3bed3 - arm-trusted-firmware/plat/imx/common/include/sci/sci_ipc.h daeb14deb7c4f498330bb44186346cd1ac4eef92 - arm-trusted-firmware/plat/imx/common/include/sci/sci_types.h 8a65436d5e0b335e9003a30f2da5f7892d23dc05 - arm-trusted-firmware/plat/imx/common/include/sci/sci_scfw.h f6e6cd4d5b145f5abd0aa4d840fd7757d4b02c04 - arm-trusted-firmware/plat/imx/common/include/sci/sci_rpc.h 2507eeb7a0cd662322ea96553146f0f0dc8c6e45 - arm-trusted-firmware/plat/imx/common/include/sci/svc/timer/sci_timer_api.h 70210ef96ff1f0ccd4e790bb79a148f1bf02efcc - arm-trusted-firmware/plat/imx/common/include/sci/svc/rm/sci_rm_api.h d3b138328cc81b7fe0a830b3cec8bd87f7d62835 - arm-trusted-firmware/plat/imx/common/include/sci/svc/pm/sci_pm_api.h 4be7f4400810802474258ed3e4b8f7a73170db33 - arm-trusted-firmware/plat/imx/common/include/sci/svc/pad/sci_pad_api.h cf9e73e1a62f99ecb17abeeda5efbdad0f7b1c21 - arm-trusted-firmware/plat/imx/common/include/sci/svc/misc/sci_misc_api.h 70b424f89fe607f915cf904aa5cad38d0436c662 - arm-trusted-firmware/plat/imx/imx8qm/imx8qm_bl31_setup.c 08a0687e7c3b77de90198dc7e5d8ca2ec448ae90 - arm-trusted-firmware/plat/imx/imx8qm/imx8qm_psci.c 6beb54a392291f2d54d207842b2620c7c344af8e - arm-trusted-firmware/plat/imx/imx8qm/include/sec_rsrc.h 1fdf9dd0a1e00cee360596ce35842f77598cbf1e - arm-trusted-firmware/plat/imx/imx8qm/include/platform_def.h b9316c7a608b29b530aaf325e401e06f62647525 - arm-trusted-firmware/plat/imx/imx8qx/imx8qx_psci.c e7eb3b5579a7d3d715c929b447affb833b3fd404 - arm-trusted-firmware/plat/imx/imx8qx/imx8qx_bl31_setup.c 06458d5a3b748df586e9ba2064614354842c162f - arm-trusted-firmware/plat/imx/imx8qx/include/sec_rsrc.h 5f45eb6e98ea9c90548afd5ee153f8d14c105e48 - arm-trusted-firmware/plat/imx/imx8qx/include/platform_def.h 5ef0dab419f42df9935d7fbc4e30baa8ea83d75e - arm-trusted-firmware/bl32/sp_min/wa_cve_2017_5715_bpiall.S 68e3f9565c5bf338271a1445ca22507fb2afc5af - arm-trusted-firmware/bl32/sp_min/wa_cve_2017_5715_icache_inv.S b224dca2e5ea95c46e1062767709b1bb1d7d766c - arm-trusted-firmware/bl32/sp_min/sp_min.ld.S 333a280c5264ca6c42b06d977d15e2fd4809f2d9 - arm-trusted-firmware/bl32/sp_min/sp_min_main.c abbd0cb6ee3ce9ca8584fa872468754316b868ce - arm-trusted-firmware/bl32/sp_min/sp_min_private.h 67b3173fdfcebee2caa8efff9eeb6bb5d2a31299 - arm-trusted-firmware/bl32/sp_min/aarch32/entrypoint.S 55d638eb236613c3acf5bfe7e1cedf8377db19c6 - arm-trusted-firmware/bl32/tsp/tsp_main.c 3301ad439bae604f492e996029e4a4cacf75fdc3 - arm-trusted-firmware/bl32/tsp/ffa_helpers.h bf48b15b9f75300c1f11366746538bd62a99a5ef - arm-trusted-firmware/bl32/tsp/tsp.ld.S ce18ee377caddd4c98c7c5cda7301f82d9dd2bd8 - arm-trusted-firmware/bl32/tsp/tsp_ffa_main.c 9f6902c275e597242e2fd0fd5632c2a20877b08c - arm-trusted-firmware/bl32/tsp/tsp_common.c 4e781569b56307f905581fbcfcd902ea8fa66b17 - arm-trusted-firmware/bl32/tsp/ffa_helpers.c 6727eccb78b649034342ffa087bb189e40734608 - arm-trusted-firmware/bl32/tsp/tsp_timer.c 9e87e30c75c48b862081fb04c17a8bfa6846ce77 - arm-trusted-firmware/bl32/tsp/tsp_interrupt.c cff876b0d1c0c61c7c0bf3c11d01e5dd636e357a - arm-trusted-firmware/bl32/tsp/tsp_private.h e94cc0b80bb21c55fc68026d8a981988414ab611 - arm-trusted-firmware/bl32/tsp/aarch64/tsp_exceptions.S 8d77cc1453037a319f4a5da2e5b77b37bb406277 - arm-trusted-firmware/bl32/tsp/aarch64/tsp_request.S 8899af4cf35b59bed20e51e7d3fc8d6f684ceded - arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S 2e63b0dd99041f913d992fc557f39d47f05937cc - arm-trusted-firmware/lib/coreboot/coreboot_table.c 68ae2dc18c0d7057681cee07cdfded26ef8fde36 - arm-trusted-firmware/lib/psci/psci_on.c 17d3cd14512874d1a8570b1b17b8c883744a6113 - arm-trusted-firmware/lib/psci/psci_main.c 829a7e8232b3efde8c6ad84aff7745c16582da77 - arm-trusted-firmware/lib/psci/psci_system_off.c 59e17378e4e23063ec4aff36f4f343437548b91c - arm-trusted-firmware/lib/psci/psci_suspend.c 70484461d77679b66812b09dd8b56cb0c17acaf9 - arm-trusted-firmware/lib/psci/psci_mem_protect.c 741cb1ca4722a4062052f5ec8cbb9d6f1d4ee468 - arm-trusted-firmware/lib/psci/psci_setup.c e119abbeaf1562a7ae5a66bdeaf8a29270c4cff4 - arm-trusted-firmware/lib/psci/psci_off.c 1e867e5b0fc7b461b5764519cc0d85973df6b5e5 - arm-trusted-firmware/lib/psci/psci_private.h 490e1ae91038753f30a42e4c48908a8f3a41c7c6 - arm-trusted-firmware/lib/psci/psci_common.c 96cf95201b14289b9fd8994f635436bd603c2e2c - arm-trusted-firmware/lib/psci/psci_stat.c e3019770bfa11512ec7d2d6785e37d28c72cd2c9 - arm-trusted-firmware/lib/psci/aarch32/psci_helpers.S 2c7b752ae78666bc171dbc6858abbe2c9cff4013 - arm-trusted-firmware/lib/psci/aarch64/psci_helpers.S c3816ecbb18ec120734f1bea8e79ea2ce6e4f631 - arm-trusted-firmware/lib/xlat_tables_v2/xlat_tables_core.c c56014f913bcddf7eb4618bc48a2d7e188df93e8 - arm-trusted-firmware/lib/xlat_tables_v2/xlat_tables_utils.c eaf23114b5279a2e5177c2d4a103265159f839d9 - arm-trusted-firmware/lib/xlat_tables_v2/xlat_tables_private.h 499b3843cd918ded79d9b4067c70be77235a831e - arm-trusted-firmware/lib/xlat_tables_v2/xlat_tables_context.c ade75a712dde9020d79686a61994595c14f73163 - arm-trusted-firmware/lib/xlat_tables_v2/aarch32/enable_mmu.S 990536d736898528cf4565171fb83f57604dd3d8 - arm-trusted-firmware/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c 21604c58893e3fda032bac4d88417fff189d89ca - arm-trusted-firmware/lib/xlat_tables_v2/aarch64/enable_mmu.S 48fbcd0295e7c9d2581d235e6c80eced4a10a422 - arm-trusted-firmware/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c 762fd5c3cfedb51fbb599859ca157f4a1275dbe1 - arm-trusted-firmware/lib/fconf/fconf_dyn_cfg_getter.c fd4c5030299c6c43d7dcde650254301c4a185c84 - arm-trusted-firmware/lib/fconf/fconf.c 06052beb76737879a3430c42f32068e7630ce940 - arm-trusted-firmware/lib/fconf/fconf_cot_getter.c 3567bc768ff2f143e4933244eb221b010bd91f80 - arm-trusted-firmware/lib/fconf/fconf_amu_getter.c 18fdfde595d6c7a6409f3d91382d81f736bf775d - arm-trusted-firmware/lib/fconf/fconf_mpmm_getter.c 9ad7e79093e5a9eee5c2b34fbfcef507564686b9 - arm-trusted-firmware/lib/fconf/fconf_tbbr_getter.c d2dc4f22a3f4d18e90f3c200fc9236e910900b67 - arm-trusted-firmware/lib/libfdt/fdt_rw.c 71e3b9e723c948c08594cfa38c65a708d0ab7f88 - arm-trusted-firmware/lib/libfdt/fdt_sw.c ea823073be5d673a06dfad272a7582df4482b150 - arm-trusted-firmware/lib/libfdt/fdt_ro.c fdf423cffe52c2e918c815f60c8bea0d7f7c8d70 - arm-trusted-firmware/lib/libfdt/fdt_overlay.c 1888e43d0d65ec169628a14ff94eb9d06adb47b2 - arm-trusted-firmware/lib/libfdt/fdt_strerror.c e01b7a0052b837a4650f2c9ac75ad38c40edc583 - arm-trusted-firmware/lib/libfdt/fdt_empty_tree.c a9e7388adeea4bb813155c62caacc545e9e98bfc - arm-trusted-firmware/lib/libfdt/libfdt_internal.h 938e224bf813570bb74a023ddca3a0c2652fa053 - arm-trusted-firmware/lib/libfdt/fdt.c 282524cbc0a8f7d16c36b9954bb4fad4c0d76c0a - arm-trusted-firmware/lib/libfdt/fdt_addresses.c c16e3571ab87b0ea9f8067989a5b0f97251ff8cb - arm-trusted-firmware/lib/libfdt/fdt_wip.c 14efe65532640ad904e16c0fcfdf2a0aa8ef7892 - arm-trusted-firmware/lib/aarch32/cache_helpers.S 00169552baea8da03759257b44162edf097abcd0 - arm-trusted-firmware/lib/aarch32/arm32_aeabi_divmod.c 50b2fea23411834a7cdb5cb61cc8559bcfd872b1 - arm-trusted-firmware/lib/aarch32/armclang_printf.S c975d8abfe42e48d68e0e592ba3989ae3f7f0853 - arm-trusted-firmware/lib/aarch32/arm32_aeabi_divmod_a32.S 8a00fe14195497b3dfb4323af7775b79c89a645c - arm-trusted-firmware/lib/aarch32/misc_helpers.S ccbf0a74a73d6eb9563cb282272e41c9decadde5 - arm-trusted-firmware/lib/el3_runtime/cpu_data_array.c c695b34410d51831efce05bb15a4684addbab078 - arm-trusted-firmware/lib/el3_runtime/aarch32/context_mgmt.c c16b6a90e04aa66123dde223fa202f33ab70aa51 - arm-trusted-firmware/lib/el3_runtime/aarch32/cpu_data.S e7b6438f14de0b60459f65a916240cab0cc8887d - arm-trusted-firmware/lib/el3_runtime/aarch64/context.S c09dfdc2088c652c6ec53661a85ac5541a85ac4d - arm-trusted-firmware/lib/el3_runtime/aarch64/context_mgmt.c a748c18c9c1bed5bfa7ad7bc2d42f1241b4eeb59 - arm-trusted-firmware/lib/el3_runtime/aarch64/cpu_data.S 35242ceafb8e7c1ac58158cde6672b601b1a88f9 - arm-trusted-firmware/lib/mpmm/mpmm.c 7c85c537adcb24f5e03d6c71424a2618815086e3 - arm-trusted-firmware/lib/debugfs/devc.c 758f3be3354709a4f69ee89cacf0db10dd68c75c - arm-trusted-firmware/lib/debugfs/debugfs_smc.c 5260672b27f35a4368d3be1f6ee66ec91d4beb26 - arm-trusted-firmware/lib/debugfs/dev.h db9f0e301c7178c315a1c6e72358bae572ce85db - arm-trusted-firmware/lib/debugfs/devfip.c 8102f862edb5ab07783993999c8781385e261628 - arm-trusted-firmware/lib/debugfs/dev.c 78982645d4d3008984c9307ee68bfa8eeb1a43a7 - arm-trusted-firmware/lib/debugfs/blobs.h 9802d55cbbaff09010b37afad6d494d8e755eae2 - arm-trusted-firmware/lib/debugfs/devroot.c 57633f55f011eec32b09f4867a18db8725ad24d4 - arm-trusted-firmware/lib/xlat_tables/xlat_tables_common.c 489fa8c2a31654d4ab05e281acbabb0f8a64608d - arm-trusted-firmware/lib/xlat_tables/xlat_tables_private.h 08dd595ae97e585c165a02faaeecbc5c0615ecca - arm-trusted-firmware/lib/xlat_tables/aarch32/nonlpae_tables.c bb710f3b156b87d08faaffa4bfdb60074c5bf5b0 - arm-trusted-firmware/lib/xlat_tables/aarch32/xlat_tables.c 83fd34388e89c93efcad1998551854558c28ad99 - arm-trusted-firmware/lib/xlat_tables/aarch64/xlat_tables.c 655c16e59bc70c4782c58f76a458853aeb35f2f1 - arm-trusted-firmware/lib/xlat_mpu/xlat_mpu_utils.c 6d8e14259a3bddae74927623e68b6e95a578b3a2 - arm-trusted-firmware/lib/xlat_mpu/xlat_mpu_private.h c8e552a0ec8c6fbc0008de98e8cc7e6ac08f1980 - arm-trusted-firmware/lib/xlat_mpu/xlat_mpu_context.c 3da3d4c987ce40660bb10580236ee870f603a567 - arm-trusted-firmware/lib/xlat_mpu/xlat_mpu_core.c 250ce42c1d1df6103d9a7eb84f739a52570e85c9 - arm-trusted-firmware/lib/xlat_mpu/aarch64/xlat_mpu_arch.c 97a06786c9d53286c3d0d861d9e6578551650e5e - arm-trusted-firmware/lib/xlat_mpu/aarch64/enable_mpu.S e42771f220b36b73f9c39aae94929b0df7ef1e99 - arm-trusted-firmware/lib/semihosting/semihosting.c bed75bc5da772504027fb7c033a1c918acc82c48 - arm-trusted-firmware/lib/semihosting/aarch32/semihosting_call.S 79d2f0e3c6477c7632a9d7b9d01b42625bf0cbb3 - arm-trusted-firmware/lib/semihosting/aarch64/semihosting_call.S bc8857833413ad776fefee7b3a4fe3ad74c7cd04 - arm-trusted-firmware/lib/romlib/gen_combined_bl1_romlib.sh a9efa4120656b54bbfaf91befd1a82dafb8640a0 - arm-trusted-firmware/lib/romlib/romlib_generator.py 0b4fe827956659566fa763cd1b1e15b1cdb505b6 - arm-trusted-firmware/lib/romlib/jmptbl.i 3a7bca01cf9d3b67b9d93fec625c4591ad106379 - arm-trusted-firmware/lib/romlib/Makefile 1a7d8adbdd571058f2d7cdf2dad5d51e735dfe8d - arm-trusted-firmware/lib/romlib/romlib.ld.S aca0167af243d551e7068e10251ccc62e1b800ea - arm-trusted-firmware/lib/romlib/init.s 5c8a013e889e7653f0cbff1346cd13128ff2fd69 - arm-trusted-firmware/lib/romlib/templates/wrapper.S 91d0e6f060cd659ba73d0db8886497a823814c65 - arm-trusted-firmware/lib/romlib/templates/jmptbl_entry_reserved_bti.S fa26b89e848f7affd6fd3be71153b55961fbf971 - arm-trusted-firmware/lib/romlib/templates/jmptbl_glob_var.S e0406a34add19465d2ace2d60bc6c5048bf0a9ff - arm-trusted-firmware/lib/romlib/templates/wrapper_bti.S f9c9050fd5c89b246d718f406a9d9a13f3388a5e - arm-trusted-firmware/lib/romlib/templates/jmptbl_entry_reserved.S b022feb15f3e84d4eefd318657af38a3a523e363 - arm-trusted-firmware/lib/romlib/templates/jmptbl_entry_function_bti.S 8bd9f16af17fc4a81e921654d50217d6ba334d4f - arm-trusted-firmware/lib/romlib/templates/jmptbl_header.S 56fc8c8a2950a0303783ced6bd0e388176043a47 - arm-trusted-firmware/lib/romlib/templates/jmptbl_entry_function.S 3c63f678cd78b3c4c10b6d13ffb32f245deb8ef6 - arm-trusted-firmware/lib/stack_protector/stack_protector.c c50c9ce39f46bbbfebd47c8645445585727f5b7d - arm-trusted-firmware/lib/stack_protector/aarch32/asm_stack_protector.S 7c77f07a1d4fda36a4af38ed18da2e22607b53e9 - arm-trusted-firmware/lib/stack_protector/aarch64/asm_stack_protector.S 6a483cdcf59e571fb3de6dc286c76b1419d8ab3b - arm-trusted-firmware/lib/psa/delegated_attestation.c 3e69f530713e4fc85a31fb6899bc0383b8fbe844 - arm-trusted-firmware/lib/psa/measured_boot_private.h c102b9d66a03f201f0eb156a0abbb18286c273b6 - arm-trusted-firmware/lib/psa/measured_boot.c ecb8e335fe4a2681e714ea9d5c5f2b8f5e1a8e07 - arm-trusted-firmware/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c ba76ca96162e88bc6bc13591b4dbe2d955320a45 - arm-trusted-firmware/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c 8ba45af3c4e396b6e2abeb7e839f0c7b9be45ed5 - arm-trusted-firmware/lib/extensions/sve/sve.c 5ccbd178b5c5eb953d97ca519229837a0537e821 - arm-trusted-firmware/lib/extensions/trf/aarch32/trf.c e3dc484cb8d981ceb0cdc03a7bdb8f24e2f9ae85 - arm-trusted-firmware/lib/extensions/trf/aarch64/trf.c afd6141e2e07c1fd692c8e845ce6e65899fbbb7d - arm-trusted-firmware/lib/extensions/amu/amu_private.h 21d2bec3b0a822561dc68c9dab32b97d35ea848a - arm-trusted-firmware/lib/extensions/amu/aarch32/amu.c 3dbb067dc92b40dd63f5ee3b50d0e88978e7e528 - arm-trusted-firmware/lib/extensions/amu/aarch32/amu_helpers.S 06332e25b6cb419fa11e991ca5790c705039b896 - arm-trusted-firmware/lib/extensions/amu/aarch64/amu.c 7f3f609a1bb0c4b5287f43cd817a535c4e497353 - arm-trusted-firmware/lib/extensions/amu/aarch64/amu_helpers.S aee505d9d1071c6c819d07bc02c1e963cf8c6025 - arm-trusted-firmware/lib/extensions/mtpmu/aarch32/mtpmu.S 1e8ea4b9d81a41c874fd1c0e7b3915a5337cf966 - arm-trusted-firmware/lib/extensions/mtpmu/aarch64/mtpmu.S 4125c51fd3f075d4d291f56b53175ca0683e12eb - arm-trusted-firmware/lib/extensions/spe/spe.c 20d0c78eb348c8af3b08c93b390276fee89b8b76 - arm-trusted-firmware/lib/extensions/sme/sme.c 0acc9bd09ec3324b57eb2ce0028d74f6d6ccf06f - arm-trusted-firmware/lib/extensions/mpam/mpam.c d4300647e97df26ef23b17d8fb3cc7ae615e328e - arm-trusted-firmware/lib/extensions/trbe/trbe.c 89127b3a5db7c0a3311d57870814e016ea42869a - arm-trusted-firmware/lib/extensions/brbe/brbe.c ebe5066f50de32f019ea11419b6ef11da4604812 - arm-trusted-firmware/lib/extensions/pauth/pauth_helpers.S 9b56d2cedbd5417e75959a7c83b6361dc3c48f6e - arm-trusted-firmware/lib/extensions/ras/std_err_record.c 785751601e97ed8f6b006cbe5a6e26dac81addf3 - arm-trusted-firmware/lib/extensions/ras/ras_common.c 0a99e4e59337ea7c2c2fe6dd428552019fc1f053 - arm-trusted-firmware/lib/libc/memset.c e68d6a0053ae9810517f220d26386a2ae6290766 - arm-trusted-firmware/lib/libc/exit.c 06782e2bb8b5e2b70cd089f061be9c1a08621523 - arm-trusted-firmware/lib/libc/memrchr.c a13fb76d1efd1532d6265ca7e3753be123c5fbef - arm-trusted-firmware/lib/libc/strnlen.c 44c32455e06c8ee38e1d4774fa8f70de1d9e3f00 - arm-trusted-firmware/lib/libc/memcmp.c 6867746f3c7df568cb9fa92aacfdceb641c951f1 - arm-trusted-firmware/lib/libc/putchar.c 315e4d792f50e1a2f37ec14616fb2aaeaa866ae8 - arm-trusted-firmware/lib/libc/strncmp.c e99c723c3292973758d597558fd929976df82eff - arm-trusted-firmware/lib/libc/strlen.c 0e11c2ba3c9318cdcc4c28e3e3663337046128b8 - arm-trusted-firmware/lib/libc/memchr.c 045917a873ae9e6ad3f96e3d127eb474b0f0baf9 - arm-trusted-firmware/lib/libc/puts.c 1a98830ccfe805a879a87ff7eb90306cb197e72d - arm-trusted-firmware/lib/libc/strcmp.c e7eb31dbd9893d98f8ab6cbef6a11143aa052581 - arm-trusted-firmware/lib/libc/strtok.c 41bef2adfe6410e3512e7f63f500c8f0cf5a4434 - arm-trusted-firmware/lib/libc/snprintf.c 8c9668a348c3ffbe4509aa2246941450a7b0de00 - arm-trusted-firmware/lib/libc/strtoll.c 2e041624618747b95a70ac92007814f04d42907c - arm-trusted-firmware/lib/libc/strchr.c f5fe2af7f4f0cad25866aa2422d946f47a11943e - arm-trusted-firmware/lib/libc/abort.c 71dcdebcd271206fe31508ddb0899748c542e285 - arm-trusted-firmware/lib/libc/assert.c be9487ae2df331c4b6d1e8eb831fe36f80300829 - arm-trusted-firmware/lib/libc/strlcpy.c 82032c79de7b24a84341c8bd5d72baba75337f1e - arm-trusted-firmware/lib/libc/strtoull.c 07dbfb512cae53c03504d60ec4b02bfc74c2af8a - arm-trusted-firmware/lib/libc/strtol.c 6d62f8972d334e9b7016abfa5fd60039fd045392 - arm-trusted-firmware/lib/libc/strlcat.c cf851bb6ce469797f295f4789ce50110b175893f - arm-trusted-firmware/lib/libc/memcpy.c a1876df5c0fef0a62bc57d6a13bab2234ad7b1ea - arm-trusted-firmware/lib/libc/memmove.c 27418446d5790356d6ad6fc8d277417e1a8cd167 - arm-trusted-firmware/lib/libc/printf.c c72f1f1842a78fb427805c7447d370fc148dc89f - arm-trusted-firmware/lib/libc/strtoul.c c64e54b9d37e79c6a5ddf5440518980b4d8023d6 - arm-trusted-firmware/lib/libc/strrchr.c 75786d0b78f57474b1c6f960b2c8ecbc07ba830b - arm-trusted-firmware/lib/libc/aarch32/memset.S 02977fbcda3d55ed39cafa721d2bd2a901f0c637 - arm-trusted-firmware/lib/libc/aarch64/memset.S fd7697000146d99611e6aaf57e0f3856602daf6b - arm-trusted-firmware/lib/libc/aarch64/setjmp.S dfe9d1459f2afc808df76389971581e7cd156c05 - arm-trusted-firmware/lib/compiler-rt/LICENSE.TXT f52a708d75b9d9c60122419e55b239506faf48d0 - arm-trusted-firmware/lib/compiler-rt/builtins/int_math.h 000625b949a613a9817001876b01107b0bc9bf0b - arm-trusted-firmware/lib/compiler-rt/builtins/int_types.h 1ce7c11507532414c0328c081b09944fedebad24 - arm-trusted-firmware/lib/compiler-rt/builtins/int_endianness.h 4f48352a7f48fd9c24a1614ee50cbdfa563ef3de - arm-trusted-firmware/lib/compiler-rt/builtins/assembly.h f07542388c57814e54f0c96a951e2ef2bbe405d9 - arm-trusted-firmware/lib/compiler-rt/builtins/ctzdi2.c 2825c4fe3f2bde2399e20fa3077233f1f8450429 - arm-trusted-firmware/lib/compiler-rt/builtins/divmoddi4.c ca5ea990905079d8c53e6e335f64ee671ba845b3 - arm-trusted-firmware/lib/compiler-rt/builtins/int_div_impl.inc b6be19539d8655496dc24041788f2230aae64b8a - arm-trusted-firmware/lib/compiler-rt/builtins/popcountdi2.c 43ef4b5dd652db346a1d160c3bca2884964f8891 - arm-trusted-firmware/lib/compiler-rt/builtins/popcountsi2.c 7d685a1dc442b6d30876e3e6d1b4100fc45224bd - arm-trusted-firmware/lib/compiler-rt/builtins/int_lib.h ff2207836a40606df69ec1e611e158aa0ed14f04 - arm-trusted-firmware/lib/compiler-rt/builtins/lshrdi3.c 73ea5b88f90e306be69dd8ecb81f834d49c9160e - arm-trusted-firmware/lib/compiler-rt/builtins/divdi3.c 34b18e6e0c6ebd07cb7fa4cadd2b07a0e7084147 - arm-trusted-firmware/lib/compiler-rt/builtins/udivmoddi4.c 277a460ac9c4747b9da6d700bbf4ca70f7bd8412 - arm-trusted-firmware/lib/compiler-rt/builtins/int_util.h c45f0973450713a6714be330fb6ea8345d666b07 - arm-trusted-firmware/lib/compiler-rt/builtins/arm/aeabi_ldivmod.S 4906ba0646aef187813f1fa743316b986052234d - arm-trusted-firmware/lib/compiler-rt/builtins/arm/aeabi_uldivmod.S 872cb517e7f08860b62b6224c1d79ddb1912c998 - arm-trusted-firmware/lib/compiler-rt/builtins/arm/aeabi_memcpy.S edbe27a26695b90b039ea42ae87e3756c047631a - arm-trusted-firmware/lib/gpt_rme/gpt_rme_private.h fc4f96e3d58ed8dc410c78f987292e3aeb3a2e1f - arm-trusted-firmware/lib/gpt_rme/gpt_rme.c 3ac2e5a07791e75f8ed81d0c1088a639a14142de - arm-trusted-firmware/lib/cpus/errata_report.c 531b8790149c59c6d2a7528e480dc52235a0b5f3 - arm-trusted-firmware/lib/cpus/aarch32/cortex_a32.S 4bd6136e7c566e86577b42f173af618fff3ec5ce - arm-trusted-firmware/lib/cpus/aarch32/cortex_a17.S 9111c66d4eacadc99f95ed552b93509a2040bfdd - arm-trusted-firmware/lib/cpus/aarch32/cortex_a57.S 0011de1efcc751a018cb652d35bf6dfb77ee5da5 - arm-trusted-firmware/lib/cpus/aarch32/cortex_a53.S 20d8dafab232bf71d66f52da52efe0ff2d9a69cc - arm-trusted-firmware/lib/cpus/aarch32/cortex_a15.S dd4d708971e42cb6726bd6bcaeaaeb1ea62cc302 - arm-trusted-firmware/lib/cpus/aarch32/cortex_a7.S 33d1e02fb1f40c2b2147fdf1911b9f6d0de2592d - arm-trusted-firmware/lib/cpus/aarch32/cpu_helpers.S 698a71205b1dfcca91b0dc7e75cd8633685859b4 - arm-trusted-firmware/lib/cpus/aarch32/cortex_a9.S b548ad1b6baee85f650824152f83082709116643 - arm-trusted-firmware/lib/cpus/aarch32/cortex_a72.S 70588b0d27cc22a3c28dcf235cb80cb80658e875 - arm-trusted-firmware/lib/cpus/aarch32/cortex_a5.S 504aecaaa931ada33617064d0c95d4514d583971 - arm-trusted-firmware/lib/cpus/aarch32/aem_generic.S bbcb12f3afb37a6763f26ed91a5859a16a9185f6 - arm-trusted-firmware/lib/cpus/aarch32/cortex_a12.S 0dc9a7f3f035cf6c322da9c77eacf5cdfd5be43b - arm-trusted-firmware/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S 814012a88912a712842aaaf04053a1a8fc46c29c - arm-trusted-firmware/lib/cpus/aarch64/cortex_hayes.S 72048eac4311606ffc73da9f951caa25155c2bee - arm-trusted-firmware/lib/cpus/aarch64/cortex_a510.S b479434b370f4c6c3d65fe58338e18dbfbf5b569 - arm-trusted-firmware/lib/cpus/aarch64/neoverse_n1.S 6c59fcd106e14d7120f6a715ba57542d71f097d9 - arm-trusted-firmware/lib/cpus/aarch64/rainier.S cb4c93c4378ac407239bea5dd2f24065aa1c9c18 - arm-trusted-firmware/lib/cpus/aarch64/cortex_hunter_elp_arm.S bb044127b0f5b6908597c1915659ebabb4b9d8ff - arm-trusted-firmware/lib/cpus/aarch64/neoverse_e1.S 82e100cb356dc2848983a918e3ce932199eb717f - arm-trusted-firmware/lib/cpus/aarch64/cortex_a55.S f382f5af3fd88a0d159f0fc27bf3ff89e6e6517b - arm-trusted-firmware/lib/cpus/aarch64/neoverse_n_common.S 3a0842db6538fada52fd0764e2942e9edcfa61e5 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a65ae.S 516e5e5482ec47fb50a91b19c7c8d86572bd9844 - arm-trusted-firmware/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S 5f647f968abf60452f7ff94f5132206c0a9f64d5 - arm-trusted-firmware/lib/cpus/aarch64/cortex_x2.S 62e253dfa61bf57bc7c8af97146dc643070630b6 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a75_pubsub.c 4076b184f1c8b586d8b7e9c16daffa08e81812c6 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a73.S 8203c676ff19bae3895e97ac72cefe67967782b1 - arm-trusted-firmware/lib/cpus/aarch64/neoverse_v2.S 8753b581e7bd70b0612f529761cb2e2f789d26ce - arm-trusted-firmware/lib/cpus/aarch64/cortex_a75.S 9745ddbfe3bad71ac283cf7afe3f3a58848729fe - arm-trusted-firmware/lib/cpus/aarch64/generic.S b69d55e31f6a022246c70e0fabbaac7e1e2f378f - arm-trusted-firmware/lib/cpus/aarch64/cortex_hunter.S 6c5232d349afaa099b1de4b8274de771a075d0ce - arm-trusted-firmware/lib/cpus/aarch64/cortex_a57.S 12ca25a02fbf7c172709fe538cde38c04b128db8 - arm-trusted-firmware/lib/cpus/aarch64/cortex_x1.S ba50ea7f4f16945c39ca1cca0725a08c99db4a76 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a715.S dd46ea61bba696867fb1ab60d0f54a5955c1f181 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a65.S cc0aec4aad1e8ed68289b5819028f6122f47514c - arm-trusted-firmware/lib/cpus/aarch64/cortex_a710.S c4fd030315f0eaaca36274d49140aeefdccdac43 - arm-trusted-firmware/lib/cpus/aarch64/cortex_x3.S 4a54551934d78de626e562b6685c37bc485b9d38 - arm-trusted-firmware/lib/cpus/aarch64/neoverse_v1.S d45e9ed16b9d3e632da99c2f60372ba17455293f - arm-trusted-firmware/lib/cpus/aarch64/neoverse_poseidon.S 0183572f056c98431e9ee40e1ca22f149c8d1995 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a53.S 5e64126fe122470b5f906cbd26adc7b19c2b1cbd - arm-trusted-firmware/lib/cpus/aarch64/wa_cve_2022_23960_bhb_vector.S fbdc2dd66c632d700bdf6c05b4694fee4e67c42c - arm-trusted-firmware/lib/cpus/aarch64/cortex_a77.S edb24154359f6a874c199325c9d7072c4dedba3b - arm-trusted-firmware/lib/cpus/aarch64/neoverse_n1_pubsub.c 2395220984e4ebe2e10ec3658f908b7a208fb99a - arm-trusted-firmware/lib/cpus/aarch64/cortex_a35.S a9fca207a2b590b4ee1d2fbc18b63720bcb84c63 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a78.S f564c0486f48ae6f3a52992b7c09815b537df2eb - arm-trusted-firmware/lib/cpus/aarch64/dsu_helpers.S 7ff21ebdc83ea3c05558a7c0798f1424648d5a34 - arm-trusted-firmware/lib/cpus/aarch64/qemu_max.S 03c0a2d3e033df508520b527dd03c5487d139556 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a76ae.S 939321e58c0410803055382e79797fe401300830 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a78_ae.S f245d765bc664b16acec02a6040885c8a59f9a54 - arm-trusted-firmware/lib/cpus/aarch64/cpu_helpers.S a2b53794ecd06182d27382c870fa38dda8665b25 - arm-trusted-firmware/lib/cpus/aarch64/neoverse_n2.S 4e151a4890a5d1efb65a0f7ea8600dc4e70dcde1 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a78c.S 527f0453b6bcc1e3cdbc68d25c5949e9c6d90d21 - arm-trusted-firmware/lib/cpus/aarch64/denver.S fd805b6e43d1e39ad08ba1cc47e1bf0f58bd7916 - arm-trusted-firmware/lib/cpus/aarch64/cortex_a76.S 87817fd4d0f4db7bb9527cfe0b1107c39d33bd8b - arm-trusted-firmware/lib/cpus/aarch64/cortex_a72.S e314809e018d3bcc1cb805e4412443d918934828 - arm-trusted-firmware/lib/cpus/aarch64/cpuamu_helpers.S fd801851b71a05fbc5920f6815d5ab8025a7f156 - arm-trusted-firmware/lib/cpus/aarch64/cpuamu.c 5f3bf45f19baa196f8537ea9fa6db1c00692c35f - arm-trusted-firmware/lib/cpus/aarch64/aem_generic.S 2f584ae35b4c22e1c951fec5a9e78130f3cccbae - arm-trusted-firmware/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S c86abd9bf2685dab74d5844d44b08b1c1a76fd8d - arm-trusted-firmware/lib/cpus/aarch64/a64fx.S 4ef2e504a667d7529f6e9f0629c04db77435a28a - arm-trusted-firmware/lib/utils/mem_region.c cf339f00e977a47612e93384a6a0b8e73d731c21 - arm-trusted-firmware/lib/locks/bakery/bakery_lock_coherent.c 977e6d078bc957f8bdaaf5007e9192de38d79bee - arm-trusted-firmware/lib/locks/bakery/bakery_lock_normal.c edf2b7a02784eccffa70a8f06817929dd1a8f993 - arm-trusted-firmware/lib/locks/exclusive/aarch32/spinlock.S 70011c90369b5b9a9d55faec233e60b90b31801e - arm-trusted-firmware/lib/locks/exclusive/aarch64/spinlock.S 6b60742d3e420cad2de83925c184cc98fd66505b - arm-trusted-firmware/lib/pmf/pmf_smc.c b3f793c7bec8ccc037a4cb9796f2bcd15f5bf4eb - arm-trusted-firmware/lib/pmf/pmf_main.c 520eaa82ebafcd44f850b2d49c5e9d500fbf4c2d - arm-trusted-firmware/lib/optee/optee_utils.c 5b4b8798bdd0c34e076d2e3cf365ea5451837b57 - arm-trusted-firmware/lib/zlib/inflate.h 1c1467906f8d4ff84cc17a4dc057cf4913dbbeeb - arm-trusted-firmware/lib/zlib/zutil.c 7e5be478693b1a35e1e4cd1ce317b4500829c6c9 - arm-trusted-firmware/lib/zlib/inflate.c 083ae032c7ce5cde8a3324c4887e88d3bb667e32 - arm-trusted-firmware/lib/zlib/crc32.h 8770ab43c9050b824c646f6e6cee8b3c0628cbda - arm-trusted-firmware/lib/zlib/inffixed.h 4fc803c43a562b2b92a97e22300754ddfe44c603 - arm-trusted-firmware/lib/zlib/inffast.h 81a3e31c1cf436b7b37d0fd2173f5d2cb41842a2 - arm-trusted-firmware/lib/zlib/inftrees.c 370f01d26f5b8fa7030cd5fb054c5f8117d3efc6 - arm-trusted-firmware/lib/zlib/inftrees.h 6c1114794db137af50f9b060aaade1a1a35ed784 - arm-trusted-firmware/lib/zlib/adler32.c 37d67e3a5edffcda681cd70c6ba56f76ede5352b - arm-trusted-firmware/lib/zlib/inffast.c 8bb206723f10a7635c07f3e77abad21e4e47f520 - arm-trusted-firmware/lib/zlib/tf_gunzip.c f5d71470e37d9b6a4e22ff3cf83db854217f3672 - arm-trusted-firmware/lib/zlib/crc32.c 5e3458a3e458b1bea750c6007fc259e233d37887 - arm-trusted-firmware/lib/zlib/zutil.h 915a3be354066f5d3af420ceec193b411076c68b - arm-trusted-firmware/lib/zlib/zlib.h e3329c0bcd4fb66dbba89f8181a971f61cab6ea0 - arm-trusted-firmware/lib/zlib/zconf.h 886c1e8212ddafb0663811837c76ce60a9afb42a - arm-trusted-firmware/lib/bl_aux_params/bl_aux_params.c 8f6358e8adff333d53864e9d728b50b3cfccdd57 - arm-trusted-firmware/lib/aarch64/cache_helpers.S 96718b39d24ee4ca5fd1eb4f87d53c45c9e4f079 - arm-trusted-firmware/lib/aarch64/armclang_printf.S da63c15641cb6cf532770db54efc30b3f8122a7c - arm-trusted-firmware/lib/aarch64/misc_helpers.S 88bbfcb3f9b827bdab7f16cdfe892b2aa1470576 - arm-trusted-firmware/bl2/bl2_image_load_v2.c 4e6964af8a924859ce477b03706fa91fac4ab723 - arm-trusted-firmware/bl2/bl2.ld.S d8756b1a7295709e6757c7dbfc53741267823e2a - arm-trusted-firmware/bl2/bl2_main.c 991c05cee7a30247e2edcade94405aef95480121 - arm-trusted-firmware/bl2/bl2_private.h 6f387fa12de655645d96da6fce67619f1377bda9 - arm-trusted-firmware/bl2/bl2_el3.ld.S 2534665e628b7612c3896fed4e659f3351601296 - arm-trusted-firmware/bl2/aarch32/bl2_arch_setup.c aac463ba1d35408d94f960ade6d2db95d68455ab - arm-trusted-firmware/bl2/aarch32/bl2_el3_entrypoint.S 1f72bb253974087b2a555dc3a89651f7ad462387 - arm-trusted-firmware/bl2/aarch32/bl2_entrypoint.S 44692bdbcbccddc6c4fc022d5028cacb8842376a - arm-trusted-firmware/bl2/aarch32/bl2_el3_exceptions.S f64693060b1ef904b4abfc04b8480a0f458494c5 - arm-trusted-firmware/bl2/aarch32/bl2_run_next_image.S 776c1699268eee43ba9230cb7e785e298e56a233 - arm-trusted-firmware/bl2/aarch64/bl2_arch_setup.c a34048b4cc67bca14b7594e2c1a53b4c0376d779 - arm-trusted-firmware/bl2/aarch64/bl2_el3_entrypoint.S c426fa02b617581d2495667828e9430110cf713a - arm-trusted-firmware/bl2/aarch64/bl2_entrypoint.S 62ef4221f56feaf0907dbe17cad47a9bab86bf03 - arm-trusted-firmware/bl2/aarch64/bl2_el3_exceptions.S 777576955f2ae3959035c33791a33835fe6578f4 - arm-trusted-firmware/bl2/aarch64/bl2_rme_entrypoint.S 247751d71fb2863f439cc217ac18c219dbf15453 - arm-trusted-firmware/bl2/aarch64/bl2_run_next_image.S 20113f49289a58e42b03525ea9427f94e093f58f - arm-trusted-firmware/bl1/bl1_private.h d006178768f88929b34ddd8b6f7caf6ffb1577b4 - arm-trusted-firmware/bl1/bl1_main.c 653f6de57d95cb1d74a23acc6389ab9292ef0451 - arm-trusted-firmware/bl1/bl1_fwu.c 77c0d42875cfa4640d3c5e481334bbb62f6a7a3e - arm-trusted-firmware/bl1/bl1.ld.S 85b2afc44851dc57e79c264641730d0e2eca3016 - arm-trusted-firmware/bl1/tbbr/tbbr_img_desc.c caf76eacd5e8708391bbf7db7315acad4b89c7fd - arm-trusted-firmware/bl1/aarch32/bl1_entrypoint.S 095ac3b2483b968f263618a4bd6cdd8d6f66d321 - arm-trusted-firmware/bl1/aarch32/bl1_context_mgmt.c 8d6e2008e280f848fb14017ba5ba559a10724421 - arm-trusted-firmware/bl1/aarch32/bl1_arch_setup.c bea69e37646041aff3c96bf107e1db48f382a1b4 - arm-trusted-firmware/bl1/aarch32/bl1_exceptions.S 5c5e2355ca375fa98ae30f56bcf2f57ea7056c71 - arm-trusted-firmware/bl1/aarch64/bl1_entrypoint.S 587ecb158bf5940ddc7f95250a8802df39806ef0 - arm-trusted-firmware/bl1/aarch64/bl1_context_mgmt.c 284a0afe619de982f2bd1d4b1c625831ef7b3b5e - arm-trusted-firmware/bl1/aarch64/bl1_arch_setup.c d6181e93a353f492a54a5222fe53d793cc6d46d7 - arm-trusted-firmware/bl1/aarch64/bl1_exceptions.S 2c87153926f8a458cffc9a435e15571ba721c2fa - arm-trusted-firmware/licenses/LICENSE.MIT 201f68ff32e77e6400dc5624a726bb46fafe1ac3 - arm-trusted-firmware/.husky/commit-msg.gerrit fd32ceb86780ba4682d238401c5bdc6c51f6652f - arm-trusted-firmware/.husky/prepare-commit-msg.cz edf09f8f672ed108a22d57c3be9c64c542957347 - arm-trusted-firmware/.husky/commit-msg.commitlint d04e79c7e2d1ff0546074efcfda2290f20c1c923 - arm-trusted-firmware/.husky/commit-msg 11dae66f5031e4fc368d8b20d11916dbcc90b1c0 - arm-trusted-firmware/.husky/prepare-commit-msg Change-Id: Ib6bb4a9e11f3cbf5bb30815dd2b4f24150816e82
This commit is contained in:
svcmobrel-release
91
arm-trusted-firmware/.checkpatch.conf
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91
arm-trusted-firmware/.checkpatch.conf
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#
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# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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# Configure how the Linux checkpatch script should be invoked in the context of
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# the Trusted Firmware source tree.
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#
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# This is not Linux so don't expect a Linux tree!
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--no-tree
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# The Linux kernel expects the SPDX license tag in the first line of each file.
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# We don't follow this in the Trusted Firmware.
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--ignore SPDX_LICENSE_TAG
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# This clarifes the lines indications in the report.
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#
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# E.g.:
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# Without this option, we have the following output:
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# #333: FILE: drivers/arm/gic/arm_gic.c:160:
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# So we have 2 lines indications (333 and 160), which is confusing.
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# We only care about the position in the source file.
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#
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# With this option, it becomes:
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# drivers/arm/gic/arm_gic.c:160:
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--showfile
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# Don't show some messages like the list of ignored types or the suggestion to
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# use "--fix" or report changes to the maintainers.
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--quiet
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#
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# Ignore the following message types, as they don't necessarily make sense in
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# the context of the Trusted Firmware.
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#
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# COMPLEX_MACRO generates false positives.
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--ignore COMPLEX_MACRO
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# Commit messages might contain a Gerrit Change-Id.
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--ignore GERRIT_CHANGE_ID
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# Do not check the format of commit messages, as Gerrit's merge commits do not
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# preserve it.
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--ignore GIT_COMMIT_ID
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# FILE_PATH_CHANGES reports this kind of message:
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# "added, moved or deleted file(s), does MAINTAINERS need updating?"
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# We do not use this MAINTAINERS file process in TF.
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--ignore FILE_PATH_CHANGES
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# AVOID_EXTERNS reports this kind of messages:
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# "externs should be avoided in .c files"
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# We don't follow this convention in TF.
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--ignore AVOID_EXTERNS
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# NEW_TYPEDEFS reports this kind of messages:
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# "do not add new typedefs"
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# We allow adding new typedefs in TF.
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--ignore NEW_TYPEDEFS
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# Avoid "Does not appear to be a unified-diff format patch" message
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--ignore NOT_UNIFIED_DIFF
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# VOLATILE reports this kind of messages:
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# "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt"
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# We allow the usage of the volatile keyword in TF.
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--ignore VOLATILE
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# BRACES reports this kind of messages:
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# braces {} are not necessary for any arm of this statement
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--ignore BRACES
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# PREFER_KERNEL_TYPES reports this kind of messages (when using --strict):
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# "Prefer kernel type 'u32' over 'uint32_t'"
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--ignore PREFER_KERNEL_TYPES
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# USLEEP_RANGE reports this kind of messages (when using --strict):
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# "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt"
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--ignore USLEEP_RANGE
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# COMPARISON_TO_NULL reports this kind of messages (when using --strict):
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# Comparison to NULL could be written ""
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--ignore COMPARISON_TO_NULL
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# UNNECESSARY_PARENTHESES reports this kind of messages (when using --strict):
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# Unnecessary parentheses around ""
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--ignore UNNECESSARY_PARENTHESES
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73
arm-trusted-firmware/.commitlintrc.js
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73
arm-trusted-firmware/.commitlintrc.js
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* eslint-env es6 */
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"use strict";
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const fs = require("fs");
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const yaml = require("js-yaml");
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const { "trailer-exists": trailerExists } = require("@commitlint/rules").default;
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/*
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* The types and scopes accepted by both Commitlint and Commitizen are defined by the changelog
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* configuration file - `changelog.yaml` - as they decide which section of the changelog commits
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* with a given type and scope are placed in.
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*/
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let changelog;
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try {
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const contents = fs.readFileSync("changelog.yaml", "utf8");
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changelog = yaml.load(contents);
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} catch (err) {
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console.log(err);
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throw err;
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}
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function getTypes(sections) {
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return sections.map(section => section.type)
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}
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function getScopes(subsections) {
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return subsections.flatMap(subsection => {
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const scope = subsection.scope ? [ subsection.scope ] : [];
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const subscopes = getScopes(subsection.subsections || []);
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return scope.concat(subscopes);
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})
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};
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const types = getTypes(changelog.sections).sort(); /* Sort alphabetically */
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const scopes = getScopes(changelog.subsections).sort(); /* Sort alphabetically */
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module.exports = {
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||||||
|
extends: ["@commitlint/config-conventional"],
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plugins: [
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{
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|
rules: {
|
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"signed-off-by-exists": trailerExists,
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"change-id-exists": trailerExists,
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},
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|
},
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],
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rules: {
|
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"header-max-length": [1, "always", 50], /* Warning */
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"body-max-line-length": [1, "always", 72], /* Warning */
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|
||||||
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"change-id-exists": [1, "always", "Change-Id:"], /* Warning */
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||||||
|
"signed-off-by-exists": [1, "always", "Signed-off-by:"], /* Warning */
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||||||
|
|
||||||
|
"type-case": [2, "always", "lower-case" ], /* Error */
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|
"type-enum": [2, "always", types], /* Error */
|
||||||
|
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||||||
|
"scope-case": [2, "always", "lower-case"], /* Error */
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|
"scope-enum": [1, "always", scopes] /* Warning */
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||||||
|
},
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||||||
|
};
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||||||
3
arm-trusted-firmware/.cz.json
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3
arm-trusted-firmware/.cz.json
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|||||||
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{
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||||||
|
"path": "@commitlint/cz-commitlint"
|
||||||
|
}
|
||||||
72
arm-trusted-firmware/.editorconfig
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72
arm-trusted-firmware/.editorconfig
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|||||||
|
#
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||||||
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# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
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||||||
|
#
|
||||||
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# SPDX-License-Identifier: BSD-3-Clause
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||||||
|
#
|
||||||
|
|
||||||
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# Trusted Firmware-A Coding style spec for editors.
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||||||
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# References:
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||||||
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# [EC] http://editorconfig.org/
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|
# [CONT] contributing.rst
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||||||
|
# [LCS] Linux Coding Style
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# (https://www.kernel.org/doc/html/v4.10/process/coding-style.html)
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# [PEP8] Style Guide for Python Code
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||||||
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# (https://www.python.org/dev/peps/pep-0008)
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||||||
|
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||||||
|
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||||||
|
root = true
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||||||
|
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||||||
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# set default to match [LCS] .c/.h settings.
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||||||
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# This will also apply to .S, .mk, .sh, Makefile, .dts, etc.
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||||||
|
[*]
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||||||
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# Not specified, but fits current ARM-TF sources.
|
||||||
|
charset = utf-8
|
||||||
|
|
||||||
|
# Not specified, but implicit for "LINUX coding style".
|
||||||
|
end_of_line = lf
|
||||||
|
|
||||||
|
# [LCS] Chapter 1: Indentation
|
||||||
|
# "and thus indentations are also 8 characters"
|
||||||
|
indent_size = 8
|
||||||
|
|
||||||
|
# [LCS] Chapter 1: Indentation
|
||||||
|
# "Outside of comments,...spaces are never used for indentation"
|
||||||
|
indent_style = tab
|
||||||
|
|
||||||
|
# Not specified by [LCS], but sensible
|
||||||
|
insert_final_newline = true
|
||||||
|
|
||||||
|
# [LCS] Chapter 2: Breaking long lines and strings
|
||||||
|
# "The limit on the length of lines is 100 columns"
|
||||||
|
# This is a "soft" requirement for Arm-TF, and should not be the sole
|
||||||
|
# reason for changes.
|
||||||
|
max_line_length = 100
|
||||||
|
|
||||||
|
# [LCS] Chapter 1: Indentation
|
||||||
|
# "Tabs are 8 characters"
|
||||||
|
tab_width = 8
|
||||||
|
|
||||||
|
# [LCS] Chapter 1: Indentation
|
||||||
|
# "Get a decent editor and don't leave whitespace at the end of lines."
|
||||||
|
# [LCS] Chapter 3.1: Spaces
|
||||||
|
# "Do not leave trailing whitespace at the ends of lines."
|
||||||
|
trim_trailing_whitespace = true
|
||||||
|
|
||||||
|
|
||||||
|
# Adjustment for ReStructuredText (RST) documentation
|
||||||
|
[*.{rst}]
|
||||||
|
indent_size = 4
|
||||||
|
indent_style = space
|
||||||
|
|
||||||
|
|
||||||
|
# Adjustment for python which prefers a different style
|
||||||
|
[*.py]
|
||||||
|
# [PEP8] Indentation
|
||||||
|
# "Use 4 spaces per indentation level."
|
||||||
|
indent_size = 4
|
||||||
|
indent_style = space
|
||||||
|
|
||||||
|
# [PEP8] Maximum Line Length
|
||||||
|
# "Limit all lines to a maximum of 79 characters."
|
||||||
|
max_line_length = 79
|
||||||
5
arm-trusted-firmware/.gitreview
Normal file
5
arm-trusted-firmware/.gitreview
Normal file
@@ -0,0 +1,5 @@
|
|||||||
|
[gerrit]
|
||||||
|
host=review.trustedfirmware.org
|
||||||
|
port=29418
|
||||||
|
project=TF-A/trusted-firmware-a
|
||||||
|
defaultbranch=integration
|
||||||
7
arm-trusted-firmware/.husky/commit-msg
Executable file
7
arm-trusted-firmware/.husky/commit-msg
Executable file
@@ -0,0 +1,7 @@
|
|||||||
|
#!/bin/sh
|
||||||
|
|
||||||
|
# shellcheck source=./_/husky.sh
|
||||||
|
. "$(dirname "$0")/_/husky.sh"
|
||||||
|
|
||||||
|
"$(dirname "$0")/commit-msg.gerrit" "$@"
|
||||||
|
"$(dirname "$0")/commit-msg.commitlint" "$@"
|
||||||
3
arm-trusted-firmware/.husky/commit-msg.commitlint
Executable file
3
arm-trusted-firmware/.husky/commit-msg.commitlint
Executable file
@@ -0,0 +1,3 @@
|
|||||||
|
#!/bin/sh
|
||||||
|
|
||||||
|
npx --no-install commitlint --edit "$1"
|
||||||
194
arm-trusted-firmware/.husky/commit-msg.gerrit
Executable file
194
arm-trusted-firmware/.husky/commit-msg.gerrit
Executable file
@@ -0,0 +1,194 @@
|
|||||||
|
#!/bin/sh
|
||||||
|
# From Gerrit Code Review 2.14.20
|
||||||
|
#
|
||||||
|
# Part of Gerrit Code Review (https://www.gerritcodereview.com/)
|
||||||
|
#
|
||||||
|
# Copyright (C) 2009 The Android Open Source Project
|
||||||
|
#
|
||||||
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
# you may not use this file except in compliance with the License.
|
||||||
|
# You may obtain a copy of the License at
|
||||||
|
#
|
||||||
|
# http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
#
|
||||||
|
# Unless required by applicable law or agreed to in writing, software
|
||||||
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
# See the License for the specific language governing permissions and
|
||||||
|
# limitations under the License.
|
||||||
|
#
|
||||||
|
|
||||||
|
unset GREP_OPTIONS
|
||||||
|
|
||||||
|
CHANGE_ID_AFTER="Bug|Depends-On|Issue|Test|Feature|Fixes|Fixed"
|
||||||
|
MSG="$1"
|
||||||
|
|
||||||
|
# Check for, and add if missing, a unique Change-Id
|
||||||
|
#
|
||||||
|
add_ChangeId() {
|
||||||
|
clean_message=`sed -e '
|
||||||
|
/^diff --git .*/{
|
||||||
|
s///
|
||||||
|
q
|
||||||
|
}
|
||||||
|
/^Signed-off-by:/d
|
||||||
|
/^#/d
|
||||||
|
' "$MSG" | git stripspace`
|
||||||
|
if test -z "$clean_message"
|
||||||
|
then
|
||||||
|
return
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Do not add Change-Id to temp commits
|
||||||
|
if echo "$clean_message" | head -1 | grep -q '^\(fixup\|squash\)!'
|
||||||
|
then
|
||||||
|
return
|
||||||
|
fi
|
||||||
|
|
||||||
|
if test "false" = "`git config --bool --get gerrit.createChangeId`"
|
||||||
|
then
|
||||||
|
return
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Does Change-Id: already exist? if so, exit (no change).
|
||||||
|
if grep -i '^Change-Id:' "$MSG" >/dev/null
|
||||||
|
then
|
||||||
|
return
|
||||||
|
fi
|
||||||
|
|
||||||
|
id=`_gen_ChangeId`
|
||||||
|
T="$MSG.tmp.$$"
|
||||||
|
AWK=awk
|
||||||
|
if [ -x /usr/xpg4/bin/awk ]; then
|
||||||
|
# Solaris AWK is just too broken
|
||||||
|
AWK=/usr/xpg4/bin/awk
|
||||||
|
fi
|
||||||
|
|
||||||
|
# Get core.commentChar from git config or use default symbol
|
||||||
|
commentChar=`git config --get core.commentChar`
|
||||||
|
commentChar=${commentChar:-#}
|
||||||
|
|
||||||
|
# How this works:
|
||||||
|
# - parse the commit message as (textLine+ blankLine*)*
|
||||||
|
# - assume textLine+ to be a footer until proven otherwise
|
||||||
|
# - exception: the first block is not footer (as it is the title)
|
||||||
|
# - read textLine+ into a variable
|
||||||
|
# - then count blankLines
|
||||||
|
# - once the next textLine appears, print textLine+ blankLine* as these
|
||||||
|
# aren't footer
|
||||||
|
# - in END, the last textLine+ block is available for footer parsing
|
||||||
|
$AWK '
|
||||||
|
BEGIN {
|
||||||
|
if (match(ENVIRON["OS"], "Windows")) {
|
||||||
|
RS="\r?\n" # Required on recent Cygwin
|
||||||
|
}
|
||||||
|
# while we start with the assumption that textLine+
|
||||||
|
# is a footer, the first block is not.
|
||||||
|
isFooter = 0
|
||||||
|
footerComment = 0
|
||||||
|
blankLines = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
# Skip lines starting with commentChar without any spaces before it.
|
||||||
|
/^'"$commentChar"'/ { next }
|
||||||
|
|
||||||
|
# Skip the line starting with the diff command and everything after it,
|
||||||
|
# up to the end of the file, assuming it is only patch data.
|
||||||
|
# If more than one line before the diff was empty, strip all but one.
|
||||||
|
/^diff --git / {
|
||||||
|
blankLines = 0
|
||||||
|
while (getline) { }
|
||||||
|
next
|
||||||
|
}
|
||||||
|
|
||||||
|
# Count blank lines outside footer comments
|
||||||
|
/^$/ && (footerComment == 0) {
|
||||||
|
blankLines++
|
||||||
|
next
|
||||||
|
}
|
||||||
|
|
||||||
|
# Catch footer comment
|
||||||
|
/^\[[a-zA-Z0-9-]+:/ && (isFooter == 1) {
|
||||||
|
footerComment = 1
|
||||||
|
}
|
||||||
|
|
||||||
|
/]$/ && (footerComment == 1) {
|
||||||
|
footerComment = 2
|
||||||
|
}
|
||||||
|
|
||||||
|
# We have a non-blank line after blank lines. Handle this.
|
||||||
|
(blankLines > 0) {
|
||||||
|
print lines
|
||||||
|
for (i = 0; i < blankLines; i++) {
|
||||||
|
print ""
|
||||||
|
}
|
||||||
|
|
||||||
|
lines = ""
|
||||||
|
blankLines = 0
|
||||||
|
isFooter = 1
|
||||||
|
footerComment = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
# Detect that the current block is not the footer
|
||||||
|
(footerComment == 0) && (!/^\[?[a-zA-Z0-9-]+:/ || /^[a-zA-Z0-9-]+:\/\//) {
|
||||||
|
isFooter = 0
|
||||||
|
}
|
||||||
|
|
||||||
|
{
|
||||||
|
# We need this information about the current last comment line
|
||||||
|
if (footerComment == 2) {
|
||||||
|
footerComment = 0
|
||||||
|
}
|
||||||
|
if (lines != "") {
|
||||||
|
lines = lines "\n";
|
||||||
|
}
|
||||||
|
lines = lines $0
|
||||||
|
}
|
||||||
|
|
||||||
|
# Footer handling:
|
||||||
|
# If the last block is considered a footer, splice in the Change-Id at the
|
||||||
|
# right place.
|
||||||
|
# Look for the right place to inject Change-Id by considering
|
||||||
|
# CHANGE_ID_AFTER. Keys listed in it (case insensitive) come first,
|
||||||
|
# then Change-Id, then everything else (eg. Signed-off-by:).
|
||||||
|
#
|
||||||
|
# Otherwise just print the last block, a new line and the Change-Id as a
|
||||||
|
# block of its own.
|
||||||
|
END {
|
||||||
|
unprinted = 1
|
||||||
|
if (isFooter == 0) {
|
||||||
|
print lines "\n"
|
||||||
|
lines = ""
|
||||||
|
}
|
||||||
|
changeIdAfter = "^(" tolower("'"$CHANGE_ID_AFTER"'") "):"
|
||||||
|
numlines = split(lines, footer, "\n")
|
||||||
|
for (line = 1; line <= numlines; line++) {
|
||||||
|
if (unprinted && match(tolower(footer[line]), changeIdAfter) != 1) {
|
||||||
|
unprinted = 0
|
||||||
|
print "Change-Id: I'"$id"'"
|
||||||
|
}
|
||||||
|
print footer[line]
|
||||||
|
}
|
||||||
|
if (unprinted) {
|
||||||
|
print "Change-Id: I'"$id"'"
|
||||||
|
}
|
||||||
|
}' "$MSG" > "$T" && mv "$T" "$MSG" || rm -f "$T"
|
||||||
|
}
|
||||||
|
_gen_ChangeIdInput() {
|
||||||
|
echo "tree `git write-tree`"
|
||||||
|
if parent=`git rev-parse "HEAD^0" 2>/dev/null`
|
||||||
|
then
|
||||||
|
echo "parent $parent"
|
||||||
|
fi
|
||||||
|
echo "author `git var GIT_AUTHOR_IDENT`"
|
||||||
|
echo "committer `git var GIT_COMMITTER_IDENT`"
|
||||||
|
echo
|
||||||
|
printf '%s' "$clean_message"
|
||||||
|
}
|
||||||
|
_gen_ChangeId() {
|
||||||
|
_gen_ChangeIdInput |
|
||||||
|
git hash-object -t commit --stdin
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
add_ChangeId
|
||||||
6
arm-trusted-firmware/.husky/prepare-commit-msg
Executable file
6
arm-trusted-firmware/.husky/prepare-commit-msg
Executable file
@@ -0,0 +1,6 @@
|
|||||||
|
#!/bin/sh
|
||||||
|
|
||||||
|
# shellcheck source=./_/husky.sh
|
||||||
|
. "$(dirname "$0")/_/husky.sh"
|
||||||
|
|
||||||
|
"$(dirname "$0")/prepare-commit-msg.cz" "$@"
|
||||||
28
arm-trusted-firmware/.husky/prepare-commit-msg.cz
Executable file
28
arm-trusted-firmware/.husky/prepare-commit-msg.cz
Executable file
@@ -0,0 +1,28 @@
|
|||||||
|
#!/bin/bash
|
||||||
|
|
||||||
|
file="$1"
|
||||||
|
type="$2"
|
||||||
|
|
||||||
|
if [ -z "$type" ]; then # only run on new commits
|
||||||
|
#
|
||||||
|
# Save any commit message trailers generated by Git.
|
||||||
|
#
|
||||||
|
|
||||||
|
trailers=$(git interpret-trailers --parse "$file")
|
||||||
|
|
||||||
|
#
|
||||||
|
# Execute the Commitizen hook.
|
||||||
|
#
|
||||||
|
|
||||||
|
(exec < "/dev/tty" && npx --no-install git-cz --hook) || true
|
||||||
|
|
||||||
|
#
|
||||||
|
# Restore any trailers that Commitizen might have overwritten.
|
||||||
|
#
|
||||||
|
|
||||||
|
printf "\n" >> "$file"
|
||||||
|
|
||||||
|
while IFS= read -r trailer; do
|
||||||
|
git interpret-trailers --in-place --trailer "$trailer" "$file"
|
||||||
|
done <<< "$trailers"
|
||||||
|
fi
|
||||||
1
arm-trusted-firmware/.nvmrc
Normal file
1
arm-trusted-firmware/.nvmrc
Normal file
@@ -0,0 +1 @@
|
|||||||
|
v16.17.1
|
||||||
113
arm-trusted-firmware/.versionrc.js
Normal file
113
arm-trusted-firmware/.versionrc.js
Normal file
@@ -0,0 +1,113 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* eslint-env es6 */
|
||||||
|
|
||||||
|
"use strict";
|
||||||
|
|
||||||
|
const fs = require("fs");
|
||||||
|
const yaml = require("js-yaml");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The types and scopes accepted by both Commitlint and Commitizen are defined by the changelog
|
||||||
|
* configuration file - `changelog.yaml` - as they decide which section of the changelog commits
|
||||||
|
* with a given type and scope are placed in.
|
||||||
|
*/
|
||||||
|
|
||||||
|
let changelog;
|
||||||
|
|
||||||
|
try {
|
||||||
|
const contents = fs.readFileSync("changelog.yaml", "utf8");
|
||||||
|
|
||||||
|
changelog = yaml.load(contents);
|
||||||
|
} catch (err) {
|
||||||
|
console.log(err);
|
||||||
|
|
||||||
|
throw err;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The next couple of functions are just used to transform the changelog YAML configuration
|
||||||
|
* structure into one accepted by the Conventional Changelog adapter (conventional-changelog-tf-a).
|
||||||
|
*/
|
||||||
|
|
||||||
|
function getTypes(sections) {
|
||||||
|
return sections.map(section => {
|
||||||
|
return {
|
||||||
|
"type": section.type,
|
||||||
|
"section": section.hidden ? undefined : section.title,
|
||||||
|
"hidden": section.hidden || false,
|
||||||
|
};
|
||||||
|
})
|
||||||
|
}
|
||||||
|
|
||||||
|
function getSections(subsections) {
|
||||||
|
return subsections.flatMap(subsection => {
|
||||||
|
const scope = subsection.scope ? [ subsection.scope ] : [];
|
||||||
|
|
||||||
|
return {
|
||||||
|
"title": subsection.title,
|
||||||
|
"sections": getSections(subsection.subsections || []),
|
||||||
|
"scopes": scope.concat(subsection.deprecated || []),
|
||||||
|
};
|
||||||
|
})
|
||||||
|
};
|
||||||
|
|
||||||
|
const types = getTypes(changelog.sections);
|
||||||
|
const sections = getSections(changelog.subsections);
|
||||||
|
|
||||||
|
module.exports = {
|
||||||
|
"header": "# Change Log & Release Notes\n\nThis document contains a summary of the new features, changes, fixes and known\nissues in each release of Trusted Firmware-A.\n",
|
||||||
|
"preset": {
|
||||||
|
"name": "tf-a",
|
||||||
|
"commitUrlFormat": "https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/{{hash}}",
|
||||||
|
"compareUrlFormat": "https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/{{previousTag}}..refs/tags/{{currentTag}}",
|
||||||
|
"userUrlFormat": "https://github.com/{{user}}",
|
||||||
|
|
||||||
|
"types": types,
|
||||||
|
"sections": sections,
|
||||||
|
},
|
||||||
|
"infile": "docs/change-log.md",
|
||||||
|
"skip": {
|
||||||
|
"commit": true,
|
||||||
|
"tag": true
|
||||||
|
},
|
||||||
|
"bumpFiles": [
|
||||||
|
{
|
||||||
|
"filename": "package.json",
|
||||||
|
"type": "json"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"filename": "package-lock.json",
|
||||||
|
"type": "json"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"filename": "tools/conventional-changelog-tf-a/package.json",
|
||||||
|
"type": "json"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"filename": "Makefile",
|
||||||
|
"updater": {
|
||||||
|
"readVersion": function (contents) {
|
||||||
|
const major = contents.match(/^VERSION_MAJOR\s*:=\s*(\d+?)$/m)[1];
|
||||||
|
const minor = contents.match(/^VERSION_MINOR\s*:=\s*(\d+?)$/m)[1];
|
||||||
|
|
||||||
|
return `${major}.${minor}.0`;
|
||||||
|
},
|
||||||
|
|
||||||
|
"writeVersion": function (contents, version) {
|
||||||
|
const major = version.split(".")[0];
|
||||||
|
const minor = version.split(".")[1];
|
||||||
|
|
||||||
|
contents = contents.replace(/^(VERSION_MAJOR\s*:=\s*)(\d+?)$/m, `$1${major}`);
|
||||||
|
contents = contents.replace(/^(VERSION_MINOR\s*:=\s*)(\d+?)$/m, `$1${minor}`);
|
||||||
|
|
||||||
|
return contents;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
]
|
||||||
|
};
|
||||||
1596
arm-trusted-firmware/Makefile
Normal file
1596
arm-trusted-firmware/Makefile
Normal file
File diff suppressed because it is too large
Load Diff
15
arm-trusted-firmware/bl1/aarch32/bl1_arch_setup.c
Normal file
15
arm-trusted-firmware/bl1/aarch32/bl1_arch_setup.c
Normal file
@@ -0,0 +1,15 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../bl1_private.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* TODO: Function that does the first bit of architectural setup.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_arch_setup(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
172
arm-trusted-firmware/bl1/aarch32/bl1_context_mgmt.c
Normal file
172
arm-trusted-firmware/bl1/aarch32/bl1_context_mgmt.c
Normal file
@@ -0,0 +1,172 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <lib/el3_runtime/context_mgmt.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
#include <smccc_helpers.h>
|
||||||
|
|
||||||
|
#include "../bl1_private.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Following arrays will be used for context management.
|
||||||
|
* There are 2 instances, for the Secure and Non-Secure contexts.
|
||||||
|
*/
|
||||||
|
static cpu_context_t bl1_cpu_context[2];
|
||||||
|
static smc_ctx_t bl1_smc_context[2];
|
||||||
|
|
||||||
|
/* Following contains the next cpu context pointer. */
|
||||||
|
static void *bl1_next_cpu_context_ptr;
|
||||||
|
|
||||||
|
/* Following contains the next smc context pointer. */
|
||||||
|
static void *bl1_next_smc_context_ptr;
|
||||||
|
|
||||||
|
/* Following functions are used for SMC context handling */
|
||||||
|
void *smc_get_ctx(unsigned int security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
return &bl1_smc_context[security_state];
|
||||||
|
}
|
||||||
|
|
||||||
|
void smc_set_next_ctx(unsigned int security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
bl1_next_smc_context_ptr = &bl1_smc_context[security_state];
|
||||||
|
}
|
||||||
|
|
||||||
|
void *smc_get_next_ctx(void)
|
||||||
|
{
|
||||||
|
return bl1_next_smc_context_ptr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Following functions are used for CPU context handling */
|
||||||
|
void *cm_get_context(uint32_t security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
return &bl1_cpu_context[security_state];
|
||||||
|
}
|
||||||
|
|
||||||
|
void cm_set_next_context(void *context)
|
||||||
|
{
|
||||||
|
assert(context != NULL);
|
||||||
|
bl1_next_cpu_context_ptr = context;
|
||||||
|
}
|
||||||
|
|
||||||
|
void *cm_get_next_context(void)
|
||||||
|
{
|
||||||
|
return bl1_next_cpu_context_ptr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Following function copies GP regs r0-r4, lr and spsr,
|
||||||
|
* from the CPU context to the SMC context structures.
|
||||||
|
******************************************************************************/
|
||||||
|
static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx,
|
||||||
|
smc_ctx_t *next_smc_ctx)
|
||||||
|
{
|
||||||
|
next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
|
||||||
|
next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
|
||||||
|
next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
|
||||||
|
next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
|
||||||
|
next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
|
||||||
|
next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
|
||||||
|
next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Following function flushes the SMC & CPU context pointer and its data.
|
||||||
|
******************************************************************************/
|
||||||
|
static void flush_smc_and_cpu_ctx(void)
|
||||||
|
{
|
||||||
|
flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr,
|
||||||
|
sizeof(bl1_next_smc_context_ptr));
|
||||||
|
flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr,
|
||||||
|
sizeof(smc_ctx_t));
|
||||||
|
|
||||||
|
flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr,
|
||||||
|
sizeof(bl1_next_cpu_context_ptr));
|
||||||
|
flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr,
|
||||||
|
sizeof(cpu_context_t));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function prepares the context for Secure/Normal world images.
|
||||||
|
* Normal world images are transitioned to HYP(if supported) else SVC.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_prepare_next_image(unsigned int image_id)
|
||||||
|
{
|
||||||
|
unsigned int security_state, mode = MODE32_svc;
|
||||||
|
image_desc_t *desc;
|
||||||
|
entry_point_info_t *next_bl_ep;
|
||||||
|
|
||||||
|
/* Get the image descriptor. */
|
||||||
|
desc = bl1_plat_get_image_desc(image_id);
|
||||||
|
assert(desc != NULL);
|
||||||
|
|
||||||
|
/* Get the entry point info. */
|
||||||
|
next_bl_ep = &desc->ep_info;
|
||||||
|
|
||||||
|
/* Get the image security state. */
|
||||||
|
security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
|
||||||
|
|
||||||
|
/* Prepare the SPSR for the next BL image. */
|
||||||
|
if ((security_state != SECURE) && (GET_VIRT_EXT(read_id_pfr1()) != 0U)) {
|
||||||
|
mode = MODE32_hyp;
|
||||||
|
}
|
||||||
|
|
||||||
|
next_bl_ep->spsr = SPSR_MODE32(mode, SPSR_T_ARM,
|
||||||
|
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
|
||||||
|
|
||||||
|
/* Allow platform to make change */
|
||||||
|
bl1_plat_set_ep_info(image_id, next_bl_ep);
|
||||||
|
|
||||||
|
/* Prepare the cpu context for the next BL image. */
|
||||||
|
cm_init_my_context(next_bl_ep);
|
||||||
|
cm_prepare_el3_exit(security_state);
|
||||||
|
cm_set_next_context(cm_get_context(security_state));
|
||||||
|
|
||||||
|
/* Prepare the smc context for the next BL image. */
|
||||||
|
smc_set_next_ctx(security_state);
|
||||||
|
copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()),
|
||||||
|
smc_get_next_ctx());
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If the next image is non-secure, then we need to program the banked
|
||||||
|
* non secure sctlr. This is not required when the next image is secure
|
||||||
|
* because in AArch32, we expect the secure world to have the same
|
||||||
|
* SCTLR settings.
|
||||||
|
*/
|
||||||
|
if (security_state == NON_SECURE) {
|
||||||
|
cpu_context_t *ctx = cm_get_context(security_state);
|
||||||
|
u_register_t ns_sctlr;
|
||||||
|
|
||||||
|
/* Temporarily set the NS bit to access NS SCTLR */
|
||||||
|
write_scr(read_scr() | SCR_NS_BIT);
|
||||||
|
isb();
|
||||||
|
|
||||||
|
ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
|
||||||
|
write_sctlr(ns_sctlr);
|
||||||
|
isb();
|
||||||
|
|
||||||
|
write_scr(read_scr() & ~SCR_NS_BIT);
|
||||||
|
isb();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Flush the SMC & CPU context and the (next)pointers,
|
||||||
|
* to access them after caches are disabled.
|
||||||
|
*/
|
||||||
|
flush_smc_and_cpu_ctx();
|
||||||
|
|
||||||
|
/* Indicate that image is in execution state. */
|
||||||
|
desc->state = IMAGE_STATE_EXECUTED;
|
||||||
|
|
||||||
|
print_entry_point_info(next_bl_ep);
|
||||||
|
}
|
||||||
99
arm-trusted-firmware/bl1/aarch32/bl1_entrypoint.S
Normal file
99
arm-trusted-firmware/bl1/aarch32/bl1_entrypoint.S
Normal file
@@ -0,0 +1,99 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <el3_common_macros.S>
|
||||||
|
#include <smccc_helpers.h>
|
||||||
|
#include <smccc_macros.S>
|
||||||
|
|
||||||
|
.globl bl1_vector_table
|
||||||
|
.globl bl1_entrypoint
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Setup the vector table to support SVC & MON mode.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_base bl1_vector_table
|
||||||
|
b bl1_entrypoint
|
||||||
|
b report_exception /* Undef */
|
||||||
|
b bl1_aarch32_smc_handler /* SMC call */
|
||||||
|
b report_prefetch_abort /* Prefetch abort */
|
||||||
|
b report_data_abort /* Data abort */
|
||||||
|
b report_exception /* Reserved */
|
||||||
|
b report_exception /* IRQ */
|
||||||
|
b report_exception /* FIQ */
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* bl1_entrypoint() is the entry point into the trusted
|
||||||
|
* firmware code when a cpu is released from warm or
|
||||||
|
* cold reset.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
func bl1_entrypoint
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* If the reset address is programmable then bl1_entrypoint() is
|
||||||
|
* executed only on the cold boot path. Therefore, we can skip the warm
|
||||||
|
* boot mailbox mechanism.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=1 \
|
||||||
|
_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
|
||||||
|
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
|
||||||
|
_init_memory=1 \
|
||||||
|
_init_c_runtime=1 \
|
||||||
|
_exception_vectors=bl1_vector_table \
|
||||||
|
_pie_fixup_size=0
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Perform BL1 setup
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl1_setup
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Jump to main function.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl1_main
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Jump to next image.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the smc_context for next BL image,
|
||||||
|
* program the gp/system registers and save it in `r4`.
|
||||||
|
*/
|
||||||
|
bl smc_get_next_ctx
|
||||||
|
mov r4, r0
|
||||||
|
|
||||||
|
/* Only turn-off MMU if going to secure world */
|
||||||
|
ldr r5, [r4, #SMC_CTX_SCR]
|
||||||
|
tst r5, #SCR_NS_BIT
|
||||||
|
bne skip_mmu_off
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MMU needs to be disabled because both BL1 and BL2/BL2U execute
|
||||||
|
* in PL1, and therefore share the same address space.
|
||||||
|
* BL2/BL2U will initialize the address space according to its
|
||||||
|
* own requirement.
|
||||||
|
*/
|
||||||
|
bl disable_mmu_icache_secure
|
||||||
|
stcopr r0, TLBIALL
|
||||||
|
dsb sy
|
||||||
|
isb
|
||||||
|
|
||||||
|
skip_mmu_off:
|
||||||
|
/* Restore smc_context from `r4` and exit secure monitor mode. */
|
||||||
|
mov r0, r4
|
||||||
|
monitor_exit
|
||||||
|
endfunc bl1_entrypoint
|
||||||
165
arm-trusted-firmware/bl1/aarch32/bl1_exceptions.S
Normal file
165
arm-trusted-firmware/bl1/aarch32/bl1_exceptions.S
Normal file
@@ -0,0 +1,165 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <bl1/bl1.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables.h>
|
||||||
|
#include <smccc_helpers.h>
|
||||||
|
#include <smccc_macros.S>
|
||||||
|
|
||||||
|
.globl bl1_aarch32_smc_handler
|
||||||
|
|
||||||
|
|
||||||
|
func bl1_aarch32_smc_handler
|
||||||
|
/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
|
||||||
|
str lr, [sp, #SMC_CTX_LR_MON]
|
||||||
|
|
||||||
|
/* ------------------------------------------------
|
||||||
|
* SMC in BL1 is handled assuming that the MMU is
|
||||||
|
* turned off by BL2.
|
||||||
|
* ------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ----------------------------------------------
|
||||||
|
* Detect if this is a RUN_IMAGE or other SMC.
|
||||||
|
* ----------------------------------------------
|
||||||
|
*/
|
||||||
|
mov lr, #BL1_SMC_RUN_IMAGE
|
||||||
|
cmp lr, r0
|
||||||
|
bne smc_handler
|
||||||
|
|
||||||
|
/* ------------------------------------------------
|
||||||
|
* Make sure only Secure world reaches here.
|
||||||
|
* ------------------------------------------------
|
||||||
|
*/
|
||||||
|
ldcopr r8, SCR
|
||||||
|
tst r8, #SCR_NS_BIT
|
||||||
|
blne report_exception
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* Pass control to next secure image.
|
||||||
|
* Here it expects r1 to contain the address of a entry_point_info_t
|
||||||
|
* structure describing the BL entrypoint.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
mov r8, r1
|
||||||
|
mov r0, r1
|
||||||
|
bl bl1_print_next_bl_ep_info
|
||||||
|
|
||||||
|
#if SPIN_ON_BL1_EXIT
|
||||||
|
bl print_debug_loop_message
|
||||||
|
debug_loop:
|
||||||
|
b debug_loop
|
||||||
|
#endif
|
||||||
|
|
||||||
|
mov r0, r8
|
||||||
|
bl bl1_plat_prepare_exit
|
||||||
|
|
||||||
|
stcopr r0, TLBIALL
|
||||||
|
dsb sy
|
||||||
|
isb
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Extract PC and SPSR based on struct `entry_point_info_t`
|
||||||
|
* and load it in LR and SPSR registers respectively.
|
||||||
|
*/
|
||||||
|
ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
|
||||||
|
ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
|
||||||
|
msr spsr_xc, r1
|
||||||
|
|
||||||
|
/* Some BL32 stages expect lr_svc to provide the BL33 entry address */
|
||||||
|
cps #MODE32_svc
|
||||||
|
ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET]
|
||||||
|
cps #MODE32_mon
|
||||||
|
|
||||||
|
add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
|
||||||
|
ldm r8, {r0, r1, r2, r3}
|
||||||
|
exception_return
|
||||||
|
endfunc bl1_aarch32_smc_handler
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Save Secure/Normal world context and jump to
|
||||||
|
* BL1 SMC handler.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
func smc_handler
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Save the GP registers.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
smccc_save_gp_mode_regs
|
||||||
|
|
||||||
|
/*
|
||||||
|
* `sp` still points to `smc_ctx_t`. Save it to a register
|
||||||
|
* and restore the C runtime stack pointer to `sp`.
|
||||||
|
*/
|
||||||
|
mov r6, sp
|
||||||
|
ldr sp, [r6, #SMC_CTX_SP_MON]
|
||||||
|
|
||||||
|
ldr r0, [r6, #SMC_CTX_SCR]
|
||||||
|
and r7, r0, #SCR_NS_BIT /* flags */
|
||||||
|
|
||||||
|
/* Switch to Secure Mode */
|
||||||
|
bic r0, #SCR_NS_BIT
|
||||||
|
stcopr r0, SCR
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* If caller is from Secure world then turn on the MMU */
|
||||||
|
tst r7, #SCR_NS_BIT
|
||||||
|
bne skip_mmu_on
|
||||||
|
|
||||||
|
/* Turn on the MMU */
|
||||||
|
mov r0, #DISABLE_DCACHE
|
||||||
|
bl enable_mmu_svc_mon
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Invalidate `smc_ctx_t` in data cache to prevent dirty data being
|
||||||
|
* used.
|
||||||
|
*/
|
||||||
|
mov r0, r6
|
||||||
|
mov r1, #SMC_CTX_SIZE
|
||||||
|
bl inv_dcache_range
|
||||||
|
|
||||||
|
/* Enable the data cache. */
|
||||||
|
ldcopr r9, SCTLR
|
||||||
|
orr r9, r9, #SCTLR_C_BIT
|
||||||
|
stcopr r9, SCTLR
|
||||||
|
isb
|
||||||
|
|
||||||
|
skip_mmu_on:
|
||||||
|
/* Prepare arguments for BL1 SMC wrapper. */
|
||||||
|
ldr r0, [r6, #SMC_CTX_GPREG_R0] /* smc_fid */
|
||||||
|
mov r1, #0 /* cookie */
|
||||||
|
mov r2, r6 /* handle */
|
||||||
|
mov r3, r7 /* flags */
|
||||||
|
bl bl1_smc_wrapper
|
||||||
|
|
||||||
|
/* Get the smc_context for next BL image */
|
||||||
|
bl smc_get_next_ctx
|
||||||
|
mov r4, r0
|
||||||
|
|
||||||
|
/* Only turn-off MMU if going to secure world */
|
||||||
|
ldr r5, [r4, #SMC_CTX_SCR]
|
||||||
|
tst r5, #SCR_NS_BIT
|
||||||
|
bne skip_mmu_off
|
||||||
|
|
||||||
|
/* Disable the MMU */
|
||||||
|
bl disable_mmu_icache_secure
|
||||||
|
stcopr r0, TLBIALL
|
||||||
|
dsb sy
|
||||||
|
isb
|
||||||
|
|
||||||
|
skip_mmu_off:
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Do the transition to next BL image.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
mov r0, r4
|
||||||
|
monitor_exit
|
||||||
|
endfunc smc_handler
|
||||||
35
arm-trusted-firmware/bl1/aarch64/bl1_arch_setup.c
Normal file
35
arm-trusted-firmware/bl1/aarch64/bl1_arch_setup.c
Normal file
@@ -0,0 +1,35 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include "../bl1_private.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Function that does the first bit of architectural setup that affects
|
||||||
|
* execution in the non-secure address space.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_arch_setup(void)
|
||||||
|
{
|
||||||
|
/* Set the next EL to be AArch64 */
|
||||||
|
write_scr_el3(read_scr_el3() | SCR_RW_BIT);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Set the Secure EL1 required architectural state
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_arch_next_el_setup(void)
|
||||||
|
{
|
||||||
|
u_register_t next_sctlr;
|
||||||
|
|
||||||
|
/* Use the same endianness than the current BL */
|
||||||
|
next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
|
||||||
|
|
||||||
|
/* Set SCTLR Secure EL1 */
|
||||||
|
next_sctlr |= SCTLR_EL1_RES1;
|
||||||
|
|
||||||
|
write_sctlr_el1(next_sctlr);
|
||||||
|
}
|
||||||
131
arm-trusted-firmware/bl1/aarch64/bl1_context_mgmt.c
Normal file
131
arm-trusted-firmware/bl1/aarch64/bl1_context_mgmt.c
Normal file
@@ -0,0 +1,131 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <lib/el3_runtime/context_mgmt.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
#include "../bl1_private.h"
|
||||||
|
|
||||||
|
/* Following contains the cpu context pointers. */
|
||||||
|
static void *bl1_cpu_context_ptr[2];
|
||||||
|
entry_point_info_t *bl2_ep_info;
|
||||||
|
|
||||||
|
|
||||||
|
void *cm_get_context(uint32_t security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
return bl1_cpu_context_ptr[security_state];
|
||||||
|
}
|
||||||
|
|
||||||
|
void cm_set_context(void *context, uint32_t security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
bl1_cpu_context_ptr[security_state] = context;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ENABLE_RME
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function prepares the entry point information to run BL2 in Root world,
|
||||||
|
* i.e. EL3, for the case when FEAT_RME is enabled.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_prepare_next_image(unsigned int image_id)
|
||||||
|
{
|
||||||
|
image_desc_t *bl2_desc;
|
||||||
|
|
||||||
|
assert(image_id == BL2_IMAGE_ID);
|
||||||
|
|
||||||
|
/* Get the image descriptor. */
|
||||||
|
bl2_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
|
||||||
|
assert(bl2_desc != NULL);
|
||||||
|
|
||||||
|
/* Get the entry point info. */
|
||||||
|
bl2_ep_info = &bl2_desc->ep_info;
|
||||||
|
|
||||||
|
bl2_ep_info->spsr = (uint32_t)SPSR_64(MODE_EL3, MODE_SP_ELX,
|
||||||
|
DISABLE_ALL_EXCEPTIONS);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Flush cache since bl2_ep_info is accessed after MMU is disabled
|
||||||
|
* before jumping to BL2.
|
||||||
|
*/
|
||||||
|
flush_dcache_range((uintptr_t)bl2_ep_info, sizeof(entry_point_info_t));
|
||||||
|
|
||||||
|
/* Indicate that image is in execution state. */
|
||||||
|
bl2_desc->state = IMAGE_STATE_EXECUTED;
|
||||||
|
|
||||||
|
/* Print debug info and flush the console before running BL2. */
|
||||||
|
print_entry_point_info(bl2_ep_info);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function prepares the context for Secure/Normal world images.
|
||||||
|
* Normal world images are transitioned to EL2(if supported) else EL1.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_prepare_next_image(unsigned int image_id)
|
||||||
|
{
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Following array will be used for context management.
|
||||||
|
* There are 2 instances, for the Secure and Non-Secure contexts.
|
||||||
|
*/
|
||||||
|
static cpu_context_t bl1_cpu_context[2];
|
||||||
|
|
||||||
|
unsigned int security_state, mode = MODE_EL1;
|
||||||
|
image_desc_t *desc;
|
||||||
|
entry_point_info_t *next_bl_ep;
|
||||||
|
|
||||||
|
#if CTX_INCLUDE_AARCH32_REGS
|
||||||
|
/*
|
||||||
|
* Ensure that the build flag to save AArch32 system registers in CPU
|
||||||
|
* context is not set for AArch64-only platforms.
|
||||||
|
*/
|
||||||
|
if (el_implemented(1) == EL_IMPL_A64ONLY) {
|
||||||
|
ERROR("EL1 supports AArch64-only. Please set build flag "
|
||||||
|
"CTX_INCLUDE_AARCH32_REGS = 0\n");
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Get the image descriptor. */
|
||||||
|
desc = bl1_plat_get_image_desc(image_id);
|
||||||
|
assert(desc != NULL);
|
||||||
|
|
||||||
|
/* Get the entry point info. */
|
||||||
|
next_bl_ep = &desc->ep_info;
|
||||||
|
|
||||||
|
/* Get the image security state. */
|
||||||
|
security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
|
||||||
|
|
||||||
|
/* Setup the Secure/Non-Secure context if not done already. */
|
||||||
|
if (cm_get_context(security_state) == NULL)
|
||||||
|
cm_set_context(&bl1_cpu_context[security_state], security_state);
|
||||||
|
|
||||||
|
/* Prepare the SPSR for the next BL image. */
|
||||||
|
if ((security_state != SECURE) && (el_implemented(2) != EL_IMPL_NONE)) {
|
||||||
|
mode = MODE_EL2;
|
||||||
|
}
|
||||||
|
|
||||||
|
next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
|
||||||
|
(uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
|
||||||
|
|
||||||
|
/* Allow platform to make change */
|
||||||
|
bl1_plat_set_ep_info(image_id, next_bl_ep);
|
||||||
|
|
||||||
|
/* Prepare the context for the next BL image. */
|
||||||
|
cm_init_my_context(next_bl_ep);
|
||||||
|
cm_prepare_el3_exit(security_state);
|
||||||
|
|
||||||
|
/* Indicate that image is in execution state. */
|
||||||
|
desc->state = IMAGE_STATE_EXECUTED;
|
||||||
|
|
||||||
|
print_entry_point_info(next_bl_ep);
|
||||||
|
}
|
||||||
|
#endif /* ENABLE_RME */
|
||||||
108
arm-trusted-firmware/bl1/aarch64/bl1_entrypoint.S
Normal file
108
arm-trusted-firmware/bl1/aarch64/bl1_entrypoint.S
Normal file
@@ -0,0 +1,108 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <el3_common_macros.S>
|
||||||
|
|
||||||
|
.globl bl1_entrypoint
|
||||||
|
.globl bl1_run_bl2_in_root
|
||||||
|
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* bl1_entrypoint() is the entry point into the trusted
|
||||||
|
* firmware code when a cpu is released from warm or
|
||||||
|
* cold reset.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
func bl1_entrypoint
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* If the reset address is programmable then bl1_entrypoint() is
|
||||||
|
* executed only on the cold boot path. Therefore, we can skip the warm
|
||||||
|
* boot mailbox mechanism.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=1 \
|
||||||
|
_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
|
||||||
|
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
|
||||||
|
_init_memory=1 \
|
||||||
|
_init_c_runtime=1 \
|
||||||
|
_exception_vectors=bl1_exceptions \
|
||||||
|
_pie_fixup_size=0
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Perform BL1 setup
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl1_setup
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Program APIAKey_EL1 and enable pointer authentication.
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_init_enable_el3
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Initialize platform and jump to our c-entry point
|
||||||
|
* for this type of reset.
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl1_main
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Disable pointer authentication before jumping to next boot image.
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_disable_el3
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/* --------------------------------------------------
|
||||||
|
* Do the transition to next boot image.
|
||||||
|
* --------------------------------------------------
|
||||||
|
*/
|
||||||
|
#if ENABLE_RME
|
||||||
|
b bl1_run_bl2_in_root
|
||||||
|
#else
|
||||||
|
b el3_exit
|
||||||
|
#endif
|
||||||
|
endfunc bl1_entrypoint
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* void bl1_run_bl2_in_root();
|
||||||
|
* This function runs BL2 in root/EL3 when RME is enabled.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
func bl1_run_bl2_in_root
|
||||||
|
/* read bl2_ep_info */
|
||||||
|
adrp x20, bl2_ep_info
|
||||||
|
add x20, x20, :lo12:bl2_ep_info
|
||||||
|
ldr x20, [x20]
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* MMU needs to be disabled because BL2 executes
|
||||||
|
* in EL3. It will initialize the address space
|
||||||
|
* according to its own requirements.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl disable_mmu_icache_el3
|
||||||
|
tlbi alle3
|
||||||
|
|
||||||
|
ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
|
||||||
|
msr elr_el3, x0
|
||||||
|
msr spsr_el3, x1
|
||||||
|
|
||||||
|
ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
|
||||||
|
ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
|
||||||
|
ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
|
||||||
|
ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
|
||||||
|
exception_return
|
||||||
|
endfunc bl1_run_bl2_in_root
|
||||||
289
arm-trusted-firmware/bl1/aarch64/bl1_exceptions.S
Normal file
289
arm-trusted-firmware/bl1/aarch64/bl1_exceptions.S
Normal file
@@ -0,0 +1,289 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <bl1/bl1.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <context.h>
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------------------------
|
||||||
|
* Very simple stackless exception handlers used by BL1.
|
||||||
|
* -----------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
.globl bl1_exceptions
|
||||||
|
|
||||||
|
vector_base bl1_exceptions
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Current EL with SP0 : 0x0 - 0x200
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionSP0
|
||||||
|
mov x0, #SYNC_EXCEPTION_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionSP0
|
||||||
|
|
||||||
|
vector_entry IrqSP0
|
||||||
|
mov x0, #IRQ_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqSP0
|
||||||
|
|
||||||
|
vector_entry FiqSP0
|
||||||
|
mov x0, #FIQ_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqSP0
|
||||||
|
|
||||||
|
vector_entry SErrorSP0
|
||||||
|
mov x0, #SERROR_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorSP0
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Current EL with SPx: 0x200 - 0x400
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionSPx
|
||||||
|
mov x0, #SYNC_EXCEPTION_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionSPx
|
||||||
|
|
||||||
|
vector_entry IrqSPx
|
||||||
|
mov x0, #IRQ_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqSPx
|
||||||
|
|
||||||
|
vector_entry FiqSPx
|
||||||
|
mov x0, #FIQ_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqSPx
|
||||||
|
|
||||||
|
vector_entry SErrorSPx
|
||||||
|
mov x0, #SERROR_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorSPx
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Lower EL using AArch64 : 0x400 - 0x600
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionA64
|
||||||
|
/* Enable the SError interrupt */
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
|
||||||
|
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
|
||||||
|
/* Expect only SMC exceptions */
|
||||||
|
mrs x30, esr_el3
|
||||||
|
ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
|
||||||
|
cmp x30, #EC_AARCH64_SMC
|
||||||
|
b.ne unexpected_sync_exception
|
||||||
|
|
||||||
|
b smc_handler64
|
||||||
|
end_vector_entry SynchronousExceptionA64
|
||||||
|
|
||||||
|
vector_entry IrqA64
|
||||||
|
mov x0, #IRQ_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqA64
|
||||||
|
|
||||||
|
vector_entry FiqA64
|
||||||
|
mov x0, #FIQ_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqA64
|
||||||
|
|
||||||
|
vector_entry SErrorA64
|
||||||
|
mov x0, #SERROR_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorA64
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Lower EL using AArch32 : 0x600 - 0x800
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionA32
|
||||||
|
mov x0, #SYNC_EXCEPTION_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionA32
|
||||||
|
|
||||||
|
vector_entry IrqA32
|
||||||
|
mov x0, #IRQ_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqA32
|
||||||
|
|
||||||
|
vector_entry FiqA32
|
||||||
|
mov x0, #FIQ_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqA32
|
||||||
|
|
||||||
|
vector_entry SErrorA32
|
||||||
|
mov x0, #SERROR_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorA32
|
||||||
|
|
||||||
|
|
||||||
|
func smc_handler64
|
||||||
|
|
||||||
|
/* ----------------------------------------------
|
||||||
|
* Detect if this is a RUN_IMAGE or other SMC.
|
||||||
|
* ----------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x30, #BL1_SMC_RUN_IMAGE
|
||||||
|
cmp x30, x0
|
||||||
|
b.ne smc_handler
|
||||||
|
|
||||||
|
/* ------------------------------------------------
|
||||||
|
* Make sure only Secure world reaches here.
|
||||||
|
* ------------------------------------------------
|
||||||
|
*/
|
||||||
|
mrs x30, scr_el3
|
||||||
|
tst x30, #SCR_NS_BIT
|
||||||
|
b.ne unexpected_sync_exception
|
||||||
|
|
||||||
|
/* ----------------------------------------------
|
||||||
|
* Handling RUN_IMAGE SMC. First switch back to
|
||||||
|
* SP_EL0 for the C runtime stack.
|
||||||
|
* ----------------------------------------------
|
||||||
|
*/
|
||||||
|
ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
|
||||||
|
msr spsel, #MODE_SP_EL0
|
||||||
|
mov sp, x30
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* Pass EL3 control to next BL image.
|
||||||
|
* Here it expects X1 with the address of a entry_point_info_t
|
||||||
|
* structure describing the next BL image entrypoint.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x20, x1
|
||||||
|
|
||||||
|
mov x0, x20
|
||||||
|
bl bl1_print_next_bl_ep_info
|
||||||
|
|
||||||
|
ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
|
||||||
|
msr elr_el3, x0
|
||||||
|
msr spsr_el3, x1
|
||||||
|
ubfx x0, x1, #MODE_EL_SHIFT, #2
|
||||||
|
cmp x0, #MODE_EL3
|
||||||
|
b.ne unexpected_sync_exception
|
||||||
|
|
||||||
|
bl disable_mmu_icache_el3
|
||||||
|
tlbi alle3
|
||||||
|
dsb ish /* ERET implies ISB, so it is not needed here */
|
||||||
|
|
||||||
|
#if SPIN_ON_BL1_EXIT
|
||||||
|
bl print_debug_loop_message
|
||||||
|
debug_loop:
|
||||||
|
b debug_loop
|
||||||
|
#endif
|
||||||
|
|
||||||
|
mov x0, x20
|
||||||
|
bl bl1_plat_prepare_exit
|
||||||
|
|
||||||
|
ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
|
||||||
|
ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
|
||||||
|
ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
|
||||||
|
ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
|
||||||
|
exception_return
|
||||||
|
endfunc smc_handler64
|
||||||
|
|
||||||
|
unexpected_sync_exception:
|
||||||
|
mov x0, #SYNC_EXCEPTION_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Save Secure/Normal world context and jump to
|
||||||
|
* BL1 SMC handler.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
smc_handler:
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Save x0-x29 and ARMv8.3-PAuth (if enabled) registers.
|
||||||
|
* If Secure Cycle Counter is not disabled in MDCR_EL3
|
||||||
|
* when ARMv8.5-PMU is implemented, save PMCR_EL0 and
|
||||||
|
* disable Cycle Counter.
|
||||||
|
* TODO: Revisit to store only SMCCC specified registers.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl prepare_el3_entry
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Load and program stored APIAKey firmware key.
|
||||||
|
* Re-enable pointer authentication in EL3, as it was
|
||||||
|
* disabled before jumping to the next boot image.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_load_bl1_apiakey_enable
|
||||||
|
#endif
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Populate the parameters for the SMC handler. We
|
||||||
|
* already have x0-x4 in place. x5 will point to a
|
||||||
|
* cookie (not used now). x6 will point to the context
|
||||||
|
* structure (SP_EL3) and x7 will contain flags we need
|
||||||
|
* to pass to the handler.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x5, xzr
|
||||||
|
mov x6, sp
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Restore the saved C runtime stack value which will
|
||||||
|
* become the new SP_EL0 i.e. EL3 runtime stack. It was
|
||||||
|
* saved in the 'cpu_context' structure prior to the last
|
||||||
|
* ERET from EL3.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Switch back to SP_EL0 for the C runtime stack.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
msr spsel, #MODE_SP_EL0
|
||||||
|
mov sp, x12
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
|
||||||
|
* is a world switch during SMC handling.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
mrs x16, spsr_el3
|
||||||
|
mrs x17, elr_el3
|
||||||
|
mrs x18, scr_el3
|
||||||
|
stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
|
||||||
|
str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
|
||||||
|
|
||||||
|
/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
|
||||||
|
bfi x7, x18, #0, #1
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Go to BL1 SMC handler.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl1_smc_handler
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Do the transition to next BL image.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
b el3_exit
|
||||||
149
arm-trusted-firmware/bl1/bl1.ld.S
Normal file
149
arm-trusted-firmware/bl1/bl1.ld.S
Normal file
@@ -0,0 +1,149 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The .data section gets copied from ROM to RAM at runtime.
|
||||||
|
* Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes
|
||||||
|
* aligned regions in it.
|
||||||
|
* Its VMA must be page-aligned as it marks the first read/write page.
|
||||||
|
*/
|
||||||
|
#define DATA_ALIGN 16
|
||||||
|
|
||||||
|
#include <common/bl_common.ld.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
|
||||||
|
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
|
||||||
|
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
|
||||||
|
ENTRY(bl1_entrypoint)
|
||||||
|
|
||||||
|
MEMORY {
|
||||||
|
ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
|
||||||
|
RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
|
||||||
|
}
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = BL1_RO_BASE;
|
||||||
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
||||||
|
"BL1_RO_BASE address is not aligned on a page boundary.")
|
||||||
|
|
||||||
|
#if SEPARATE_CODE_AND_RODATA
|
||||||
|
.text . : {
|
||||||
|
__TEXT_START__ = .;
|
||||||
|
*bl1_entrypoint.o(.text*)
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(.vectors)
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__TEXT_END__ = .;
|
||||||
|
} >ROM
|
||||||
|
|
||||||
|
/* .ARM.extab and .ARM.exidx are only added because Clang need them */
|
||||||
|
.ARM.extab . : {
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >ROM
|
||||||
|
|
||||||
|
.ARM.exidx . : {
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
} >ROM
|
||||||
|
|
||||||
|
.rodata . : {
|
||||||
|
__RODATA_START__ = .;
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
/*
|
||||||
|
* No need to pad out the .rodata section to a page boundary. Next is
|
||||||
|
* the .data section, which can mapped in ROM with the same memory
|
||||||
|
* attributes as the .rodata section.
|
||||||
|
*
|
||||||
|
* Pad out to 16 bytes though as .data section needs to be 16 byte
|
||||||
|
* aligned and lld does not align the LMA to the aligment specified
|
||||||
|
* on the .data section.
|
||||||
|
*/
|
||||||
|
__RODATA_END__ = .;
|
||||||
|
. = ALIGN(16);
|
||||||
|
} >ROM
|
||||||
|
#else
|
||||||
|
ro . : {
|
||||||
|
__RO_START__ = .;
|
||||||
|
*bl1_entrypoint.o(.text*)
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
*(.vectors)
|
||||||
|
__RO_END__ = .;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Pad out to 16 bytes as .data section needs to be 16 byte aligned and
|
||||||
|
* lld does not align the LMA to the aligment specified on the .data
|
||||||
|
* section.
|
||||||
|
*/
|
||||||
|
. = ALIGN(16);
|
||||||
|
} >ROM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
|
||||||
|
"cpu_ops not defined for this platform.")
|
||||||
|
|
||||||
|
. = BL1_RW_BASE;
|
||||||
|
ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
|
||||||
|
"BL1_RW_BASE address is not aligned on a page boundary.")
|
||||||
|
|
||||||
|
DATA_SECTION >RAM AT>ROM
|
||||||
|
__DATA_RAM_START__ = __DATA_START__;
|
||||||
|
__DATA_RAM_END__ = __DATA_END__;
|
||||||
|
|
||||||
|
STACK_SECTION >RAM
|
||||||
|
BSS_SECTION >RAM
|
||||||
|
XLAT_TABLE_SECTION >RAM
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
/*
|
||||||
|
* The base address of the coherent memory section must be page-aligned (4K)
|
||||||
|
* to guarantee that the coherent data are stored on their own pages and
|
||||||
|
* are not mixed with normal data. This is required to set up the correct
|
||||||
|
* memory attributes for the coherent data page tables.
|
||||||
|
*/
|
||||||
|
coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
|
||||||
|
__COHERENT_RAM_START__ = .;
|
||||||
|
*(tzfw_coherent_mem)
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked
|
||||||
|
* as device memory. No other unexpected data must creep in.
|
||||||
|
* Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__COHERENT_RAM_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
__BL1_RAM_START__ = ADDR(.data);
|
||||||
|
__BL1_RAM_END__ = .;
|
||||||
|
|
||||||
|
__DATA_ROM_START__ = LOADADDR(.data);
|
||||||
|
__DATA_SIZE__ = SIZEOF(.data);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The .data section is the last PROGBITS section so its end marks the end
|
||||||
|
* of BL1's actual content in Trusted ROM.
|
||||||
|
*/
|
||||||
|
__BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
|
||||||
|
ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
|
||||||
|
"BL1's ROM content has exceeded its limit.")
|
||||||
|
|
||||||
|
__BSS_SIZE__ = SIZEOF(.bss);
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
__COHERENT_RAM_UNALIGNED_SIZE__ =
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
|
||||||
|
}
|
||||||
32
arm-trusted-firmware/bl1/bl1.mk
Normal file
32
arm-trusted-firmware/bl1/bl1.mk
Normal file
@@ -0,0 +1,32 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
|
||||||
|
BL1_SOURCES += bl1/${ARCH}/bl1_arch_setup.c \
|
||||||
|
bl1/${ARCH}/bl1_context_mgmt.c \
|
||||||
|
bl1/${ARCH}/bl1_entrypoint.S \
|
||||||
|
bl1/${ARCH}/bl1_exceptions.S \
|
||||||
|
bl1/bl1_main.c \
|
||||||
|
lib/cpus/${ARCH}/cpu_helpers.S \
|
||||||
|
lib/cpus/errata_report.c \
|
||||||
|
lib/el3_runtime/${ARCH}/context_mgmt.c \
|
||||||
|
plat/common/plat_bl1_common.c \
|
||||||
|
plat/common/${ARCH}/platform_up_stack.S \
|
||||||
|
${MBEDTLS_SOURCES}
|
||||||
|
|
||||||
|
ifeq (${DISABLE_MTPMU},1)
|
||||||
|
BL1_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ARCH},aarch64)
|
||||||
|
BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \
|
||||||
|
lib/el3_runtime/aarch64/context.S
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${TRUSTED_BOARD_BOOT},1)
|
||||||
|
BL1_SOURCES += bl1/bl1_fwu.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
BL1_LINKERFILE := bl1/bl1.ld.S
|
||||||
745
arm-trusted-firmware/bl1/bl1_fwu.c
Normal file
745
arm-trusted-firmware/bl1/bl1_fwu.c
Normal file
@@ -0,0 +1,745 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <bl1/bl1.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <drivers/auth/auth_mod.h>
|
||||||
|
#include <lib/el3_runtime/context_mgmt.h>
|
||||||
|
#include <lib/utils.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
#include <smccc_helpers.h>
|
||||||
|
|
||||||
|
#include "bl1_private.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function declarations.
|
||||||
|
*/
|
||||||
|
static int bl1_fwu_image_copy(unsigned int image_id,
|
||||||
|
uintptr_t image_src,
|
||||||
|
unsigned int block_size,
|
||||||
|
unsigned int image_size,
|
||||||
|
unsigned int flags);
|
||||||
|
static int bl1_fwu_image_auth(unsigned int image_id,
|
||||||
|
uintptr_t image_src,
|
||||||
|
unsigned int image_size,
|
||||||
|
unsigned int flags);
|
||||||
|
static int bl1_fwu_image_execute(unsigned int image_id,
|
||||||
|
void **handle,
|
||||||
|
unsigned int flags);
|
||||||
|
static register_t bl1_fwu_image_resume(register_t image_param,
|
||||||
|
void **handle,
|
||||||
|
unsigned int flags);
|
||||||
|
static int bl1_fwu_sec_image_done(void **handle,
|
||||||
|
unsigned int flags);
|
||||||
|
static int bl1_fwu_image_reset(unsigned int image_id,
|
||||||
|
unsigned int flags);
|
||||||
|
__dead2 static void bl1_fwu_done(void *client_cookie, void *reserved);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This keeps track of last executed secure image id.
|
||||||
|
*/
|
||||||
|
static unsigned int sec_exec_image_id = INVALID_IMAGE_ID;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Top level handler for servicing FWU SMCs.
|
||||||
|
******************************************************************************/
|
||||||
|
u_register_t bl1_fwu_smc_handler(unsigned int smc_fid,
|
||||||
|
u_register_t x1,
|
||||||
|
u_register_t x2,
|
||||||
|
u_register_t x3,
|
||||||
|
u_register_t x4,
|
||||||
|
void *cookie,
|
||||||
|
void *handle,
|
||||||
|
unsigned int flags)
|
||||||
|
{
|
||||||
|
|
||||||
|
switch (smc_fid) {
|
||||||
|
case FWU_SMC_IMAGE_COPY:
|
||||||
|
SMC_RET1(handle, bl1_fwu_image_copy((uint32_t)x1, x2,
|
||||||
|
(uint32_t)x3, (uint32_t)x4, flags));
|
||||||
|
|
||||||
|
case FWU_SMC_IMAGE_AUTH:
|
||||||
|
SMC_RET1(handle, bl1_fwu_image_auth((uint32_t)x1, x2,
|
||||||
|
(uint32_t)x3, flags));
|
||||||
|
|
||||||
|
case FWU_SMC_IMAGE_EXECUTE:
|
||||||
|
SMC_RET1(handle, bl1_fwu_image_execute((uint32_t)x1, &handle,
|
||||||
|
flags));
|
||||||
|
|
||||||
|
case FWU_SMC_IMAGE_RESUME:
|
||||||
|
SMC_RET1(handle, bl1_fwu_image_resume((register_t)x1, &handle,
|
||||||
|
flags));
|
||||||
|
|
||||||
|
case FWU_SMC_SEC_IMAGE_DONE:
|
||||||
|
SMC_RET1(handle, bl1_fwu_sec_image_done(&handle, flags));
|
||||||
|
|
||||||
|
case FWU_SMC_IMAGE_RESET:
|
||||||
|
SMC_RET1(handle, bl1_fwu_image_reset((uint32_t)x1, flags));
|
||||||
|
|
||||||
|
case FWU_SMC_UPDATE_DONE:
|
||||||
|
bl1_fwu_done((void *)x1, NULL);
|
||||||
|
|
||||||
|
default:
|
||||||
|
assert(false); /* Unreachable */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
SMC_RET1(handle, SMC_UNK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Utility functions to keep track of the images that are loaded at any time.
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#ifdef PLAT_FWU_MAX_SIMULTANEOUS_IMAGES
|
||||||
|
#define FWU_MAX_SIMULTANEOUS_IMAGES PLAT_FWU_MAX_SIMULTANEOUS_IMAGES
|
||||||
|
#else
|
||||||
|
#define FWU_MAX_SIMULTANEOUS_IMAGES 10
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static unsigned int bl1_fwu_loaded_ids[FWU_MAX_SIMULTANEOUS_IMAGES] = {
|
||||||
|
[0 ... FWU_MAX_SIMULTANEOUS_IMAGES-1] = INVALID_IMAGE_ID
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Adds an image_id to the bl1_fwu_loaded_ids array.
|
||||||
|
* Returns 0 on success, 1 on error.
|
||||||
|
*/
|
||||||
|
static int bl1_fwu_add_loaded_id(unsigned int image_id)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* Check if the ID is already in the list */
|
||||||
|
for (i = 0; i < FWU_MAX_SIMULTANEOUS_IMAGES; i++) {
|
||||||
|
if (bl1_fwu_loaded_ids[i] == image_id)
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Find an empty slot */
|
||||||
|
for (i = 0; i < FWU_MAX_SIMULTANEOUS_IMAGES; i++) {
|
||||||
|
if (bl1_fwu_loaded_ids[i] == INVALID_IMAGE_ID) {
|
||||||
|
bl1_fwu_loaded_ids[i] = image_id;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Removes an image_id from the bl1_fwu_loaded_ids array.
|
||||||
|
* Returns 0 on success, 1 on error.
|
||||||
|
*/
|
||||||
|
static int bl1_fwu_remove_loaded_id(unsigned int image_id)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* Find the ID */
|
||||||
|
for (i = 0; i < FWU_MAX_SIMULTANEOUS_IMAGES; i++) {
|
||||||
|
if (bl1_fwu_loaded_ids[i] == image_id) {
|
||||||
|
bl1_fwu_loaded_ids[i] = INVALID_IMAGE_ID;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function checks if the specified image overlaps another image already
|
||||||
|
* loaded. It returns 0 if there is no overlap, a negative error code otherwise.
|
||||||
|
******************************************************************************/
|
||||||
|
static int bl1_fwu_image_check_overlaps(unsigned int image_id)
|
||||||
|
{
|
||||||
|
const image_desc_t *desc, *checked_desc;
|
||||||
|
const image_info_t *info, *checked_info;
|
||||||
|
|
||||||
|
uintptr_t image_base, image_end;
|
||||||
|
uintptr_t checked_image_base, checked_image_end;
|
||||||
|
|
||||||
|
checked_desc = bl1_plat_get_image_desc(image_id);
|
||||||
|
checked_info = &checked_desc->image_info;
|
||||||
|
|
||||||
|
/* Image being checked mustn't be empty. */
|
||||||
|
assert(checked_info->image_size != 0);
|
||||||
|
|
||||||
|
checked_image_base = checked_info->image_base;
|
||||||
|
checked_image_end = checked_image_base + checked_info->image_size - 1;
|
||||||
|
/* No need to check for overflows, it's done in bl1_fwu_image_copy(). */
|
||||||
|
|
||||||
|
for (int i = 0; i < FWU_MAX_SIMULTANEOUS_IMAGES; i++) {
|
||||||
|
|
||||||
|
/* Skip INVALID_IMAGE_IDs and don't check image against itself */
|
||||||
|
if ((bl1_fwu_loaded_ids[i] == INVALID_IMAGE_ID) ||
|
||||||
|
(bl1_fwu_loaded_ids[i] == image_id))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
desc = bl1_plat_get_image_desc(bl1_fwu_loaded_ids[i]);
|
||||||
|
|
||||||
|
/* Only check images that are loaded or being loaded. */
|
||||||
|
assert ((desc != NULL) && (desc->state != IMAGE_STATE_RESET));
|
||||||
|
|
||||||
|
info = &desc->image_info;
|
||||||
|
|
||||||
|
/* There cannot be overlaps with an empty image. */
|
||||||
|
if (info->image_size == 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
image_base = info->image_base;
|
||||||
|
image_end = image_base + info->image_size - 1;
|
||||||
|
/*
|
||||||
|
* Overflows cannot happen. It is checked in
|
||||||
|
* bl1_fwu_image_copy() when the image goes from RESET to
|
||||||
|
* COPYING or COPIED.
|
||||||
|
*/
|
||||||
|
assert (image_end > image_base);
|
||||||
|
|
||||||
|
/* Check if there are overlaps. */
|
||||||
|
if (!((image_end < checked_image_base) ||
|
||||||
|
(checked_image_end < image_base))) {
|
||||||
|
VERBOSE("Image with ID %d overlaps existing image with ID %d",
|
||||||
|
checked_desc->image_id, desc->image_id);
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function is responsible for copying secure images in AP Secure RAM.
|
||||||
|
******************************************************************************/
|
||||||
|
static int bl1_fwu_image_copy(unsigned int image_id,
|
||||||
|
uintptr_t image_src,
|
||||||
|
unsigned int block_size,
|
||||||
|
unsigned int image_size,
|
||||||
|
unsigned int flags)
|
||||||
|
{
|
||||||
|
uintptr_t dest_addr;
|
||||||
|
unsigned int remaining;
|
||||||
|
image_desc_t *desc;
|
||||||
|
|
||||||
|
/* Get the image descriptor. */
|
||||||
|
desc = bl1_plat_get_image_desc(image_id);
|
||||||
|
if (desc == NULL) {
|
||||||
|
WARN("BL1-FWU: Invalid image ID %u\n", image_id);
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The request must originate from a non-secure caller and target a
|
||||||
|
* secure image. Any other scenario is invalid.
|
||||||
|
*/
|
||||||
|
if (GET_SECURITY_STATE(flags) == SECURE) {
|
||||||
|
WARN("BL1-FWU: Copy not allowed from secure world.\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
if (GET_SECURITY_STATE(desc->ep_info.h.attr) == NON_SECURE) {
|
||||||
|
WARN("BL1-FWU: Copy not allowed for non-secure images.\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check whether the FWU state machine is in the correct state. */
|
||||||
|
if ((desc->state != IMAGE_STATE_RESET) &&
|
||||||
|
(desc->state != IMAGE_STATE_COPYING)) {
|
||||||
|
WARN("BL1-FWU: Copy not allowed at this point of the FWU"
|
||||||
|
" process.\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((image_src == 0U) || (block_size == 0U) ||
|
||||||
|
check_uptr_overflow(image_src, block_size - 1)) {
|
||||||
|
WARN("BL1-FWU: Copy not allowed due to invalid image source"
|
||||||
|
" or block size\n");
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (desc->state == IMAGE_STATE_COPYING) {
|
||||||
|
/*
|
||||||
|
* There must have been at least 1 copy operation for this image
|
||||||
|
* previously.
|
||||||
|
*/
|
||||||
|
assert(desc->copied_size != 0U);
|
||||||
|
/*
|
||||||
|
* The image size must have been recorded in the 1st copy
|
||||||
|
* operation.
|
||||||
|
*/
|
||||||
|
image_size = desc->image_info.image_size;
|
||||||
|
assert(image_size != 0);
|
||||||
|
assert(desc->copied_size < image_size);
|
||||||
|
|
||||||
|
INFO("BL1-FWU: Continuing image copy in blocks\n");
|
||||||
|
} else { /* desc->state == IMAGE_STATE_RESET */
|
||||||
|
INFO("BL1-FWU: Initial call to copy an image\n");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* image_size is relevant only for the 1st copy request, it is
|
||||||
|
* then ignored for subsequent calls for this image.
|
||||||
|
*/
|
||||||
|
if (image_size == 0) {
|
||||||
|
WARN("BL1-FWU: Copy not allowed due to invalid image"
|
||||||
|
" size\n");
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check that the image size to load is within limit */
|
||||||
|
if (image_size > desc->image_info.image_max_size) {
|
||||||
|
WARN("BL1-FWU: Image size out of bounds\n");
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Save the given image size. */
|
||||||
|
desc->image_info.image_size = image_size;
|
||||||
|
|
||||||
|
/* Make sure the image doesn't overlap other images. */
|
||||||
|
if (bl1_fwu_image_check_overlaps(image_id) != 0) {
|
||||||
|
desc->image_info.image_size = 0;
|
||||||
|
WARN("BL1-FWU: This image overlaps another one\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* copied_size must be explicitly initialized here because the
|
||||||
|
* FWU code doesn't necessarily do it when it resets the state
|
||||||
|
* machine.
|
||||||
|
*/
|
||||||
|
desc->copied_size = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If the given block size is more than the total image size
|
||||||
|
* then clip the former to the latter.
|
||||||
|
*/
|
||||||
|
remaining = image_size - desc->copied_size;
|
||||||
|
if (block_size > remaining) {
|
||||||
|
WARN("BL1-FWU: Block size is too big, clipping it.\n");
|
||||||
|
block_size = remaining;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Make sure the source image is mapped in memory. */
|
||||||
|
if (bl1_plat_mem_check(image_src, block_size, flags) != 0) {
|
||||||
|
WARN("BL1-FWU: Source image is not mapped.\n");
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (bl1_fwu_add_loaded_id(image_id) != 0) {
|
||||||
|
WARN("BL1-FWU: Too many images loaded at the same time.\n");
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allow the platform to handle pre-image load before copying */
|
||||||
|
if (desc->state == IMAGE_STATE_RESET) {
|
||||||
|
if (bl1_plat_handle_pre_image_load(image_id) != 0) {
|
||||||
|
ERROR("BL1-FWU: Failure in pre-image load of image id %d\n",
|
||||||
|
image_id);
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Everything looks sane. Go ahead and copy the block of data. */
|
||||||
|
dest_addr = desc->image_info.image_base + desc->copied_size;
|
||||||
|
(void)memcpy((void *) dest_addr, (const void *) image_src, block_size);
|
||||||
|
flush_dcache_range(dest_addr, block_size);
|
||||||
|
|
||||||
|
desc->copied_size += block_size;
|
||||||
|
desc->state = (block_size == remaining) ?
|
||||||
|
IMAGE_STATE_COPIED : IMAGE_STATE_COPYING;
|
||||||
|
|
||||||
|
INFO("BL1-FWU: Copy operation successful.\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function is responsible for authenticating Normal/Secure images.
|
||||||
|
******************************************************************************/
|
||||||
|
static int bl1_fwu_image_auth(unsigned int image_id,
|
||||||
|
uintptr_t image_src,
|
||||||
|
unsigned int image_size,
|
||||||
|
unsigned int flags)
|
||||||
|
{
|
||||||
|
int result;
|
||||||
|
uintptr_t base_addr;
|
||||||
|
unsigned int total_size;
|
||||||
|
image_desc_t *desc;
|
||||||
|
|
||||||
|
/* Get the image descriptor. */
|
||||||
|
desc = bl1_plat_get_image_desc(image_id);
|
||||||
|
if (desc == NULL)
|
||||||
|
return -EPERM;
|
||||||
|
|
||||||
|
if (GET_SECURITY_STATE(flags) == SECURE) {
|
||||||
|
if (desc->state != IMAGE_STATE_RESET) {
|
||||||
|
WARN("BL1-FWU: Authentication from secure world "
|
||||||
|
"while in invalid state\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
if (GET_SECURITY_STATE(desc->ep_info.h.attr) == SECURE) {
|
||||||
|
if (desc->state != IMAGE_STATE_COPIED) {
|
||||||
|
WARN("BL1-FWU: Authentication of secure image "
|
||||||
|
"from non-secure world while not in copied state\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
if (desc->state != IMAGE_STATE_RESET) {
|
||||||
|
WARN("BL1-FWU: Authentication of non-secure image "
|
||||||
|
"from non-secure world while in invalid state\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (desc->state == IMAGE_STATE_COPIED) {
|
||||||
|
/*
|
||||||
|
* Image is in COPIED state.
|
||||||
|
* Use the stored address and size.
|
||||||
|
*/
|
||||||
|
base_addr = desc->image_info.image_base;
|
||||||
|
total_size = desc->image_info.image_size;
|
||||||
|
} else {
|
||||||
|
if ((image_src == 0U) || (image_size == 0U) ||
|
||||||
|
check_uptr_overflow(image_src, image_size - 1)) {
|
||||||
|
WARN("BL1-FWU: Auth not allowed due to invalid"
|
||||||
|
" image source/size\n");
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Image is in RESET state.
|
||||||
|
* Check the parameters and authenticate the source image in place.
|
||||||
|
*/
|
||||||
|
if (bl1_plat_mem_check(image_src, image_size, \
|
||||||
|
desc->ep_info.h.attr) != 0) {
|
||||||
|
WARN("BL1-FWU: Authentication arguments source/size not mapped\n");
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (bl1_fwu_add_loaded_id(image_id) != 0) {
|
||||||
|
WARN("BL1-FWU: Too many images loaded at the same time.\n");
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
base_addr = image_src;
|
||||||
|
total_size = image_size;
|
||||||
|
|
||||||
|
/* Update the image size in the descriptor. */
|
||||||
|
desc->image_info.image_size = total_size;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Authenticate the image.
|
||||||
|
*/
|
||||||
|
INFO("BL1-FWU: Authenticating image_id:%d\n", image_id);
|
||||||
|
result = auth_mod_verify_img(image_id, (void *)base_addr, total_size);
|
||||||
|
if (result != 0) {
|
||||||
|
WARN("BL1-FWU: Authentication Failed err=%d\n", result);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Authentication has failed.
|
||||||
|
* Clear the memory if the image was copied.
|
||||||
|
* This is to prevent an attack where this contains
|
||||||
|
* some malicious code that can somehow be executed later.
|
||||||
|
*/
|
||||||
|
if (desc->state == IMAGE_STATE_COPIED) {
|
||||||
|
/* Clear the memory.*/
|
||||||
|
zero_normalmem((void *)base_addr, total_size);
|
||||||
|
flush_dcache_range(base_addr, total_size);
|
||||||
|
|
||||||
|
/* Indicate that image can be copied again*/
|
||||||
|
desc->state = IMAGE_STATE_RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Even if this fails it's ok because the ID isn't in the array.
|
||||||
|
* The image cannot be in RESET state here, it is checked at the
|
||||||
|
* beginning of the function.
|
||||||
|
*/
|
||||||
|
(void)bl1_fwu_remove_loaded_id(image_id);
|
||||||
|
return -EAUTH;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Indicate that image is in authenticated state. */
|
||||||
|
desc->state = IMAGE_STATE_AUTHENTICATED;
|
||||||
|
|
||||||
|
/* Allow the platform to handle post-image load */
|
||||||
|
result = bl1_plat_handle_post_image_load(image_id);
|
||||||
|
if (result != 0) {
|
||||||
|
ERROR("BL1-FWU: Failure %d in post-image load of image id %d\n",
|
||||||
|
result, image_id);
|
||||||
|
/*
|
||||||
|
* Panic here as the platform handling of post-image load is
|
||||||
|
* not correct.
|
||||||
|
*/
|
||||||
|
plat_error_handler(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Flush image_info to memory so that other
|
||||||
|
* secure world images can see changes.
|
||||||
|
*/
|
||||||
|
flush_dcache_range((uintptr_t)&desc->image_info,
|
||||||
|
sizeof(image_info_t));
|
||||||
|
|
||||||
|
INFO("BL1-FWU: Authentication was successful\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function is responsible for executing Secure images.
|
||||||
|
******************************************************************************/
|
||||||
|
static int bl1_fwu_image_execute(unsigned int image_id,
|
||||||
|
void **handle,
|
||||||
|
unsigned int flags)
|
||||||
|
{
|
||||||
|
/* Get the image descriptor. */
|
||||||
|
image_desc_t *desc = bl1_plat_get_image_desc(image_id);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Execution is NOT allowed if:
|
||||||
|
* image_id is invalid OR
|
||||||
|
* Caller is from Secure world OR
|
||||||
|
* Image is Non-Secure OR
|
||||||
|
* Image is Non-Executable OR
|
||||||
|
* Image is NOT in AUTHENTICATED state.
|
||||||
|
*/
|
||||||
|
if ((desc == NULL) ||
|
||||||
|
(GET_SECURITY_STATE(flags) == SECURE) ||
|
||||||
|
(GET_SECURITY_STATE(desc->ep_info.h.attr) == NON_SECURE) ||
|
||||||
|
(EP_GET_EXE(desc->ep_info.h.attr) == NON_EXECUTABLE) ||
|
||||||
|
(desc->state != IMAGE_STATE_AUTHENTICATED)) {
|
||||||
|
WARN("BL1-FWU: Execution not allowed due to invalid state/args\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
|
||||||
|
INFO("BL1-FWU: Executing Secure image\n");
|
||||||
|
|
||||||
|
#ifdef __aarch64__
|
||||||
|
/* Save NS-EL1 system registers. */
|
||||||
|
cm_el1_sysregs_context_save(NON_SECURE);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Prepare the image for execution. */
|
||||||
|
bl1_prepare_next_image(image_id);
|
||||||
|
|
||||||
|
/* Update the secure image id. */
|
||||||
|
sec_exec_image_id = image_id;
|
||||||
|
|
||||||
|
#ifdef __aarch64__
|
||||||
|
*handle = cm_get_context(SECURE);
|
||||||
|
#else
|
||||||
|
*handle = smc_get_ctx(SECURE);
|
||||||
|
#endif
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function is responsible for resuming execution in the other security
|
||||||
|
* world
|
||||||
|
******************************************************************************/
|
||||||
|
static register_t bl1_fwu_image_resume(register_t image_param,
|
||||||
|
void **handle,
|
||||||
|
unsigned int flags)
|
||||||
|
{
|
||||||
|
image_desc_t *desc;
|
||||||
|
unsigned int resume_sec_state;
|
||||||
|
unsigned int caller_sec_state = GET_SECURITY_STATE(flags);
|
||||||
|
|
||||||
|
/* Get the image descriptor for last executed secure image id. */
|
||||||
|
desc = bl1_plat_get_image_desc(sec_exec_image_id);
|
||||||
|
if (caller_sec_state == NON_SECURE) {
|
||||||
|
if (desc == NULL) {
|
||||||
|
WARN("BL1-FWU: Resume not allowed due to no available"
|
||||||
|
"secure image\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
/* desc must be valid for secure world callers */
|
||||||
|
assert(desc != NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(GET_SECURITY_STATE(desc->ep_info.h.attr) == SECURE);
|
||||||
|
assert(EP_GET_EXE(desc->ep_info.h.attr) == EXECUTABLE);
|
||||||
|
|
||||||
|
if (caller_sec_state == SECURE) {
|
||||||
|
assert(desc->state == IMAGE_STATE_EXECUTED);
|
||||||
|
|
||||||
|
/* Update the flags. */
|
||||||
|
desc->state = IMAGE_STATE_INTERRUPTED;
|
||||||
|
resume_sec_state = NON_SECURE;
|
||||||
|
} else {
|
||||||
|
assert(desc->state == IMAGE_STATE_INTERRUPTED);
|
||||||
|
|
||||||
|
/* Update the flags. */
|
||||||
|
desc->state = IMAGE_STATE_EXECUTED;
|
||||||
|
resume_sec_state = SECURE;
|
||||||
|
}
|
||||||
|
|
||||||
|
INFO("BL1-FWU: Resuming %s world context\n",
|
||||||
|
(resume_sec_state == SECURE) ? "secure" : "normal");
|
||||||
|
|
||||||
|
#ifdef __aarch64__
|
||||||
|
/* Save the EL1 system registers of calling world. */
|
||||||
|
cm_el1_sysregs_context_save(caller_sec_state);
|
||||||
|
|
||||||
|
/* Restore the EL1 system registers of resuming world. */
|
||||||
|
cm_el1_sysregs_context_restore(resume_sec_state);
|
||||||
|
|
||||||
|
/* Update the next context. */
|
||||||
|
cm_set_next_eret_context(resume_sec_state);
|
||||||
|
|
||||||
|
*handle = cm_get_context(resume_sec_state);
|
||||||
|
#else
|
||||||
|
/* Update the next context. */
|
||||||
|
cm_set_next_context(cm_get_context(resume_sec_state));
|
||||||
|
|
||||||
|
/* Prepare the smc context for the next BL image. */
|
||||||
|
smc_set_next_ctx(resume_sec_state);
|
||||||
|
|
||||||
|
*handle = smc_get_ctx(resume_sec_state);
|
||||||
|
#endif
|
||||||
|
return image_param;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function is responsible for resuming normal world context.
|
||||||
|
******************************************************************************/
|
||||||
|
static int bl1_fwu_sec_image_done(void **handle, unsigned int flags)
|
||||||
|
{
|
||||||
|
image_desc_t *desc;
|
||||||
|
|
||||||
|
/* Make sure caller is from the secure world */
|
||||||
|
if (GET_SECURITY_STATE(flags) == NON_SECURE) {
|
||||||
|
WARN("BL1-FWU: Image done not allowed from normal world\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get the image descriptor for last executed secure image id */
|
||||||
|
desc = bl1_plat_get_image_desc(sec_exec_image_id);
|
||||||
|
|
||||||
|
/* desc must correspond to a valid secure executing image */
|
||||||
|
assert(desc != NULL);
|
||||||
|
assert(GET_SECURITY_STATE(desc->ep_info.h.attr) == SECURE);
|
||||||
|
assert(EP_GET_EXE(desc->ep_info.h.attr) == EXECUTABLE);
|
||||||
|
assert(desc->state == IMAGE_STATE_EXECUTED);
|
||||||
|
|
||||||
|
#if ENABLE_ASSERTIONS
|
||||||
|
int rc = bl1_fwu_remove_loaded_id(sec_exec_image_id);
|
||||||
|
assert(rc == 0);
|
||||||
|
#else
|
||||||
|
bl1_fwu_remove_loaded_id(sec_exec_image_id);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Update the flags. */
|
||||||
|
desc->state = IMAGE_STATE_RESET;
|
||||||
|
sec_exec_image_id = INVALID_IMAGE_ID;
|
||||||
|
|
||||||
|
INFO("BL1-FWU: Resuming Normal world context\n");
|
||||||
|
#ifdef __aarch64__
|
||||||
|
/*
|
||||||
|
* Secure world is done so no need to save the context.
|
||||||
|
* Just restore the Non-Secure context.
|
||||||
|
*/
|
||||||
|
cm_el1_sysregs_context_restore(NON_SECURE);
|
||||||
|
|
||||||
|
/* Update the next context. */
|
||||||
|
cm_set_next_eret_context(NON_SECURE);
|
||||||
|
|
||||||
|
*handle = cm_get_context(NON_SECURE);
|
||||||
|
#else
|
||||||
|
/* Update the next context. */
|
||||||
|
cm_set_next_context(cm_get_context(NON_SECURE));
|
||||||
|
|
||||||
|
/* Prepare the smc context for the next BL image. */
|
||||||
|
smc_set_next_ctx(NON_SECURE);
|
||||||
|
|
||||||
|
*handle = smc_get_ctx(NON_SECURE);
|
||||||
|
#endif
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function provides the opportunity for users to perform any
|
||||||
|
* platform specific handling after the Firmware update is done.
|
||||||
|
******************************************************************************/
|
||||||
|
__dead2 static void bl1_fwu_done(void *client_cookie, void *reserved)
|
||||||
|
{
|
||||||
|
NOTICE("BL1-FWU: *******FWU Process Completed*******\n");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Call platform done function.
|
||||||
|
*/
|
||||||
|
bl1_plat_fwu_done(client_cookie, reserved);
|
||||||
|
assert(false);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function resets an image to IMAGE_STATE_RESET. It fails if the image is
|
||||||
|
* being executed.
|
||||||
|
******************************************************************************/
|
||||||
|
static int bl1_fwu_image_reset(unsigned int image_id, unsigned int flags)
|
||||||
|
{
|
||||||
|
image_desc_t *desc = bl1_plat_get_image_desc(image_id);
|
||||||
|
|
||||||
|
if ((desc == NULL) || (GET_SECURITY_STATE(flags) == SECURE)) {
|
||||||
|
WARN("BL1-FWU: Reset not allowed due to invalid args\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (desc->state) {
|
||||||
|
|
||||||
|
case IMAGE_STATE_RESET:
|
||||||
|
/* Nothing to do. */
|
||||||
|
break;
|
||||||
|
|
||||||
|
case IMAGE_STATE_INTERRUPTED:
|
||||||
|
case IMAGE_STATE_AUTHENTICATED:
|
||||||
|
case IMAGE_STATE_COPIED:
|
||||||
|
case IMAGE_STATE_COPYING:
|
||||||
|
|
||||||
|
if (bl1_fwu_remove_loaded_id(image_id) != 0) {
|
||||||
|
WARN("BL1-FWU: Image reset couldn't find the image ID\n");
|
||||||
|
return -EPERM;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (desc->copied_size != 0U) {
|
||||||
|
/* Clear the memory if the image is copied */
|
||||||
|
assert(GET_SECURITY_STATE(desc->ep_info.h.attr)
|
||||||
|
== SECURE);
|
||||||
|
|
||||||
|
zero_normalmem((void *)desc->image_info.image_base,
|
||||||
|
desc->copied_size);
|
||||||
|
flush_dcache_range(desc->image_info.image_base,
|
||||||
|
desc->copied_size);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Reset status variables */
|
||||||
|
desc->copied_size = 0;
|
||||||
|
desc->image_info.image_size = 0;
|
||||||
|
desc->state = IMAGE_STATE_RESET;
|
||||||
|
|
||||||
|
/* Clear authentication state */
|
||||||
|
auth_img_flags[image_id] = 0;
|
||||||
|
|
||||||
|
break;
|
||||||
|
|
||||||
|
case IMAGE_STATE_EXECUTED:
|
||||||
|
default:
|
||||||
|
assert(false); /* Unreachable */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
287
arm-trusted-firmware/bl1/bl1_main.c
Normal file
287
arm-trusted-firmware/bl1/bl1_main.c
Normal file
@@ -0,0 +1,287 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <arch_features.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <bl1/bl1.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <drivers/auth/auth_mod.h>
|
||||||
|
#include <drivers/auth/crypto_mod.h>
|
||||||
|
#include <drivers/console.h>
|
||||||
|
#include <lib/cpus/errata_report.h>
|
||||||
|
#include <lib/utils.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
#include <smccc_helpers.h>
|
||||||
|
#include <tools_share/uuid.h>
|
||||||
|
|
||||||
|
#include "bl1_private.h"
|
||||||
|
|
||||||
|
static void bl1_load_bl2(void);
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
uint64_t bl1_apiakey[2];
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Helper utility to calculate the BL2 memory layout taking into consideration
|
||||||
|
* the BL1 RW data assuming that it is at the top of the memory layout.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
|
||||||
|
meminfo_t *bl2_mem_layout)
|
||||||
|
{
|
||||||
|
assert(bl1_mem_layout != NULL);
|
||||||
|
assert(bl2_mem_layout != NULL);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Remove BL1 RW data from the scope of memory visible to BL2.
|
||||||
|
* This is assuming BL1 RW data is at the top of bl1_mem_layout.
|
||||||
|
*/
|
||||||
|
assert(BL1_RW_BASE > bl1_mem_layout->total_base);
|
||||||
|
bl2_mem_layout->total_base = bl1_mem_layout->total_base;
|
||||||
|
bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
|
||||||
|
|
||||||
|
flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Setup function for BL1.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_setup(void)
|
||||||
|
{
|
||||||
|
/* Perform early platform-specific setup */
|
||||||
|
bl1_early_platform_setup();
|
||||||
|
|
||||||
|
/* Perform late platform-specific setup */
|
||||||
|
bl1_plat_arch_setup();
|
||||||
|
|
||||||
|
#if CTX_INCLUDE_PAUTH_REGS
|
||||||
|
/*
|
||||||
|
* Assert that the ARMv8.3-PAuth registers are present or an access
|
||||||
|
* fault will be triggered when they are being saved or restored.
|
||||||
|
*/
|
||||||
|
assert(is_armv8_3_pauth_present());
|
||||||
|
#endif /* CTX_INCLUDE_PAUTH_REGS */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Function to perform late architectural and platform specific initialization.
|
||||||
|
* It also queries the platform to load and run next BL image. Only called
|
||||||
|
* by the primary cpu after a cold boot.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_main(void)
|
||||||
|
{
|
||||||
|
unsigned int image_id;
|
||||||
|
|
||||||
|
/* Announce our arrival */
|
||||||
|
NOTICE(FIRMWARE_WELCOME_STR);
|
||||||
|
NOTICE("BL1: %s\n", version_string);
|
||||||
|
NOTICE("BL1: %s\n", build_message);
|
||||||
|
|
||||||
|
INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
|
||||||
|
|
||||||
|
print_errata_status();
|
||||||
|
|
||||||
|
#if ENABLE_ASSERTIONS
|
||||||
|
u_register_t val;
|
||||||
|
/*
|
||||||
|
* Ensure that MMU/Caches and coherency are turned on
|
||||||
|
*/
|
||||||
|
#ifdef __aarch64__
|
||||||
|
val = read_sctlr_el3();
|
||||||
|
#else
|
||||||
|
val = read_sctlr();
|
||||||
|
#endif
|
||||||
|
assert((val & SCTLR_M_BIT) != 0);
|
||||||
|
assert((val & SCTLR_C_BIT) != 0);
|
||||||
|
assert((val & SCTLR_I_BIT) != 0);
|
||||||
|
/*
|
||||||
|
* Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
|
||||||
|
* provided platform value
|
||||||
|
*/
|
||||||
|
val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
|
||||||
|
/*
|
||||||
|
* If CWG is zero, then no CWG information is available but we can
|
||||||
|
* at least check the platform value is less than the architectural
|
||||||
|
* maximum.
|
||||||
|
*/
|
||||||
|
if (val != 0)
|
||||||
|
assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
|
||||||
|
else
|
||||||
|
assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
|
||||||
|
#endif /* ENABLE_ASSERTIONS */
|
||||||
|
|
||||||
|
/* Perform remaining generic architectural setup from EL3 */
|
||||||
|
bl1_arch_setup();
|
||||||
|
|
||||||
|
crypto_mod_init();
|
||||||
|
|
||||||
|
/* Initialize authentication module */
|
||||||
|
auth_mod_init();
|
||||||
|
|
||||||
|
/* Initialize the measured boot */
|
||||||
|
bl1_plat_mboot_init();
|
||||||
|
|
||||||
|
/* Perform platform setup in BL1. */
|
||||||
|
bl1_platform_setup();
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* Store APIAKey_EL1 key */
|
||||||
|
bl1_apiakey[0] = read_apiakeylo_el1();
|
||||||
|
bl1_apiakey[1] = read_apiakeyhi_el1();
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/* Get the image id of next image to load and run. */
|
||||||
|
image_id = bl1_plat_get_next_image_id();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We currently interpret any image id other than
|
||||||
|
* BL2_IMAGE_ID as the start of firmware update.
|
||||||
|
*/
|
||||||
|
if (image_id == BL2_IMAGE_ID)
|
||||||
|
bl1_load_bl2();
|
||||||
|
else
|
||||||
|
NOTICE("BL1-FWU: *******FWU Process Started*******\n");
|
||||||
|
|
||||||
|
/* Teardown the measured boot driver */
|
||||||
|
bl1_plat_mboot_finish();
|
||||||
|
|
||||||
|
bl1_prepare_next_image(image_id);
|
||||||
|
|
||||||
|
console_flush();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function locates and loads the BL2 raw binary image in the trusted SRAM.
|
||||||
|
* Called by the primary cpu after a cold boot.
|
||||||
|
* TODO: Add support for alternative image load mechanism e.g using virtio/elf
|
||||||
|
* loader etc.
|
||||||
|
******************************************************************************/
|
||||||
|
static void bl1_load_bl2(void)
|
||||||
|
{
|
||||||
|
image_desc_t *desc;
|
||||||
|
image_info_t *info;
|
||||||
|
int err;
|
||||||
|
|
||||||
|
/* Get the image descriptor */
|
||||||
|
desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
|
||||||
|
assert(desc != NULL);
|
||||||
|
|
||||||
|
/* Get the image info */
|
||||||
|
info = &desc->image_info;
|
||||||
|
INFO("BL1: Loading BL2\n");
|
||||||
|
|
||||||
|
err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
|
||||||
|
if (err != 0) {
|
||||||
|
ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
|
||||||
|
plat_error_handler(err);
|
||||||
|
}
|
||||||
|
|
||||||
|
err = load_auth_image(BL2_IMAGE_ID, info);
|
||||||
|
if (err != 0) {
|
||||||
|
ERROR("Failed to load BL2 firmware.\n");
|
||||||
|
plat_error_handler(err);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allow platform to handle image information. */
|
||||||
|
err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
|
||||||
|
if (err != 0) {
|
||||||
|
ERROR("Failure in post image load handling of BL2 (%d)\n", err);
|
||||||
|
plat_error_handler(err);
|
||||||
|
}
|
||||||
|
|
||||||
|
NOTICE("BL1: Booting BL2\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Function called just before handing over to the next BL to inform the user
|
||||||
|
* about the boot progress. In debug mode, also print details about the BL
|
||||||
|
* image's execution context.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
|
||||||
|
{
|
||||||
|
#ifdef __aarch64__
|
||||||
|
NOTICE("BL1: Booting BL31\n");
|
||||||
|
#else
|
||||||
|
NOTICE("BL1: Booting BL32\n");
|
||||||
|
#endif /* __aarch64__ */
|
||||||
|
print_entry_point_info(bl_ep_info);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if SPIN_ON_BL1_EXIT
|
||||||
|
void print_debug_loop_message(void)
|
||||||
|
{
|
||||||
|
NOTICE("BL1: Debug loop, spinning forever\n");
|
||||||
|
NOTICE("BL1: Please connect the debugger to continue\n");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Top level handler for servicing BL1 SMCs.
|
||||||
|
******************************************************************************/
|
||||||
|
u_register_t bl1_smc_handler(unsigned int smc_fid,
|
||||||
|
u_register_t x1,
|
||||||
|
u_register_t x2,
|
||||||
|
u_register_t x3,
|
||||||
|
u_register_t x4,
|
||||||
|
void *cookie,
|
||||||
|
void *handle,
|
||||||
|
unsigned int flags)
|
||||||
|
{
|
||||||
|
/* BL1 Service UUID */
|
||||||
|
DEFINE_SVC_UUID2(bl1_svc_uid,
|
||||||
|
U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75,
|
||||||
|
0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
|
||||||
|
|
||||||
|
|
||||||
|
#if TRUSTED_BOARD_BOOT
|
||||||
|
/*
|
||||||
|
* Dispatch FWU calls to FWU SMC handler and return its return
|
||||||
|
* value
|
||||||
|
*/
|
||||||
|
if (is_fwu_fid(smc_fid)) {
|
||||||
|
return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
|
||||||
|
handle, flags);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
switch (smc_fid) {
|
||||||
|
case BL1_SMC_CALL_COUNT:
|
||||||
|
SMC_RET1(handle, BL1_NUM_SMC_CALLS);
|
||||||
|
|
||||||
|
case BL1_SMC_UID:
|
||||||
|
SMC_UUID_RET(handle, bl1_svc_uid);
|
||||||
|
|
||||||
|
case BL1_SMC_VERSION:
|
||||||
|
SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
|
||||||
|
|
||||||
|
default:
|
||||||
|
WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid);
|
||||||
|
SMC_RET1(handle, SMC_UNK);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
|
||||||
|
* compliance when invoking bl1_smc_handler.
|
||||||
|
******************************************************************************/
|
||||||
|
u_register_t bl1_smc_wrapper(uint32_t smc_fid,
|
||||||
|
void *cookie,
|
||||||
|
void *handle,
|
||||||
|
unsigned int flags)
|
||||||
|
{
|
||||||
|
u_register_t x1, x2, x3, x4;
|
||||||
|
|
||||||
|
assert(handle != NULL);
|
||||||
|
|
||||||
|
get_smc_params_from_ctx(handle, x1, x2, x3, x4);
|
||||||
|
return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
|
||||||
|
}
|
||||||
34
arm-trusted-firmware/bl1/bl1_private.h
Normal file
34
arm-trusted-firmware/bl1/bl1_private.h
Normal file
@@ -0,0 +1,34 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef BL1_PRIVATE_H
|
||||||
|
#define BL1_PRIVATE_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
extern entry_point_info_t *bl2_ep_info;
|
||||||
|
|
||||||
|
/******************************************
|
||||||
|
* Function prototypes
|
||||||
|
*****************************************/
|
||||||
|
void bl1_arch_setup(void);
|
||||||
|
void bl1_arch_next_el_setup(void);
|
||||||
|
|
||||||
|
void bl1_prepare_next_image(unsigned int image_id);
|
||||||
|
void bl1_run_bl2_in_root(void);
|
||||||
|
|
||||||
|
u_register_t bl1_fwu_smc_handler(unsigned int smc_fid,
|
||||||
|
u_register_t x1,
|
||||||
|
u_register_t x2,
|
||||||
|
u_register_t x3,
|
||||||
|
u_register_t x4,
|
||||||
|
void *cookie,
|
||||||
|
void *handle,
|
||||||
|
unsigned int flags);
|
||||||
|
|
||||||
|
#endif /* BL1_PRIVATE_H */
|
||||||
65
arm-trusted-firmware/bl1/tbbr/tbbr_img_desc.c
Normal file
65
arm-trusted-firmware/bl1/tbbr/tbbr_img_desc.c
Normal file
@@ -0,0 +1,65 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <bl1/tbbr/tbbr_img_desc.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
image_desc_t bl1_tbbr_image_descs[] = {
|
||||||
|
{
|
||||||
|
.image_id = FWU_CERT_ID,
|
||||||
|
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
|
||||||
|
VERSION_1, image_info_t, 0),
|
||||||
|
.image_info.image_base = BL2_BASE,
|
||||||
|
.image_info.image_max_size = BL2_LIMIT - BL2_BASE,
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
|
||||||
|
VERSION_1, entry_point_info_t, SECURE),
|
||||||
|
},
|
||||||
|
#if NS_BL1U_BASE
|
||||||
|
{
|
||||||
|
.image_id = NS_BL1U_IMAGE_ID,
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||||
|
VERSION_1, entry_point_info_t, NON_SECURE | EXECUTABLE),
|
||||||
|
.ep_info.pc = NS_BL1U_BASE,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if SCP_BL2U_BASE
|
||||||
|
{
|
||||||
|
.image_id = SCP_BL2U_IMAGE_ID,
|
||||||
|
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
|
||||||
|
VERSION_1, image_info_t, 0),
|
||||||
|
.image_info.image_base = SCP_BL2U_BASE,
|
||||||
|
.image_info.image_max_size = SCP_BL2U_LIMIT - SCP_BL2U_BASE,
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
|
||||||
|
VERSION_1, entry_point_info_t, SECURE),
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if BL2U_BASE
|
||||||
|
{
|
||||||
|
.image_id = BL2U_IMAGE_ID,
|
||||||
|
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||||
|
VERSION_1, image_info_t, 0),
|
||||||
|
.image_info.image_base = BL2U_BASE,
|
||||||
|
.image_info.image_max_size = BL2U_LIMIT - BL2U_BASE,
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||||
|
VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),
|
||||||
|
.ep_info.pc = BL2U_BASE,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if NS_BL2U_BASE
|
||||||
|
{
|
||||||
|
.image_id = NS_BL2U_IMAGE_ID,
|
||||||
|
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||||
|
VERSION_1, entry_point_info_t, NON_SECURE),
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
BL2_IMAGE_DESC,
|
||||||
|
|
||||||
|
{
|
||||||
|
.image_id = INVALID_IMAGE_ID,
|
||||||
|
}
|
||||||
|
};
|
||||||
16
arm-trusted-firmware/bl2/aarch32/bl2_arch_setup.c
Normal file
16
arm-trusted-firmware/bl2/aarch32/bl2_arch_setup.c
Normal file
@@ -0,0 +1,16 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "../bl2_private.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Place holder function to perform any Secure SVC specific architectural
|
||||||
|
* setup. At the moment there is nothing to do.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl2_arch_setup(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
57
arm-trusted-firmware/bl2/aarch32/bl2_el3_entrypoint.S
Normal file
57
arm-trusted-firmware/bl2/aarch32/bl2_el3_entrypoint.S
Normal file
@@ -0,0 +1,57 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <el3_common_macros.S>
|
||||||
|
|
||||||
|
.globl bl2_entrypoint
|
||||||
|
|
||||||
|
|
||||||
|
func bl2_entrypoint
|
||||||
|
/* Save arguments x0-x3 from previous Boot loader */
|
||||||
|
mov r9, r0
|
||||||
|
mov r10, r1
|
||||||
|
mov r11, r2
|
||||||
|
mov r12, r3
|
||||||
|
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=1 \
|
||||||
|
_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
|
||||||
|
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
|
||||||
|
_init_memory=1 \
|
||||||
|
_init_c_runtime=1 \
|
||||||
|
_exception_vectors=bl2_vector_table \
|
||||||
|
_pie_fixup_size=0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Restore parameters of boot rom
|
||||||
|
*/
|
||||||
|
mov r0, r9
|
||||||
|
mov r1, r10
|
||||||
|
mov r2, r11
|
||||||
|
mov r3, r12
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Perform BL2 setup
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2_el3_setup
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Jump to main function.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2_main
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Should never reach this point.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
|
||||||
|
endfunc bl2_entrypoint
|
||||||
21
arm-trusted-firmware/bl2/aarch32/bl2_el3_exceptions.S
Normal file
21
arm-trusted-firmware/bl2/aarch32/bl2_el3_exceptions.S
Normal file
@@ -0,0 +1,21 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
.globl bl2_vector_table
|
||||||
|
|
||||||
|
vector_base bl2_vector_table
|
||||||
|
b bl2_entrypoint
|
||||||
|
b report_exception /* Undef */
|
||||||
|
b report_exception /* SVC call */
|
||||||
|
b report_prefetch_abort /* Prefetch abort */
|
||||||
|
b report_data_abort /* Data abort */
|
||||||
|
b report_exception /* Reserved */
|
||||||
|
b report_exception /* IRQ */
|
||||||
|
b report_exception /* FIQ */
|
||||||
136
arm-trusted-firmware/bl2/aarch32/bl2_entrypoint.S
Normal file
136
arm-trusted-firmware/bl2/aarch32/bl2_entrypoint.S
Normal file
@@ -0,0 +1,136 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
.globl bl2_vector_table
|
||||||
|
.globl bl2_entrypoint
|
||||||
|
|
||||||
|
|
||||||
|
vector_base bl2_vector_table
|
||||||
|
b bl2_entrypoint
|
||||||
|
b report_exception /* Undef */
|
||||||
|
b report_exception /* SVC call */
|
||||||
|
b report_prefetch_abort /* Prefetch abort */
|
||||||
|
b report_data_abort /* Data abort */
|
||||||
|
b report_exception /* Reserved */
|
||||||
|
b report_exception /* IRQ */
|
||||||
|
b report_exception /* FIQ */
|
||||||
|
|
||||||
|
|
||||||
|
func bl2_entrypoint
|
||||||
|
/*---------------------------------------------
|
||||||
|
* Save arguments x0 - x3 from BL1 for future
|
||||||
|
* use.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov r9, r0
|
||||||
|
mov r10, r1
|
||||||
|
mov r11, r2
|
||||||
|
mov r12, r3
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Set the exception vector to something sane.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
ldr r0, =bl2_vector_table
|
||||||
|
stcopr r0, VBAR
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* --------------------------------------------------------
|
||||||
|
* Enable the instruction cache - disable speculative loads
|
||||||
|
* --------------------------------------------------------
|
||||||
|
*/
|
||||||
|
ldcopr r0, SCTLR
|
||||||
|
orr r0, r0, #SCTLR_I_BIT
|
||||||
|
bic r0, r0, #SCTLR_DSSBS_BIT
|
||||||
|
stcopr r0, SCTLR
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Since BL2 executes after BL1, it is assumed
|
||||||
|
* here that BL1 has already has done the
|
||||||
|
* necessary register initializations.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Invalidate the RW memory used by the BL2
|
||||||
|
* image. This includes the data and NOBITS
|
||||||
|
* sections. This is done to safeguard against
|
||||||
|
* possible corruption of this memory by dirty
|
||||||
|
* cache lines in a system cache as a result of
|
||||||
|
* use by an earlier boot loader stage.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
ldr r0, =__RW_START__
|
||||||
|
ldr r1, =__RW_END__
|
||||||
|
sub r1, r1, r0
|
||||||
|
bl inv_dcache_range
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Zero out NOBITS sections. There are 2 of them:
|
||||||
|
* - the .bss section;
|
||||||
|
* - the coherent memory section.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
ldr r0, =__BSS_START__
|
||||||
|
ldr r1, =__BSS_END__
|
||||||
|
sub r1, r1, r0
|
||||||
|
bl zeromem
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
ldr r0, =__COHERENT_RAM_START__
|
||||||
|
ldr r1, =__COHERENT_RAM_END_UNALIGNED__
|
||||||
|
sub r1, r1, r0
|
||||||
|
bl zeromem
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* --------------------------------------------
|
||||||
|
* Allocate a stack whose memory will be marked
|
||||||
|
* as Normal-IS-WBWA when the MMU is enabled.
|
||||||
|
* There is no risk of reading stale stack
|
||||||
|
* memory after enabling the MMU as only the
|
||||||
|
* primary cpu is running at the moment.
|
||||||
|
* --------------------------------------------
|
||||||
|
*/
|
||||||
|
bl plat_set_my_stack
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Initialize the stack protector canary before
|
||||||
|
* any C code is called.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
#if STACK_PROTECTOR_ENABLED
|
||||||
|
bl update_stack_protector_canary
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Perform BL2 setup
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov r0, r9
|
||||||
|
mov r1, r10
|
||||||
|
mov r2, r11
|
||||||
|
mov r3, r12
|
||||||
|
|
||||||
|
bl bl2_setup
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Jump to main function.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2_main
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Should never reach this point.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
|
||||||
|
endfunc bl2_entrypoint
|
||||||
46
arm-trusted-firmware/bl2/aarch32/bl2_run_next_image.S
Normal file
46
arm-trusted-firmware/bl2/aarch32/bl2_run_next_image.S
Normal file
@@ -0,0 +1,46 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
.globl bl2_run_next_image
|
||||||
|
|
||||||
|
|
||||||
|
func bl2_run_next_image
|
||||||
|
mov r8,r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MMU needs to be disabled because both BL2 and BL32 execute
|
||||||
|
* in PL1, and therefore share the same address space.
|
||||||
|
* BL32 will initialize the address space according to its
|
||||||
|
* own requirement.
|
||||||
|
*/
|
||||||
|
bl disable_mmu_icache_secure
|
||||||
|
stcopr r0, TLBIALL
|
||||||
|
dsb sy
|
||||||
|
isb
|
||||||
|
mov r0, r8
|
||||||
|
bl bl2_el3_plat_prepare_exit
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Extract PC and SPSR based on struct `entry_point_info_t`
|
||||||
|
* and load it in LR and SPSR registers respectively.
|
||||||
|
*/
|
||||||
|
ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
|
||||||
|
ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
|
||||||
|
msr spsr_xc, r1
|
||||||
|
|
||||||
|
/* Some BL32 stages expect lr_svc to provide the BL33 entry address */
|
||||||
|
cps #MODE32_svc
|
||||||
|
ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET]
|
||||||
|
cps #MODE32_mon
|
||||||
|
|
||||||
|
add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
|
||||||
|
ldm r8, {r0, r1, r2, r3}
|
||||||
|
exception_return
|
||||||
|
endfunc bl2_run_next_image
|
||||||
19
arm-trusted-firmware/bl2/aarch64/bl2_arch_setup.c
Normal file
19
arm-trusted-firmware/bl2/aarch64/bl2_arch_setup.c
Normal file
@@ -0,0 +1,19 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include "../bl2_private.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Place holder function to perform any S-EL1 specific architectural setup. At
|
||||||
|
* the moment there is nothing to do.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl2_arch_setup(void)
|
||||||
|
{
|
||||||
|
/* Give access to FP/SIMD registers */
|
||||||
|
write_cpacr(CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
|
||||||
|
}
|
||||||
72
arm-trusted-firmware/bl2/aarch64/bl2_el3_entrypoint.S
Normal file
72
arm-trusted-firmware/bl2/aarch64/bl2_el3_entrypoint.S
Normal file
@@ -0,0 +1,72 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <el3_common_macros.S>
|
||||||
|
|
||||||
|
.globl bl2_entrypoint
|
||||||
|
|
||||||
|
#if BL2_IN_XIP_MEM
|
||||||
|
#define FIXUP_SIZE 0
|
||||||
|
#else
|
||||||
|
#define FIXUP_SIZE ((BL2_LIMIT) - (BL2_BASE))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
func bl2_entrypoint
|
||||||
|
/* Save arguments x0-x3 from previous Boot loader */
|
||||||
|
mov x20, x0
|
||||||
|
mov x21, x1
|
||||||
|
mov x22, x2
|
||||||
|
mov x23, x3
|
||||||
|
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=1 \
|
||||||
|
_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
|
||||||
|
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
|
||||||
|
_init_memory=1 \
|
||||||
|
_init_c_runtime=1 \
|
||||||
|
_exception_vectors=bl2_el3_exceptions \
|
||||||
|
_pie_fixup_size=FIXUP_SIZE
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Restore parameters of boot rom
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x0, x20
|
||||||
|
mov x1, x21
|
||||||
|
mov x2, x22
|
||||||
|
mov x3, x23
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Perform BL2 setup
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2_el3_setup
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Program APIAKey_EL1 and enable pointer authentication.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_init_enable_el3
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Jump to main function.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2_main
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Should never reach this point.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc bl2_entrypoint
|
||||||
131
arm-trusted-firmware/bl2/aarch64/bl2_el3_exceptions.S
Normal file
131
arm-trusted-firmware/bl2/aarch64/bl2_el3_exceptions.S
Normal file
@@ -0,0 +1,131 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <bl1/bl1.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <context.h>
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------------------------
|
||||||
|
* Very simple stackless exception handlers used by BL2.
|
||||||
|
* -----------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
.globl bl2_el3_exceptions
|
||||||
|
|
||||||
|
vector_base bl2_el3_exceptions
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Current EL with SP0 : 0x0 - 0x200
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionSP0
|
||||||
|
mov x0, #SYNC_EXCEPTION_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionSP0
|
||||||
|
|
||||||
|
vector_entry IrqSP0
|
||||||
|
mov x0, #IRQ_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqSP0
|
||||||
|
|
||||||
|
vector_entry FiqSP0
|
||||||
|
mov x0, #FIQ_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqSP0
|
||||||
|
|
||||||
|
vector_entry SErrorSP0
|
||||||
|
mov x0, #SERROR_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorSP0
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Current EL with SPx: 0x200 - 0x400
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionSPx
|
||||||
|
mov x0, #SYNC_EXCEPTION_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionSPx
|
||||||
|
|
||||||
|
vector_entry IrqSPx
|
||||||
|
mov x0, #IRQ_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqSPx
|
||||||
|
|
||||||
|
vector_entry FiqSPx
|
||||||
|
mov x0, #FIQ_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqSPx
|
||||||
|
|
||||||
|
vector_entry SErrorSPx
|
||||||
|
mov x0, #SERROR_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorSPx
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Lower EL using AArch64 : 0x400 - 0x600
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionA64
|
||||||
|
mov x0, #SYNC_EXCEPTION_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionA64
|
||||||
|
|
||||||
|
vector_entry IrqA64
|
||||||
|
mov x0, #IRQ_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqA64
|
||||||
|
|
||||||
|
vector_entry FiqA64
|
||||||
|
mov x0, #FIQ_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqA64
|
||||||
|
|
||||||
|
vector_entry SErrorA64
|
||||||
|
mov x0, #SERROR_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorA64
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Lower EL using AArch32 : 0x600 - 0x800
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionA32
|
||||||
|
mov x0, #SYNC_EXCEPTION_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionA32
|
||||||
|
|
||||||
|
vector_entry IrqA32
|
||||||
|
mov x0, #IRQ_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqA32
|
||||||
|
|
||||||
|
vector_entry FiqA32
|
||||||
|
mov x0, #FIQ_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqA32
|
||||||
|
|
||||||
|
vector_entry SErrorA32
|
||||||
|
mov x0, #SERROR_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorA32
|
||||||
141
arm-trusted-firmware/bl2/aarch64/bl2_entrypoint.S
Normal file
141
arm-trusted-firmware/bl2/aarch64/bl2_entrypoint.S
Normal file
@@ -0,0 +1,141 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
|
||||||
|
.globl bl2_entrypoint
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
func bl2_entrypoint
|
||||||
|
/*---------------------------------------------
|
||||||
|
* Save arguments x0 - x3 from BL1 for future
|
||||||
|
* use.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x20, x0
|
||||||
|
mov x21, x1
|
||||||
|
mov x22, x2
|
||||||
|
mov x23, x3
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Set the exception vector to something sane.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
adr x0, early_exceptions
|
||||||
|
msr vbar_el1, x0
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Enable the SError interrupt now that the
|
||||||
|
* exception vectors have been setup.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Enable the instruction cache, stack pointer
|
||||||
|
* and data access alignment checks and disable
|
||||||
|
* speculative loads.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
|
||||||
|
mrs x0, sctlr_el1
|
||||||
|
orr x0, x0, x1
|
||||||
|
bic x0, x0, #SCTLR_DSSBS_BIT
|
||||||
|
msr sctlr_el1, x0
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Invalidate the RW memory used by the BL2
|
||||||
|
* image. This includes the data and NOBITS
|
||||||
|
* sections. This is done to safeguard against
|
||||||
|
* possible corruption of this memory by dirty
|
||||||
|
* cache lines in a system cache as a result of
|
||||||
|
* use by an earlier boot loader stage.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
adr x0, __RW_START__
|
||||||
|
adr x1, __RW_END__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl inv_dcache_range
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Zero out NOBITS sections. There are 2 of them:
|
||||||
|
* - the .bss section;
|
||||||
|
* - the coherent memory section.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
adrp x0, __BSS_START__
|
||||||
|
add x0, x0, :lo12:__BSS_START__
|
||||||
|
adrp x1, __BSS_END__
|
||||||
|
add x1, x1, :lo12:__BSS_END__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl zeromem
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
adrp x0, __COHERENT_RAM_START__
|
||||||
|
add x0, x0, :lo12:__COHERENT_RAM_START__
|
||||||
|
adrp x1, __COHERENT_RAM_END_UNALIGNED__
|
||||||
|
add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl zeromem
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* --------------------------------------------
|
||||||
|
* Allocate a stack whose memory will be marked
|
||||||
|
* as Normal-IS-WBWA when the MMU is enabled.
|
||||||
|
* There is no risk of reading stale stack
|
||||||
|
* memory after enabling the MMU as only the
|
||||||
|
* primary cpu is running at the moment.
|
||||||
|
* --------------------------------------------
|
||||||
|
*/
|
||||||
|
bl plat_set_my_stack
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Initialize the stack protector canary before
|
||||||
|
* any C code is called.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
#if STACK_PROTECTOR_ENABLED
|
||||||
|
bl update_stack_protector_canary
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Perform BL2 setup
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x0, x20
|
||||||
|
mov x1, x21
|
||||||
|
mov x2, x22
|
||||||
|
mov x3, x23
|
||||||
|
bl bl2_setup
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Program APIAKey_EL1
|
||||||
|
* and enable pointer authentication.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_init_enable_el1
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Jump to main function.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2_main
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Should never reach this point.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
|
||||||
|
endfunc bl2_entrypoint
|
||||||
67
arm-trusted-firmware/bl2/aarch64/bl2_rme_entrypoint.S
Normal file
67
arm-trusted-firmware/bl2/aarch64/bl2_rme_entrypoint.S
Normal file
@@ -0,0 +1,67 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <el3_common_macros.S>
|
||||||
|
|
||||||
|
.globl bl2_entrypoint
|
||||||
|
|
||||||
|
|
||||||
|
func bl2_entrypoint
|
||||||
|
/* Save arguments x0-x3 from previous Boot loader */
|
||||||
|
mov x20, x0
|
||||||
|
mov x21, x1
|
||||||
|
mov x22, x2
|
||||||
|
mov x23, x3
|
||||||
|
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=0 \
|
||||||
|
_warm_boot_mailbox=0 \
|
||||||
|
_secondary_cold_boot=0 \
|
||||||
|
_init_memory=0 \
|
||||||
|
_init_c_runtime=1 \
|
||||||
|
_exception_vectors=bl2_el3_exceptions \
|
||||||
|
_pie_fixup_size=0
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Restore parameters of boot rom
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x0, x20
|
||||||
|
mov x1, x21
|
||||||
|
mov x2, x22
|
||||||
|
mov x3, x23
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Perform BL2 setup
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2_setup
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Program APIAKey_EL1 and enable pointer authentication.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_init_enable_el3
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Jump to main function.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2_main
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Should never reach this point.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc bl2_entrypoint
|
||||||
45
arm-trusted-firmware/bl2/aarch64/bl2_run_next_image.S
Normal file
45
arm-trusted-firmware/bl2/aarch64/bl2_run_next_image.S
Normal file
@@ -0,0 +1,45 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
.globl bl2_run_next_image
|
||||||
|
|
||||||
|
|
||||||
|
func bl2_run_next_image
|
||||||
|
mov x20,x0
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* MMU needs to be disabled because both BL2 and BL31 execute
|
||||||
|
* in EL3, and therefore share the same address space.
|
||||||
|
* BL31 will initialize the address space according to its
|
||||||
|
* own requirement.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl disable_mmu_icache_el3
|
||||||
|
tlbi alle3
|
||||||
|
bl bl2_el3_plat_prepare_exit
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Disable pointer authentication before jumping
|
||||||
|
* to next boot image.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_disable_el3
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
|
||||||
|
msr elr_el3, x0
|
||||||
|
msr spsr_el3, x1
|
||||||
|
|
||||||
|
ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
|
||||||
|
ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
|
||||||
|
ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
|
||||||
|
ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
|
||||||
|
exception_return
|
||||||
|
endfunc bl2_run_next_image
|
||||||
125
arm-trusted-firmware/bl2/bl2.ld.S
Normal file
125
arm-trusted-firmware/bl2/bl2.ld.S
Normal file
@@ -0,0 +1,125 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common/bl_common.ld.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
|
||||||
|
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
|
||||||
|
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
|
||||||
|
ENTRY(bl2_entrypoint)
|
||||||
|
|
||||||
|
MEMORY {
|
||||||
|
RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = BL2_BASE;
|
||||||
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
||||||
|
"BL2_BASE address is not aligned on a page boundary.")
|
||||||
|
|
||||||
|
#if SEPARATE_CODE_AND_RODATA
|
||||||
|
.text . : {
|
||||||
|
__TEXT_START__ = .;
|
||||||
|
#if ENABLE_RME
|
||||||
|
*bl2_rme_entrypoint.o(.text*)
|
||||||
|
#else /* ENABLE_RME */
|
||||||
|
*bl2_entrypoint.o(.text*)
|
||||||
|
#endif /* ENABLE_RME */
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(.vectors)
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__TEXT_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* .ARM.extab and .ARM.exidx are only added because Clang need them */
|
||||||
|
.ARM.extab . : {
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
.ARM.exidx . : {
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
.rodata . : {
|
||||||
|
__RODATA_START__ = .;
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RODATA_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#else
|
||||||
|
ro . : {
|
||||||
|
__RO_START__ = .;
|
||||||
|
*bl2_entrypoint.o(.text*)
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
*(.vectors)
|
||||||
|
__RO_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked as
|
||||||
|
* read-only, executable. No RW data from the next section must
|
||||||
|
* creep in. Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RO_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark start of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_START__ = . ;
|
||||||
|
|
||||||
|
DATA_SECTION >RAM
|
||||||
|
STACK_SECTION >RAM
|
||||||
|
BSS_SECTION >RAM
|
||||||
|
XLAT_TABLE_SECTION >RAM
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
/*
|
||||||
|
* The base address of the coherent memory section must be page-aligned (4K)
|
||||||
|
* to guarantee that the coherent data are stored on their own pages and
|
||||||
|
* are not mixed with normal data. This is required to set up the correct
|
||||||
|
* memory attributes for the coherent data page tables.
|
||||||
|
*/
|
||||||
|
coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
|
||||||
|
__COHERENT_RAM_START__ = .;
|
||||||
|
*(tzfw_coherent_mem)
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked
|
||||||
|
* as device memory. No other unexpected data must creep in.
|
||||||
|
* Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__COHERENT_RAM_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark end of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_END__ = .;
|
||||||
|
__BL2_END__ = .;
|
||||||
|
|
||||||
|
__BSS_SIZE__ = SIZEOF(.bss);
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
__COHERENT_RAM_UNALIGNED_SIZE__ =
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
|
||||||
|
}
|
||||||
50
arm-trusted-firmware/bl2/bl2.mk
Normal file
50
arm-trusted-firmware/bl2/bl2.mk
Normal file
@@ -0,0 +1,50 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
|
||||||
|
BL2_SOURCES += bl2/bl2_image_load_v2.c \
|
||||||
|
bl2/bl2_main.c \
|
||||||
|
bl2/${ARCH}/bl2_arch_setup.c \
|
||||||
|
lib/locks/exclusive/${ARCH}/spinlock.S \
|
||||||
|
plat/common/${ARCH}/platform_up_stack.S \
|
||||||
|
${MBEDTLS_SOURCES}
|
||||||
|
|
||||||
|
ifeq (${ARCH},aarch64)
|
||||||
|
BL2_SOURCES += common/aarch64/early_exceptions.S
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_RME},1)
|
||||||
|
# Using RME, run BL2 at EL3
|
||||||
|
include lib/gpt_rme/gpt_rme.mk
|
||||||
|
|
||||||
|
BL2_SOURCES += bl2/${ARCH}/bl2_rme_entrypoint.S \
|
||||||
|
bl2/${ARCH}/bl2_el3_exceptions.S \
|
||||||
|
bl2/${ARCH}/bl2_run_next_image.S \
|
||||||
|
${GPT_LIB_SRCS}
|
||||||
|
BL2_LINKERFILE := bl2/bl2.ld.S
|
||||||
|
|
||||||
|
else ifeq (${BL2_AT_EL3},0)
|
||||||
|
# Normal operation, no RME, no BL2 at EL3
|
||||||
|
BL2_SOURCES += bl2/${ARCH}/bl2_entrypoint.S
|
||||||
|
BL2_LINKERFILE := bl2/bl2.ld.S
|
||||||
|
|
||||||
|
else
|
||||||
|
# BL2 at EL3, no RME
|
||||||
|
BL2_SOURCES += bl2/${ARCH}/bl2_el3_entrypoint.S \
|
||||||
|
bl2/${ARCH}/bl2_el3_exceptions.S \
|
||||||
|
bl2/${ARCH}/bl2_run_next_image.S \
|
||||||
|
lib/cpus/${ARCH}/cpu_helpers.S \
|
||||||
|
lib/cpus/errata_report.c
|
||||||
|
|
||||||
|
ifeq (${DISABLE_MTPMU},1)
|
||||||
|
BL2_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ARCH},aarch64)
|
||||||
|
BL2_SOURCES += lib/cpus/aarch64/dsu_helpers.S
|
||||||
|
endif
|
||||||
|
|
||||||
|
BL2_LINKERFILE := bl2/bl2_el3.ld.S
|
||||||
|
endif
|
||||||
187
arm-trusted-firmware/bl2/bl2_el3.ld.S
Normal file
187
arm-trusted-firmware/bl2/bl2_el3.ld.S
Normal file
@@ -0,0 +1,187 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common/bl_common.ld.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
|
||||||
|
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
|
||||||
|
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
|
||||||
|
ENTRY(bl2_entrypoint)
|
||||||
|
|
||||||
|
MEMORY {
|
||||||
|
#if BL2_IN_XIP_MEM
|
||||||
|
ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
|
||||||
|
RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
|
||||||
|
#else
|
||||||
|
RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
|
||||||
|
#endif
|
||||||
|
#if SEPARATE_BL2_NOLOAD_REGION
|
||||||
|
RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START
|
||||||
|
#else
|
||||||
|
#define RAM_NOLOAD RAM
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#if !BL2_IN_XIP_MEM
|
||||||
|
#define ROM RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
#if BL2_IN_XIP_MEM
|
||||||
|
. = BL2_RO_BASE;
|
||||||
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
||||||
|
"BL2_RO_BASE address is not aligned on a page boundary.")
|
||||||
|
#else
|
||||||
|
. = BL2_BASE;
|
||||||
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
||||||
|
"BL2_BASE address is not aligned on a page boundary.")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if SEPARATE_CODE_AND_RODATA
|
||||||
|
.text . : {
|
||||||
|
__TEXT_START__ = .;
|
||||||
|
__TEXT_RESIDENT_START__ = .;
|
||||||
|
*bl2_el3_entrypoint.o(.text*)
|
||||||
|
*(.text.asm.*)
|
||||||
|
__TEXT_RESIDENT_END__ = .;
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(.vectors)
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__TEXT_END__ = .;
|
||||||
|
} >ROM
|
||||||
|
|
||||||
|
.rodata . : {
|
||||||
|
__RODATA_START__ = .;
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RODATA_END__ = .;
|
||||||
|
} >ROM
|
||||||
|
|
||||||
|
ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
|
||||||
|
"Resident part of BL2 has exceeded its limit.")
|
||||||
|
#else
|
||||||
|
ro . : {
|
||||||
|
__RO_START__ = .;
|
||||||
|
__TEXT_RESIDENT_START__ = .;
|
||||||
|
*bl2_el3_entrypoint.o(.text*)
|
||||||
|
*(.text.asm.*)
|
||||||
|
__TEXT_RESIDENT_END__ = .;
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
*(.vectors)
|
||||||
|
__RO_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked as
|
||||||
|
* read-only, executable. No RW data from the next section must
|
||||||
|
* creep in. Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
|
||||||
|
__RO_END__ = .;
|
||||||
|
} >ROM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
|
||||||
|
"cpu_ops not defined for this platform.")
|
||||||
|
|
||||||
|
#if BL2_IN_XIP_MEM
|
||||||
|
. = BL2_RW_BASE;
|
||||||
|
ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
|
||||||
|
"BL2_RW_BASE address is not aligned on a page boundary.")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark start of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_START__ = . ;
|
||||||
|
|
||||||
|
DATA_SECTION >RAM AT>ROM
|
||||||
|
__DATA_RAM_START__ = __DATA_START__;
|
||||||
|
__DATA_RAM_END__ = __DATA_END__;
|
||||||
|
|
||||||
|
RELA_SECTION >RAM
|
||||||
|
#if SEPARATE_BL2_NOLOAD_REGION
|
||||||
|
SAVED_ADDR = .;
|
||||||
|
. = BL2_NOLOAD_START;
|
||||||
|
__BL2_NOLOAD_START__ = .;
|
||||||
|
#endif
|
||||||
|
STACK_SECTION >RAM_NOLOAD
|
||||||
|
BSS_SECTION >RAM_NOLOAD
|
||||||
|
XLAT_TABLE_SECTION >RAM_NOLOAD
|
||||||
|
#if SEPARATE_BL2_NOLOAD_REGION
|
||||||
|
__BL2_NOLOAD_END__ = .;
|
||||||
|
. = SAVED_ADDR;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
/*
|
||||||
|
* The base address of the coherent memory section must be page-aligned (4K)
|
||||||
|
* to guarantee that the coherent data are stored on their own pages and
|
||||||
|
* are not mixed with normal data. This is required to set up the correct
|
||||||
|
* memory attributes for the coherent data page tables.
|
||||||
|
*/
|
||||||
|
coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
|
||||||
|
__COHERENT_RAM_START__ = .;
|
||||||
|
*(tzfw_coherent_mem)
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked
|
||||||
|
* as device memory. No other unexpected data must creep in.
|
||||||
|
* Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__COHERENT_RAM_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark end of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_END__ = .;
|
||||||
|
__BL2_END__ = .;
|
||||||
|
|
||||||
|
/DISCARD/ : {
|
||||||
|
*(.dynsym .dynstr .hash .gnu.hash)
|
||||||
|
}
|
||||||
|
|
||||||
|
#if BL2_IN_XIP_MEM
|
||||||
|
__BL2_RAM_START__ = ADDR(.data);
|
||||||
|
__BL2_RAM_END__ = .;
|
||||||
|
|
||||||
|
__DATA_ROM_START__ = LOADADDR(.data);
|
||||||
|
__DATA_SIZE__ = SIZEOF(.data);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The .data section is the last PROGBITS section so its end marks the end
|
||||||
|
* of BL2's RO content in XIP memory..
|
||||||
|
*/
|
||||||
|
__BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
|
||||||
|
ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT,
|
||||||
|
"BL2's RO content has exceeded its limit.")
|
||||||
|
#endif
|
||||||
|
__BSS_SIZE__ = SIZEOF(.bss);
|
||||||
|
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
__COHERENT_RAM_UNALIGNED_SIZE__ =
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if BL2_IN_XIP_MEM
|
||||||
|
ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.")
|
||||||
|
#else
|
||||||
|
ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
|
||||||
|
#endif
|
||||||
|
}
|
||||||
110
arm-trusted-firmware/bl2/bl2_image_load_v2.c
Normal file
110
arm-trusted-firmware/bl2/bl2_image_load_v2.c
Normal file
@@ -0,0 +1,110 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include "bl2_private.h"
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <common/desc_image_load.h>
|
||||||
|
#include <drivers/auth/auth_mod.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function loads SCP_BL2/BL3x images and returns the ep_info for
|
||||||
|
* the next executable image.
|
||||||
|
******************************************************************************/
|
||||||
|
struct entry_point_info *bl2_load_images(void)
|
||||||
|
{
|
||||||
|
bl_params_t *bl2_to_next_bl_params;
|
||||||
|
bl_load_info_t *bl2_load_info;
|
||||||
|
const bl_load_info_node_t *bl2_node_info;
|
||||||
|
int plat_setup_done = 0;
|
||||||
|
int err;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get information about the images to load.
|
||||||
|
*/
|
||||||
|
bl2_load_info = plat_get_bl_image_load_info();
|
||||||
|
assert(bl2_load_info != NULL);
|
||||||
|
assert(bl2_load_info->head != NULL);
|
||||||
|
assert(bl2_load_info->h.type == PARAM_BL_LOAD_INFO);
|
||||||
|
assert(bl2_load_info->h.version >= VERSION_2);
|
||||||
|
bl2_node_info = bl2_load_info->head;
|
||||||
|
|
||||||
|
while (bl2_node_info != NULL) {
|
||||||
|
/*
|
||||||
|
* Perform platform setup before loading the image,
|
||||||
|
* if indicated in the image attributes AND if NOT
|
||||||
|
* already done before.
|
||||||
|
*/
|
||||||
|
if ((bl2_node_info->image_info->h.attr &
|
||||||
|
IMAGE_ATTRIB_PLAT_SETUP) != 0U) {
|
||||||
|
if (plat_setup_done != 0) {
|
||||||
|
WARN("BL2: Platform setup already done!!\n");
|
||||||
|
} else {
|
||||||
|
INFO("BL2: Doing platform setup\n");
|
||||||
|
bl2_platform_setup();
|
||||||
|
plat_setup_done = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
err = bl2_plat_handle_pre_image_load(bl2_node_info->image_id);
|
||||||
|
if (err != 0) {
|
||||||
|
ERROR("BL2: Failure in pre image load handling (%i)\n", err);
|
||||||
|
plat_error_handler(err);
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((bl2_node_info->image_info->h.attr &
|
||||||
|
IMAGE_ATTRIB_SKIP_LOADING) == 0U) {
|
||||||
|
INFO("BL2: Loading image id %u\n", bl2_node_info->image_id);
|
||||||
|
err = load_auth_image(bl2_node_info->image_id,
|
||||||
|
bl2_node_info->image_info);
|
||||||
|
if (err != 0) {
|
||||||
|
ERROR("BL2: Failed to load image id %u (%i)\n",
|
||||||
|
bl2_node_info->image_id, err);
|
||||||
|
plat_error_handler(err);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
INFO("BL2: Skip loading image id %u\n", bl2_node_info->image_id);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allow platform to handle image information. */
|
||||||
|
err = bl2_plat_handle_post_image_load(bl2_node_info->image_id);
|
||||||
|
if (err != 0) {
|
||||||
|
ERROR("BL2: Failure in post image load handling (%i)\n", err);
|
||||||
|
plat_error_handler(err);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Go to next image */
|
||||||
|
bl2_node_info = bl2_node_info->next_load_info;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get information to pass to the next image.
|
||||||
|
*/
|
||||||
|
bl2_to_next_bl_params = plat_get_next_bl_params();
|
||||||
|
assert(bl2_to_next_bl_params != NULL);
|
||||||
|
assert(bl2_to_next_bl_params->head != NULL);
|
||||||
|
assert(bl2_to_next_bl_params->h.type == PARAM_BL_PARAMS);
|
||||||
|
assert(bl2_to_next_bl_params->h.version >= VERSION_2);
|
||||||
|
assert(bl2_to_next_bl_params->head->ep_info != NULL);
|
||||||
|
|
||||||
|
/* Populate arg0 for the next BL image if not already provided */
|
||||||
|
if (bl2_to_next_bl_params->head->ep_info->args.arg0 == (u_register_t)0)
|
||||||
|
bl2_to_next_bl_params->head->ep_info->args.arg0 =
|
||||||
|
(u_register_t)bl2_to_next_bl_params;
|
||||||
|
|
||||||
|
/* Flush the parameters to be passed to next image */
|
||||||
|
plat_flush_next_bl_params();
|
||||||
|
|
||||||
|
return bl2_to_next_bl_params->head->ep_info;
|
||||||
|
}
|
||||||
149
arm-trusted-firmware/bl2/bl2_main.c
Normal file
149
arm-trusted-firmware/bl2/bl2_main.c
Normal file
@@ -0,0 +1,149 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <arch_features.h>
|
||||||
|
#include <bl1/bl1.h>
|
||||||
|
#include <bl2/bl2.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <drivers/auth/auth_mod.h>
|
||||||
|
#include <drivers/auth/crypto_mod.h>
|
||||||
|
#include <drivers/console.h>
|
||||||
|
#include <drivers/fwu/fwu.h>
|
||||||
|
#include <lib/extensions/pauth.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
#include "bl2_private.h"
|
||||||
|
|
||||||
|
#ifdef __aarch64__
|
||||||
|
#define NEXT_IMAGE "BL31"
|
||||||
|
#else
|
||||||
|
#define NEXT_IMAGE "BL32"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if BL2_AT_EL3
|
||||||
|
/*******************************************************************************
|
||||||
|
* Setup function for BL2 when BL2_AT_EL3=1
|
||||||
|
******************************************************************************/
|
||||||
|
void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
|
||||||
|
u_register_t arg3)
|
||||||
|
{
|
||||||
|
/* Perform early platform-specific setup */
|
||||||
|
bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3);
|
||||||
|
|
||||||
|
/* Perform late platform-specific setup */
|
||||||
|
bl2_el3_plat_arch_setup();
|
||||||
|
|
||||||
|
#if CTX_INCLUDE_PAUTH_REGS
|
||||||
|
/*
|
||||||
|
* Assert that the ARMv8.3-PAuth registers are present or an access
|
||||||
|
* fault will be triggered when they are being saved or restored.
|
||||||
|
*/
|
||||||
|
assert(is_armv8_3_pauth_present());
|
||||||
|
#endif /* CTX_INCLUDE_PAUTH_REGS */
|
||||||
|
}
|
||||||
|
#else /* BL2_AT_EL3 */
|
||||||
|
/*******************************************************************************
|
||||||
|
* Setup function for BL2 when BL2_AT_EL3=0
|
||||||
|
******************************************************************************/
|
||||||
|
void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
|
||||||
|
u_register_t arg3)
|
||||||
|
{
|
||||||
|
/* Perform early platform-specific setup */
|
||||||
|
bl2_early_platform_setup2(arg0, arg1, arg2, arg3);
|
||||||
|
|
||||||
|
/* Perform late platform-specific setup */
|
||||||
|
bl2_plat_arch_setup();
|
||||||
|
|
||||||
|
#if CTX_INCLUDE_PAUTH_REGS
|
||||||
|
/*
|
||||||
|
* Assert that the ARMv8.3-PAuth registers are present or an access
|
||||||
|
* fault will be triggered when they are being saved or restored.
|
||||||
|
*/
|
||||||
|
assert(is_armv8_3_pauth_present());
|
||||||
|
#endif /* CTX_INCLUDE_PAUTH_REGS */
|
||||||
|
}
|
||||||
|
#endif /* BL2_AT_EL3 */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* The only thing to do in BL2 is to load further images and pass control to
|
||||||
|
* next BL. The memory occupied by BL2 will be reclaimed by BL3x stages. BL2
|
||||||
|
* runs entirely in S-EL1.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl2_main(void)
|
||||||
|
{
|
||||||
|
entry_point_info_t *next_bl_ep_info;
|
||||||
|
|
||||||
|
NOTICE("BL2: %s\n", version_string);
|
||||||
|
NOTICE("BL2: %s\n", build_message);
|
||||||
|
|
||||||
|
/* Perform remaining generic architectural setup in S-EL1 */
|
||||||
|
bl2_arch_setup();
|
||||||
|
|
||||||
|
#if PSA_FWU_SUPPORT
|
||||||
|
fwu_init();
|
||||||
|
#endif /* PSA_FWU_SUPPORT */
|
||||||
|
|
||||||
|
crypto_mod_init();
|
||||||
|
|
||||||
|
/* Initialize authentication module */
|
||||||
|
auth_mod_init();
|
||||||
|
|
||||||
|
/* Initialize the Measured Boot backend */
|
||||||
|
bl2_plat_mboot_init();
|
||||||
|
|
||||||
|
/* Initialize boot source */
|
||||||
|
bl2_plat_preload_setup();
|
||||||
|
|
||||||
|
/* Load the subsequent bootloader images. */
|
||||||
|
next_bl_ep_info = bl2_load_images();
|
||||||
|
|
||||||
|
/* Teardown the Measured Boot backend */
|
||||||
|
bl2_plat_mboot_finish();
|
||||||
|
|
||||||
|
#if !BL2_AT_EL3 && !ENABLE_RME
|
||||||
|
#ifndef __aarch64__
|
||||||
|
/*
|
||||||
|
* For AArch32 state BL1 and BL2 share the MMU setup.
|
||||||
|
* Given that BL2 does not map BL1 regions, MMU needs
|
||||||
|
* to be disabled in order to go back to BL1.
|
||||||
|
*/
|
||||||
|
disable_mmu_icache_secure();
|
||||||
|
#endif /* !__aarch64__ */
|
||||||
|
|
||||||
|
console_flush();
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/*
|
||||||
|
* Disable pointer authentication before running next boot image
|
||||||
|
*/
|
||||||
|
pauth_disable_el1();
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Run next BL image via an SMC to BL1. Information on how to pass
|
||||||
|
* control to the BL32 (if present) and BL33 software images will
|
||||||
|
* be passed to next BL image as an argument.
|
||||||
|
*/
|
||||||
|
smc(BL1_SMC_RUN_IMAGE, (unsigned long)next_bl_ep_info, 0, 0, 0, 0, 0, 0);
|
||||||
|
#else /* if BL2_AT_EL3 || ENABLE_RME */
|
||||||
|
NOTICE("BL2: Booting " NEXT_IMAGE "\n");
|
||||||
|
print_entry_point_info(next_bl_ep_info);
|
||||||
|
console_flush();
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/*
|
||||||
|
* Disable pointer authentication before running next boot image
|
||||||
|
*/
|
||||||
|
pauth_disable_el3();
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
bl2_run_next_image(next_bl_ep_info);
|
||||||
|
#endif /* BL2_AT_EL3 && ENABLE_RME */
|
||||||
|
}
|
||||||
24
arm-trusted-firmware/bl2/bl2_private.h
Normal file
24
arm-trusted-firmware/bl2/bl2_private.h
Normal file
@@ -0,0 +1,24 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef BL2_PRIVATE_H
|
||||||
|
#define BL2_PRIVATE_H
|
||||||
|
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
/******************************************
|
||||||
|
* Forward declarations
|
||||||
|
*****************************************/
|
||||||
|
struct entry_point_info;
|
||||||
|
|
||||||
|
/******************************************
|
||||||
|
* Function prototypes
|
||||||
|
*****************************************/
|
||||||
|
void bl2_arch_setup(void);
|
||||||
|
struct entry_point_info *bl2_load_images(void);
|
||||||
|
void bl2_run_next_image(const struct entry_point_info *bl_ep_info);
|
||||||
|
|
||||||
|
#endif /* BL2_PRIVATE_H */
|
||||||
127
arm-trusted-firmware/bl2u/aarch32/bl2u_entrypoint.S
Normal file
127
arm-trusted-firmware/bl2u/aarch32/bl2u_entrypoint.S
Normal file
@@ -0,0 +1,127 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
.globl bl2u_vector_table
|
||||||
|
.globl bl2u_entrypoint
|
||||||
|
|
||||||
|
|
||||||
|
vector_base bl2u_vector_table
|
||||||
|
b bl2u_entrypoint
|
||||||
|
b report_exception /* Undef */
|
||||||
|
b report_exception /* SVC call */
|
||||||
|
b report_prefetch_abort /* Prefetch abort */
|
||||||
|
b report_data_abort /* Data abort */
|
||||||
|
b report_exception /* Reserved */
|
||||||
|
b report_exception /* IRQ */
|
||||||
|
b report_exception /* FIQ */
|
||||||
|
|
||||||
|
|
||||||
|
func bl2u_entrypoint
|
||||||
|
/*---------------------------------------------
|
||||||
|
* Save from r1 the extents of the trusted ram
|
||||||
|
* available to BL2U for future use.
|
||||||
|
* r0 is not currently used.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov r11, r1
|
||||||
|
mov r10, r2
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Set the exception vector to something sane.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
ldr r0, =bl2u_vector_table
|
||||||
|
stcopr r0, VBAR
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* --------------------------------------------------------
|
||||||
|
* Enable the instruction cache - disable speculative loads
|
||||||
|
* --------------------------------------------------------
|
||||||
|
*/
|
||||||
|
ldcopr r0, SCTLR
|
||||||
|
orr r0, r0, #SCTLR_I_BIT
|
||||||
|
bic r0, r0, #SCTLR_DSSBS_BIT
|
||||||
|
stcopr r0, SCTLR
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Since BL2U executes after BL1, it is assumed
|
||||||
|
* here that BL1 has already has done the
|
||||||
|
* necessary register initializations.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Invalidate the RW memory used by the BL2U
|
||||||
|
* image. This includes the data and NOBITS
|
||||||
|
* sections. This is done to safeguard against
|
||||||
|
* possible corruption of this memory by dirty
|
||||||
|
* cache lines in a system cache as a result of
|
||||||
|
* use by an earlier boot loader stage.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
ldr r0, =__RW_START__
|
||||||
|
ldr r1, =__RW_END__
|
||||||
|
sub r1, r1, r0
|
||||||
|
bl inv_dcache_range
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Zero out NOBITS sections. There are 2 of them:
|
||||||
|
* - the .bss section;
|
||||||
|
* - the coherent memory section.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
ldr r0, =__BSS_START__
|
||||||
|
ldr r1, =__BSS_END__
|
||||||
|
sub r1, r1, r0
|
||||||
|
bl zeromem
|
||||||
|
|
||||||
|
/* --------------------------------------------
|
||||||
|
* Allocate a stack whose memory will be marked
|
||||||
|
* as Normal-IS-WBWA when the MMU is enabled.
|
||||||
|
* There is no risk of reading stale stack
|
||||||
|
* memory after enabling the MMU as only the
|
||||||
|
* primary cpu is running at the moment.
|
||||||
|
* --------------------------------------------
|
||||||
|
*/
|
||||||
|
bl plat_set_my_stack
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Initialize the stack protector canary before
|
||||||
|
* any C code is called.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
#if STACK_PROTECTOR_ENABLED
|
||||||
|
bl update_stack_protector_canary
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Perform early platform setup & platform
|
||||||
|
* specific early arch. setup e.g. mmu setup
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov r0, r11
|
||||||
|
mov r1, r10
|
||||||
|
bl bl2u_early_platform_setup
|
||||||
|
bl bl2u_plat_arch_setup
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Jump to main function.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2u_main
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Should never reach this point.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
|
||||||
|
endfunc bl2u_entrypoint
|
||||||
129
arm-trusted-firmware/bl2u/aarch64/bl2u_entrypoint.S
Normal file
129
arm-trusted-firmware/bl2u/aarch64/bl2u_entrypoint.S
Normal file
@@ -0,0 +1,129 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
.globl bl2u_entrypoint
|
||||||
|
|
||||||
|
|
||||||
|
func bl2u_entrypoint
|
||||||
|
/*---------------------------------------------
|
||||||
|
* Store the extents of the tzram available to
|
||||||
|
* BL2U and other platform specific information
|
||||||
|
* for future use. x0 is currently not used.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x20, x1
|
||||||
|
mov x21, x2
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Set the exception vector to something sane.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
adr x0, early_exceptions
|
||||||
|
msr vbar_el1, x0
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Enable the SError interrupt now that the
|
||||||
|
* exception vectors have been setup.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Enable the instruction cache, stack pointer
|
||||||
|
* and data access alignment checks and disable
|
||||||
|
* speculative loads.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
|
||||||
|
mrs x0, sctlr_el1
|
||||||
|
orr x0, x0, x1
|
||||||
|
bic x0, x0, #SCTLR_DSSBS_BIT
|
||||||
|
msr sctlr_el1, x0
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Invalidate the RW memory used by the BL2U
|
||||||
|
* image. This includes the data and NOBITS
|
||||||
|
* sections. This is done to safeguard against
|
||||||
|
* possible corruption of this memory by dirty
|
||||||
|
* cache lines in a system cache as a result of
|
||||||
|
* use by an earlier boot loader stage.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
adr x0, __RW_START__
|
||||||
|
adr x1, __RW_END__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl inv_dcache_range
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Zero out NOBITS sections. There are 2 of them:
|
||||||
|
* - the .bss section;
|
||||||
|
* - the coherent memory section.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
adrp x0, __BSS_START__
|
||||||
|
add x0, x0, :lo12:__BSS_START__
|
||||||
|
adrp x1, __BSS_END__
|
||||||
|
add x1, x1, :lo12:__BSS_END__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl zeromem
|
||||||
|
|
||||||
|
/* --------------------------------------------
|
||||||
|
* Allocate a stack whose memory will be marked
|
||||||
|
* as Normal-IS-WBWA when the MMU is enabled.
|
||||||
|
* There is no risk of reading stale stack
|
||||||
|
* memory after enabling the MMU as only the
|
||||||
|
* primary cpu is running at the moment.
|
||||||
|
* --------------------------------------------
|
||||||
|
*/
|
||||||
|
bl plat_set_my_stack
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Initialize the stack protector canary before
|
||||||
|
* any C code is called.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
#if STACK_PROTECTOR_ENABLED
|
||||||
|
bl update_stack_protector_canary
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Perform early platform setup & platform
|
||||||
|
* specific early arch. setup e.g. mmu setup
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x0, x20
|
||||||
|
mov x1, x21
|
||||||
|
bl bl2u_early_platform_setup
|
||||||
|
bl bl2u_plat_arch_setup
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Program APIAKey_EL1
|
||||||
|
* and enable pointer authentication.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_init_enable_el1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Jump to bl2u_main function.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl2u_main
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Should never reach this point.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
|
||||||
|
endfunc bl2u_entrypoint
|
||||||
118
arm-trusted-firmware/bl2u/bl2u.ld.S
Normal file
118
arm-trusted-firmware/bl2u/bl2u.ld.S
Normal file
@@ -0,0 +1,118 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <common/bl_common.ld.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
|
||||||
|
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
|
||||||
|
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
|
||||||
|
ENTRY(bl2u_entrypoint)
|
||||||
|
|
||||||
|
MEMORY {
|
||||||
|
RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = BL2U_BASE;
|
||||||
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
||||||
|
"BL2U_BASE address is not aligned on a page boundary.")
|
||||||
|
|
||||||
|
#if SEPARATE_CODE_AND_RODATA
|
||||||
|
.text . : {
|
||||||
|
__TEXT_START__ = .;
|
||||||
|
*bl2u_entrypoint.o(.text*)
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(.vectors)
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__TEXT_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* .ARM.extab and .ARM.exidx are only added because Clang need them */
|
||||||
|
.ARM.extab . : {
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
.ARM.exidx . : {
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
.rodata . : {
|
||||||
|
__RODATA_START__ = .;
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RODATA_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#else
|
||||||
|
ro . : {
|
||||||
|
__RO_START__ = .;
|
||||||
|
*bl2u_entrypoint.o(.text*)
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
*(.vectors)
|
||||||
|
__RO_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked as
|
||||||
|
* read-only, executable. No RW data from the next section must
|
||||||
|
* creep in. Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RO_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark start of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_START__ = . ;
|
||||||
|
|
||||||
|
DATA_SECTION >RAM
|
||||||
|
STACK_SECTION >RAM
|
||||||
|
BSS_SECTION >RAM
|
||||||
|
XLAT_TABLE_SECTION >RAM
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
/*
|
||||||
|
* The base address of the coherent memory section must be page-aligned (4K)
|
||||||
|
* to guarantee that the coherent data are stored on their own pages and
|
||||||
|
* are not mixed with normal data. This is required to set up the correct
|
||||||
|
* memory attributes for the coherent data page tables.
|
||||||
|
*/
|
||||||
|
coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
|
||||||
|
__COHERENT_RAM_START__ = .;
|
||||||
|
*(tzfw_coherent_mem)
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked
|
||||||
|
* as device memory. No other unexpected data must creep in.
|
||||||
|
* Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__COHERENT_RAM_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark end of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_END__ = .;
|
||||||
|
__BL2U_END__ = .;
|
||||||
|
|
||||||
|
__BSS_SIZE__ = SIZEOF(.bss);
|
||||||
|
|
||||||
|
ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
|
||||||
|
}
|
||||||
15
arm-trusted-firmware/bl2u/bl2u.mk
Normal file
15
arm-trusted-firmware/bl2u/bl2u.mk
Normal file
@@ -0,0 +1,15 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
|
||||||
|
BL2U_SOURCES += bl2u/bl2u_main.c \
|
||||||
|
bl2u/${ARCH}/bl2u_entrypoint.S \
|
||||||
|
plat/common/${ARCH}/platform_up_stack.S
|
||||||
|
|
||||||
|
ifeq (${ARCH},aarch64)
|
||||||
|
BL2U_SOURCES += common/aarch64/early_exceptions.S
|
||||||
|
endif
|
||||||
|
|
||||||
|
BL2U_LINKERFILE := bl2u/bl2u.ld.S
|
||||||
65
arm-trusted-firmware/bl2u/bl2u_main.c
Normal file
65
arm-trusted-firmware/bl2u/bl2u_main.c
Normal file
@@ -0,0 +1,65 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <bl1/bl1.h>
|
||||||
|
#include <bl2u/bl2u.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <drivers/auth/auth_mod.h>
|
||||||
|
#include <drivers/console.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function is responsible to:
|
||||||
|
* Load SCP_BL2U if platform has defined SCP_BL2U_BASE
|
||||||
|
* Perform platform setup.
|
||||||
|
* Go back to EL3.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl2u_main(void)
|
||||||
|
{
|
||||||
|
NOTICE("BL2U: %s\n", version_string);
|
||||||
|
NOTICE("BL2U: %s\n", build_message);
|
||||||
|
|
||||||
|
#if SCP_BL2U_BASE
|
||||||
|
int rc;
|
||||||
|
/* Load the subsequent bootloader images */
|
||||||
|
rc = bl2u_plat_handle_scp_bl2u();
|
||||||
|
if (rc != 0) {
|
||||||
|
ERROR("Failed to load SCP_BL2U (%i)\n", rc);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Perform platform setup in BL2U after loading SCP_BL2U */
|
||||||
|
bl2u_platform_setup();
|
||||||
|
|
||||||
|
console_flush();
|
||||||
|
|
||||||
|
#ifndef __aarch64__
|
||||||
|
/*
|
||||||
|
* For AArch32 state BL1 and BL2U share the MMU setup.
|
||||||
|
* Given that BL2U does not map BL1 regions, MMU needs
|
||||||
|
* to be disabled in order to go back to BL1.
|
||||||
|
*/
|
||||||
|
disable_mmu_icache_secure();
|
||||||
|
#endif /* !__aarch64__ */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Indicate that BL2U is done and resume back to
|
||||||
|
* normal world via an SMC to BL1.
|
||||||
|
* x1 could be passed to Normal world,
|
||||||
|
* so DO NOT pass any secret information.
|
||||||
|
*/
|
||||||
|
smc(FWU_SMC_SEC_IMAGE_DONE, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
wfi();
|
||||||
|
}
|
||||||
242
arm-trusted-firmware/bl31/aarch64/bl31_entrypoint.S
Normal file
242
arm-trusted-firmware/bl31/aarch64/bl31_entrypoint.S
Normal file
@@ -0,0 +1,242 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <el3_common_macros.S>
|
||||||
|
#include <lib/pmf/aarch64/pmf_asm_macros.S>
|
||||||
|
#include <lib/runtime_instr.h>
|
||||||
|
#include <lib/xlat_tables/xlat_mmu_helpers.h>
|
||||||
|
|
||||||
|
.globl bl31_entrypoint
|
||||||
|
.globl bl31_warm_entrypoint
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* bl31_entrypoint() is the cold boot entrypoint,
|
||||||
|
* executed only by the primary cpu.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
func bl31_entrypoint
|
||||||
|
/* ---------------------------------------------------------------
|
||||||
|
* Stash the previous bootloader arguments x0 - x3 for later use.
|
||||||
|
* ---------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x20, x0
|
||||||
|
mov x21, x1
|
||||||
|
mov x22, x2
|
||||||
|
mov x23, x3
|
||||||
|
|
||||||
|
#if !RESET_TO_BL31
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* For !RESET_TO_BL31 systems, only the primary CPU ever reaches
|
||||||
|
* bl31_entrypoint() during the cold boot flow, so the cold/warm boot
|
||||||
|
* and primary/secondary CPU logic should not be executed in this case.
|
||||||
|
*
|
||||||
|
* Also, assume that the previous bootloader has already initialised the
|
||||||
|
* SCTLR_EL3, including the endianness, and has initialised the memory.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=0 \
|
||||||
|
_warm_boot_mailbox=0 \
|
||||||
|
_secondary_cold_boot=0 \
|
||||||
|
_init_memory=0 \
|
||||||
|
_init_c_runtime=1 \
|
||||||
|
_exception_vectors=runtime_exceptions \
|
||||||
|
_pie_fixup_size=BL31_LIMIT - BL31_BASE
|
||||||
|
#else
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* For RESET_TO_BL31 systems which have a programmable reset address,
|
||||||
|
* bl31_entrypoint() is executed only on the cold boot path so we can
|
||||||
|
* skip the warm boot mailbox mechanism.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=1 \
|
||||||
|
_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
|
||||||
|
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
|
||||||
|
_init_memory=1 \
|
||||||
|
_init_c_runtime=1 \
|
||||||
|
_exception_vectors=runtime_exceptions \
|
||||||
|
_pie_fixup_size=BL31_LIMIT - BL31_BASE
|
||||||
|
|
||||||
|
#if !RESET_TO_BL31_WITH_PARAMS
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
|
||||||
|
* there's no argument to relay from a previous bootloader. Zero the
|
||||||
|
* arguments passed to the platform layer to reflect that.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x20, 0
|
||||||
|
mov x21, 0
|
||||||
|
mov x22, 0
|
||||||
|
mov x23, 0
|
||||||
|
#endif /* RESET_TO_BL31_WITH_PARAMS */
|
||||||
|
#endif /* RESET_TO_BL31 */
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Perform BL31 setup
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x0, x20
|
||||||
|
mov x1, x21
|
||||||
|
mov x2, x22
|
||||||
|
mov x3, x23
|
||||||
|
bl bl31_setup
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Program APIAKey_EL1 and enable pointer authentication
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_init_enable_el3
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Jump to main function
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl bl31_main
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Clean the .data & .bss sections to main memory. This ensures
|
||||||
|
* that any global data which was initialised by the primary CPU
|
||||||
|
* is visible to secondary CPUs before they enable their data
|
||||||
|
* caches and participate in coherency.
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
adrp x0, __DATA_START__
|
||||||
|
add x0, x0, :lo12:__DATA_START__
|
||||||
|
adrp x1, __DATA_END__
|
||||||
|
add x1, x1, :lo12:__DATA_END__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl clean_dcache_range
|
||||||
|
|
||||||
|
adrp x0, __BSS_START__
|
||||||
|
add x0, x0, :lo12:__BSS_START__
|
||||||
|
adrp x1, __BSS_END__
|
||||||
|
add x1, x1, :lo12:__BSS_END__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl clean_dcache_range
|
||||||
|
|
||||||
|
b el3_exit
|
||||||
|
endfunc bl31_entrypoint
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* This CPU has been physically powered up. It is either resuming from
|
||||||
|
* suspend or has simply been turned on. In both cases, call the BL31
|
||||||
|
* warmboot entrypoint
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
func bl31_warm_entrypoint
|
||||||
|
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This timestamp update happens with cache off. The next
|
||||||
|
* timestamp collection will need to do cache maintenance prior
|
||||||
|
* to timestamp update.
|
||||||
|
*/
|
||||||
|
pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR
|
||||||
|
mrs x1, cntpct_el0
|
||||||
|
str x1, [x0]
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* On the warm boot path, most of the EL3 initialisations performed by
|
||||||
|
* 'el3_entrypoint_common' must be skipped:
|
||||||
|
*
|
||||||
|
* - Only when the platform bypasses the BL1/BL31 entrypoint by
|
||||||
|
* programming the reset address do we need to initialise SCTLR_EL3.
|
||||||
|
* In other cases, we assume this has been taken care by the
|
||||||
|
* entrypoint code.
|
||||||
|
*
|
||||||
|
* - No need to determine the type of boot, we know it is a warm boot.
|
||||||
|
*
|
||||||
|
* - Do not try to distinguish between primary and secondary CPUs, this
|
||||||
|
* notion only exists for a cold boot.
|
||||||
|
*
|
||||||
|
* - No need to initialise the memory or the C runtime environment,
|
||||||
|
* it has been done once and for all on the cold boot path.
|
||||||
|
*/
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
|
||||||
|
_warm_boot_mailbox=0 \
|
||||||
|
_secondary_cold_boot=0 \
|
||||||
|
_init_memory=0 \
|
||||||
|
_init_c_runtime=0 \
|
||||||
|
_exception_vectors=runtime_exceptions \
|
||||||
|
_pie_fixup_size=0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We're about to enable MMU and participate in PSCI state coordination.
|
||||||
|
*
|
||||||
|
* The PSCI implementation invokes platform routines that enable CPUs to
|
||||||
|
* participate in coherency. On a system where CPUs are not
|
||||||
|
* cache-coherent without appropriate platform specific programming,
|
||||||
|
* having caches enabled until such time might lead to coherency issues
|
||||||
|
* (resulting from stale data getting speculatively fetched, among
|
||||||
|
* others). Therefore we keep data caches disabled even after enabling
|
||||||
|
* the MMU for such platforms.
|
||||||
|
*
|
||||||
|
* On systems with hardware-assisted coherency, or on single cluster
|
||||||
|
* platforms, such platform specific programming is not required to
|
||||||
|
* enter coherency (as CPUs already are); and there's no reason to have
|
||||||
|
* caches disabled either.
|
||||||
|
*/
|
||||||
|
#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
|
||||||
|
mov x0, xzr
|
||||||
|
#else
|
||||||
|
mov x0, #DISABLE_DCACHE
|
||||||
|
#endif
|
||||||
|
bl bl31_plat_enable_mmu
|
||||||
|
|
||||||
|
#if ENABLE_RME
|
||||||
|
/*
|
||||||
|
* At warm boot GPT data structures have already been initialized in RAM
|
||||||
|
* but the sysregs for this CPU need to be initialized. Note that the GPT
|
||||||
|
* accesses are controlled attributes in GPCCR and do not depend on the
|
||||||
|
* SCR_EL3.C bit.
|
||||||
|
*/
|
||||||
|
bl gpt_enable
|
||||||
|
cbz x0, 1f
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
1:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Program APIAKey_EL1 and enable pointer authentication
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_init_enable_el3
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
bl psci_warmboot_entrypoint
|
||||||
|
|
||||||
|
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||||
|
pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI
|
||||||
|
mov x19, x0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Invalidate before updating timestamp to ensure previous timestamp
|
||||||
|
* updates on the same cache line with caches disabled are properly
|
||||||
|
* seen by the same core. Without the cache invalidate, the core might
|
||||||
|
* write into a stale cache line.
|
||||||
|
*/
|
||||||
|
mov x1, #PMF_TS_SIZE
|
||||||
|
mov x20, x30
|
||||||
|
bl inv_dcache_range
|
||||||
|
mov x30, x20
|
||||||
|
|
||||||
|
mrs x0, cntpct_el0
|
||||||
|
str x0, [x19]
|
||||||
|
#endif
|
||||||
|
b el3_exit
|
||||||
|
endfunc bl31_warm_entrypoint
|
||||||
477
arm-trusted-firmware/bl31/aarch64/crash_reporting.S
Normal file
477
arm-trusted-firmware/bl31/aarch64/crash_reporting.S
Normal file
@@ -0,0 +1,477 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <plat_macros.S>
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <context.h>
|
||||||
|
#include <lib/el3_runtime/cpu_data.h>
|
||||||
|
#include <lib/utils_def.h>
|
||||||
|
|
||||||
|
.globl report_unhandled_exception
|
||||||
|
.globl report_unhandled_interrupt
|
||||||
|
.globl el3_panic
|
||||||
|
.globl elx_panic
|
||||||
|
|
||||||
|
#if CRASH_REPORTING
|
||||||
|
|
||||||
|
/* ------------------------------------------------------
|
||||||
|
* The below section deals with dumping the system state
|
||||||
|
* when an unhandled exception is taken in EL3.
|
||||||
|
* The layout and the names of the registers which will
|
||||||
|
* be dumped during a unhandled exception is given below.
|
||||||
|
* ------------------------------------------------------
|
||||||
|
*/
|
||||||
|
.section .rodata.crash_prints, "aS"
|
||||||
|
print_spacer:
|
||||||
|
.asciz " = 0x"
|
||||||
|
|
||||||
|
gp_regs:
|
||||||
|
.asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\
|
||||||
|
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",\
|
||||||
|
"x16", "x17", "x18", "x19", "x20", "x21", "x22",\
|
||||||
|
"x23", "x24", "x25", "x26", "x27", "x28", "x29", ""
|
||||||
|
el3_sys_regs:
|
||||||
|
.asciz "scr_el3", "sctlr_el3", "cptr_el3", "tcr_el3",\
|
||||||
|
"daif", "mair_el3", "spsr_el3", "elr_el3", "ttbr0_el3",\
|
||||||
|
"esr_el3", "far_el3", ""
|
||||||
|
|
||||||
|
non_el3_sys_regs:
|
||||||
|
.asciz "spsr_el1", "elr_el1", "spsr_abt", "spsr_und",\
|
||||||
|
"spsr_irq", "spsr_fiq", "sctlr_el1", "actlr_el1", "cpacr_el1",\
|
||||||
|
"csselr_el1", "sp_el1", "esr_el1", "ttbr0_el1", "ttbr1_el1",\
|
||||||
|
"mair_el1", "amair_el1", "tcr_el1", "tpidr_el1", "tpidr_el0",\
|
||||||
|
"tpidrro_el0", "par_el1", "mpidr_el1", "afsr0_el1", "afsr1_el1",\
|
||||||
|
"contextidr_el1", "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0",\
|
||||||
|
"cntv_ctl_el0", "cntv_cval_el0", "cntkctl_el1", "sp_el0", "isr_el1", ""
|
||||||
|
|
||||||
|
#if CTX_INCLUDE_AARCH32_REGS
|
||||||
|
aarch32_regs:
|
||||||
|
.asciz "dacr32_el2", "ifsr32_el2", ""
|
||||||
|
#endif /* CTX_INCLUDE_AARCH32_REGS */
|
||||||
|
|
||||||
|
panic_msg:
|
||||||
|
.asciz "PANIC in EL3.\nx30"
|
||||||
|
excpt_msg:
|
||||||
|
.asciz "Unhandled Exception in EL3.\nx30"
|
||||||
|
intr_excpt_msg:
|
||||||
|
.ascii "Unhandled Interrupt Exception in EL3.\n"
|
||||||
|
x30_msg:
|
||||||
|
.asciz "x30"
|
||||||
|
excpt_msg_el:
|
||||||
|
.asciz "Unhandled Exception from EL"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Helper function to print from crash buf.
|
||||||
|
* The print loop is controlled by the buf size and
|
||||||
|
* ascii reg name list which is passed in x6. The
|
||||||
|
* function returns the crash buf address in x0.
|
||||||
|
* Clobbers : x0 - x7, sp
|
||||||
|
*/
|
||||||
|
func size_controlled_print
|
||||||
|
/* Save the lr */
|
||||||
|
mov sp, x30
|
||||||
|
/* load the crash buf address */
|
||||||
|
mrs x7, tpidr_el3
|
||||||
|
test_size_list:
|
||||||
|
/* Calculate x5 always as it will be clobbered by asm_print_hex */
|
||||||
|
mrs x5, tpidr_el3
|
||||||
|
add x5, x5, #CPU_DATA_CRASH_BUF_SIZE
|
||||||
|
/* Test whether we have reached end of crash buf */
|
||||||
|
cmp x7, x5
|
||||||
|
b.eq exit_size_print
|
||||||
|
ldrb w4, [x6]
|
||||||
|
/* Test whether we are at end of list */
|
||||||
|
cbz w4, exit_size_print
|
||||||
|
mov x4, x6
|
||||||
|
/* asm_print_str updates x4 to point to next entry in list */
|
||||||
|
bl asm_print_str
|
||||||
|
/* x0 = number of symbols printed + 1 */
|
||||||
|
sub x0, x4, x6
|
||||||
|
/* update x6 with the updated list pointer */
|
||||||
|
mov x6, x4
|
||||||
|
bl print_alignment
|
||||||
|
ldr x4, [x7], #REGSZ
|
||||||
|
bl asm_print_hex
|
||||||
|
bl asm_print_newline
|
||||||
|
b test_size_list
|
||||||
|
exit_size_print:
|
||||||
|
mov x30, sp
|
||||||
|
ret
|
||||||
|
endfunc size_controlled_print
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* This function calculates and prints required number
|
||||||
|
* of space characters followed by "= 0x", based on the
|
||||||
|
* length of ascii register name.
|
||||||
|
* x0: length of ascii register name + 1
|
||||||
|
* ------------------------------------------------------
|
||||||
|
*/
|
||||||
|
func print_alignment
|
||||||
|
/* The minimum ascii length is 3, e.g. for "x0" */
|
||||||
|
adr x4, print_spacer - 3
|
||||||
|
add x4, x4, x0
|
||||||
|
b asm_print_str
|
||||||
|
endfunc print_alignment
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Helper function to store x8 - x15 registers to
|
||||||
|
* the crash buf. The system registers values are
|
||||||
|
* copied to x8 to x15 by the caller which are then
|
||||||
|
* copied to the crash buf by this function.
|
||||||
|
* x0 points to the crash buf. It then calls
|
||||||
|
* size_controlled_print to print to console.
|
||||||
|
* Clobbers : x0 - x7, sp
|
||||||
|
*/
|
||||||
|
func str_in_crash_buf_print
|
||||||
|
/* restore the crash buf address in x0 */
|
||||||
|
mrs x0, tpidr_el3
|
||||||
|
stp x8, x9, [x0]
|
||||||
|
stp x10, x11, [x0, #REGSZ * 2]
|
||||||
|
stp x12, x13, [x0, #REGSZ * 4]
|
||||||
|
stp x14, x15, [x0, #REGSZ * 6]
|
||||||
|
b size_controlled_print
|
||||||
|
endfunc str_in_crash_buf_print
|
||||||
|
|
||||||
|
/* ------------------------------------------------------
|
||||||
|
* This macro calculates the offset to crash buf from
|
||||||
|
* cpu_data and stores it in tpidr_el3. It also saves x0
|
||||||
|
* and x1 in the crash buf by using sp as a temporary
|
||||||
|
* register.
|
||||||
|
* ------------------------------------------------------
|
||||||
|
*/
|
||||||
|
.macro prepare_crash_buf_save_x0_x1
|
||||||
|
/* we can corrupt this reg to free up x0 */
|
||||||
|
mov sp, x0
|
||||||
|
/* tpidr_el3 contains the address to cpu_data structure */
|
||||||
|
mrs x0, tpidr_el3
|
||||||
|
/* Calculate the Crash buffer offset in cpu_data */
|
||||||
|
add x0, x0, #CPU_DATA_CRASH_BUF_OFFSET
|
||||||
|
/* Store crash buffer address in tpidr_el3 */
|
||||||
|
msr tpidr_el3, x0
|
||||||
|
str x1, [x0, #REGSZ]
|
||||||
|
mov x1, sp
|
||||||
|
str x1, [x0]
|
||||||
|
.endm
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* This function allows to report a crash (if crash
|
||||||
|
* reporting is enabled) when an unhandled exception
|
||||||
|
* occurs. It prints the CPU state via the crash console
|
||||||
|
* making use of the crash buf. This function will
|
||||||
|
* not return.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
func report_unhandled_exception
|
||||||
|
prepare_crash_buf_save_x0_x1
|
||||||
|
adr x0, excpt_msg
|
||||||
|
mov sp, x0
|
||||||
|
/* This call will not return */
|
||||||
|
b do_crash_reporting
|
||||||
|
endfunc report_unhandled_exception
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* This function allows to report a crash (if crash
|
||||||
|
* reporting is enabled) when an unhandled interrupt
|
||||||
|
* occurs. It prints the CPU state via the crash console
|
||||||
|
* making use of the crash buf. This function will
|
||||||
|
* not return.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
func report_unhandled_interrupt
|
||||||
|
prepare_crash_buf_save_x0_x1
|
||||||
|
adr x0, intr_excpt_msg
|
||||||
|
mov sp, x0
|
||||||
|
/* This call will not return */
|
||||||
|
b do_crash_reporting
|
||||||
|
endfunc report_unhandled_interrupt
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* This function allows to report a crash from the lower
|
||||||
|
* exception level (if crash reporting is enabled) when
|
||||||
|
* panic() is invoked from C Runtime.
|
||||||
|
* It prints the CPU state via the crash console making
|
||||||
|
* use of 'cpu_context' structure where general purpose
|
||||||
|
* registers are saved and the crash buf.
|
||||||
|
* This function will not return.
|
||||||
|
*
|
||||||
|
* x0: Exception level
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
func elx_panic
|
||||||
|
msr spsel, #MODE_SP_ELX
|
||||||
|
mov x8, x0
|
||||||
|
|
||||||
|
/* Print the crash message */
|
||||||
|
adr x4, excpt_msg_el
|
||||||
|
bl asm_print_str
|
||||||
|
|
||||||
|
/* Print exception level */
|
||||||
|
add x0, x8, #'0'
|
||||||
|
bl plat_crash_console_putc
|
||||||
|
bl asm_print_newline
|
||||||
|
|
||||||
|
/* Report x0 - x29 values stored in 'gpregs_ctx' structure */
|
||||||
|
/* Store the ascii list pointer in x6 */
|
||||||
|
adr x6, gp_regs
|
||||||
|
add x7, sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0
|
||||||
|
|
||||||
|
print_next:
|
||||||
|
ldrb w4, [x6]
|
||||||
|
/* Test whether we are at end of list */
|
||||||
|
cbz w4, print_x30
|
||||||
|
mov x4, x6
|
||||||
|
/* asm_print_str updates x4 to point to next entry in list */
|
||||||
|
bl asm_print_str
|
||||||
|
/* x0 = number of symbols printed + 1 */
|
||||||
|
sub x0, x4, x6
|
||||||
|
/* Update x6 with the updated list pointer */
|
||||||
|
mov x6, x4
|
||||||
|
bl print_alignment
|
||||||
|
ldr x4, [x7], #REGSZ
|
||||||
|
bl asm_print_hex
|
||||||
|
bl asm_print_newline
|
||||||
|
b print_next
|
||||||
|
|
||||||
|
print_x30:
|
||||||
|
adr x4, x30_msg
|
||||||
|
bl asm_print_str
|
||||||
|
|
||||||
|
/* Print spaces to align "x30" string */
|
||||||
|
mov x0, #4
|
||||||
|
bl print_alignment
|
||||||
|
|
||||||
|
/* Report x30 */
|
||||||
|
ldr x4, [x7]
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------
|
||||||
|
* Different virtual address space size can be defined for each EL.
|
||||||
|
* Ensure that we use the proper one by reading the corresponding
|
||||||
|
* TCR_ELx register.
|
||||||
|
* ----------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
cmp x8, #MODE_EL2
|
||||||
|
b.lt from_el1 /* EL1 */
|
||||||
|
mrs x2, sctlr_el2
|
||||||
|
mrs x1, tcr_el2
|
||||||
|
|
||||||
|
/* ----------------------------------------------------------------
|
||||||
|
* Check if pointer authentication is enabled at the specified EL.
|
||||||
|
* If it isn't, we can then skip stripping a PAC code.
|
||||||
|
* ----------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
test_pauth:
|
||||||
|
tst x2, #(SCTLR_EnIA_BIT | SCTLR_EnIB_BIT)
|
||||||
|
b.eq no_pauth
|
||||||
|
|
||||||
|
/* Demangle address */
|
||||||
|
and x1, x1, #0x3F /* T0SZ = TCR_ELx[5:0] */
|
||||||
|
sub x1, x1, #64
|
||||||
|
neg x1, x1 /* bottom_pac_bit = 64 - T0SZ */
|
||||||
|
mov x2, #-1
|
||||||
|
lsl x2, x2, x1
|
||||||
|
bic x4, x4, x2
|
||||||
|
|
||||||
|
no_pauth:
|
||||||
|
bl asm_print_hex
|
||||||
|
bl asm_print_newline
|
||||||
|
|
||||||
|
/* tpidr_el3 contains the address to cpu_data structure */
|
||||||
|
mrs x0, tpidr_el3
|
||||||
|
/* Calculate the Crash buffer offset in cpu_data */
|
||||||
|
add x0, x0, #CPU_DATA_CRASH_BUF_OFFSET
|
||||||
|
/* Store crash buffer address in tpidr_el3 */
|
||||||
|
msr tpidr_el3, x0
|
||||||
|
|
||||||
|
/* Print the rest of crash dump */
|
||||||
|
b print_el3_sys_regs
|
||||||
|
|
||||||
|
from_el1:
|
||||||
|
mrs x2, sctlr_el1
|
||||||
|
mrs x1, tcr_el1
|
||||||
|
b test_pauth
|
||||||
|
endfunc elx_panic
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* This function allows to report a crash (if crash
|
||||||
|
* reporting is enabled) when panic() is invoked from
|
||||||
|
* C Runtime. It prints the CPU state via the crash
|
||||||
|
* console making use of the crash buf. This function
|
||||||
|
* will not return.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
func el3_panic
|
||||||
|
msr spsel, #MODE_SP_ELX
|
||||||
|
prepare_crash_buf_save_x0_x1
|
||||||
|
adr x0, panic_msg
|
||||||
|
mov sp, x0
|
||||||
|
/* Fall through to 'do_crash_reporting' */
|
||||||
|
|
||||||
|
/* ------------------------------------------------------------
|
||||||
|
* The common crash reporting functionality. It requires x0
|
||||||
|
* and x1 has already been stored in crash buf, sp points to
|
||||||
|
* crash message and tpidr_el3 contains the crash buf address.
|
||||||
|
* The function does the following:
|
||||||
|
* - Retrieve the crash buffer from tpidr_el3
|
||||||
|
* - Store x2 to x6 in the crash buffer
|
||||||
|
* - Initialise the crash console.
|
||||||
|
* - Print the crash message by using the address in sp.
|
||||||
|
* - Print x30 value to the crash console.
|
||||||
|
* - Print x0 - x7 from the crash buf to the crash console.
|
||||||
|
* - Print x8 - x29 (in groups of 8 registers) using the
|
||||||
|
* crash buf to the crash console.
|
||||||
|
* - Print el3 sys regs (in groups of 8 registers) using the
|
||||||
|
* crash buf to the crash console.
|
||||||
|
* - Print non el3 sys regs (in groups of 8 registers) using
|
||||||
|
* the crash buf to the crash console.
|
||||||
|
* ------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
do_crash_reporting:
|
||||||
|
/* Retrieve the crash buf from tpidr_el3 */
|
||||||
|
mrs x0, tpidr_el3
|
||||||
|
/* Store x2 - x6, x30 in the crash buffer */
|
||||||
|
stp x2, x3, [x0, #REGSZ * 2]
|
||||||
|
stp x4, x5, [x0, #REGSZ * 4]
|
||||||
|
stp x6, x30, [x0, #REGSZ * 6]
|
||||||
|
/* Initialize the crash console */
|
||||||
|
bl plat_crash_console_init
|
||||||
|
/* Verify the console is initialized */
|
||||||
|
cbz x0, crash_panic
|
||||||
|
/* Print the crash message. sp points to the crash message */
|
||||||
|
mov x4, sp
|
||||||
|
bl asm_print_str
|
||||||
|
/* Print spaces to align "x30" string */
|
||||||
|
mov x0, #4
|
||||||
|
bl print_alignment
|
||||||
|
/* Load the crash buf address */
|
||||||
|
mrs x0, tpidr_el3
|
||||||
|
/* Report x30 first from the crash buf */
|
||||||
|
ldr x4, [x0, #REGSZ * 7]
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* Demangle address */
|
||||||
|
xpaci x4
|
||||||
|
#endif
|
||||||
|
bl asm_print_hex
|
||||||
|
bl asm_print_newline
|
||||||
|
/* Load the crash buf address */
|
||||||
|
mrs x0, tpidr_el3
|
||||||
|
/* Now mov x7 into crash buf */
|
||||||
|
str x7, [x0, #REGSZ * 7]
|
||||||
|
|
||||||
|
/* Report x0 - x29 values stored in crash buf */
|
||||||
|
/* Store the ascii list pointer in x6 */
|
||||||
|
adr x6, gp_regs
|
||||||
|
/* Print x0 to x7 from the crash buf */
|
||||||
|
bl size_controlled_print
|
||||||
|
/* Store x8 - x15 in crash buf and print */
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
/* Load the crash buf address */
|
||||||
|
mrs x0, tpidr_el3
|
||||||
|
/* Store the rest of gp regs and print */
|
||||||
|
stp x16, x17, [x0]
|
||||||
|
stp x18, x19, [x0, #REGSZ * 2]
|
||||||
|
stp x20, x21, [x0, #REGSZ * 4]
|
||||||
|
stp x22, x23, [x0, #REGSZ * 6]
|
||||||
|
bl size_controlled_print
|
||||||
|
/* Load the crash buf address */
|
||||||
|
mrs x0, tpidr_el3
|
||||||
|
stp x24, x25, [x0]
|
||||||
|
stp x26, x27, [x0, #REGSZ * 2]
|
||||||
|
stp x28, x29, [x0, #REGSZ * 4]
|
||||||
|
bl size_controlled_print
|
||||||
|
|
||||||
|
/* Print the el3 sys registers */
|
||||||
|
print_el3_sys_regs:
|
||||||
|
adr x6, el3_sys_regs
|
||||||
|
mrs x8, scr_el3
|
||||||
|
mrs x9, sctlr_el3
|
||||||
|
mrs x10, cptr_el3
|
||||||
|
mrs x11, tcr_el3
|
||||||
|
mrs x12, daif
|
||||||
|
mrs x13, mair_el3
|
||||||
|
mrs x14, spsr_el3
|
||||||
|
mrs x15, elr_el3
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
mrs x8, ttbr0_el3
|
||||||
|
mrs x9, esr_el3
|
||||||
|
mrs x10, far_el3
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
|
||||||
|
/* Print the non el3 sys registers */
|
||||||
|
adr x6, non_el3_sys_regs
|
||||||
|
mrs x8, spsr_el1
|
||||||
|
mrs x9, elr_el1
|
||||||
|
mrs x10, spsr_abt
|
||||||
|
mrs x11, spsr_und
|
||||||
|
mrs x12, spsr_irq
|
||||||
|
mrs x13, spsr_fiq
|
||||||
|
mrs x14, sctlr_el1
|
||||||
|
mrs x15, actlr_el1
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
mrs x8, cpacr_el1
|
||||||
|
mrs x9, csselr_el1
|
||||||
|
mrs x10, sp_el1
|
||||||
|
mrs x11, esr_el1
|
||||||
|
mrs x12, ttbr0_el1
|
||||||
|
mrs x13, ttbr1_el1
|
||||||
|
mrs x14, mair_el1
|
||||||
|
mrs x15, amair_el1
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
mrs x8, tcr_el1
|
||||||
|
mrs x9, tpidr_el1
|
||||||
|
mrs x10, tpidr_el0
|
||||||
|
mrs x11, tpidrro_el0
|
||||||
|
mrs x12, par_el1
|
||||||
|
mrs x13, mpidr_el1
|
||||||
|
mrs x14, afsr0_el1
|
||||||
|
mrs x15, afsr1_el1
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
mrs x8, contextidr_el1
|
||||||
|
mrs x9, vbar_el1
|
||||||
|
mrs x10, cntp_ctl_el0
|
||||||
|
mrs x11, cntp_cval_el0
|
||||||
|
mrs x12, cntv_ctl_el0
|
||||||
|
mrs x13, cntv_cval_el0
|
||||||
|
mrs x14, cntkctl_el1
|
||||||
|
mrs x15, sp_el0
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
mrs x8, isr_el1
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
|
||||||
|
#if CTX_INCLUDE_AARCH32_REGS
|
||||||
|
/* Print the AArch32 registers */
|
||||||
|
adr x6, aarch32_regs
|
||||||
|
mrs x8, dacr32_el2
|
||||||
|
mrs x9, ifsr32_el2
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
#endif /* CTX_INCLUDE_AARCH32_REGS */
|
||||||
|
|
||||||
|
/* Get the cpu specific registers to report */
|
||||||
|
bl do_cpu_reg_dump
|
||||||
|
bl str_in_crash_buf_print
|
||||||
|
|
||||||
|
/* Print some platform registers */
|
||||||
|
plat_crash_print_regs
|
||||||
|
|
||||||
|
bl plat_crash_console_flush
|
||||||
|
|
||||||
|
/* Done reporting */
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc el3_panic
|
||||||
|
|
||||||
|
#else /* CRASH_REPORTING */
|
||||||
|
func report_unhandled_exception
|
||||||
|
report_unhandled_interrupt:
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc report_unhandled_exception
|
||||||
|
#endif /* CRASH_REPORTING */
|
||||||
|
|
||||||
|
func crash_panic
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc crash_panic
|
||||||
320
arm-trusted-firmware/bl31/aarch64/ea_delegate.S
Normal file
320
arm-trusted-firmware/bl31/aarch64/ea_delegate.S
Normal file
@@ -0,0 +1,320 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
* Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include <assert_macros.S>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <assert_macros.S>
|
||||||
|
#include <bl31/ea_handle.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <lib/extensions/ras_arch.h>
|
||||||
|
#include <cpu_macros.S>
|
||||||
|
#include <context.h>
|
||||||
|
|
||||||
|
.globl handle_lower_el_ea_esb
|
||||||
|
.globl handle_lower_el_async_ea
|
||||||
|
.globl enter_lower_el_sync_ea
|
||||||
|
.globl enter_lower_el_async_ea
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function to delegate External Aborts synchronized by ESB instruction at EL3
|
||||||
|
* vector entry. This function assumes GP registers x0-x29 have been saved, and
|
||||||
|
* are available for use. It delegates the handling of the EA to platform
|
||||||
|
* handler, and returns only upon successfully handling the EA; otherwise
|
||||||
|
* panics. On return from this function, the original exception handler is
|
||||||
|
* expected to resume.
|
||||||
|
*/
|
||||||
|
func handle_lower_el_ea_esb
|
||||||
|
mov x0, #ERROR_EA_ESB
|
||||||
|
mrs x1, DISR_EL1
|
||||||
|
b ea_proceed
|
||||||
|
endfunc handle_lower_el_ea_esb
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function forms the tail end of Synchronous Exception entry from lower
|
||||||
|
* EL, and expects to handle Synchronous External Aborts from lower EL and CPU
|
||||||
|
* Implementation Defined Exceptions. If any other kind of exception is detected,
|
||||||
|
* then this function reports unhandled exception.
|
||||||
|
*
|
||||||
|
* Since it's part of exception vector, this function doesn't expect any GP
|
||||||
|
* registers to have been saved. It delegates the handling of the EA to platform
|
||||||
|
* handler, and upon successfully handling the EA, exits EL3; otherwise panics.
|
||||||
|
*/
|
||||||
|
func enter_lower_el_sync_ea
|
||||||
|
/*
|
||||||
|
* Explicitly save x30 so as to free up a register and to enable
|
||||||
|
* branching.
|
||||||
|
*/
|
||||||
|
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
|
||||||
|
mrs x30, esr_el3
|
||||||
|
ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
|
||||||
|
|
||||||
|
/* Check for I/D aborts from lower EL */
|
||||||
|
cmp x30, #EC_IABORT_LOWER_EL
|
||||||
|
b.eq 1f
|
||||||
|
|
||||||
|
cmp x30, #EC_DABORT_LOWER_EL
|
||||||
|
b.eq 1f
|
||||||
|
|
||||||
|
/* Save GP registers */
|
||||||
|
stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
|
||||||
|
stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
|
||||||
|
stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
|
||||||
|
|
||||||
|
/* Get the cpu_ops pointer */
|
||||||
|
bl get_cpu_ops_ptr
|
||||||
|
|
||||||
|
/* Get the cpu_ops exception handler */
|
||||||
|
ldr x0, [x0, #CPU_E_HANDLER_FUNC]
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If the reserved function pointer is NULL, this CPU does not have an
|
||||||
|
* implementation defined exception handler function
|
||||||
|
*/
|
||||||
|
cbz x0, 2f
|
||||||
|
mrs x1, esr_el3
|
||||||
|
ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH
|
||||||
|
blr x0
|
||||||
|
b 2f
|
||||||
|
|
||||||
|
1:
|
||||||
|
/*
|
||||||
|
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
|
||||||
|
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
|
||||||
|
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
|
||||||
|
* Also set the PSTATE to a known state.
|
||||||
|
*/
|
||||||
|
bl prepare_el3_entry
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* Load and program APIAKey firmware key */
|
||||||
|
bl pauth_load_bl31_apiakey
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Setup exception class and syndrome arguments for platform handler */
|
||||||
|
mov x0, #ERROR_EA_SYNC
|
||||||
|
mrs x1, esr_el3
|
||||||
|
bl delegate_sync_ea
|
||||||
|
|
||||||
|
/* el3_exit assumes SP_EL0 on entry */
|
||||||
|
msr spsel, #MODE_SP_EL0
|
||||||
|
b el3_exit
|
||||||
|
2:
|
||||||
|
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
|
||||||
|
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
|
||||||
|
ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
|
||||||
|
|
||||||
|
/* Synchronous exceptions other than the above are assumed to be EA */
|
||||||
|
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
no_ret report_unhandled_exception
|
||||||
|
endfunc enter_lower_el_sync_ea
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function handles SErrors from lower ELs.
|
||||||
|
*
|
||||||
|
* Since it's part of exception vector, this function doesn't expect any GP
|
||||||
|
* registers to have been saved. It delegates the handling of the EA to platform
|
||||||
|
* handler, and upon successfully handling the EA, exits EL3; otherwise panics.
|
||||||
|
*/
|
||||||
|
func enter_lower_el_async_ea
|
||||||
|
/*
|
||||||
|
* Explicitly save x30 so as to free up a register and to enable
|
||||||
|
* branching
|
||||||
|
*/
|
||||||
|
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
|
||||||
|
handle_lower_el_async_ea:
|
||||||
|
/*
|
||||||
|
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
|
||||||
|
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
|
||||||
|
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
|
||||||
|
* Also set the PSTATE to a known state.
|
||||||
|
*/
|
||||||
|
bl prepare_el3_entry
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* Load and program APIAKey firmware key */
|
||||||
|
bl pauth_load_bl31_apiakey
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Setup exception class and syndrome arguments for platform handler */
|
||||||
|
mov x0, #ERROR_EA_ASYNC
|
||||||
|
mrs x1, esr_el3
|
||||||
|
bl delegate_async_ea
|
||||||
|
|
||||||
|
/* el3_exit assumes SP_EL0 on entry */
|
||||||
|
msr spsel, #MODE_SP_EL0
|
||||||
|
b el3_exit
|
||||||
|
endfunc enter_lower_el_async_ea
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Prelude for Synchronous External Abort handling. This function assumes that
|
||||||
|
* all GP registers have been saved by the caller.
|
||||||
|
*
|
||||||
|
* x0: EA reason
|
||||||
|
* x1: EA syndrome
|
||||||
|
*/
|
||||||
|
func delegate_sync_ea
|
||||||
|
#if RAS_EXTENSION
|
||||||
|
/*
|
||||||
|
* Check for Uncontainable error type. If so, route to the platform
|
||||||
|
* fatal error handler rather than the generic EA one.
|
||||||
|
*/
|
||||||
|
ubfx x2, x1, #EABORT_SET_SHIFT, #EABORT_SET_WIDTH
|
||||||
|
cmp x2, #ERROR_STATUS_SET_UC
|
||||||
|
b.ne 1f
|
||||||
|
|
||||||
|
/* Check fault status code */
|
||||||
|
ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
|
||||||
|
cmp x3, #SYNC_EA_FSC
|
||||||
|
b.ne 1f
|
||||||
|
|
||||||
|
no_ret plat_handle_uncontainable_ea
|
||||||
|
1:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
b ea_proceed
|
||||||
|
endfunc delegate_sync_ea
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Prelude for Asynchronous External Abort handling. This function assumes that
|
||||||
|
* all GP registers have been saved by the caller.
|
||||||
|
*
|
||||||
|
* x0: EA reason
|
||||||
|
* x1: EA syndrome
|
||||||
|
*/
|
||||||
|
func delegate_async_ea
|
||||||
|
#if RAS_EXTENSION
|
||||||
|
/* Check Exception Class to ensure SError, as this function should
|
||||||
|
* only be invoked for SError. If that is not the case, which implies
|
||||||
|
* either an HW error or programming error, panic.
|
||||||
|
*/
|
||||||
|
ubfx x2, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH
|
||||||
|
cmp x2, EC_SERROR
|
||||||
|
b.ne do_panic
|
||||||
|
/*
|
||||||
|
* Check for Implementation Defined Syndrome. If so, skip checking
|
||||||
|
* Uncontainable error type from the syndrome as the format is unknown.
|
||||||
|
*/
|
||||||
|
tbnz x1, #SERROR_IDS_BIT, 1f
|
||||||
|
|
||||||
|
/* AET only valid when DFSC is 0x11 */
|
||||||
|
ubfx x2, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
|
||||||
|
cmp x2, #DFSC_SERROR
|
||||||
|
b.ne 1f
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check for Uncontainable error type. If so, route to the platform
|
||||||
|
* fatal error handler rather than the generic EA one.
|
||||||
|
*/
|
||||||
|
ubfx x3, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH
|
||||||
|
cmp x3, #ERROR_STATUS_UET_UC
|
||||||
|
b.ne 1f
|
||||||
|
|
||||||
|
no_ret plat_handle_uncontainable_ea
|
||||||
|
1:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
b ea_proceed
|
||||||
|
endfunc delegate_async_ea
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Delegate External Abort handling to platform's EA handler. This function
|
||||||
|
* assumes that all GP registers have been saved by the caller.
|
||||||
|
*
|
||||||
|
* x0: EA reason
|
||||||
|
* x1: EA syndrome
|
||||||
|
*/
|
||||||
|
func ea_proceed
|
||||||
|
/*
|
||||||
|
* If the ESR loaded earlier is not zero, we were processing an EA
|
||||||
|
* already, and this is a double fault.
|
||||||
|
*/
|
||||||
|
ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
|
||||||
|
cbz x5, 1f
|
||||||
|
no_ret plat_handle_double_fault
|
||||||
|
|
||||||
|
1:
|
||||||
|
/* Save EL3 state */
|
||||||
|
mrs x2, spsr_el3
|
||||||
|
mrs x3, elr_el3
|
||||||
|
stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Save ESR as handling might involve lower ELs, and returning back to
|
||||||
|
* EL3 from there would trample the original ESR.
|
||||||
|
*/
|
||||||
|
mrs x4, scr_el3
|
||||||
|
mrs x5, esr_el3
|
||||||
|
stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Setup rest of arguments, and call platform External Abort handler.
|
||||||
|
*
|
||||||
|
* x0: EA reason (already in place)
|
||||||
|
* x1: Exception syndrome (already in place).
|
||||||
|
* x2: Cookie (unused for now).
|
||||||
|
* x3: Context pointer.
|
||||||
|
* x4: Flags (security state from SCR for now).
|
||||||
|
*/
|
||||||
|
mov x2, xzr
|
||||||
|
mov x3, sp
|
||||||
|
ubfx x4, x4, #0, #1
|
||||||
|
|
||||||
|
/* Switch to runtime stack */
|
||||||
|
ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
|
||||||
|
msr spsel, #MODE_SP_EL0
|
||||||
|
mov sp, x5
|
||||||
|
|
||||||
|
mov x29, x30
|
||||||
|
#if ENABLE_ASSERTIONS
|
||||||
|
/* Stash the stack pointer */
|
||||||
|
mov x28, sp
|
||||||
|
#endif
|
||||||
|
bl plat_ea_handler
|
||||||
|
|
||||||
|
#if ENABLE_ASSERTIONS
|
||||||
|
/*
|
||||||
|
* Error handling flows might involve long jumps; so upon returning from
|
||||||
|
* the platform error handler, validate that the we've completely
|
||||||
|
* unwound the stack.
|
||||||
|
*/
|
||||||
|
mov x27, sp
|
||||||
|
cmp x28, x27
|
||||||
|
ASM_ASSERT(eq)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Make SP point to context */
|
||||||
|
msr spsel, #MODE_SP_ELX
|
||||||
|
|
||||||
|
/* Restore EL3 state and ESR */
|
||||||
|
ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
|
||||||
|
msr spsr_el3, x1
|
||||||
|
msr elr_el3, x2
|
||||||
|
|
||||||
|
/* Restore ESR_EL3 and SCR_EL3 */
|
||||||
|
ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
|
||||||
|
msr scr_el3, x3
|
||||||
|
msr esr_el3, x4
|
||||||
|
|
||||||
|
#if ENABLE_ASSERTIONS
|
||||||
|
cmp x4, xzr
|
||||||
|
ASM_ASSERT(ne)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Clear ESR storage */
|
||||||
|
str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
|
||||||
|
|
||||||
|
ret x29
|
||||||
|
endfunc ea_proceed
|
||||||
667
arm-trusted-firmware/bl31/aarch64/runtime_exceptions.S
Normal file
667
arm-trusted-firmware/bl31/aarch64/runtime_exceptions.S
Normal file
@@ -0,0 +1,667 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <bl31/ea_handle.h>
|
||||||
|
#include <bl31/interrupt_mgmt.h>
|
||||||
|
#include <bl31/sync_handle.h>
|
||||||
|
#include <common/runtime_svc.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <el3_common_macros.S>
|
||||||
|
#include <lib/el3_runtime/cpu_data.h>
|
||||||
|
#include <lib/smccc.h>
|
||||||
|
|
||||||
|
.globl runtime_exceptions
|
||||||
|
|
||||||
|
.globl sync_exception_sp_el0
|
||||||
|
.globl irq_sp_el0
|
||||||
|
.globl fiq_sp_el0
|
||||||
|
.globl serror_sp_el0
|
||||||
|
|
||||||
|
.globl sync_exception_sp_elx
|
||||||
|
.globl irq_sp_elx
|
||||||
|
.globl fiq_sp_elx
|
||||||
|
.globl serror_sp_elx
|
||||||
|
|
||||||
|
.globl sync_exception_aarch64
|
||||||
|
.globl irq_aarch64
|
||||||
|
.globl fiq_aarch64
|
||||||
|
.globl serror_aarch64
|
||||||
|
|
||||||
|
.globl sync_exception_aarch32
|
||||||
|
.globl irq_aarch32
|
||||||
|
.globl fiq_aarch32
|
||||||
|
.globl serror_aarch32
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Macro that prepares entry to EL3 upon taking an exception.
|
||||||
|
*
|
||||||
|
* With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
|
||||||
|
* instruction. When an error is thus synchronized, the handling is
|
||||||
|
* delegated to platform EA handler.
|
||||||
|
*
|
||||||
|
* Without RAS_EXTENSION, this macro synchronizes pending errors using
|
||||||
|
* a DSB, unmasks Asynchronous External Aborts and saves X30 before
|
||||||
|
* setting the flag CTX_IS_IN_EL3.
|
||||||
|
*/
|
||||||
|
.macro check_and_unmask_ea
|
||||||
|
#if RAS_EXTENSION
|
||||||
|
/* Synchronize pending External Aborts */
|
||||||
|
esb
|
||||||
|
|
||||||
|
/* Unmask the SError interrupt */
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Explicitly save x30 so as to free up a register and to enable
|
||||||
|
* branching
|
||||||
|
*/
|
||||||
|
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
|
||||||
|
/* Check for SErrors synchronized by the ESB instruction */
|
||||||
|
mrs x30, DISR_EL1
|
||||||
|
tbz x30, #DISR_A_BIT, 1f
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
|
||||||
|
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
|
||||||
|
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
|
||||||
|
* Also set the PSTATE to a known state.
|
||||||
|
*/
|
||||||
|
bl prepare_el3_entry
|
||||||
|
|
||||||
|
bl handle_lower_el_ea_esb
|
||||||
|
|
||||||
|
/* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */
|
||||||
|
bl restore_gp_pmcr_pauth_regs
|
||||||
|
1:
|
||||||
|
#else
|
||||||
|
/*
|
||||||
|
* For SoCs which do not implement RAS, use DSB as a barrier to
|
||||||
|
* synchronize pending external aborts.
|
||||||
|
*/
|
||||||
|
dsb sy
|
||||||
|
|
||||||
|
/* Unmask the SError interrupt */
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
|
||||||
|
/* Use ISB for the above unmask operation to take effect immediately */
|
||||||
|
isb
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Refer Note 1. No need to restore X30 as both handle_sync_exception
|
||||||
|
* and handle_interrupt_exception macro which follow this macro modify
|
||||||
|
* X30 anyway.
|
||||||
|
*/
|
||||||
|
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
mov x30, #1
|
||||||
|
str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
|
||||||
|
dmb sy
|
||||||
|
#endif
|
||||||
|
.endm
|
||||||
|
|
||||||
|
#if !RAS_EXTENSION
|
||||||
|
/*
|
||||||
|
* Note 1: The explicit DSB at the entry of various exception vectors
|
||||||
|
* for handling exceptions from lower ELs can inadvertently trigger an
|
||||||
|
* SError exception in EL3 due to pending asynchronous aborts in lower
|
||||||
|
* ELs. This will end up being handled by serror_sp_elx which will
|
||||||
|
* ultimately panic and die.
|
||||||
|
* The way to workaround is to update a flag to indicate if the exception
|
||||||
|
* truly came from EL3. This flag is allocated in the cpu_context
|
||||||
|
* structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3"
|
||||||
|
* This is not a bullet proof solution to the problem at hand because
|
||||||
|
* we assume the instructions following "isb" that help to update the
|
||||||
|
* flag execute without causing further exceptions.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* This macro handles Asynchronous External Aborts.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
.macro handle_async_ea
|
||||||
|
/*
|
||||||
|
* Use a barrier to synchronize pending external aborts.
|
||||||
|
*/
|
||||||
|
dsb sy
|
||||||
|
|
||||||
|
/* Unmask the SError interrupt */
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
|
||||||
|
/* Use ISB for the above unmask operation to take effect immediately */
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* Refer Note 1 */
|
||||||
|
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
mov x30, #1
|
||||||
|
str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
|
||||||
|
dmb sy
|
||||||
|
|
||||||
|
b handle_lower_el_async_ea
|
||||||
|
.endm
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This macro checks if the exception was taken due to SError in EL3 or
|
||||||
|
* because of pending asynchronous external aborts from lower EL that got
|
||||||
|
* triggered due to explicit synchronization in EL3. Refer Note 1.
|
||||||
|
*/
|
||||||
|
.macro check_if_serror_from_EL3
|
||||||
|
/* Assumes SP_EL3 on entry */
|
||||||
|
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
|
||||||
|
cbnz x30, exp_from_EL3
|
||||||
|
|
||||||
|
/* Handle asynchronous external abort from lower EL */
|
||||||
|
b handle_lower_el_async_ea
|
||||||
|
|
||||||
|
exp_from_EL3:
|
||||||
|
/* Jump to plat_handle_el3_ea which does not return */
|
||||||
|
.endm
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* This macro handles Synchronous exceptions.
|
||||||
|
* Only SMC exceptions are supported.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
.macro handle_sync_exception
|
||||||
|
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||||
|
/*
|
||||||
|
* Read the timestamp value and store it in per-cpu data. The value
|
||||||
|
* will be extracted from per-cpu data by the C level SMC handler and
|
||||||
|
* saved to the PMF timestamp region.
|
||||||
|
*/
|
||||||
|
mrs x30, cntpct_el0
|
||||||
|
str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
|
||||||
|
mrs x29, tpidr_el3
|
||||||
|
str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
|
||||||
|
ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
|
||||||
|
#endif
|
||||||
|
|
||||||
|
mrs x30, esr_el3
|
||||||
|
ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
|
||||||
|
|
||||||
|
/* Handle SMC exceptions separately from other synchronous exceptions */
|
||||||
|
cmp x30, #EC_AARCH32_SMC
|
||||||
|
b.eq smc_handler32
|
||||||
|
|
||||||
|
cmp x30, #EC_AARCH64_SMC
|
||||||
|
b.eq sync_handler64
|
||||||
|
|
||||||
|
cmp x30, #EC_AARCH64_SYS
|
||||||
|
b.eq sync_handler64
|
||||||
|
|
||||||
|
/* Synchronous exceptions other than the above are assumed to be EA */
|
||||||
|
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
b enter_lower_el_sync_ea
|
||||||
|
.endm
|
||||||
|
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
|
||||||
|
* interrupts.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
.macro handle_interrupt_exception label
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
|
||||||
|
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
|
||||||
|
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
|
||||||
|
* Also set the PSTATE to a known state.
|
||||||
|
*/
|
||||||
|
bl prepare_el3_entry
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* Load and program APIAKey firmware key */
|
||||||
|
bl pauth_load_bl31_apiakey
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Save the EL3 system registers needed to return from this exception */
|
||||||
|
mrs x0, spsr_el3
|
||||||
|
mrs x1, elr_el3
|
||||||
|
stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
|
||||||
|
|
||||||
|
/* Switch to the runtime stack i.e. SP_EL0 */
|
||||||
|
ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
|
||||||
|
mov x20, sp
|
||||||
|
msr spsel, #MODE_SP_EL0
|
||||||
|
mov sp, x2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Find out whether this is a valid interrupt type.
|
||||||
|
* If the interrupt controller reports a spurious interrupt then return
|
||||||
|
* to where we came from.
|
||||||
|
*/
|
||||||
|
bl plat_ic_get_pending_interrupt_type
|
||||||
|
cmp x0, #INTR_TYPE_INVAL
|
||||||
|
b.eq interrupt_exit_\label
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the registered handler for this interrupt type.
|
||||||
|
* A NULL return value could be 'cause of the following conditions:
|
||||||
|
*
|
||||||
|
* a. An interrupt of a type was routed correctly but a handler for its
|
||||||
|
* type was not registered.
|
||||||
|
*
|
||||||
|
* b. An interrupt of a type was not routed correctly so a handler for
|
||||||
|
* its type was not registered.
|
||||||
|
*
|
||||||
|
* c. An interrupt of a type was routed correctly to EL3, but was
|
||||||
|
* deasserted before its pending state could be read. Another
|
||||||
|
* interrupt of a different type pended at the same time and its
|
||||||
|
* type was reported as pending instead. However, a handler for this
|
||||||
|
* type was not registered.
|
||||||
|
*
|
||||||
|
* a. and b. can only happen due to a programming error. The
|
||||||
|
* occurrence of c. could be beyond the control of Trusted Firmware.
|
||||||
|
* It makes sense to return from this exception instead of reporting an
|
||||||
|
* error.
|
||||||
|
*/
|
||||||
|
bl get_interrupt_type_handler
|
||||||
|
cbz x0, interrupt_exit_\label
|
||||||
|
mov x21, x0
|
||||||
|
|
||||||
|
mov x0, #INTR_ID_UNAVAILABLE
|
||||||
|
|
||||||
|
/* Set the current security state in the 'flags' parameter */
|
||||||
|
mrs x2, scr_el3
|
||||||
|
ubfx x1, x2, #0, #1
|
||||||
|
|
||||||
|
/* Restore the reference to the 'handle' i.e. SP_EL3 */
|
||||||
|
mov x2, x20
|
||||||
|
|
||||||
|
/* x3 will point to a cookie (not used now) */
|
||||||
|
mov x3, xzr
|
||||||
|
|
||||||
|
/* Call the interrupt type handler */
|
||||||
|
blr x21
|
||||||
|
|
||||||
|
interrupt_exit_\label:
|
||||||
|
/* Return from exception, possibly in a different security state */
|
||||||
|
b el3_exit
|
||||||
|
|
||||||
|
.endm
|
||||||
|
|
||||||
|
|
||||||
|
vector_base runtime_exceptions
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* Current EL with SP_EL0 : 0x0 - 0x200
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry sync_exception_sp_el0
|
||||||
|
#ifdef MONITOR_TRAPS
|
||||||
|
stp x29, x30, [sp, #-16]!
|
||||||
|
|
||||||
|
mrs x30, esr_el3
|
||||||
|
ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
|
||||||
|
|
||||||
|
/* Check for BRK */
|
||||||
|
cmp x30, #EC_BRK
|
||||||
|
b.eq brk_handler
|
||||||
|
|
||||||
|
ldp x29, x30, [sp], #16
|
||||||
|
#endif /* MONITOR_TRAPS */
|
||||||
|
|
||||||
|
/* We don't expect any synchronous exceptions from EL3 */
|
||||||
|
b report_unhandled_exception
|
||||||
|
end_vector_entry sync_exception_sp_el0
|
||||||
|
|
||||||
|
vector_entry irq_sp_el0
|
||||||
|
/*
|
||||||
|
* EL3 code is non-reentrant. Any asynchronous exception is a serious
|
||||||
|
* error. Loop infinitely.
|
||||||
|
*/
|
||||||
|
b report_unhandled_interrupt
|
||||||
|
end_vector_entry irq_sp_el0
|
||||||
|
|
||||||
|
|
||||||
|
vector_entry fiq_sp_el0
|
||||||
|
b report_unhandled_interrupt
|
||||||
|
end_vector_entry fiq_sp_el0
|
||||||
|
|
||||||
|
|
||||||
|
vector_entry serror_sp_el0
|
||||||
|
no_ret plat_handle_el3_ea
|
||||||
|
end_vector_entry serror_sp_el0
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* Current EL with SP_ELx: 0x200 - 0x400
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry sync_exception_sp_elx
|
||||||
|
/*
|
||||||
|
* This exception will trigger if anything went wrong during a previous
|
||||||
|
* exception entry or exit or while handling an earlier unexpected
|
||||||
|
* synchronous exception. There is a high probability that SP_EL3 is
|
||||||
|
* corrupted.
|
||||||
|
*/
|
||||||
|
b report_unhandled_exception
|
||||||
|
end_vector_entry sync_exception_sp_elx
|
||||||
|
|
||||||
|
vector_entry irq_sp_elx
|
||||||
|
b report_unhandled_interrupt
|
||||||
|
end_vector_entry irq_sp_elx
|
||||||
|
|
||||||
|
vector_entry fiq_sp_elx
|
||||||
|
b report_unhandled_interrupt
|
||||||
|
end_vector_entry fiq_sp_elx
|
||||||
|
|
||||||
|
vector_entry serror_sp_elx
|
||||||
|
#if !RAS_EXTENSION
|
||||||
|
check_if_serror_from_EL3
|
||||||
|
#endif
|
||||||
|
no_ret plat_handle_el3_ea
|
||||||
|
end_vector_entry serror_sp_elx
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* Lower EL using AArch64 : 0x400 - 0x600
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry sync_exception_aarch64
|
||||||
|
/*
|
||||||
|
* This exception vector will be the entry point for SMCs and traps
|
||||||
|
* that are unhandled at lower ELs most commonly. SP_EL3 should point
|
||||||
|
* to a valid cpu context where the general purpose and system register
|
||||||
|
* state can be saved.
|
||||||
|
*/
|
||||||
|
apply_at_speculative_wa
|
||||||
|
check_and_unmask_ea
|
||||||
|
handle_sync_exception
|
||||||
|
end_vector_entry sync_exception_aarch64
|
||||||
|
|
||||||
|
vector_entry irq_aarch64
|
||||||
|
apply_at_speculative_wa
|
||||||
|
check_and_unmask_ea
|
||||||
|
handle_interrupt_exception irq_aarch64
|
||||||
|
end_vector_entry irq_aarch64
|
||||||
|
|
||||||
|
vector_entry fiq_aarch64
|
||||||
|
apply_at_speculative_wa
|
||||||
|
check_and_unmask_ea
|
||||||
|
handle_interrupt_exception fiq_aarch64
|
||||||
|
end_vector_entry fiq_aarch64
|
||||||
|
|
||||||
|
vector_entry serror_aarch64
|
||||||
|
apply_at_speculative_wa
|
||||||
|
#if RAS_EXTENSION
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
b enter_lower_el_async_ea
|
||||||
|
#else
|
||||||
|
handle_async_ea
|
||||||
|
#endif
|
||||||
|
end_vector_entry serror_aarch64
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* Lower EL using AArch32 : 0x600 - 0x800
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry sync_exception_aarch32
|
||||||
|
/*
|
||||||
|
* This exception vector will be the entry point for SMCs and traps
|
||||||
|
* that are unhandled at lower ELs most commonly. SP_EL3 should point
|
||||||
|
* to a valid cpu context where the general purpose and system register
|
||||||
|
* state can be saved.
|
||||||
|
*/
|
||||||
|
apply_at_speculative_wa
|
||||||
|
check_and_unmask_ea
|
||||||
|
handle_sync_exception
|
||||||
|
end_vector_entry sync_exception_aarch32
|
||||||
|
|
||||||
|
vector_entry irq_aarch32
|
||||||
|
apply_at_speculative_wa
|
||||||
|
check_and_unmask_ea
|
||||||
|
handle_interrupt_exception irq_aarch32
|
||||||
|
end_vector_entry irq_aarch32
|
||||||
|
|
||||||
|
vector_entry fiq_aarch32
|
||||||
|
apply_at_speculative_wa
|
||||||
|
check_and_unmask_ea
|
||||||
|
handle_interrupt_exception fiq_aarch32
|
||||||
|
end_vector_entry fiq_aarch32
|
||||||
|
|
||||||
|
vector_entry serror_aarch32
|
||||||
|
apply_at_speculative_wa
|
||||||
|
#if RAS_EXTENSION
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
b enter_lower_el_async_ea
|
||||||
|
#else
|
||||||
|
handle_async_ea
|
||||||
|
#endif
|
||||||
|
end_vector_entry serror_aarch32
|
||||||
|
|
||||||
|
#ifdef MONITOR_TRAPS
|
||||||
|
.section .rodata.brk_string, "aS"
|
||||||
|
brk_location:
|
||||||
|
.asciz "Error at instruction 0x"
|
||||||
|
brk_message:
|
||||||
|
.asciz "Unexpected BRK instruction with value 0x"
|
||||||
|
#endif /* MONITOR_TRAPS */
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* The following code handles secure monitor calls.
|
||||||
|
* Depending upon the execution state from where the SMC has been
|
||||||
|
* invoked, it frees some general purpose registers to perform the
|
||||||
|
* remaining tasks. They involve finding the runtime service handler
|
||||||
|
* that is the target of the SMC & switching to runtime stacks (SP_EL0)
|
||||||
|
* before calling the handler.
|
||||||
|
*
|
||||||
|
* Note that x30 has been explicitly saved and can be used here
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
func sync_exception_handler
|
||||||
|
smc_handler32:
|
||||||
|
/* Check whether aarch32 issued an SMC64 */
|
||||||
|
tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
|
||||||
|
|
||||||
|
sync_handler64:
|
||||||
|
/* NOTE: The code below must preserve x0-x4 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
|
||||||
|
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
|
||||||
|
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
|
||||||
|
* Also set the PSTATE to a known state.
|
||||||
|
*/
|
||||||
|
bl prepare_el3_entry
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* Load and program APIAKey firmware key */
|
||||||
|
bl pauth_load_bl31_apiakey
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Populate the parameters for the SMC handler.
|
||||||
|
* We already have x0-x4 in place. x5 will point to a cookie (not used
|
||||||
|
* now). x6 will point to the context structure (SP_EL3) and x7 will
|
||||||
|
* contain flags we need to pass to the handler.
|
||||||
|
*/
|
||||||
|
mov x5, xzr
|
||||||
|
mov x6, sp
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Restore the saved C runtime stack value which will become the new
|
||||||
|
* SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
|
||||||
|
* structure prior to the last ERET from EL3.
|
||||||
|
*/
|
||||||
|
ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
|
||||||
|
|
||||||
|
/* Switch to SP_EL0 */
|
||||||
|
msr spsel, #MODE_SP_EL0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
|
||||||
|
* switch during SMC handling.
|
||||||
|
* TODO: Revisit if all system registers can be saved later.
|
||||||
|
*/
|
||||||
|
mrs x16, spsr_el3
|
||||||
|
mrs x17, elr_el3
|
||||||
|
mrs x18, scr_el3
|
||||||
|
stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
|
||||||
|
str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
|
||||||
|
|
||||||
|
/* check for system register traps */
|
||||||
|
mrs x16, esr_el3
|
||||||
|
ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH
|
||||||
|
cmp x17, #EC_AARCH64_SYS
|
||||||
|
b.eq sysreg_handler64
|
||||||
|
|
||||||
|
/* Clear flag register */
|
||||||
|
mov x7, xzr
|
||||||
|
|
||||||
|
#if ENABLE_RME
|
||||||
|
/* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */
|
||||||
|
ubfx x7, x18, #SCR_NSE_SHIFT, 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Shift copied SCR_EL3.NSE bit by 5 to create space for
|
||||||
|
* SCR_EL3.NS bit. Bit 5 of the flag corresponds to
|
||||||
|
* the SCR_EL3.NSE bit.
|
||||||
|
*/
|
||||||
|
lsl x7, x7, #5
|
||||||
|
#endif /* ENABLE_RME */
|
||||||
|
|
||||||
|
/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
|
||||||
|
bfi x7, x18, #0, #1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID
|
||||||
|
* passed through x0. Copy the SVE hint bit to flags and mask the
|
||||||
|
* bit in smc_fid passed to the standard service dispatcher.
|
||||||
|
* A service/dispatcher can retrieve the SVE hint bit state from
|
||||||
|
* flags using the appropriate helper.
|
||||||
|
*/
|
||||||
|
bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK
|
||||||
|
bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT)
|
||||||
|
|
||||||
|
mov sp, x12
|
||||||
|
|
||||||
|
/* Get the unique owning entity number */
|
||||||
|
ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
|
||||||
|
ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
|
||||||
|
orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
|
||||||
|
|
||||||
|
/* Load descriptor index from array of indices */
|
||||||
|
adrp x14, rt_svc_descs_indices
|
||||||
|
add x14, x14, :lo12:rt_svc_descs_indices
|
||||||
|
ldrb w15, [x14, x16]
|
||||||
|
|
||||||
|
/* Any index greater than 127 is invalid. Check bit 7. */
|
||||||
|
tbnz w15, 7, smc_unknown
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the descriptor using the index
|
||||||
|
* x11 = (base + off), w15 = index
|
||||||
|
*
|
||||||
|
* handler = (base + off) + (index << log2(size))
|
||||||
|
*/
|
||||||
|
adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
|
||||||
|
lsl w10, w15, #RT_SVC_SIZE_LOG2
|
||||||
|
ldr x15, [x11, w10, uxtw]
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Call the Secure Monitor Call handler and then drop directly into
|
||||||
|
* el3_exit() which will program any remaining architectural state
|
||||||
|
* prior to issuing the ERET to the desired lower EL.
|
||||||
|
*/
|
||||||
|
#if DEBUG
|
||||||
|
cbz x15, rt_svc_fw_critical_error
|
||||||
|
#endif
|
||||||
|
blr x15
|
||||||
|
|
||||||
|
b el3_exit
|
||||||
|
|
||||||
|
sysreg_handler64:
|
||||||
|
mov x0, x16 /* ESR_EL3, containing syndrome information */
|
||||||
|
mov x1, x6 /* lower EL's context */
|
||||||
|
mov x19, x6 /* save context pointer for after the call */
|
||||||
|
mov sp, x12 /* EL3 runtime stack, as loaded above */
|
||||||
|
|
||||||
|
/* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */
|
||||||
|
bl handle_sysreg_trap
|
||||||
|
/*
|
||||||
|
* returns:
|
||||||
|
* -1: unhandled trap, panic
|
||||||
|
* 0: handled trap, return to the trapping instruction (repeating it)
|
||||||
|
* 1: handled trap, return to the next instruction
|
||||||
|
*/
|
||||||
|
|
||||||
|
tst w0, w0
|
||||||
|
b.mi do_panic /* negative return value: panic */
|
||||||
|
b.eq 1f /* zero: do not change ELR_EL3 */
|
||||||
|
|
||||||
|
/* advance the PC to continue after the instruction */
|
||||||
|
ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
|
||||||
|
add x1, x1, #4
|
||||||
|
str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
|
||||||
|
1:
|
||||||
|
b el3_exit
|
||||||
|
|
||||||
|
smc_unknown:
|
||||||
|
/*
|
||||||
|
* Unknown SMC call. Populate return value with SMC_UNK and call
|
||||||
|
* el3_exit() which will restore the remaining architectural state
|
||||||
|
* i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET
|
||||||
|
* to the desired lower EL.
|
||||||
|
*/
|
||||||
|
mov x0, #SMC_UNK
|
||||||
|
str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
|
||||||
|
b el3_exit
|
||||||
|
|
||||||
|
smc_prohibited:
|
||||||
|
restore_ptw_el1_sys_regs
|
||||||
|
ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
|
||||||
|
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
mov x0, #SMC_UNK
|
||||||
|
exception_return
|
||||||
|
|
||||||
|
#if DEBUG
|
||||||
|
rt_svc_fw_critical_error:
|
||||||
|
/* Switch to SP_ELx */
|
||||||
|
msr spsel, #MODE_SP_ELX
|
||||||
|
no_ret report_unhandled_exception
|
||||||
|
#endif
|
||||||
|
endfunc sync_exception_handler
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* The following code handles exceptions caused by BRK instructions.
|
||||||
|
* Following a BRK instruction, the only real valid cause of action is
|
||||||
|
* to print some information and panic, as the code that caused it is
|
||||||
|
* likely in an inconsistent internal state.
|
||||||
|
*
|
||||||
|
* This is initially intended to be used in conjunction with
|
||||||
|
* __builtin_trap.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
#ifdef MONITOR_TRAPS
|
||||||
|
func brk_handler
|
||||||
|
/* Extract the ISS */
|
||||||
|
mrs x10, esr_el3
|
||||||
|
ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH
|
||||||
|
|
||||||
|
/* Ensure the console is initialized */
|
||||||
|
bl plat_crash_console_init
|
||||||
|
|
||||||
|
adr x4, brk_location
|
||||||
|
bl asm_print_str
|
||||||
|
mrs x4, elr_el3
|
||||||
|
bl asm_print_hex
|
||||||
|
bl asm_print_newline
|
||||||
|
|
||||||
|
adr x4, brk_message
|
||||||
|
bl asm_print_str
|
||||||
|
mov x4, x10
|
||||||
|
mov x5, #28
|
||||||
|
bl asm_print_hex_bits
|
||||||
|
bl asm_print_newline
|
||||||
|
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc brk_handler
|
||||||
|
#endif /* MONITOR_TRAPS */
|
||||||
199
arm-trusted-firmware/bl31/bl31.ld.S
Normal file
199
arm-trusted-firmware/bl31/bl31.ld.S
Normal file
@@ -0,0 +1,199 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common/bl_common.ld.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
|
||||||
|
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
|
||||||
|
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
|
||||||
|
ENTRY(bl31_entrypoint)
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY {
|
||||||
|
RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
|
||||||
|
#if SEPARATE_NOBITS_REGION
|
||||||
|
NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE
|
||||||
|
#else
|
||||||
|
#define NOBITS RAM
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef PLAT_EXTRA_LD_SCRIPT
|
||||||
|
#include <plat.ld.S>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = BL31_BASE;
|
||||||
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
||||||
|
"BL31_BASE address is not aligned on a page boundary.")
|
||||||
|
|
||||||
|
__BL31_START__ = .;
|
||||||
|
|
||||||
|
#if SEPARATE_CODE_AND_RODATA
|
||||||
|
.text . : {
|
||||||
|
__TEXT_START__ = .;
|
||||||
|
*bl31_entrypoint.o(.text*)
|
||||||
|
*(SORT_BY_ALIGNMENT(SORT(.text*)))
|
||||||
|
*(.vectors)
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__TEXT_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
.rodata . : {
|
||||||
|
__RODATA_START__ = .;
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
#if PLAT_EXTRA_RODATA_INCLUDES
|
||||||
|
#include <plat.ld.rodata.inc>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
/* Place pubsub sections for events */
|
||||||
|
. = ALIGN(8);
|
||||||
|
#include <lib/el3_runtime/pubsub_events.h>
|
||||||
|
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RODATA_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#else
|
||||||
|
ro . : {
|
||||||
|
__RO_START__ = .;
|
||||||
|
*bl31_entrypoint.o(.text*)
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
/* Place pubsub sections for events */
|
||||||
|
. = ALIGN(8);
|
||||||
|
#include <lib/el3_runtime/pubsub_events.h>
|
||||||
|
|
||||||
|
*(.vectors)
|
||||||
|
__RO_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked as read-only,
|
||||||
|
* executable. No RW data from the next section must creep in.
|
||||||
|
* Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RO_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
|
||||||
|
"cpu_ops not defined for this platform.")
|
||||||
|
|
||||||
|
#if SPM_MM
|
||||||
|
#ifndef SPM_SHIM_EXCEPTIONS_VMA
|
||||||
|
#define SPM_SHIM_EXCEPTIONS_VMA RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Exception vectors of the SPM shim layer. They must be aligned to a 2K
|
||||||
|
* address, but we need to place them in a separate page so that we can set
|
||||||
|
* individual permissions to them, so the actual alignment needed is 4K.
|
||||||
|
*
|
||||||
|
* There's no need to include this into the RO section of BL31 because it
|
||||||
|
* doesn't need to be accessed by BL31.
|
||||||
|
*/
|
||||||
|
spm_shim_exceptions : ALIGN(PAGE_SIZE) {
|
||||||
|
__SPM_SHIM_EXCEPTIONS_START__ = .;
|
||||||
|
*(.spm_shim_exceptions)
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__SPM_SHIM_EXCEPTIONS_END__ = .;
|
||||||
|
} >SPM_SHIM_EXCEPTIONS_VMA AT>RAM
|
||||||
|
|
||||||
|
PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions));
|
||||||
|
. = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark start of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_START__ = . ;
|
||||||
|
|
||||||
|
DATA_SECTION >RAM
|
||||||
|
RELA_SECTION >RAM
|
||||||
|
|
||||||
|
#ifdef BL31_PROGBITS_LIMIT
|
||||||
|
ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if SEPARATE_NOBITS_REGION
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark end of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RW_END__ = .;
|
||||||
|
__BL31_END__ = .;
|
||||||
|
|
||||||
|
ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
|
||||||
|
|
||||||
|
. = BL31_NOBITS_BASE;
|
||||||
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
||||||
|
"BL31 NOBITS base address is not aligned on a page boundary.")
|
||||||
|
|
||||||
|
__NOBITS_START__ = .;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
STACK_SECTION >NOBITS
|
||||||
|
BSS_SECTION >NOBITS
|
||||||
|
XLAT_TABLE_SECTION >NOBITS
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
/*
|
||||||
|
* The base address of the coherent memory section must be page-aligned (4K)
|
||||||
|
* to guarantee that the coherent data are stored on their own pages and
|
||||||
|
* are not mixed with normal data. This is required to set up the correct
|
||||||
|
* memory attributes for the coherent data page tables.
|
||||||
|
*/
|
||||||
|
coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
|
||||||
|
__COHERENT_RAM_START__ = .;
|
||||||
|
/*
|
||||||
|
* Bakery locks are stored in coherent memory
|
||||||
|
*
|
||||||
|
* Each lock's data is contiguous and fully allocated by the compiler
|
||||||
|
*/
|
||||||
|
*(bakery_lock)
|
||||||
|
*(tzfw_coherent_mem)
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked
|
||||||
|
* as device memory. No other unexpected data must creep in.
|
||||||
|
* Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__COHERENT_RAM_END__ = .;
|
||||||
|
} >NOBITS
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if SEPARATE_NOBITS_REGION
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark end of the NOBITS memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__NOBITS_END__ = .;
|
||||||
|
|
||||||
|
ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.")
|
||||||
|
#else
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark end of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_END__ = .;
|
||||||
|
__BL31_END__ = .;
|
||||||
|
|
||||||
|
ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/DISCARD/ : {
|
||||||
|
*(.dynsym .dynstr .hash .gnu.hash)
|
||||||
|
}
|
||||||
|
}
|
||||||
180
arm-trusted-firmware/bl31/bl31.mk
Normal file
180
arm-trusted-firmware/bl31/bl31.mk
Normal file
@@ -0,0 +1,180 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# Include Makefile for the SPM-MM implementation
|
||||||
|
################################################################################
|
||||||
|
ifeq (${SUPPORT_UNKNOWN_MPID},1)
|
||||||
|
ifeq (${DEBUG},0)
|
||||||
|
$(warning WARNING: SUPPORT_UNKNOWN_MPID enabled)
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${SPM_MM},1)
|
||||||
|
ifeq (${EL3_EXCEPTION_HANDLING},0)
|
||||||
|
$(error EL3_EXCEPTION_HANDLING must be 1 for SPM-MM support)
|
||||||
|
else
|
||||||
|
$(info Including SPM Management Mode (MM) makefile)
|
||||||
|
include services/std_svc/spm/common/spm.mk
|
||||||
|
include services/std_svc/spm/spm_mm/spm_mm.mk
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
include lib/extensions/amu/amu.mk
|
||||||
|
include lib/mpmm/mpmm.mk
|
||||||
|
|
||||||
|
ifeq (${SPMC_AT_EL3},1)
|
||||||
|
$(warning "EL3 SPMC is an experimental feature")
|
||||||
|
$(info Including EL3 SPMC makefile)
|
||||||
|
include services/std_svc/spm/common/spm.mk
|
||||||
|
include services/std_svc/spm/el3_spmc/spmc.mk
|
||||||
|
endif
|
||||||
|
|
||||||
|
include lib/psci/psci_lib.mk
|
||||||
|
|
||||||
|
BL31_SOURCES += bl31/bl31_main.c \
|
||||||
|
bl31/interrupt_mgmt.c \
|
||||||
|
bl31/aarch64/bl31_entrypoint.S \
|
||||||
|
bl31/aarch64/crash_reporting.S \
|
||||||
|
bl31/aarch64/ea_delegate.S \
|
||||||
|
bl31/aarch64/runtime_exceptions.S \
|
||||||
|
bl31/bl31_context_mgmt.c \
|
||||||
|
bl31/bl31_traps.c \
|
||||||
|
common/runtime_svc.c \
|
||||||
|
lib/cpus/aarch64/dsu_helpers.S \
|
||||||
|
plat/common/aarch64/platform_mp_stack.S \
|
||||||
|
services/arm_arch_svc/arm_arch_svc_setup.c \
|
||||||
|
services/std_svc/std_svc_setup.c \
|
||||||
|
${PSCI_LIB_SOURCES} \
|
||||||
|
${SPMD_SOURCES} \
|
||||||
|
${SPM_MM_SOURCES} \
|
||||||
|
${SPMC_SOURCES} \
|
||||||
|
${SPM_SOURCES}
|
||||||
|
|
||||||
|
ifeq (${DISABLE_MTPMU},1)
|
||||||
|
BL31_SOURCES += lib/extensions/mtpmu/aarch64/mtpmu.S
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_PMF}, 1)
|
||||||
|
BL31_SOURCES += lib/pmf/pmf_main.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
include lib/debugfs/debugfs.mk
|
||||||
|
ifeq (${USE_DEBUGFS},1)
|
||||||
|
BL31_SOURCES += $(DEBUGFS_SRCS)
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${EL3_EXCEPTION_HANDLING},1)
|
||||||
|
BL31_SOURCES += bl31/ehf.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${SDEI_SUPPORT},1)
|
||||||
|
ifeq (${EL3_EXCEPTION_HANDLING},0)
|
||||||
|
$(error EL3_EXCEPTION_HANDLING must be 1 for SDEI support)
|
||||||
|
endif
|
||||||
|
BL31_SOURCES += services/std_svc/sdei/sdei_dispatch.S \
|
||||||
|
services/std_svc/sdei/sdei_event.c \
|
||||||
|
services/std_svc/sdei/sdei_intr_mgmt.c \
|
||||||
|
services/std_svc/sdei/sdei_main.c \
|
||||||
|
services/std_svc/sdei/sdei_state.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${TRNG_SUPPORT},1)
|
||||||
|
BL31_SOURCES += services/std_svc/trng/trng_main.c \
|
||||||
|
services/std_svc/trng/trng_entropy_pool.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_SPE_FOR_LOWER_ELS},1)
|
||||||
|
BL31_SOURCES += lib/extensions/spe/spe.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_AMU},1)
|
||||||
|
BL31_SOURCES += ${AMU_SOURCES}
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_MPMM},1)
|
||||||
|
BL31_SOURCES += ${MPMM_SOURCES}
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_SME_FOR_NS},1)
|
||||||
|
BL31_SOURCES += lib/extensions/sme/sme.c
|
||||||
|
BL31_SOURCES += lib/extensions/sve/sve.c
|
||||||
|
else
|
||||||
|
ifeq (${ENABLE_SVE_FOR_NS},1)
|
||||||
|
BL31_SOURCES += lib/extensions/sve/sve.c
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_MPAM_FOR_LOWER_ELS},1)
|
||||||
|
BL31_SOURCES += lib/extensions/mpam/mpam.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_TRBE_FOR_NS},1)
|
||||||
|
BL31_SOURCES += lib/extensions/trbe/trbe.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_BRBE_FOR_NS},1)
|
||||||
|
BL31_SOURCES += lib/extensions/brbe/brbe.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_SYS_REG_TRACE_FOR_NS},1)
|
||||||
|
BL31_SOURCES += lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_TRF_FOR_NS},1)
|
||||||
|
BL31_SOURCES += lib/extensions/trf/aarch64/trf.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${WORKAROUND_CVE_2017_5715},1)
|
||||||
|
BL31_SOURCES += lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S \
|
||||||
|
lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(SMC_PCI_SUPPORT),1)
|
||||||
|
BL31_SOURCES += services/std_svc/pci_svc.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_RME},1)
|
||||||
|
include lib/gpt_rme/gpt_rme.mk
|
||||||
|
|
||||||
|
BL31_SOURCES += ${GPT_LIB_SRCS} \
|
||||||
|
${RMMD_SOURCES}
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(FEATURE_DETECTION),1)
|
||||||
|
BL31_SOURCES += common/feat_detect.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${DRTM_SUPPORT},1)
|
||||||
|
BL31_SOURCES += services/std_svc/drtm/drtm_main.c \
|
||||||
|
services/std_svc/drtm/drtm_dma_prot.c \
|
||||||
|
services/std_svc/drtm/drtm_res_address_map.c \
|
||||||
|
services/std_svc/drtm/drtm_measurements.c \
|
||||||
|
services/std_svc/drtm/drtm_remediation.c \
|
||||||
|
${MBEDTLS_SOURCES}
|
||||||
|
endif
|
||||||
|
|
||||||
|
BL31_LINKERFILE := bl31/bl31.ld.S
|
||||||
|
|
||||||
|
# Flag used to indicate if Crash reporting via console should be included
|
||||||
|
# in BL31. This defaults to being present in DEBUG builds only
|
||||||
|
ifndef CRASH_REPORTING
|
||||||
|
CRASH_REPORTING := $(DEBUG)
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(eval $(call assert_booleans,\
|
||||||
|
$(sort \
|
||||||
|
CRASH_REPORTING \
|
||||||
|
EL3_EXCEPTION_HANDLING \
|
||||||
|
SDEI_SUPPORT \
|
||||||
|
)))
|
||||||
|
|
||||||
|
$(eval $(call add_defines,\
|
||||||
|
$(sort \
|
||||||
|
CRASH_REPORTING \
|
||||||
|
EL3_EXCEPTION_HANDLING \
|
||||||
|
SDEI_SUPPORT \
|
||||||
|
)))
|
||||||
66
arm-trusted-firmware/bl31/bl31_context_mgmt.c
Normal file
66
arm-trusted-firmware/bl31/bl31_context_mgmt.c
Normal file
@@ -0,0 +1,66 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
|
||||||
|
#include <bl31/bl31.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <lib/el3_runtime/context_mgmt.h>
|
||||||
|
#include <lib/el3_runtime/cpu_data.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns a pointer to the most recent 'cpu_context' structure
|
||||||
|
* for the calling CPU that was set as the context for the specified security
|
||||||
|
* state. NULL is returned if no such structure has been specified.
|
||||||
|
******************************************************************************/
|
||||||
|
void *cm_get_context(uint32_t security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
|
||||||
|
return get_cpu_data(cpu_context[get_cpu_context_index(security_state)]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function sets the pointer to the current 'cpu_context' structure for the
|
||||||
|
* specified security state for the calling CPU
|
||||||
|
******************************************************************************/
|
||||||
|
void cm_set_context(void *context, uint32_t security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
|
||||||
|
set_cpu_data(cpu_context[get_cpu_context_index(security_state)],
|
||||||
|
context);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns a pointer to the most recent 'cpu_context' structure
|
||||||
|
* for the CPU identified by `cpu_idx` that was set as the context for the
|
||||||
|
* specified security state. NULL is returned if no such structure has been
|
||||||
|
* specified.
|
||||||
|
******************************************************************************/
|
||||||
|
void *cm_get_context_by_index(unsigned int cpu_idx,
|
||||||
|
unsigned int security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
|
||||||
|
return get_cpu_data_by_index(cpu_idx,
|
||||||
|
cpu_context[get_cpu_context_index(security_state)]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function sets the pointer to the current 'cpu_context' structure for the
|
||||||
|
* specified security state for the CPU identified by CPU index.
|
||||||
|
******************************************************************************/
|
||||||
|
void cm_set_context_by_index(unsigned int cpu_idx, void *context,
|
||||||
|
unsigned int security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
|
||||||
|
set_cpu_data_by_index(cpu_idx,
|
||||||
|
cpu_context[get_cpu_context_index(security_state)],
|
||||||
|
context);
|
||||||
|
}
|
||||||
292
arm-trusted-firmware/bl31/bl31_main.c
Normal file
292
arm-trusted-firmware/bl31/bl31_main.c
Normal file
@@ -0,0 +1,292 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <arch_features.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <bl31/bl31.h>
|
||||||
|
#include <bl31/ehf.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <common/feat_detect.h>
|
||||||
|
#include <common/runtime_svc.h>
|
||||||
|
#include <drivers/console.h>
|
||||||
|
#include <lib/el3_runtime/context_mgmt.h>
|
||||||
|
#include <lib/pmf/pmf.h>
|
||||||
|
#include <lib/runtime_instr.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
#include <services/std_svc.h>
|
||||||
|
|
||||||
|
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||||
|
PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
|
||||||
|
RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function pointer is used to initialise the BL32 image. It's initialized
|
||||||
|
* by SPD calling bl31_register_bl32_init after setting up all things necessary
|
||||||
|
* for SP execution. In cases where both SPD and SP are absent, or when SPD
|
||||||
|
* finds it impossible to execute SP, this pointer is left as NULL
|
||||||
|
******************************************************************************/
|
||||||
|
static int32_t (*bl32_init)(void);
|
||||||
|
|
||||||
|
/*****************************************************************************
|
||||||
|
* Function used to initialise RMM if RME is enabled
|
||||||
|
*****************************************************************************/
|
||||||
|
#if ENABLE_RME
|
||||||
|
static int32_t (*rmm_init)(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variable to indicate whether next image to execute after BL31 is BL33
|
||||||
|
* (non-secure & default) or BL32 (secure).
|
||||||
|
******************************************************************************/
|
||||||
|
static uint32_t next_image_type = NON_SECURE;
|
||||||
|
|
||||||
|
#ifdef SUPPORT_UNKNOWN_MPID
|
||||||
|
/*
|
||||||
|
* Flag to know whether an unsupported MPID has been detected. To avoid having it
|
||||||
|
* landing on the .bss section, it is initialized to a non-zero value, this way
|
||||||
|
* we avoid potential WAW hazards during system bring up.
|
||||||
|
* */
|
||||||
|
volatile uint32_t unsupported_mpid_flag = 1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Implement the ARM Standard Service function to get arguments for a
|
||||||
|
* particular service.
|
||||||
|
*/
|
||||||
|
uintptr_t get_arm_std_svc_args(unsigned int svc_mask)
|
||||||
|
{
|
||||||
|
/* Setup the arguments for PSCI Library */
|
||||||
|
DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, bl31_warm_entrypoint);
|
||||||
|
|
||||||
|
/* PSCI is the only ARM Standard Service implemented */
|
||||||
|
assert(svc_mask == PSCI_FID_MASK);
|
||||||
|
|
||||||
|
return (uintptr_t)&psci_args;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Simple function to initialise all BL31 helper libraries.
|
||||||
|
******************************************************************************/
|
||||||
|
void __init bl31_lib_init(void)
|
||||||
|
{
|
||||||
|
cm_init();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Setup function for BL31.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl31_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
|
||||||
|
u_register_t arg3)
|
||||||
|
{
|
||||||
|
/* Perform early platform-specific setup */
|
||||||
|
bl31_early_platform_setup2(arg0, arg1, arg2, arg3);
|
||||||
|
|
||||||
|
/* Perform late platform-specific setup */
|
||||||
|
bl31_plat_arch_setup();
|
||||||
|
|
||||||
|
#if ENABLE_FEAT_HCX
|
||||||
|
/*
|
||||||
|
* Assert that FEAT_HCX is supported on this system, without this check
|
||||||
|
* an exception would occur during context save/restore if enabled but
|
||||||
|
* not supported.
|
||||||
|
*/
|
||||||
|
assert(is_feat_hcx_present());
|
||||||
|
#endif /* ENABLE_FEAT_HCX */
|
||||||
|
|
||||||
|
#if CTX_INCLUDE_PAUTH_REGS
|
||||||
|
/*
|
||||||
|
* Assert that the ARMv8.3-PAuth registers are present or an access
|
||||||
|
* fault will be triggered when they are being saved or restored.
|
||||||
|
*/
|
||||||
|
assert(is_armv8_3_pauth_present());
|
||||||
|
#endif /* CTX_INCLUDE_PAUTH_REGS */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* BL31 is responsible for setting up the runtime services for the primary cpu
|
||||||
|
* before passing control to the bootloader or an Operating System. This
|
||||||
|
* function calls runtime_svc_init() which initializes all registered runtime
|
||||||
|
* services. The run time services would setup enough context for the core to
|
||||||
|
* switch to the next exception level. When this function returns, the core will
|
||||||
|
* switch to the programmed exception level via an ERET.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl31_main(void)
|
||||||
|
{
|
||||||
|
NOTICE("BL31: %s\n", version_string);
|
||||||
|
NOTICE("BL31: %s\n", build_message);
|
||||||
|
|
||||||
|
#if FEATURE_DETECTION
|
||||||
|
/* Detect if features enabled during compilation are supported by PE. */
|
||||||
|
detect_arch_features();
|
||||||
|
#endif /* FEATURE_DETECTION */
|
||||||
|
|
||||||
|
#ifdef SUPPORT_UNKNOWN_MPID
|
||||||
|
if (unsupported_mpid_flag == 0) {
|
||||||
|
NOTICE("Unsupported MPID detected!\n");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Perform platform setup in BL31 */
|
||||||
|
bl31_platform_setup();
|
||||||
|
|
||||||
|
/* Initialise helper libraries */
|
||||||
|
bl31_lib_init();
|
||||||
|
|
||||||
|
#if EL3_EXCEPTION_HANDLING
|
||||||
|
INFO("BL31: Initialising Exception Handling Framework\n");
|
||||||
|
ehf_init();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Initialize the runtime services e.g. psci. */
|
||||||
|
INFO("BL31: Initializing runtime services\n");
|
||||||
|
runtime_svc_init();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* All the cold boot actions on the primary cpu are done. We now need to
|
||||||
|
* decide which is the next image and how to execute it.
|
||||||
|
* If the SPD runtime service is present, it would want to pass control
|
||||||
|
* to BL32 first in S-EL1. In that case, SPD would have registered a
|
||||||
|
* function to initialize bl32 where it takes responsibility of entering
|
||||||
|
* S-EL1 and returning control back to bl31_main. Similarly, if RME is
|
||||||
|
* enabled and a function is registered to initialize RMM, control is
|
||||||
|
* transferred to RMM in R-EL2. After RMM initialization, control is
|
||||||
|
* returned back to bl31_main. Once this is done we can prepare entry
|
||||||
|
* into BL33 as normal.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If SPD had registered an init hook, invoke it.
|
||||||
|
*/
|
||||||
|
if (bl32_init != NULL) {
|
||||||
|
INFO("BL31: Initializing BL32\n");
|
||||||
|
|
||||||
|
int32_t rc = (*bl32_init)();
|
||||||
|
|
||||||
|
if (rc == 0) {
|
||||||
|
WARN("BL31: BL32 initialization failed\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If RME is enabled and init hook is registered, initialize RMM
|
||||||
|
* in R-EL2.
|
||||||
|
*/
|
||||||
|
#if ENABLE_RME
|
||||||
|
if (rmm_init != NULL) {
|
||||||
|
INFO("BL31: Initializing RMM\n");
|
||||||
|
|
||||||
|
int32_t rc = (*rmm_init)();
|
||||||
|
|
||||||
|
if (rc == 0) {
|
||||||
|
WARN("BL31: RMM initialization failed\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are ready to enter the next EL. Prepare entry into the image
|
||||||
|
* corresponding to the desired security state after the next ERET.
|
||||||
|
*/
|
||||||
|
bl31_prepare_next_image_entry();
|
||||||
|
|
||||||
|
console_flush();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Perform any platform specific runtime setup prior to cold boot exit
|
||||||
|
* from BL31
|
||||||
|
*/
|
||||||
|
bl31_plat_runtime_setup();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Accessor functions to help runtime services decide which image should be
|
||||||
|
* executed after BL31. This is BL33 or the non-secure bootloader image by
|
||||||
|
* default but the Secure payload dispatcher could override this by requesting
|
||||||
|
* an entry into BL32 (Secure payload) first. If it does so then it should use
|
||||||
|
* the same API to program an entry into BL33 once BL32 initialisation is
|
||||||
|
* complete.
|
||||||
|
******************************************************************************/
|
||||||
|
void bl31_set_next_image_type(uint32_t security_state)
|
||||||
|
{
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
next_image_type = security_state;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t bl31_get_next_image_type(void)
|
||||||
|
{
|
||||||
|
return next_image_type;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function programs EL3 registers and performs other setup to enable entry
|
||||||
|
* into the next image after BL31 at the next ERET.
|
||||||
|
******************************************************************************/
|
||||||
|
void __init bl31_prepare_next_image_entry(void)
|
||||||
|
{
|
||||||
|
entry_point_info_t *next_image_info;
|
||||||
|
uint32_t image_type;
|
||||||
|
|
||||||
|
#if CTX_INCLUDE_AARCH32_REGS
|
||||||
|
/*
|
||||||
|
* Ensure that the build flag to save AArch32 system registers in CPU
|
||||||
|
* context is not set for AArch64-only platforms.
|
||||||
|
*/
|
||||||
|
if (el_implemented(1) == EL_IMPL_A64ONLY) {
|
||||||
|
ERROR("EL1 supports AArch64-only. Please set build flag "
|
||||||
|
"CTX_INCLUDE_AARCH32_REGS = 0\n");
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Determine which image to execute next */
|
||||||
|
image_type = bl31_get_next_image_type();
|
||||||
|
|
||||||
|
/* Program EL3 registers to enable entry into the next EL */
|
||||||
|
next_image_info = bl31_plat_get_next_image_ep_info(image_type);
|
||||||
|
assert(next_image_info != NULL);
|
||||||
|
assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr));
|
||||||
|
|
||||||
|
INFO("BL31: Preparing for EL3 exit to %s world\n",
|
||||||
|
(image_type == SECURE) ? "secure" : "normal");
|
||||||
|
print_entry_point_info(next_image_info);
|
||||||
|
cm_init_my_context(next_image_info);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If we are entering the Non-secure world, use
|
||||||
|
* 'cm_prepare_el3_exit_ns' to exit.
|
||||||
|
*/
|
||||||
|
if (image_type == NON_SECURE) {
|
||||||
|
cm_prepare_el3_exit_ns();
|
||||||
|
} else {
|
||||||
|
cm_prepare_el3_exit(image_type);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function initializes the pointer to BL32 init function. This is expected
|
||||||
|
* to be called by the SPD after it finishes all its initialization
|
||||||
|
******************************************************************************/
|
||||||
|
void bl31_register_bl32_init(int32_t (*func)(void))
|
||||||
|
{
|
||||||
|
bl32_init = func;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ENABLE_RME
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function initializes the pointer to RMM init function. This is expected
|
||||||
|
* to be called by the RMMD after it finishes all its initialization
|
||||||
|
******************************************************************************/
|
||||||
|
void bl31_register_rmm_init(int32_t (*func)(void))
|
||||||
|
{
|
||||||
|
rmm_init = func;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
30
arm-trusted-firmware/bl31/bl31_traps.c
Normal file
30
arm-trusted-firmware/bl31/bl31_traps.c
Normal file
@@ -0,0 +1,30 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2022, ARM Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*
|
||||||
|
* Dispatch synchronous system register traps from lower ELs.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <bl31/sync_handle.h>
|
||||||
|
#include <context.h>
|
||||||
|
|
||||||
|
int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx)
|
||||||
|
{
|
||||||
|
uint64_t __unused opcode = esr_el3 & ISS_SYSREG_OPCODE_MASK;
|
||||||
|
|
||||||
|
#if ENABLE_FEAT_RNG_TRAP
|
||||||
|
if ((opcode == ISS_SYSREG_OPCODE_RNDR) || (opcode == ISS_SYSREG_OPCODE_RNDRRS)) {
|
||||||
|
return plat_handle_rng_trap(esr_el3, ctx);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLE_FEAT_IMPDEF_TRAP
|
||||||
|
if ((opcode & ISS_SYSREG_OPCODE_IMPDEF) == ISS_SYSREG_OPCODE_IMPDEF) {
|
||||||
|
return plat_handle_impdef_trap(esr_el3, ctx);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return TRAP_RET_UNHANDLED;
|
||||||
|
}
|
||||||
533
arm-trusted-firmware/bl31/ehf.c
Normal file
533
arm-trusted-firmware/bl31/ehf.c
Normal file
@@ -0,0 +1,533 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Exception handlers at EL3, their priority levels, and management.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
|
||||||
|
#include <bl31/ehf.h>
|
||||||
|
#include <bl31/interrupt_mgmt.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <drivers/arm/gic_common.h>
|
||||||
|
#include <lib/el3_runtime/context_mgmt.h>
|
||||||
|
#include <lib/el3_runtime/cpu_data.h>
|
||||||
|
#include <lib/el3_runtime/pubsub_events.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
/* Output EHF logs as verbose */
|
||||||
|
#define EHF_LOG(...) VERBOSE("EHF: " __VA_ARGS__)
|
||||||
|
|
||||||
|
#define EHF_INVALID_IDX (-1)
|
||||||
|
|
||||||
|
/* For a valid handler, return the actual function pointer; otherwise, 0. */
|
||||||
|
#define RAW_HANDLER(h) \
|
||||||
|
((ehf_handler_t) ((((h) & EHF_PRI_VALID_) != 0U) ? \
|
||||||
|
((h) & ~EHF_PRI_VALID_) : 0U))
|
||||||
|
|
||||||
|
#define PRI_BIT(idx) (((ehf_pri_bits_t) 1u) << (idx))
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Convert index into secure priority using the platform-defined priority bits
|
||||||
|
* field.
|
||||||
|
*/
|
||||||
|
#define IDX_TO_PRI(idx) \
|
||||||
|
((((unsigned) idx) << (7u - exception_data.pri_bits)) & 0x7fU)
|
||||||
|
|
||||||
|
/* Check whether a given index is valid */
|
||||||
|
#define IS_IDX_VALID(idx) \
|
||||||
|
((exception_data.ehf_priorities[idx].ehf_handler & EHF_PRI_VALID_) != 0U)
|
||||||
|
|
||||||
|
/* Returns whether given priority is in secure priority range */
|
||||||
|
#define IS_PRI_SECURE(pri) (((pri) & 0x80U) == 0U)
|
||||||
|
|
||||||
|
/* To be defined by the platform */
|
||||||
|
extern const ehf_priorities_t exception_data;
|
||||||
|
|
||||||
|
/* Translate priority to the index in the priority array */
|
||||||
|
static unsigned int pri_to_idx(unsigned int priority)
|
||||||
|
{
|
||||||
|
unsigned int idx;
|
||||||
|
|
||||||
|
idx = EHF_PRI_TO_IDX(priority, exception_data.pri_bits);
|
||||||
|
assert(idx < exception_data.num_priorities);
|
||||||
|
assert(IS_IDX_VALID(idx));
|
||||||
|
|
||||||
|
return idx;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return whether there are outstanding priority activation */
|
||||||
|
static bool has_valid_pri_activations(pe_exc_data_t *pe_data)
|
||||||
|
{
|
||||||
|
return pe_data->active_pri_bits != 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
static pe_exc_data_t *this_cpu_data(void)
|
||||||
|
{
|
||||||
|
return &get_cpu_data(ehf_data);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return the current priority index of this CPU. If no priority is active,
|
||||||
|
* return EHF_INVALID_IDX.
|
||||||
|
*/
|
||||||
|
static int get_pe_highest_active_idx(pe_exc_data_t *pe_data)
|
||||||
|
{
|
||||||
|
if (!has_valid_pri_activations(pe_data))
|
||||||
|
return EHF_INVALID_IDX;
|
||||||
|
|
||||||
|
/* Current priority is the right-most bit */
|
||||||
|
return (int) __builtin_ctz(pe_data->active_pri_bits);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Mark priority active by setting the corresponding bit in active_pri_bits and
|
||||||
|
* programming the priority mask.
|
||||||
|
*
|
||||||
|
* This API is to be used as part of delegating to lower ELs other than for
|
||||||
|
* interrupts; e.g. while handling synchronous exceptions.
|
||||||
|
*
|
||||||
|
* This API is expected to be invoked before restoring context (Secure or
|
||||||
|
* Non-secure) in preparation for the respective dispatch.
|
||||||
|
*/
|
||||||
|
void ehf_activate_priority(unsigned int priority)
|
||||||
|
{
|
||||||
|
int cur_pri_idx;
|
||||||
|
unsigned int old_mask, run_pri, idx;
|
||||||
|
pe_exc_data_t *pe_data = this_cpu_data();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Query interrupt controller for the running priority, or idle priority
|
||||||
|
* if no interrupts are being handled. The requested priority must be
|
||||||
|
* less (higher priority) than the active running priority.
|
||||||
|
*/
|
||||||
|
run_pri = plat_ic_get_running_priority();
|
||||||
|
if (priority >= run_pri) {
|
||||||
|
ERROR("Running priority higher (0x%x) than requested (0x%x)\n",
|
||||||
|
run_pri, priority);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If there were priority activations already, the requested priority
|
||||||
|
* must be less (higher priority) than the current highest priority
|
||||||
|
* activation so far.
|
||||||
|
*/
|
||||||
|
cur_pri_idx = get_pe_highest_active_idx(pe_data);
|
||||||
|
idx = pri_to_idx(priority);
|
||||||
|
if ((cur_pri_idx != EHF_INVALID_IDX) &&
|
||||||
|
(idx >= ((unsigned int) cur_pri_idx))) {
|
||||||
|
ERROR("Activation priority mismatch: req=0x%x current=0x%x\n",
|
||||||
|
priority, IDX_TO_PRI(cur_pri_idx));
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set the bit corresponding to the requested priority */
|
||||||
|
pe_data->active_pri_bits |= PRI_BIT(idx);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Program priority mask for the activated level. Check that the new
|
||||||
|
* priority mask is setting a higher priority level than the existing
|
||||||
|
* mask.
|
||||||
|
*/
|
||||||
|
old_mask = plat_ic_set_priority_mask(priority);
|
||||||
|
if (priority >= old_mask) {
|
||||||
|
ERROR("Requested priority (0x%x) lower than Priority Mask (0x%x)\n",
|
||||||
|
priority, old_mask);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If this is the first activation, save the priority mask. This will be
|
||||||
|
* restored after the last deactivation.
|
||||||
|
*/
|
||||||
|
if (cur_pri_idx == EHF_INVALID_IDX)
|
||||||
|
pe_data->init_pri_mask = (uint8_t) old_mask;
|
||||||
|
|
||||||
|
EHF_LOG("activate prio=%d\n", get_pe_highest_active_idx(pe_data));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Mark priority inactive by clearing the corresponding bit in active_pri_bits,
|
||||||
|
* and programming the priority mask.
|
||||||
|
*
|
||||||
|
* This API is expected to be used as part of delegating to to lower ELs other
|
||||||
|
* than for interrupts; e.g. while handling synchronous exceptions.
|
||||||
|
*
|
||||||
|
* This API is expected to be invoked after saving context (Secure or
|
||||||
|
* Non-secure), having concluded the respective dispatch.
|
||||||
|
*/
|
||||||
|
void ehf_deactivate_priority(unsigned int priority)
|
||||||
|
{
|
||||||
|
int cur_pri_idx;
|
||||||
|
pe_exc_data_t *pe_data = this_cpu_data();
|
||||||
|
unsigned int old_mask, run_pri, idx;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Query interrupt controller for the running priority, or idle priority
|
||||||
|
* if no interrupts are being handled. The requested priority must be
|
||||||
|
* less (higher priority) than the active running priority.
|
||||||
|
*/
|
||||||
|
run_pri = plat_ic_get_running_priority();
|
||||||
|
if (priority >= run_pri) {
|
||||||
|
ERROR("Running priority higher (0x%x) than requested (0x%x)\n",
|
||||||
|
run_pri, priority);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Deactivation is allowed only when there are priority activations, and
|
||||||
|
* the deactivation priority level must match the current activated
|
||||||
|
* priority.
|
||||||
|
*/
|
||||||
|
cur_pri_idx = get_pe_highest_active_idx(pe_data);
|
||||||
|
idx = pri_to_idx(priority);
|
||||||
|
if ((cur_pri_idx == EHF_INVALID_IDX) ||
|
||||||
|
(idx != ((unsigned int) cur_pri_idx))) {
|
||||||
|
ERROR("Deactivation priority mismatch: req=0x%x current=0x%x\n",
|
||||||
|
priority, IDX_TO_PRI(cur_pri_idx));
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear bit corresponding to highest priority */
|
||||||
|
pe_data->active_pri_bits &= (pe_data->active_pri_bits - 1u);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Restore priority mask corresponding to the next priority, or the
|
||||||
|
* one stashed earlier if there are no more to deactivate.
|
||||||
|
*/
|
||||||
|
cur_pri_idx = get_pe_highest_active_idx(pe_data);
|
||||||
|
if (cur_pri_idx == EHF_INVALID_IDX)
|
||||||
|
old_mask = plat_ic_set_priority_mask(pe_data->init_pri_mask);
|
||||||
|
else
|
||||||
|
old_mask = plat_ic_set_priority_mask(priority);
|
||||||
|
|
||||||
|
if (old_mask > priority) {
|
||||||
|
ERROR("Deactivation priority (0x%x) lower than Priority Mask (0x%x)\n",
|
||||||
|
priority, old_mask);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
EHF_LOG("deactivate prio=%d\n", get_pe_highest_active_idx(pe_data));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* After leaving Non-secure world, stash current Non-secure Priority Mask, and
|
||||||
|
* set Priority Mask to the highest Non-secure priority so that Non-secure
|
||||||
|
* interrupts cannot preempt Secure execution.
|
||||||
|
*
|
||||||
|
* If the current running priority is in the secure range, or if there are
|
||||||
|
* outstanding priority activations, this function does nothing.
|
||||||
|
*
|
||||||
|
* This function subscribes to the 'cm_exited_normal_world' event published by
|
||||||
|
* the Context Management Library.
|
||||||
|
*/
|
||||||
|
static void *ehf_exited_normal_world(const void *arg)
|
||||||
|
{
|
||||||
|
unsigned int run_pri;
|
||||||
|
pe_exc_data_t *pe_data = this_cpu_data();
|
||||||
|
|
||||||
|
/* If the running priority is in the secure range, do nothing */
|
||||||
|
run_pri = plat_ic_get_running_priority();
|
||||||
|
if (IS_PRI_SECURE(run_pri))
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
/* Do nothing if there are explicit activations */
|
||||||
|
if (has_valid_pri_activations(pe_data))
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
assert(pe_data->ns_pri_mask == 0u);
|
||||||
|
|
||||||
|
pe_data->ns_pri_mask =
|
||||||
|
(uint8_t) plat_ic_set_priority_mask(GIC_HIGHEST_NS_PRIORITY);
|
||||||
|
|
||||||
|
/* The previous Priority Mask is not expected to be in secure range */
|
||||||
|
if (IS_PRI_SECURE(pe_data->ns_pri_mask)) {
|
||||||
|
ERROR("Priority Mask (0x%x) already in secure range\n",
|
||||||
|
pe_data->ns_pri_mask);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
EHF_LOG("Priority Mask: 0x%x => 0x%x\n", pe_data->ns_pri_mask,
|
||||||
|
GIC_HIGHEST_NS_PRIORITY);
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Conclude Secure execution and prepare for return to Non-secure world. Restore
|
||||||
|
* the Non-secure Priority Mask previously stashed upon leaving Non-secure
|
||||||
|
* world.
|
||||||
|
*
|
||||||
|
* If there the current running priority is in the secure range, or if there are
|
||||||
|
* outstanding priority activations, this function does nothing.
|
||||||
|
*
|
||||||
|
* This function subscribes to the 'cm_entering_normal_world' event published by
|
||||||
|
* the Context Management Library.
|
||||||
|
*/
|
||||||
|
static void *ehf_entering_normal_world(const void *arg)
|
||||||
|
{
|
||||||
|
unsigned int old_pmr, run_pri;
|
||||||
|
pe_exc_data_t *pe_data = this_cpu_data();
|
||||||
|
|
||||||
|
/* If the running priority is in the secure range, do nothing */
|
||||||
|
run_pri = plat_ic_get_running_priority();
|
||||||
|
if (IS_PRI_SECURE(run_pri))
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If there are explicit activations, do nothing. The Priority Mask will
|
||||||
|
* be restored upon the last deactivation.
|
||||||
|
*/
|
||||||
|
if (has_valid_pri_activations(pe_data))
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
/* Do nothing if we don't have a valid Priority Mask to restore */
|
||||||
|
if (pe_data->ns_pri_mask == 0U)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
old_pmr = plat_ic_set_priority_mask(pe_data->ns_pri_mask);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* When exiting secure world, the current Priority Mask must be
|
||||||
|
* GIC_HIGHEST_NS_PRIORITY (as set during entry), or the Non-secure
|
||||||
|
* priority mask set upon calling ehf_allow_ns_preemption()
|
||||||
|
*/
|
||||||
|
if ((old_pmr != GIC_HIGHEST_NS_PRIORITY) &&
|
||||||
|
(old_pmr != pe_data->ns_pri_mask)) {
|
||||||
|
ERROR("Invalid Priority Mask (0x%x) restored\n", old_pmr);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
EHF_LOG("Priority Mask: 0x%x => 0x%x\n", old_pmr, pe_data->ns_pri_mask);
|
||||||
|
|
||||||
|
pe_data->ns_pri_mask = 0;
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Program Priority Mask to the original Non-secure priority such that
|
||||||
|
* Non-secure interrupts may preempt Secure execution (for example, during
|
||||||
|
* Yielding SMC calls). The 'preempt_ret_code' parameter indicates the Yielding
|
||||||
|
* SMC's return value in case the call was preempted.
|
||||||
|
*
|
||||||
|
* This API is expected to be invoked before delegating a yielding SMC to Secure
|
||||||
|
* EL1. I.e. within the window of secure execution after Non-secure context is
|
||||||
|
* saved (after entry into EL3) and Secure context is restored (before entering
|
||||||
|
* Secure EL1).
|
||||||
|
*/
|
||||||
|
void ehf_allow_ns_preemption(uint64_t preempt_ret_code)
|
||||||
|
{
|
||||||
|
cpu_context_t *ns_ctx;
|
||||||
|
unsigned int old_pmr __unused;
|
||||||
|
pe_exc_data_t *pe_data = this_cpu_data();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We should have been notified earlier of entering secure world, and
|
||||||
|
* therefore have stashed the Non-secure priority mask.
|
||||||
|
*/
|
||||||
|
assert(pe_data->ns_pri_mask != 0U);
|
||||||
|
|
||||||
|
/* Make sure no priority levels are active when requesting this */
|
||||||
|
if (has_valid_pri_activations(pe_data)) {
|
||||||
|
ERROR("PE %lx has priority activations: 0x%x\n",
|
||||||
|
read_mpidr_el1(), pe_data->active_pri_bits);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Program preempted return code to x0 right away so that, if the
|
||||||
|
* Yielding SMC was indeed preempted before a dispatcher gets a chance
|
||||||
|
* to populate it, the caller would find the correct return value.
|
||||||
|
*/
|
||||||
|
ns_ctx = cm_get_context(NON_SECURE);
|
||||||
|
assert(ns_ctx != NULL);
|
||||||
|
write_ctx_reg(get_gpregs_ctx(ns_ctx), CTX_GPREG_X0, preempt_ret_code);
|
||||||
|
|
||||||
|
old_pmr = plat_ic_set_priority_mask(pe_data->ns_pri_mask);
|
||||||
|
|
||||||
|
EHF_LOG("Priority Mask: 0x%x => 0x%x\n", old_pmr, pe_data->ns_pri_mask);
|
||||||
|
|
||||||
|
pe_data->ns_pri_mask = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return whether Secure execution has explicitly allowed Non-secure interrupts
|
||||||
|
* to preempt itself (for example, during Yielding SMC calls).
|
||||||
|
*/
|
||||||
|
unsigned int ehf_is_ns_preemption_allowed(void)
|
||||||
|
{
|
||||||
|
unsigned int run_pri;
|
||||||
|
pe_exc_data_t *pe_data = this_cpu_data();
|
||||||
|
|
||||||
|
/* If running priority is in secure range, return false */
|
||||||
|
run_pri = plat_ic_get_running_priority();
|
||||||
|
if (IS_PRI_SECURE(run_pri))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If Non-secure preemption was permitted by calling
|
||||||
|
* ehf_allow_ns_preemption() earlier:
|
||||||
|
*
|
||||||
|
* - There wouldn't have been priority activations;
|
||||||
|
* - We would have cleared the stashed the Non-secure Priority Mask.
|
||||||
|
*/
|
||||||
|
if (has_valid_pri_activations(pe_data))
|
||||||
|
return 0;
|
||||||
|
if (pe_data->ns_pri_mask != 0U)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Top-level EL3 interrupt handler.
|
||||||
|
*/
|
||||||
|
static uint64_t ehf_el3_interrupt_handler(uint32_t id, uint32_t flags,
|
||||||
|
void *handle, void *cookie)
|
||||||
|
{
|
||||||
|
int ret = 0;
|
||||||
|
uint32_t intr_raw;
|
||||||
|
unsigned int intr, pri, idx;
|
||||||
|
ehf_handler_t handler;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Top-level interrupt type handler from Interrupt Management Framework
|
||||||
|
* doesn't acknowledge the interrupt; so the interrupt ID must be
|
||||||
|
* invalid.
|
||||||
|
*/
|
||||||
|
assert(id == INTR_ID_UNAVAILABLE);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Acknowledge interrupt. Proceed with handling only for valid interrupt
|
||||||
|
* IDs. This situation may arise because of Interrupt Management
|
||||||
|
* Framework identifying an EL3 interrupt, but before it's been
|
||||||
|
* acknowledged here, the interrupt was either deasserted, or there was
|
||||||
|
* a higher-priority interrupt of another type.
|
||||||
|
*/
|
||||||
|
intr_raw = plat_ic_acknowledge_interrupt();
|
||||||
|
intr = plat_ic_get_interrupt_id(intr_raw);
|
||||||
|
if (intr == INTR_ID_UNAVAILABLE)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
/* Having acknowledged the interrupt, get the running priority */
|
||||||
|
pri = plat_ic_get_running_priority();
|
||||||
|
|
||||||
|
/* Check EL3 interrupt priority is in secure range */
|
||||||
|
assert(IS_PRI_SECURE(pri));
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Translate the priority to a descriptor index. We do this by masking
|
||||||
|
* and shifting the running priority value (platform-supplied).
|
||||||
|
*/
|
||||||
|
idx = pri_to_idx(pri);
|
||||||
|
|
||||||
|
/* Validate priority */
|
||||||
|
assert(pri == IDX_TO_PRI(idx));
|
||||||
|
|
||||||
|
handler = (ehf_handler_t) RAW_HANDLER(
|
||||||
|
exception_data.ehf_priorities[idx].ehf_handler);
|
||||||
|
if (handler == NULL) {
|
||||||
|
ERROR("No EL3 exception handler for priority 0x%x\n",
|
||||||
|
IDX_TO_PRI(idx));
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Call registered handler. Pass the raw interrupt value to registered
|
||||||
|
* handlers.
|
||||||
|
*/
|
||||||
|
ret = handler(intr_raw, flags, handle, cookie);
|
||||||
|
|
||||||
|
return (uint64_t) ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Initialize the EL3 exception handling.
|
||||||
|
*/
|
||||||
|
void __init ehf_init(void)
|
||||||
|
{
|
||||||
|
unsigned int flags = 0;
|
||||||
|
int ret __unused;
|
||||||
|
|
||||||
|
/* Ensure EL3 interrupts are supported */
|
||||||
|
assert(plat_ic_has_interrupt_type(INTR_TYPE_EL3) != 0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Make sure that priority water mark has enough bits to represent the
|
||||||
|
* whole priority array.
|
||||||
|
*/
|
||||||
|
assert(exception_data.num_priorities <= (sizeof(ehf_pri_bits_t) * 8U));
|
||||||
|
|
||||||
|
assert(exception_data.ehf_priorities != NULL);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Bit 7 of GIC priority must be 0 for secure interrupts. This means
|
||||||
|
* platforms must use at least 1 of the remaining 7 bits.
|
||||||
|
*/
|
||||||
|
assert((exception_data.pri_bits >= 1U) ||
|
||||||
|
(exception_data.pri_bits < 8U));
|
||||||
|
|
||||||
|
/* Route EL3 interrupts when in Non-secure. */
|
||||||
|
set_interrupt_rm_flag(flags, NON_SECURE);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Route EL3 interrupts when in secure, only when SPMC is not present
|
||||||
|
* in S-EL2.
|
||||||
|
*/
|
||||||
|
#if !(defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1))
|
||||||
|
set_interrupt_rm_flag(flags, SECURE);
|
||||||
|
#endif /* !(defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1)) */
|
||||||
|
|
||||||
|
/* Register handler for EL3 interrupts */
|
||||||
|
ret = register_interrupt_type_handler(INTR_TYPE_EL3,
|
||||||
|
ehf_el3_interrupt_handler, flags);
|
||||||
|
assert(ret == 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Register a handler at the supplied priority. Registration is allowed only if
|
||||||
|
* a handler hasn't been registered before, or one wasn't provided at build
|
||||||
|
* time. The priority for which the handler is being registered must also accord
|
||||||
|
* with the platform-supplied data.
|
||||||
|
*/
|
||||||
|
void ehf_register_priority_handler(unsigned int pri, ehf_handler_t handler)
|
||||||
|
{
|
||||||
|
unsigned int idx;
|
||||||
|
|
||||||
|
/* Sanity check for handler */
|
||||||
|
assert(handler != NULL);
|
||||||
|
|
||||||
|
/* Handler ought to be 4-byte aligned */
|
||||||
|
assert((((uintptr_t) handler) & 3U) == 0U);
|
||||||
|
|
||||||
|
/* Ensure we register for valid priority */
|
||||||
|
idx = pri_to_idx(pri);
|
||||||
|
assert(idx < exception_data.num_priorities);
|
||||||
|
assert(IDX_TO_PRI(idx) == pri);
|
||||||
|
|
||||||
|
/* Return failure if a handler was already registered */
|
||||||
|
if (exception_data.ehf_priorities[idx].ehf_handler != EHF_NO_HANDLER_) {
|
||||||
|
ERROR("Handler already registered for priority 0x%x\n", pri);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Install handler, and retain the valid bit. We assume that the handler
|
||||||
|
* is 4-byte aligned, which is usually the case.
|
||||||
|
*/
|
||||||
|
exception_data.ehf_priorities[idx].ehf_handler =
|
||||||
|
(((uintptr_t) handler) | EHF_PRI_VALID_);
|
||||||
|
|
||||||
|
EHF_LOG("register pri=0x%x handler=%p\n", pri, handler);
|
||||||
|
}
|
||||||
|
|
||||||
|
SUBSCRIBE_TO_EVENT(cm_entering_normal_world, ehf_entering_normal_world);
|
||||||
|
SUBSCRIBE_TO_EVENT(cm_exited_normal_world, ehf_exited_normal_world);
|
||||||
227
arm-trusted-firmware/bl31/interrupt_mgmt.c
Normal file
227
arm-trusted-firmware/bl31/interrupt_mgmt.c
Normal file
@@ -0,0 +1,227 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <errno.h>
|
||||||
|
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <bl31/interrupt_mgmt.h>
|
||||||
|
#include <lib/el3_runtime/context_mgmt.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Local structure and corresponding array to keep track of the state of the
|
||||||
|
* registered interrupt handlers for each interrupt type.
|
||||||
|
* The field descriptions are:
|
||||||
|
*
|
||||||
|
* 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the
|
||||||
|
* value of the SCR_EL3.IRQ or FIQ bit for each security state.
|
||||||
|
* There are two instances of this field corresponding to the
|
||||||
|
* two security states.
|
||||||
|
*
|
||||||
|
* 'flags' : Bit[0], Routing model for this interrupt type when execution is
|
||||||
|
* not in EL3 in the secure state. '1' implies that this
|
||||||
|
* interrupt will be routed to EL3. '0' implies that this
|
||||||
|
* interrupt will be routed to the current exception level.
|
||||||
|
*
|
||||||
|
* Bit[1], Routing model for this interrupt type when execution is
|
||||||
|
* not in EL3 in the non-secure state. '1' implies that this
|
||||||
|
* interrupt will be routed to EL3. '0' implies that this
|
||||||
|
* interrupt will be routed to the current exception level.
|
||||||
|
*
|
||||||
|
* All other bits are reserved and SBZ.
|
||||||
|
******************************************************************************/
|
||||||
|
typedef struct intr_type_desc {
|
||||||
|
interrupt_type_handler_t handler;
|
||||||
|
u_register_t scr_el3[2];
|
||||||
|
uint32_t flags;
|
||||||
|
} intr_type_desc_t;
|
||||||
|
|
||||||
|
static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES];
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function validates the interrupt type.
|
||||||
|
******************************************************************************/
|
||||||
|
static int32_t validate_interrupt_type(uint32_t type)
|
||||||
|
{
|
||||||
|
if ((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_NS) ||
|
||||||
|
(type == INTR_TYPE_EL3))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function validates the routing model for this type of interrupt
|
||||||
|
******************************************************************************/
|
||||||
|
static int32_t validate_routing_model(uint32_t type, uint32_t flags)
|
||||||
|
{
|
||||||
|
uint32_t rm_flags = (flags >> INTR_RM_FLAGS_SHIFT) & INTR_RM_FLAGS_MASK;
|
||||||
|
|
||||||
|
if (type == INTR_TYPE_S_EL1)
|
||||||
|
return validate_sel1_interrupt_rm(rm_flags);
|
||||||
|
|
||||||
|
if (type == INTR_TYPE_NS)
|
||||||
|
return validate_ns_interrupt_rm(rm_flags);
|
||||||
|
|
||||||
|
if (type == INTR_TYPE_EL3)
|
||||||
|
return validate_el3_interrupt_rm(rm_flags);
|
||||||
|
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns the cached copy of the SCR_EL3 which contains the
|
||||||
|
* routing model (expressed through the IRQ and FIQ bits) for a security state
|
||||||
|
* which was stored through a call to 'set_routing_model()' earlier.
|
||||||
|
******************************************************************************/
|
||||||
|
u_register_t get_scr_el3_from_routing_model(uint32_t security_state)
|
||||||
|
{
|
||||||
|
u_register_t scr_el3;
|
||||||
|
|
||||||
|
assert(sec_state_is_valid(security_state));
|
||||||
|
scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state];
|
||||||
|
scr_el3 |= intr_type_descs[INTR_TYPE_S_EL1].scr_el3[security_state];
|
||||||
|
scr_el3 |= intr_type_descs[INTR_TYPE_EL3].scr_el3[security_state];
|
||||||
|
return scr_el3;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function uses the 'interrupt_type_flags' parameter to obtain the value
|
||||||
|
* of the trap bit (IRQ/FIQ) in the SCR_EL3 for a security state for this
|
||||||
|
* interrupt type. It uses it to update the SCR_EL3 in the cpu context and the
|
||||||
|
* 'intr_type_desc' for that security state.
|
||||||
|
******************************************************************************/
|
||||||
|
static void set_scr_el3_from_rm(uint32_t type,
|
||||||
|
uint32_t interrupt_type_flags,
|
||||||
|
uint32_t security_state)
|
||||||
|
{
|
||||||
|
uint32_t flag, bit_pos;
|
||||||
|
|
||||||
|
flag = get_interrupt_rm_flag(interrupt_type_flags, security_state);
|
||||||
|
bit_pos = plat_interrupt_type_to_line(type, security_state);
|
||||||
|
intr_type_descs[type].scr_el3[security_state] = (u_register_t)flag << bit_pos;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Update scr_el3 only if there is a context available. If not, it
|
||||||
|
* will be updated later during context initialization which will obtain
|
||||||
|
* the scr_el3 value to be used via get_scr_el3_from_routing_model()
|
||||||
|
*/
|
||||||
|
if (cm_get_context(security_state) != NULL)
|
||||||
|
cm_write_scr_el3_bit(security_state, bit_pos, flag);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function validates the routing model specified in the 'flags' and
|
||||||
|
* updates internal data structures to reflect the new routing model. It also
|
||||||
|
* updates the copy of SCR_EL3 for each security state with the new routing
|
||||||
|
* model in the 'cpu_context' structure for this cpu.
|
||||||
|
******************************************************************************/
|
||||||
|
int32_t set_routing_model(uint32_t type, uint32_t flags)
|
||||||
|
{
|
||||||
|
int32_t rc;
|
||||||
|
|
||||||
|
rc = validate_interrupt_type(type);
|
||||||
|
if (rc != 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
rc = validate_routing_model(type, flags);
|
||||||
|
if (rc != 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
/* Update the routing model in internal data structures */
|
||||||
|
intr_type_descs[type].flags = flags;
|
||||||
|
set_scr_el3_from_rm(type, flags, SECURE);
|
||||||
|
set_scr_el3_from_rm(type, flags, NON_SECURE);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* This function disables the routing model of interrupt 'type' from the
|
||||||
|
* specified 'security_state' on the local core. The disable is in effect
|
||||||
|
* till the core powers down or till the next enable for that interrupt
|
||||||
|
* type.
|
||||||
|
*****************************************************************************/
|
||||||
|
int disable_intr_rm_local(uint32_t type, uint32_t security_state)
|
||||||
|
{
|
||||||
|
uint32_t bit_pos, flag;
|
||||||
|
|
||||||
|
assert(intr_type_descs[type].handler != NULL);
|
||||||
|
|
||||||
|
flag = get_interrupt_rm_flag(INTR_DEFAULT_RM, security_state);
|
||||||
|
|
||||||
|
bit_pos = plat_interrupt_type_to_line(type, security_state);
|
||||||
|
cm_write_scr_el3_bit(security_state, bit_pos, flag);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* This function enables the routing model of interrupt 'type' from the
|
||||||
|
* specified 'security_state' on the local core.
|
||||||
|
*****************************************************************************/
|
||||||
|
int enable_intr_rm_local(uint32_t type, uint32_t security_state)
|
||||||
|
{
|
||||||
|
uint32_t bit_pos, flag;
|
||||||
|
|
||||||
|
assert(intr_type_descs[type].handler != NULL);
|
||||||
|
|
||||||
|
flag = get_interrupt_rm_flag(intr_type_descs[type].flags,
|
||||||
|
security_state);
|
||||||
|
|
||||||
|
bit_pos = plat_interrupt_type_to_line(type, security_state);
|
||||||
|
cm_write_scr_el3_bit(security_state, bit_pos, flag);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function registers a handler for the 'type' of interrupt specified. It
|
||||||
|
* also validates the routing model specified in the 'flags' for this type of
|
||||||
|
* interrupt.
|
||||||
|
******************************************************************************/
|
||||||
|
int32_t register_interrupt_type_handler(uint32_t type,
|
||||||
|
interrupt_type_handler_t handler,
|
||||||
|
uint32_t flags)
|
||||||
|
{
|
||||||
|
int32_t rc;
|
||||||
|
|
||||||
|
/* Validate the 'handler' parameter */
|
||||||
|
if (handler == NULL)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
/* Validate the 'flags' parameter */
|
||||||
|
if ((flags & INTR_TYPE_FLAGS_MASK) != 0U)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
/* Check if a handler has already been registered */
|
||||||
|
if (intr_type_descs[type].handler != NULL)
|
||||||
|
return -EALREADY;
|
||||||
|
|
||||||
|
rc = set_routing_model(type, flags);
|
||||||
|
if (rc != 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
/* Save the handler */
|
||||||
|
intr_type_descs[type].handler = handler;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function is called when an interrupt is generated and returns the
|
||||||
|
* handler for the interrupt type (if registered). It returns NULL if the
|
||||||
|
* interrupt type is not supported or its handler has not been registered.
|
||||||
|
******************************************************************************/
|
||||||
|
interrupt_type_handler_t get_interrupt_type_handler(uint32_t type)
|
||||||
|
{
|
||||||
|
if (validate_interrupt_type(type) != 0)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
return intr_type_descs[type].handler;
|
||||||
|
}
|
||||||
|
|
||||||
15
arm-trusted-firmware/bl32/optee/optee.mk
Normal file
15
arm-trusted-firmware/bl32/optee/optee.mk
Normal file
@@ -0,0 +1,15 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
# This makefile only aims at complying with Trusted Firmware-A build process so
|
||||||
|
# that "optee" is a valid TF-A AArch32 Secure Playload identifier.
|
||||||
|
|
||||||
|
ifneq ($(ARCH),aarch32)
|
||||||
|
$(error This directory targets AArch32 support)
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(eval $(call add_define,AARCH32_SP_OPTEE))
|
||||||
|
|
||||||
|
$(info Trusted Firmware-A built for OP-TEE payload support)
|
||||||
382
arm-trusted-firmware/bl32/sp_min/aarch32/entrypoint.S
Normal file
382
arm-trusted-firmware/bl32/sp_min/aarch32/entrypoint.S
Normal file
@@ -0,0 +1,382 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/runtime_svc.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <el3_common_macros.S>
|
||||||
|
#include <lib/el3_runtime/cpu_data.h>
|
||||||
|
#include <lib/pmf/aarch32/pmf_asm_macros.S>
|
||||||
|
#include <lib/runtime_instr.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
#include <smccc_helpers.h>
|
||||||
|
#include <smccc_macros.S>
|
||||||
|
|
||||||
|
.globl sp_min_vector_table
|
||||||
|
.globl sp_min_entrypoint
|
||||||
|
.globl sp_min_warm_entrypoint
|
||||||
|
.globl sp_min_handle_smc
|
||||||
|
.globl sp_min_handle_fiq
|
||||||
|
|
||||||
|
#define FIXUP_SIZE ((BL32_LIMIT) - (BL32_BASE))
|
||||||
|
|
||||||
|
.macro route_fiq_to_sp_min reg
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* FIQs are secure interrupts trapped by Monitor and non
|
||||||
|
* secure is not allowed to mask the FIQs.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
ldcopr \reg, SCR
|
||||||
|
orr \reg, \reg, #SCR_FIQ_BIT
|
||||||
|
bic \reg, \reg, #SCR_FW_BIT
|
||||||
|
stcopr \reg, SCR
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro clrex_on_monitor_entry
|
||||||
|
#if (ARM_ARCH_MAJOR == 7)
|
||||||
|
/*
|
||||||
|
* ARMv7 architectures need to clear the exclusive access when
|
||||||
|
* entering Monitor mode.
|
||||||
|
*/
|
||||||
|
clrex
|
||||||
|
#endif
|
||||||
|
.endm
|
||||||
|
|
||||||
|
vector_base sp_min_vector_table
|
||||||
|
b sp_min_entrypoint
|
||||||
|
b plat_panic_handler /* Undef */
|
||||||
|
b sp_min_handle_smc /* Syscall */
|
||||||
|
b report_prefetch_abort /* Prefetch abort */
|
||||||
|
b report_data_abort /* Data abort */
|
||||||
|
b plat_panic_handler /* Reserved */
|
||||||
|
b plat_panic_handler /* IRQ */
|
||||||
|
b sp_min_handle_fiq /* FIQ */
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The Cold boot/Reset entrypoint for SP_MIN
|
||||||
|
*/
|
||||||
|
func sp_min_entrypoint
|
||||||
|
#if !RESET_TO_SP_MIN
|
||||||
|
/* ---------------------------------------------------------------
|
||||||
|
* Preceding bootloader has populated r0 with a pointer to a
|
||||||
|
* 'bl_params_t' structure & r1 with a pointer to platform
|
||||||
|
* specific structure
|
||||||
|
* ---------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
mov r9, r0
|
||||||
|
mov r10, r1
|
||||||
|
mov r11, r2
|
||||||
|
mov r12, r3
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
|
||||||
|
* sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
|
||||||
|
* and primary/secondary CPU logic should not be executed in this case.
|
||||||
|
*
|
||||||
|
* Also, assume that the previous bootloader has already initialised the
|
||||||
|
* SCTLR, including the CPU endianness, and has initialised the memory.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=0 \
|
||||||
|
_warm_boot_mailbox=0 \
|
||||||
|
_secondary_cold_boot=0 \
|
||||||
|
_init_memory=0 \
|
||||||
|
_init_c_runtime=1 \
|
||||||
|
_exception_vectors=sp_min_vector_table \
|
||||||
|
_pie_fixup_size=FIXUP_SIZE
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* Relay the previous bootloader's arguments to the platform layer
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
#else
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* For RESET_TO_SP_MIN systems which have a programmable reset address,
|
||||||
|
* sp_min_entrypoint() is executed only on the cold boot path so we can
|
||||||
|
* skip the warm boot mailbox mechanism.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=1 \
|
||||||
|
_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
|
||||||
|
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
|
||||||
|
_init_memory=1 \
|
||||||
|
_init_c_runtime=1 \
|
||||||
|
_exception_vectors=sp_min_vector_table \
|
||||||
|
_pie_fixup_size=FIXUP_SIZE
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------
|
||||||
|
* For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
|
||||||
|
* to run so there's no argument to relay from a previous bootloader.
|
||||||
|
* Zero the arguments passed to the platform layer to reflect that.
|
||||||
|
* ---------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
mov r9, #0
|
||||||
|
mov r10, #0
|
||||||
|
mov r11, #0
|
||||||
|
mov r12, #0
|
||||||
|
|
||||||
|
#endif /* RESET_TO_SP_MIN */
|
||||||
|
|
||||||
|
#if SP_MIN_WITH_SECURE_FIQ
|
||||||
|
route_fiq_to_sp_min r4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
mov r0, r9
|
||||||
|
mov r1, r10
|
||||||
|
mov r2, r11
|
||||||
|
mov r3, r12
|
||||||
|
bl sp_min_early_platform_setup2
|
||||||
|
bl sp_min_plat_arch_setup
|
||||||
|
|
||||||
|
/* Jump to the main function */
|
||||||
|
bl sp_min_main
|
||||||
|
|
||||||
|
/* -------------------------------------------------------------
|
||||||
|
* Clean the .data & .bss sections to main memory. This ensures
|
||||||
|
* that any global data which was initialised by the primary CPU
|
||||||
|
* is visible to secondary CPUs before they enable their data
|
||||||
|
* caches and participate in coherency.
|
||||||
|
* -------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
ldr r0, =__DATA_START__
|
||||||
|
ldr r1, =__DATA_END__
|
||||||
|
sub r1, r1, r0
|
||||||
|
bl clean_dcache_range
|
||||||
|
|
||||||
|
ldr r0, =__BSS_START__
|
||||||
|
ldr r1, =__BSS_END__
|
||||||
|
sub r1, r1, r0
|
||||||
|
bl clean_dcache_range
|
||||||
|
|
||||||
|
bl smc_get_next_ctx
|
||||||
|
|
||||||
|
/* r0 points to `smc_ctx_t` */
|
||||||
|
/* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
|
||||||
|
b sp_min_exit
|
||||||
|
endfunc sp_min_entrypoint
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SMC handling function for SP_MIN.
|
||||||
|
*/
|
||||||
|
func sp_min_handle_smc
|
||||||
|
/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
|
||||||
|
str lr, [sp, #SMC_CTX_LR_MON]
|
||||||
|
|
||||||
|
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||||
|
/*
|
||||||
|
* Read the timestamp value and store it on top of the C runtime stack.
|
||||||
|
* The value will be saved to the per-cpu data once the C stack is
|
||||||
|
* available, as a valid stack is needed to call _cpu_data()
|
||||||
|
*/
|
||||||
|
strd r0, r1, [sp, #SMC_CTX_GPREG_R0]
|
||||||
|
ldcopr16 r0, r1, CNTPCT_64
|
||||||
|
ldr lr, [sp, #SMC_CTX_SP_MON]
|
||||||
|
strd r0, r1, [lr, #-8]!
|
||||||
|
str lr, [sp, #SMC_CTX_SP_MON]
|
||||||
|
ldrd r0, r1, [sp, #SMC_CTX_GPREG_R0]
|
||||||
|
#endif
|
||||||
|
|
||||||
|
smccc_save_gp_mode_regs
|
||||||
|
|
||||||
|
clrex_on_monitor_entry
|
||||||
|
|
||||||
|
/*
|
||||||
|
* `sp` still points to `smc_ctx_t`. Save it to a register
|
||||||
|
* and restore the C runtime stack pointer to `sp`.
|
||||||
|
*/
|
||||||
|
mov r2, sp /* handle */
|
||||||
|
ldr sp, [r2, #SMC_CTX_SP_MON]
|
||||||
|
|
||||||
|
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||||
|
/* Save handle to a callee saved register */
|
||||||
|
mov r6, r2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Restore the timestamp value and store it in per-cpu data. The value
|
||||||
|
* will be extracted from per-cpu data by the C level SMC handler and
|
||||||
|
* saved to the PMF timestamp region.
|
||||||
|
*/
|
||||||
|
ldrd r4, r5, [sp], #8
|
||||||
|
bl _cpu_data
|
||||||
|
strd r4, r5, [r0, #CPU_DATA_PMF_TS0_OFFSET]
|
||||||
|
|
||||||
|
/* Restore handle */
|
||||||
|
mov r2, r6
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ldr r0, [r2, #SMC_CTX_SCR]
|
||||||
|
and r3, r0, #SCR_NS_BIT /* flags */
|
||||||
|
|
||||||
|
/* Switch to Secure Mode*/
|
||||||
|
bic r0, #SCR_NS_BIT
|
||||||
|
stcopr r0, SCR
|
||||||
|
isb
|
||||||
|
|
||||||
|
ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */
|
||||||
|
/* Check whether an SMC64 is issued */
|
||||||
|
tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
|
||||||
|
beq 1f
|
||||||
|
/* SMC32 is not detected. Return error back to caller */
|
||||||
|
mov r0, #SMC_UNK
|
||||||
|
str r0, [r2, #SMC_CTX_GPREG_R0]
|
||||||
|
mov r0, r2
|
||||||
|
b sp_min_exit
|
||||||
|
1:
|
||||||
|
/* SMC32 is detected */
|
||||||
|
mov r1, #0 /* cookie */
|
||||||
|
bl handle_runtime_svc
|
||||||
|
|
||||||
|
/* `r0` points to `smc_ctx_t` */
|
||||||
|
b sp_min_exit
|
||||||
|
endfunc sp_min_handle_smc
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Secure Interrupts handling function for SP_MIN.
|
||||||
|
*/
|
||||||
|
func sp_min_handle_fiq
|
||||||
|
#if !SP_MIN_WITH_SECURE_FIQ
|
||||||
|
b plat_panic_handler
|
||||||
|
#else
|
||||||
|
/* FIQ has a +4 offset for lr compared to preferred return address */
|
||||||
|
sub lr, lr, #4
|
||||||
|
/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
|
||||||
|
str lr, [sp, #SMC_CTX_LR_MON]
|
||||||
|
|
||||||
|
smccc_save_gp_mode_regs
|
||||||
|
|
||||||
|
clrex_on_monitor_entry
|
||||||
|
|
||||||
|
/* load run-time stack */
|
||||||
|
mov r2, sp
|
||||||
|
ldr sp, [r2, #SMC_CTX_SP_MON]
|
||||||
|
|
||||||
|
/* Switch to Secure Mode */
|
||||||
|
ldr r0, [r2, #SMC_CTX_SCR]
|
||||||
|
bic r0, #SCR_NS_BIT
|
||||||
|
stcopr r0, SCR
|
||||||
|
isb
|
||||||
|
|
||||||
|
push {r2, r3}
|
||||||
|
bl sp_min_fiq
|
||||||
|
pop {r0, r3}
|
||||||
|
|
||||||
|
b sp_min_exit
|
||||||
|
#endif
|
||||||
|
endfunc sp_min_handle_fiq
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The Warm boot entrypoint for SP_MIN.
|
||||||
|
*/
|
||||||
|
func sp_min_warm_entrypoint
|
||||||
|
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||||
|
/*
|
||||||
|
* This timestamp update happens with cache off. The next
|
||||||
|
* timestamp collection will need to do cache maintenance prior
|
||||||
|
* to timestamp update.
|
||||||
|
*/
|
||||||
|
pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR
|
||||||
|
ldcopr16 r2, r3, CNTPCT_64
|
||||||
|
strd r2, r3, [r0]
|
||||||
|
#endif
|
||||||
|
/*
|
||||||
|
* On the warm boot path, most of the EL3 initialisations performed by
|
||||||
|
* 'el3_entrypoint_common' must be skipped:
|
||||||
|
*
|
||||||
|
* - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by
|
||||||
|
* programming the reset address do we need to initialied the SCTLR.
|
||||||
|
* In other cases, we assume this has been taken care by the
|
||||||
|
* entrypoint code.
|
||||||
|
*
|
||||||
|
* - No need to determine the type of boot, we know it is a warm boot.
|
||||||
|
*
|
||||||
|
* - Do not try to distinguish between primary and secondary CPUs, this
|
||||||
|
* notion only exists for a cold boot.
|
||||||
|
*
|
||||||
|
* - No need to initialise the memory or the C runtime environment,
|
||||||
|
* it has been done once and for all on the cold boot path.
|
||||||
|
*/
|
||||||
|
el3_entrypoint_common \
|
||||||
|
_init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
|
||||||
|
_warm_boot_mailbox=0 \
|
||||||
|
_secondary_cold_boot=0 \
|
||||||
|
_init_memory=0 \
|
||||||
|
_init_c_runtime=0 \
|
||||||
|
_exception_vectors=sp_min_vector_table \
|
||||||
|
_pie_fixup_size=0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We're about to enable MMU and participate in PSCI state coordination.
|
||||||
|
*
|
||||||
|
* The PSCI implementation invokes platform routines that enable CPUs to
|
||||||
|
* participate in coherency. On a system where CPUs are not
|
||||||
|
* cache-coherent without appropriate platform specific programming,
|
||||||
|
* having caches enabled until such time might lead to coherency issues
|
||||||
|
* (resulting from stale data getting speculatively fetched, among
|
||||||
|
* others). Therefore we keep data caches disabled even after enabling
|
||||||
|
* the MMU for such platforms.
|
||||||
|
*
|
||||||
|
* On systems with hardware-assisted coherency, or on single cluster
|
||||||
|
* platforms, such platform specific programming is not required to
|
||||||
|
* enter coherency (as CPUs already are); and there's no reason to have
|
||||||
|
* caches disabled either.
|
||||||
|
*/
|
||||||
|
#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
|
||||||
|
mov r0, #0
|
||||||
|
#else
|
||||||
|
mov r0, #DISABLE_DCACHE
|
||||||
|
#endif
|
||||||
|
bl bl32_plat_enable_mmu
|
||||||
|
|
||||||
|
#if SP_MIN_WITH_SECURE_FIQ
|
||||||
|
route_fiq_to_sp_min r0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
bl sp_min_warm_boot
|
||||||
|
bl smc_get_next_ctx
|
||||||
|
/* r0 points to `smc_ctx_t` */
|
||||||
|
/* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
|
||||||
|
|
||||||
|
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||||
|
/* Save smc_ctx_t */
|
||||||
|
mov r5, r0
|
||||||
|
|
||||||
|
pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI
|
||||||
|
mov r4, r0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Invalidate before updating timestamp to ensure previous timestamp
|
||||||
|
* updates on the same cache line with caches disabled are properly
|
||||||
|
* seen by the same core. Without the cache invalidate, the core might
|
||||||
|
* write into a stale cache line.
|
||||||
|
*/
|
||||||
|
mov r1, #PMF_TS_SIZE
|
||||||
|
bl inv_dcache_range
|
||||||
|
|
||||||
|
ldcopr16 r0, r1, CNTPCT_64
|
||||||
|
strd r0, r1, [r4]
|
||||||
|
|
||||||
|
/* Restore smc_ctx_t */
|
||||||
|
mov r0, r5
|
||||||
|
#endif
|
||||||
|
|
||||||
|
b sp_min_exit
|
||||||
|
endfunc sp_min_warm_entrypoint
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The function to restore the registers from SMC context and return
|
||||||
|
* to the mode restored to SPSR.
|
||||||
|
*
|
||||||
|
* Arguments : r0 must point to the SMC context to restore from.
|
||||||
|
*/
|
||||||
|
func sp_min_exit
|
||||||
|
monitor_exit
|
||||||
|
endfunc sp_min_exit
|
||||||
150
arm-trusted-firmware/bl32/sp_min/sp_min.ld.S
Normal file
150
arm-trusted-firmware/bl32/sp_min/sp_min.ld.S
Normal file
@@ -0,0 +1,150 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common/bl_common.ld.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
|
||||||
|
OUTPUT_FORMAT(elf32-littlearm)
|
||||||
|
OUTPUT_ARCH(arm)
|
||||||
|
ENTRY(sp_min_vector_table)
|
||||||
|
|
||||||
|
MEMORY {
|
||||||
|
RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT
|
||||||
|
#include <plat_sp_min.ld.S>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = BL32_BASE;
|
||||||
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
||||||
|
"BL32_BASE address is not aligned on a page boundary.")
|
||||||
|
|
||||||
|
#if SEPARATE_CODE_AND_RODATA
|
||||||
|
.text . : {
|
||||||
|
__TEXT_START__ = .;
|
||||||
|
*entrypoint.o(.text*)
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(.vectors)
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__TEXT_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* .ARM.extab and .ARM.exidx are only added because Clang need them */
|
||||||
|
.ARM.extab . : {
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
.ARM.exidx . : {
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
.rodata . : {
|
||||||
|
__RODATA_START__ = .;
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
/* Place pubsub sections for events */
|
||||||
|
. = ALIGN(8);
|
||||||
|
#include <lib/el3_runtime/pubsub_events.h>
|
||||||
|
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RODATA_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#else
|
||||||
|
ro . : {
|
||||||
|
__RO_START__ = .;
|
||||||
|
*entrypoint.o(.text*)
|
||||||
|
*(SORT_BY_ALIGNMENT(.text*))
|
||||||
|
*(SORT_BY_ALIGNMENT(.rodata*))
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
/* Place pubsub sections for events */
|
||||||
|
. = ALIGN(8);
|
||||||
|
#include <lib/el3_runtime/pubsub_events.h>
|
||||||
|
|
||||||
|
*(.vectors)
|
||||||
|
__RO_END_UNALIGNED__ = .;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked as
|
||||||
|
* read-only, executable. No RW data from the next section must
|
||||||
|
* creep in. Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RO_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
|
||||||
|
"cpu_ops not defined for this platform.")
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark start of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_START__ = . ;
|
||||||
|
|
||||||
|
DATA_SECTION >RAM
|
||||||
|
RELA_SECTION >RAM
|
||||||
|
|
||||||
|
#ifdef BL32_PROGBITS_LIMIT
|
||||||
|
ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
STACK_SECTION >RAM
|
||||||
|
BSS_SECTION >RAM
|
||||||
|
XLAT_TABLE_SECTION >RAM
|
||||||
|
|
||||||
|
__BSS_SIZE__ = SIZEOF(.bss);
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
/*
|
||||||
|
* The base address of the coherent memory section must be page-aligned (4K)
|
||||||
|
* to guarantee that the coherent data are stored on their own pages and
|
||||||
|
* are not mixed with normal data. This is required to set up the correct
|
||||||
|
* memory attributes for the coherent data page tables.
|
||||||
|
*/
|
||||||
|
coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
|
||||||
|
__COHERENT_RAM_START__ = .;
|
||||||
|
/*
|
||||||
|
* Bakery locks are stored in coherent memory
|
||||||
|
*
|
||||||
|
* Each lock's data is contiguous and fully allocated by the compiler
|
||||||
|
*/
|
||||||
|
*(bakery_lock)
|
||||||
|
*(tzfw_coherent_mem)
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked
|
||||||
|
* as device memory. No other unexpected data must creep in.
|
||||||
|
* Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__COHERENT_RAM_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
__COHERENT_RAM_UNALIGNED_SIZE__ =
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark the end of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_END__ = .;
|
||||||
|
|
||||||
|
__BL32_END__ = .;
|
||||||
|
|
||||||
|
/DISCARD/ : {
|
||||||
|
*(.dynsym .dynstr .hash .gnu.hash)
|
||||||
|
}
|
||||||
|
|
||||||
|
ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
|
||||||
|
}
|
||||||
77
arm-trusted-firmware/bl32/sp_min/sp_min.mk
Normal file
77
arm-trusted-firmware/bl32/sp_min/sp_min.mk
Normal file
@@ -0,0 +1,77 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
|
||||||
|
ifneq (${ARCH}, aarch32)
|
||||||
|
$(error SP_MIN is only supported on AArch32 platforms)
|
||||||
|
endif
|
||||||
|
|
||||||
|
include lib/extensions/amu/amu.mk
|
||||||
|
include lib/psci/psci_lib.mk
|
||||||
|
|
||||||
|
INCLUDES += -Iinclude/bl32/sp_min
|
||||||
|
|
||||||
|
BL32_SOURCES += bl32/sp_min/sp_min_main.c \
|
||||||
|
bl32/sp_min/aarch32/entrypoint.S \
|
||||||
|
common/runtime_svc.c \
|
||||||
|
plat/common/aarch32/plat_sp_min_common.c\
|
||||||
|
services/std_svc/std_svc_setup.c \
|
||||||
|
${PSCI_LIB_SOURCES}
|
||||||
|
|
||||||
|
ifeq (${DISABLE_MTPMU},1)
|
||||||
|
BL32_SOURCES += lib/extensions/mtpmu/aarch32/mtpmu.S
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_PMF}, 1)
|
||||||
|
BL32_SOURCES += lib/pmf/pmf_main.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_AMU},1)
|
||||||
|
BL32_SOURCES += ${AMU_SOURCES}
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${WORKAROUND_CVE_2017_5715},1)
|
||||||
|
BL32_SOURCES += bl32/sp_min/wa_cve_2017_5715_bpiall.S \
|
||||||
|
bl32/sp_min/wa_cve_2017_5715_icache_inv.S
|
||||||
|
else
|
||||||
|
ifeq (${WORKAROUND_CVE_2022_23960},1)
|
||||||
|
BL32_SOURCES += bl32/sp_min/wa_cve_2017_5715_icache_inv.S
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${TRNG_SUPPORT},1)
|
||||||
|
BL32_SOURCES += services/std_svc/trng/trng_main.c \
|
||||||
|
services/std_svc/trng/trng_entropy_pool.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_SYS_REG_TRACE_FOR_NS},1)
|
||||||
|
BL32_SOURCES += lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_TRF_FOR_NS},1)
|
||||||
|
BL32_SOURCES += lib/extensions/trf/aarch32/trf.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
BL32_LINKERFILE := bl32/sp_min/sp_min.ld.S
|
||||||
|
|
||||||
|
# Include the platform-specific SP_MIN Makefile
|
||||||
|
# If no platform-specific SP_MIN Makefile exists, it means SP_MIN is not supported
|
||||||
|
# on this platform.
|
||||||
|
SP_MIN_PLAT_MAKEFILE := $(wildcard ${PLAT_DIR}/sp_min/sp_min-${PLAT}.mk)
|
||||||
|
ifeq (,${SP_MIN_PLAT_MAKEFILE})
|
||||||
|
$(error SP_MIN is not supported on platform ${PLAT})
|
||||||
|
else
|
||||||
|
include ${SP_MIN_PLAT_MAKEFILE}
|
||||||
|
endif
|
||||||
|
|
||||||
|
RESET_TO_SP_MIN := 0
|
||||||
|
$(eval $(call add_define,RESET_TO_SP_MIN))
|
||||||
|
$(eval $(call assert_boolean,RESET_TO_SP_MIN))
|
||||||
|
|
||||||
|
# Flag to allow SP_MIN to handle FIQ interrupts in monitor mode. The platform
|
||||||
|
# port is free to override this value. It is default disabled.
|
||||||
|
SP_MIN_WITH_SECURE_FIQ ?= 0
|
||||||
|
$(eval $(call add_define,SP_MIN_WITH_SECURE_FIQ))
|
||||||
|
$(eval $(call assert_boolean,SP_MIN_WITH_SECURE_FIQ))
|
||||||
249
arm-trusted-firmware/bl32/sp_min/sp_min_main.c
Normal file
249
arm-trusted-firmware/bl32/sp_min/sp_min_main.c
Normal file
@@ -0,0 +1,249 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <stddef.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <common/runtime_svc.h>
|
||||||
|
#include <context.h>
|
||||||
|
#include <drivers/console.h>
|
||||||
|
#include <lib/el3_runtime/context_mgmt.h>
|
||||||
|
#include <lib/pmf/pmf.h>
|
||||||
|
#include <lib/psci/psci.h>
|
||||||
|
#include <lib/runtime_instr.h>
|
||||||
|
#include <lib/utils.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
#include <platform_sp_min.h>
|
||||||
|
#include <services/std_svc.h>
|
||||||
|
#include <smccc_helpers.h>
|
||||||
|
|
||||||
|
#include "sp_min_private.h"
|
||||||
|
|
||||||
|
#if ENABLE_RUNTIME_INSTRUMENTATION
|
||||||
|
PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
|
||||||
|
RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Pointers to per-core cpu contexts */
|
||||||
|
static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT];
|
||||||
|
|
||||||
|
/* SP_MIN only stores the non secure smc context */
|
||||||
|
static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT];
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* Define the smccc helper library APIs
|
||||||
|
*****************************************************************************/
|
||||||
|
void *smc_get_ctx(unsigned int security_state)
|
||||||
|
{
|
||||||
|
assert(security_state == NON_SECURE);
|
||||||
|
return &sp_min_smc_context[plat_my_core_pos()];
|
||||||
|
}
|
||||||
|
|
||||||
|
void smc_set_next_ctx(unsigned int security_state)
|
||||||
|
{
|
||||||
|
assert(security_state == NON_SECURE);
|
||||||
|
/* SP_MIN stores only non secure smc context. Nothing to do here */
|
||||||
|
}
|
||||||
|
|
||||||
|
void *smc_get_next_ctx(void)
|
||||||
|
{
|
||||||
|
return &sp_min_smc_context[plat_my_core_pos()];
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns a pointer to the most recent 'cpu_context' structure
|
||||||
|
* for the calling CPU that was set as the context for the specified security
|
||||||
|
* state. NULL is returned if no such structure has been specified.
|
||||||
|
******************************************************************************/
|
||||||
|
void *cm_get_context(uint32_t security_state)
|
||||||
|
{
|
||||||
|
assert(security_state == NON_SECURE);
|
||||||
|
return sp_min_cpu_ctx_ptr[plat_my_core_pos()];
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function sets the pointer to the current 'cpu_context' structure for the
|
||||||
|
* specified security state for the calling CPU
|
||||||
|
******************************************************************************/
|
||||||
|
void cm_set_context(void *context, uint32_t security_state)
|
||||||
|
{
|
||||||
|
assert(security_state == NON_SECURE);
|
||||||
|
sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns a pointer to the most recent 'cpu_context' structure
|
||||||
|
* for the CPU identified by `cpu_idx` that was set as the context for the
|
||||||
|
* specified security state. NULL is returned if no such structure has been
|
||||||
|
* specified.
|
||||||
|
******************************************************************************/
|
||||||
|
void *cm_get_context_by_index(unsigned int cpu_idx,
|
||||||
|
unsigned int security_state)
|
||||||
|
{
|
||||||
|
assert(security_state == NON_SECURE);
|
||||||
|
return sp_min_cpu_ctx_ptr[cpu_idx];
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function sets the pointer to the current 'cpu_context' structure for the
|
||||||
|
* specified security state for the CPU identified by CPU index.
|
||||||
|
******************************************************************************/
|
||||||
|
void cm_set_context_by_index(unsigned int cpu_idx, void *context,
|
||||||
|
unsigned int security_state)
|
||||||
|
{
|
||||||
|
assert(security_state == NON_SECURE);
|
||||||
|
sp_min_cpu_ctx_ptr[cpu_idx] = context;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx,
|
||||||
|
smc_ctx_t *next_smc_ctx)
|
||||||
|
{
|
||||||
|
next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
|
||||||
|
next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
|
||||||
|
next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
|
||||||
|
next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
|
||||||
|
next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
|
||||||
|
next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function invokes the PSCI library interface to initialize the
|
||||||
|
* non secure cpu context and copies the relevant cpu context register values
|
||||||
|
* to smc context. These registers will get programmed during `smc_exit`.
|
||||||
|
******************************************************************************/
|
||||||
|
static void sp_min_prepare_next_image_entry(void)
|
||||||
|
{
|
||||||
|
entry_point_info_t *next_image_info;
|
||||||
|
cpu_context_t *ctx = cm_get_context(NON_SECURE);
|
||||||
|
u_register_t ns_sctlr;
|
||||||
|
|
||||||
|
/* Program system registers to proceed to non-secure */
|
||||||
|
next_image_info = sp_min_plat_get_bl33_ep_info();
|
||||||
|
assert(next_image_info);
|
||||||
|
assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr));
|
||||||
|
|
||||||
|
INFO("SP_MIN: Preparing exit to normal world\n");
|
||||||
|
|
||||||
|
psci_prepare_next_non_secure_ctx(next_image_info);
|
||||||
|
smc_set_next_ctx(NON_SECURE);
|
||||||
|
|
||||||
|
/* Copy r0, lr and spsr from cpu context to SMC context */
|
||||||
|
copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
|
||||||
|
smc_get_next_ctx());
|
||||||
|
|
||||||
|
/* Temporarily set the NS bit to access NS SCTLR */
|
||||||
|
write_scr(read_scr() | SCR_NS_BIT);
|
||||||
|
isb();
|
||||||
|
ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
|
||||||
|
write_sctlr(ns_sctlr);
|
||||||
|
isb();
|
||||||
|
|
||||||
|
write_scr(read_scr() & ~SCR_NS_BIT);
|
||||||
|
isb();
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* Implement the ARM Standard Service function to get arguments for a
|
||||||
|
* particular service.
|
||||||
|
*****************************************************************************/
|
||||||
|
uintptr_t get_arm_std_svc_args(unsigned int svc_mask)
|
||||||
|
{
|
||||||
|
/* Setup the arguments for PSCI Library */
|
||||||
|
DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint);
|
||||||
|
|
||||||
|
/* PSCI is the only ARM Standard Service implemented */
|
||||||
|
assert(svc_mask == PSCI_FID_MASK);
|
||||||
|
|
||||||
|
return (uintptr_t)&psci_args;
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* The SP_MIN main function. Do the platform and PSCI Library setup. Also
|
||||||
|
* initialize the runtime service framework.
|
||||||
|
*****************************************************************************/
|
||||||
|
void sp_min_main(void)
|
||||||
|
{
|
||||||
|
NOTICE("SP_MIN: %s\n", version_string);
|
||||||
|
NOTICE("SP_MIN: %s\n", build_message);
|
||||||
|
|
||||||
|
/* Perform the SP_MIN platform setup */
|
||||||
|
sp_min_platform_setup();
|
||||||
|
|
||||||
|
/* Initialize the runtime services e.g. psci */
|
||||||
|
INFO("SP_MIN: Initializing runtime services\n");
|
||||||
|
runtime_svc_init();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are ready to enter the next EL. Prepare entry into the image
|
||||||
|
* corresponding to the desired security state after the next ERET.
|
||||||
|
*/
|
||||||
|
sp_min_prepare_next_image_entry();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Perform any platform specific runtime setup prior to cold boot exit
|
||||||
|
* from SP_MIN.
|
||||||
|
*/
|
||||||
|
sp_min_plat_runtime_setup();
|
||||||
|
|
||||||
|
console_flush();
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* This function is invoked during warm boot. Invoke the PSCI library
|
||||||
|
* warm boot entry point which takes care of Architectural and platform setup/
|
||||||
|
* restore. Copy the relevant cpu_context register values to smc context which
|
||||||
|
* will get programmed during `smc_exit`.
|
||||||
|
*****************************************************************************/
|
||||||
|
void sp_min_warm_boot(void)
|
||||||
|
{
|
||||||
|
smc_ctx_t *next_smc_ctx;
|
||||||
|
cpu_context_t *ctx = cm_get_context(NON_SECURE);
|
||||||
|
u_register_t ns_sctlr;
|
||||||
|
|
||||||
|
psci_warmboot_entrypoint();
|
||||||
|
|
||||||
|
smc_set_next_ctx(NON_SECURE);
|
||||||
|
|
||||||
|
next_smc_ctx = smc_get_next_ctx();
|
||||||
|
zeromem(next_smc_ctx, sizeof(smc_ctx_t));
|
||||||
|
|
||||||
|
copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
|
||||||
|
next_smc_ctx);
|
||||||
|
|
||||||
|
/* Temporarily set the NS bit to access NS SCTLR */
|
||||||
|
write_scr(read_scr() | SCR_NS_BIT);
|
||||||
|
isb();
|
||||||
|
ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
|
||||||
|
write_sctlr(ns_sctlr);
|
||||||
|
isb();
|
||||||
|
|
||||||
|
write_scr(read_scr() & ~SCR_NS_BIT);
|
||||||
|
isb();
|
||||||
|
}
|
||||||
|
|
||||||
|
#if SP_MIN_WITH_SECURE_FIQ
|
||||||
|
/******************************************************************************
|
||||||
|
* This function is invoked on secure interrupts. By construction of the
|
||||||
|
* SP_MIN, secure interrupts can only be handled when core executes in non
|
||||||
|
* secure state.
|
||||||
|
*****************************************************************************/
|
||||||
|
void sp_min_fiq(void)
|
||||||
|
{
|
||||||
|
uint32_t id;
|
||||||
|
|
||||||
|
id = plat_ic_acknowledge_interrupt();
|
||||||
|
sp_min_plat_fiq_handler(id);
|
||||||
|
plat_ic_end_of_interrupt(id);
|
||||||
|
}
|
||||||
|
#endif /* SP_MIN_WITH_SECURE_FIQ */
|
||||||
14
arm-trusted-firmware/bl32/sp_min/sp_min_private.h
Normal file
14
arm-trusted-firmware/bl32/sp_min/sp_min_private.h
Normal file
@@ -0,0 +1,14 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef SP_MIN_PRIVATE_H
|
||||||
|
#define SP_MIN_PRIVATE_H
|
||||||
|
|
||||||
|
void sp_min_main(void);
|
||||||
|
void sp_min_warm_boot(void);
|
||||||
|
void sp_min_fiq(void);
|
||||||
|
|
||||||
|
#endif /* SP_MIN_PRIVATE_H */
|
||||||
74
arm-trusted-firmware/bl32/sp_min/wa_cve_2017_5715_bpiall.S
Normal file
74
arm-trusted-firmware/bl32/sp_min/wa_cve_2017_5715_bpiall.S
Normal file
@@ -0,0 +1,74 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm_macros.S>
|
||||||
|
|
||||||
|
.globl wa_cve_2017_5715_bpiall_vbar
|
||||||
|
|
||||||
|
vector_base wa_cve_2017_5715_bpiall_vbar
|
||||||
|
/* We encode the exception entry in the bottom 3 bits of SP */
|
||||||
|
add sp, sp, #1 /* Reset: 0b111 */
|
||||||
|
add sp, sp, #1 /* Undef: 0b110 */
|
||||||
|
add sp, sp, #1 /* Syscall: 0b101 */
|
||||||
|
add sp, sp, #1 /* Prefetch abort: 0b100 */
|
||||||
|
add sp, sp, #1 /* Data abort: 0b011 */
|
||||||
|
add sp, sp, #1 /* Reserved: 0b010 */
|
||||||
|
add sp, sp, #1 /* IRQ: 0b001 */
|
||||||
|
nop /* FIQ: 0b000 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Invalidate the branch predictor, `r0` is a dummy register
|
||||||
|
* and is unused.
|
||||||
|
*/
|
||||||
|
stcopr r0, BPIALL
|
||||||
|
isb
|
||||||
|
|
||||||
|
/*
|
||||||
|
* As we cannot use any temporary registers and cannot
|
||||||
|
* clobber SP, we can decode the exception entry using
|
||||||
|
* an unrolled binary search.
|
||||||
|
*
|
||||||
|
* Note, if this code is re-used by other secure payloads,
|
||||||
|
* the below exception entry vectors must be changed to
|
||||||
|
* the vectors specific to that secure payload.
|
||||||
|
*/
|
||||||
|
|
||||||
|
tst sp, #4
|
||||||
|
bne 1f
|
||||||
|
|
||||||
|
tst sp, #2
|
||||||
|
bne 3f
|
||||||
|
|
||||||
|
/* Expected encoding: 0x1 and 0x0 */
|
||||||
|
tst sp, #1
|
||||||
|
/* Restore original value of SP by clearing the bottom 3 bits */
|
||||||
|
bic sp, sp, #0x7
|
||||||
|
bne plat_panic_handler /* IRQ */
|
||||||
|
b sp_min_handle_fiq /* FIQ */
|
||||||
|
|
||||||
|
1:
|
||||||
|
tst sp, #2
|
||||||
|
bne 2f
|
||||||
|
|
||||||
|
/* Expected encoding: 0x4 and 0x5 */
|
||||||
|
tst sp, #1
|
||||||
|
bic sp, sp, #0x7
|
||||||
|
bne sp_min_handle_smc /* Syscall */
|
||||||
|
b plat_panic_handler /* Prefetch abort */
|
||||||
|
|
||||||
|
2:
|
||||||
|
/* Expected encoding: 0x7 and 0x6 */
|
||||||
|
tst sp, #1
|
||||||
|
bic sp, sp, #0x7
|
||||||
|
bne sp_min_entrypoint /* Reset */
|
||||||
|
b plat_panic_handler /* Undef */
|
||||||
|
|
||||||
|
3:
|
||||||
|
/* Expected encoding: 0x2 and 0x3 */
|
||||||
|
tst sp, #1
|
||||||
|
bic sp, sp, #0x7
|
||||||
|
bne plat_panic_handler /* Data abort */
|
||||||
|
b plat_panic_handler /* Reserved */
|
||||||
@@ -0,0 +1,75 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm_macros.S>
|
||||||
|
|
||||||
|
.globl wa_cve_2017_5715_icache_inv_vbar
|
||||||
|
|
||||||
|
vector_base wa_cve_2017_5715_icache_inv_vbar
|
||||||
|
/* We encode the exception entry in the bottom 3 bits of SP */
|
||||||
|
add sp, sp, #1 /* Reset: 0b111 */
|
||||||
|
add sp, sp, #1 /* Undef: 0b110 */
|
||||||
|
add sp, sp, #1 /* Syscall: 0b101 */
|
||||||
|
add sp, sp, #1 /* Prefetch abort: 0b100 */
|
||||||
|
add sp, sp, #1 /* Data abort: 0b011 */
|
||||||
|
add sp, sp, #1 /* Reserved: 0b010 */
|
||||||
|
add sp, sp, #1 /* IRQ: 0b001 */
|
||||||
|
nop /* FIQ: 0b000 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Invalidate the instruction cache, which we assume also
|
||||||
|
* invalidates the branch predictor. This may depend on
|
||||||
|
* other CPU specific changes (e.g. an ACTLR setting).
|
||||||
|
*/
|
||||||
|
stcopr r0, ICIALLU
|
||||||
|
isb
|
||||||
|
|
||||||
|
/*
|
||||||
|
* As we cannot use any temporary registers and cannot
|
||||||
|
* clobber SP, we can decode the exception entry using
|
||||||
|
* an unrolled binary search.
|
||||||
|
*
|
||||||
|
* Note, if this code is re-used by other secure payloads,
|
||||||
|
* the below exception entry vectors must be changed to
|
||||||
|
* the vectors specific to that secure payload.
|
||||||
|
*/
|
||||||
|
|
||||||
|
tst sp, #4
|
||||||
|
bne 1f
|
||||||
|
|
||||||
|
tst sp, #2
|
||||||
|
bne 3f
|
||||||
|
|
||||||
|
/* Expected encoding: 0x1 and 0x0 */
|
||||||
|
tst sp, #1
|
||||||
|
/* Restore original value of SP by clearing the bottom 3 bits */
|
||||||
|
bic sp, sp, #0x7
|
||||||
|
bne plat_panic_handler /* IRQ */
|
||||||
|
b sp_min_handle_fiq /* FIQ */
|
||||||
|
|
||||||
|
1:
|
||||||
|
/* Expected encoding: 0x4 and 0x5 */
|
||||||
|
tst sp, #2
|
||||||
|
bne 2f
|
||||||
|
|
||||||
|
tst sp, #1
|
||||||
|
bic sp, sp, #0x7
|
||||||
|
bne sp_min_handle_smc /* Syscall */
|
||||||
|
b plat_panic_handler /* Prefetch abort */
|
||||||
|
|
||||||
|
2:
|
||||||
|
/* Expected encoding: 0x7 and 0x6 */
|
||||||
|
tst sp, #1
|
||||||
|
bic sp, sp, #0x7
|
||||||
|
bne sp_min_entrypoint /* Reset */
|
||||||
|
b plat_panic_handler /* Undef */
|
||||||
|
|
||||||
|
3:
|
||||||
|
/* Expected encoding: 0x2 and 0x3 */
|
||||||
|
tst sp, #1
|
||||||
|
bic sp, sp, #0x7
|
||||||
|
bne plat_panic_handler /* Data abort */
|
||||||
|
b plat_panic_handler /* Reserved */
|
||||||
489
arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
Normal file
489
arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S
Normal file
@@ -0,0 +1,489 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <bl32/tsp/tsp.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
#include <smccc_helpers.h>
|
||||||
|
|
||||||
|
#include "../tsp_private.h"
|
||||||
|
|
||||||
|
|
||||||
|
.globl tsp_entrypoint
|
||||||
|
.globl tsp_vector_table
|
||||||
|
#if SPMC_AT_EL3
|
||||||
|
.globl tsp_cpu_on_entry
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Populate the params in x0-x7 from the pointer
|
||||||
|
* to the smc args structure in x0.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
.macro restore_args_call_smc
|
||||||
|
ldp x6, x7, [x0, #SMC_ARG6]
|
||||||
|
ldp x4, x5, [x0, #SMC_ARG4]
|
||||||
|
ldp x2, x3, [x0, #SMC_ARG2]
|
||||||
|
ldp x0, x1, [x0, #SMC_ARG0]
|
||||||
|
smc #0
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro save_eret_context reg1 reg2
|
||||||
|
mrs \reg1, elr_el1
|
||||||
|
mrs \reg2, spsr_el1
|
||||||
|
stp \reg1, \reg2, [sp, #-0x10]!
|
||||||
|
stp x30, x18, [sp, #-0x10]!
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro restore_eret_context reg1 reg2
|
||||||
|
ldp x30, x18, [sp], #0x10
|
||||||
|
ldp \reg1, \reg2, [sp], #0x10
|
||||||
|
msr elr_el1, \reg1
|
||||||
|
msr spsr_el1, \reg2
|
||||||
|
.endm
|
||||||
|
|
||||||
|
func tsp_entrypoint _align=3
|
||||||
|
|
||||||
|
#if ENABLE_PIE
|
||||||
|
/*
|
||||||
|
* ------------------------------------------------------------
|
||||||
|
* If PIE is enabled fixup the Global descriptor Table only
|
||||||
|
* once during primary core cold boot path.
|
||||||
|
*
|
||||||
|
* Compile time base address, required for fixup, is calculated
|
||||||
|
* using "pie_fixup" label present within first page.
|
||||||
|
* ------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
pie_fixup:
|
||||||
|
ldr x0, =pie_fixup
|
||||||
|
and x0, x0, #~(PAGE_SIZE_MASK)
|
||||||
|
mov_imm x1, (BL32_LIMIT - BL32_BASE)
|
||||||
|
add x1, x1, x0
|
||||||
|
bl fixup_gdt_reloc
|
||||||
|
#endif /* ENABLE_PIE */
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Set the exception vector to something sane.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
adr x0, tsp_exceptions
|
||||||
|
msr vbar_el1, x0
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Enable the SError interrupt now that the
|
||||||
|
* exception vectors have been setup.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Enable the instruction cache, stack pointer
|
||||||
|
* and data access alignment checks and disable
|
||||||
|
* speculative loads.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
|
||||||
|
mrs x0, sctlr_el1
|
||||||
|
orr x0, x0, x1
|
||||||
|
bic x0, x0, #SCTLR_DSSBS_BIT
|
||||||
|
msr sctlr_el1, x0
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Invalidate the RW memory used by the BL32
|
||||||
|
* image. This includes the data and NOBITS
|
||||||
|
* sections. This is done to safeguard against
|
||||||
|
* possible corruption of this memory by dirty
|
||||||
|
* cache lines in a system cache as a result of
|
||||||
|
* use by an earlier boot loader stage. If PIE
|
||||||
|
* is enabled however, RO sections including the
|
||||||
|
* GOT may be modified during pie fixup.
|
||||||
|
* Therefore, to be on the safe side, invalidate
|
||||||
|
* the entire image region if PIE is enabled.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
#if ENABLE_PIE
|
||||||
|
#if SEPARATE_CODE_AND_RODATA
|
||||||
|
adrp x0, __TEXT_START__
|
||||||
|
add x0, x0, :lo12:__TEXT_START__
|
||||||
|
#else
|
||||||
|
adrp x0, __RO_START__
|
||||||
|
add x0, x0, :lo12:__RO_START__
|
||||||
|
#endif /* SEPARATE_CODE_AND_RODATA */
|
||||||
|
#else
|
||||||
|
adrp x0, __RW_START__
|
||||||
|
add x0, x0, :lo12:__RW_START__
|
||||||
|
#endif /* ENABLE_PIE */
|
||||||
|
adrp x1, __RW_END__
|
||||||
|
add x1, x1, :lo12:__RW_END__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl inv_dcache_range
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Zero out NOBITS sections. There are 2 of them:
|
||||||
|
* - the .bss section;
|
||||||
|
* - the coherent memory section.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
adrp x0, __BSS_START__
|
||||||
|
add x0, x0, :lo12:__BSS_START__
|
||||||
|
adrp x1, __BSS_END__
|
||||||
|
add x1, x1, :lo12:__BSS_END__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl zeromem
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
adrp x0, __COHERENT_RAM_START__
|
||||||
|
add x0, x0, :lo12:__COHERENT_RAM_START__
|
||||||
|
adrp x1, __COHERENT_RAM_END_UNALIGNED__
|
||||||
|
add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
|
||||||
|
sub x1, x1, x0
|
||||||
|
bl zeromem
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* --------------------------------------------
|
||||||
|
* Allocate a stack whose memory will be marked
|
||||||
|
* as Normal-IS-WBWA when the MMU is enabled.
|
||||||
|
* There is no risk of reading stale stack
|
||||||
|
* memory after enabling the MMU as only the
|
||||||
|
* primary cpu is running at the moment.
|
||||||
|
* --------------------------------------------
|
||||||
|
*/
|
||||||
|
bl plat_set_my_stack
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Initialize the stack protector canary before
|
||||||
|
* any C code is called.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
#if STACK_PROTECTOR_ENABLED
|
||||||
|
bl update_stack_protector_canary
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Perform TSP setup
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl tsp_setup
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Program APIAKey_EL1
|
||||||
|
* and enable pointer authentication
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_init_enable_el1
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Jump to main function.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl tsp_main
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Tell TSPD that we are done initialising
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x1, x0
|
||||||
|
mov x0, #TSP_ENTRY_DONE
|
||||||
|
smc #0
|
||||||
|
|
||||||
|
tsp_entrypoint_panic:
|
||||||
|
b tsp_entrypoint_panic
|
||||||
|
endfunc tsp_entrypoint
|
||||||
|
|
||||||
|
|
||||||
|
/* -------------------------------------------
|
||||||
|
* Table of entrypoint vectors provided to the
|
||||||
|
* TSPD for the various entrypoints
|
||||||
|
* -------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_base tsp_vector_table
|
||||||
|
b tsp_yield_smc_entry
|
||||||
|
b tsp_fast_smc_entry
|
||||||
|
b tsp_cpu_on_entry
|
||||||
|
b tsp_cpu_off_entry
|
||||||
|
b tsp_cpu_resume_entry
|
||||||
|
b tsp_cpu_suspend_entry
|
||||||
|
b tsp_sel1_intr_entry
|
||||||
|
b tsp_system_off_entry
|
||||||
|
b tsp_system_reset_entry
|
||||||
|
b tsp_abort_yield_smc_entry
|
||||||
|
|
||||||
|
/*---------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD when this
|
||||||
|
* cpu is to be turned off through a CPU_OFF
|
||||||
|
* psci call to ask the TSP to perform any
|
||||||
|
* bookeeping necessary. In the current
|
||||||
|
* implementation, the TSPD expects the TSP to
|
||||||
|
* re-initialise its state so nothing is done
|
||||||
|
* here except for acknowledging the request.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_cpu_off_entry
|
||||||
|
bl tsp_cpu_off_main
|
||||||
|
restore_args_call_smc
|
||||||
|
endfunc tsp_cpu_off_entry
|
||||||
|
|
||||||
|
/*---------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD when the
|
||||||
|
* system is about to be switched off (through
|
||||||
|
* a SYSTEM_OFF psci call) to ask the TSP to
|
||||||
|
* perform any necessary bookkeeping.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_system_off_entry
|
||||||
|
bl tsp_system_off_main
|
||||||
|
restore_args_call_smc
|
||||||
|
endfunc tsp_system_off_entry
|
||||||
|
|
||||||
|
/*---------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD when the
|
||||||
|
* system is about to be reset (through a
|
||||||
|
* SYSTEM_RESET psci call) to ask the TSP to
|
||||||
|
* perform any necessary bookkeeping.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_system_reset_entry
|
||||||
|
bl tsp_system_reset_main
|
||||||
|
restore_args_call_smc
|
||||||
|
endfunc tsp_system_reset_entry
|
||||||
|
|
||||||
|
/*---------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD when this
|
||||||
|
* cpu is turned on using a CPU_ON psci call to
|
||||||
|
* ask the TSP to initialise itself i.e. setup
|
||||||
|
* the mmu, stacks etc. Minimal architectural
|
||||||
|
* state will be initialised by the TSPD when
|
||||||
|
* this function is entered i.e. Caches and MMU
|
||||||
|
* will be turned off, the execution state
|
||||||
|
* will be aarch64 and exceptions masked.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_cpu_on_entry
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Set the exception vector to something sane.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
adr x0, tsp_exceptions
|
||||||
|
msr vbar_el1, x0
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* Enable the SError interrupt */
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Enable the instruction cache, stack pointer
|
||||||
|
* and data access alignment checks
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
|
||||||
|
mrs x0, sctlr_el1
|
||||||
|
orr x0, x0, x1
|
||||||
|
msr sctlr_el1, x0
|
||||||
|
isb
|
||||||
|
|
||||||
|
/* --------------------------------------------
|
||||||
|
* Give ourselves a stack whose memory will be
|
||||||
|
* marked as Normal-IS-WBWA when the MMU is
|
||||||
|
* enabled.
|
||||||
|
* --------------------------------------------
|
||||||
|
*/
|
||||||
|
bl plat_set_my_stack
|
||||||
|
|
||||||
|
/* --------------------------------------------
|
||||||
|
* Enable MMU and D-caches together.
|
||||||
|
* --------------------------------------------
|
||||||
|
*/
|
||||||
|
mov x0, #0
|
||||||
|
bl bl32_plat_enable_mmu
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Program APIAKey_EL1
|
||||||
|
* and enable pointer authentication
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl pauth_init_enable_el1
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Enter C runtime to perform any remaining
|
||||||
|
* book keeping
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
bl tsp_cpu_on_main
|
||||||
|
restore_args_call_smc
|
||||||
|
|
||||||
|
/* Should never reach here */
|
||||||
|
tsp_cpu_on_entry_panic:
|
||||||
|
b tsp_cpu_on_entry_panic
|
||||||
|
endfunc tsp_cpu_on_entry
|
||||||
|
|
||||||
|
/*---------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD when this
|
||||||
|
* cpu is to be suspended through a CPU_SUSPEND
|
||||||
|
* psci call to ask the TSP to perform any
|
||||||
|
* bookeeping necessary. In the current
|
||||||
|
* implementation, the TSPD saves and restores
|
||||||
|
* the EL1 state.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_cpu_suspend_entry
|
||||||
|
bl tsp_cpu_suspend_main
|
||||||
|
restore_args_call_smc
|
||||||
|
endfunc tsp_cpu_suspend_entry
|
||||||
|
|
||||||
|
/*-------------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD to pass
|
||||||
|
* control for `synchronously` handling a S-EL1
|
||||||
|
* Interrupt which was triggered while executing
|
||||||
|
* in normal world. 'x0' contains a magic number
|
||||||
|
* which indicates this. TSPD expects control to
|
||||||
|
* be handed back at the end of interrupt
|
||||||
|
* processing. This is done through an SMC.
|
||||||
|
* The handover agreement is:
|
||||||
|
*
|
||||||
|
* 1. PSTATE.DAIF are set upon entry. 'x1' has
|
||||||
|
* the ELR_EL3 from the non-secure state.
|
||||||
|
* 2. TSP has to preserve the callee saved
|
||||||
|
* general purpose registers, SP_EL1/EL0 and
|
||||||
|
* LR.
|
||||||
|
* 3. TSP has to preserve the system and vfp
|
||||||
|
* registers (if applicable).
|
||||||
|
* 4. TSP can use 'x0-x18' to enable its C
|
||||||
|
* runtime.
|
||||||
|
* 5. TSP returns to TSPD using an SMC with
|
||||||
|
* 'x0' = TSP_HANDLED_S_EL1_INTR
|
||||||
|
* ------------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_sel1_intr_entry
|
||||||
|
#if DEBUG
|
||||||
|
mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN
|
||||||
|
cmp x0, x2
|
||||||
|
b.ne tsp_sel1_int_entry_panic
|
||||||
|
#endif
|
||||||
|
/*-------------------------------------------------
|
||||||
|
* Save any previous context needed to perform
|
||||||
|
* an exception return from S-EL1 e.g. context
|
||||||
|
* from a previous Non secure Interrupt.
|
||||||
|
* Update statistics and handle the S-EL1
|
||||||
|
* interrupt before returning to the TSPD.
|
||||||
|
* IRQ/FIQs are not enabled since that will
|
||||||
|
* complicate the implementation. Execution
|
||||||
|
* will be transferred back to the normal world
|
||||||
|
* in any case. The handler can return 0
|
||||||
|
* if the interrupt was handled or TSP_PREEMPTED
|
||||||
|
* if the expected interrupt was preempted
|
||||||
|
* by an interrupt that should be handled in EL3
|
||||||
|
* e.g. Group 0 interrupt in GICv3. In both
|
||||||
|
* the cases switch to EL3 using SMC with id
|
||||||
|
* TSP_HANDLED_S_EL1_INTR. Any other return value
|
||||||
|
* from the handler will result in panic.
|
||||||
|
* ------------------------------------------------
|
||||||
|
*/
|
||||||
|
save_eret_context x2 x3
|
||||||
|
bl tsp_update_sync_sel1_intr_stats
|
||||||
|
bl tsp_common_int_handler
|
||||||
|
/* Check if the S-EL1 interrupt has been handled */
|
||||||
|
cbnz x0, tsp_sel1_intr_check_preemption
|
||||||
|
b tsp_sel1_intr_return
|
||||||
|
tsp_sel1_intr_check_preemption:
|
||||||
|
/* Check if the S-EL1 interrupt has been preempted */
|
||||||
|
mov_imm x1, TSP_PREEMPTED
|
||||||
|
cmp x0, x1
|
||||||
|
b.ne tsp_sel1_int_entry_panic
|
||||||
|
tsp_sel1_intr_return:
|
||||||
|
mov_imm x0, TSP_HANDLED_S_EL1_INTR
|
||||||
|
restore_eret_context x2 x3
|
||||||
|
smc #0
|
||||||
|
|
||||||
|
/* Should never reach here */
|
||||||
|
tsp_sel1_int_entry_panic:
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc tsp_sel1_intr_entry
|
||||||
|
|
||||||
|
/*---------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD when this
|
||||||
|
* cpu resumes execution after an earlier
|
||||||
|
* CPU_SUSPEND psci call to ask the TSP to
|
||||||
|
* restore its saved context. In the current
|
||||||
|
* implementation, the TSPD saves and restores
|
||||||
|
* EL1 state so nothing is done here apart from
|
||||||
|
* acknowledging the request.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_cpu_resume_entry
|
||||||
|
bl tsp_cpu_resume_main
|
||||||
|
restore_args_call_smc
|
||||||
|
|
||||||
|
/* Should never reach here */
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc tsp_cpu_resume_entry
|
||||||
|
|
||||||
|
/*---------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD to ask
|
||||||
|
* the TSP to service a fast smc request.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_fast_smc_entry
|
||||||
|
bl tsp_smc_handler
|
||||||
|
restore_args_call_smc
|
||||||
|
|
||||||
|
/* Should never reach here */
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc tsp_fast_smc_entry
|
||||||
|
|
||||||
|
/*---------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD to ask
|
||||||
|
* the TSP to service a Yielding SMC request.
|
||||||
|
* We will enable preemption during execution
|
||||||
|
* of tsp_smc_handler.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_yield_smc_entry
|
||||||
|
msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
|
||||||
|
bl tsp_smc_handler
|
||||||
|
msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
|
||||||
|
restore_args_call_smc
|
||||||
|
|
||||||
|
/* Should never reach here */
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc tsp_yield_smc_entry
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------
|
||||||
|
* This entrypoint is used by the TSPD to abort a pre-empted Yielding
|
||||||
|
* SMC. It could be on behalf of non-secure world or because a CPU
|
||||||
|
* suspend/CPU off request needs to abort the preempted SMC.
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
func tsp_abort_yield_smc_entry
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Exceptions masking is already done by the TSPD when entering this
|
||||||
|
* hook so there is no need to do it here.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Reset the stack used by the pre-empted SMC */
|
||||||
|
bl plat_set_my_stack
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Allow some cleanup such as releasing locks.
|
||||||
|
*/
|
||||||
|
bl tsp_abort_smc_handler
|
||||||
|
|
||||||
|
restore_args_call_smc
|
||||||
|
|
||||||
|
/* Should never reach here */
|
||||||
|
bl plat_panic_handler
|
||||||
|
endfunc tsp_abort_yield_smc_entry
|
||||||
162
arm-trusted-firmware/bl32/tsp/aarch64/tsp_exceptions.S
Normal file
162
arm-trusted-firmware/bl32/tsp/aarch64/tsp_exceptions.S
Normal file
@@ -0,0 +1,162 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <bl32/tsp/tsp.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
/* ----------------------------------------------------
|
||||||
|
* The caller-saved registers x0-x18 and LR are saved
|
||||||
|
* here.
|
||||||
|
* ----------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SCRATCH_REG_SIZE #(20 * 8)
|
||||||
|
|
||||||
|
.macro save_caller_regs_and_lr
|
||||||
|
sub sp, sp, SCRATCH_REG_SIZE
|
||||||
|
stp x0, x1, [sp]
|
||||||
|
stp x2, x3, [sp, #0x10]
|
||||||
|
stp x4, x5, [sp, #0x20]
|
||||||
|
stp x6, x7, [sp, #0x30]
|
||||||
|
stp x8, x9, [sp, #0x40]
|
||||||
|
stp x10, x11, [sp, #0x50]
|
||||||
|
stp x12, x13, [sp, #0x60]
|
||||||
|
stp x14, x15, [sp, #0x70]
|
||||||
|
stp x16, x17, [sp, #0x80]
|
||||||
|
stp x18, x30, [sp, #0x90]
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro restore_caller_regs_and_lr
|
||||||
|
ldp x0, x1, [sp]
|
||||||
|
ldp x2, x3, [sp, #0x10]
|
||||||
|
ldp x4, x5, [sp, #0x20]
|
||||||
|
ldp x6, x7, [sp, #0x30]
|
||||||
|
ldp x8, x9, [sp, #0x40]
|
||||||
|
ldp x10, x11, [sp, #0x50]
|
||||||
|
ldp x12, x13, [sp, #0x60]
|
||||||
|
ldp x14, x15, [sp, #0x70]
|
||||||
|
ldp x16, x17, [sp, #0x80]
|
||||||
|
ldp x18, x30, [sp, #0x90]
|
||||||
|
add sp, sp, SCRATCH_REG_SIZE
|
||||||
|
.endm
|
||||||
|
|
||||||
|
/* ----------------------------------------------------
|
||||||
|
* Common TSP interrupt handling routine
|
||||||
|
* ----------------------------------------------------
|
||||||
|
*/
|
||||||
|
.macro handle_tsp_interrupt label
|
||||||
|
/* Enable the SError interrupt */
|
||||||
|
msr daifclr, #DAIF_ABT_BIT
|
||||||
|
|
||||||
|
save_caller_regs_and_lr
|
||||||
|
bl tsp_common_int_handler
|
||||||
|
cbz x0, interrupt_exit_\label
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This interrupt was not targetted to S-EL1 so send it to
|
||||||
|
* the monitor and wait for execution to resume.
|
||||||
|
*/
|
||||||
|
smc #0
|
||||||
|
interrupt_exit_\label:
|
||||||
|
restore_caller_regs_and_lr
|
||||||
|
exception_return
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.globl tsp_exceptions
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* TSP exception handlers.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_base tsp_exceptions
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
|
||||||
|
* are expected and treated as irrecoverable errors.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry sync_exception_sp_el0
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry sync_exception_sp_el0
|
||||||
|
|
||||||
|
vector_entry irq_sp_el0
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry irq_sp_el0
|
||||||
|
|
||||||
|
vector_entry fiq_sp_el0
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry fiq_sp_el0
|
||||||
|
|
||||||
|
vector_entry serror_sp_el0
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry serror_sp_el0
|
||||||
|
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
|
||||||
|
* are expected and handled
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry sync_exception_sp_elx
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry sync_exception_sp_elx
|
||||||
|
|
||||||
|
vector_entry irq_sp_elx
|
||||||
|
handle_tsp_interrupt irq_sp_elx
|
||||||
|
end_vector_entry irq_sp_elx
|
||||||
|
|
||||||
|
vector_entry fiq_sp_elx
|
||||||
|
handle_tsp_interrupt fiq_sp_elx
|
||||||
|
end_vector_entry fiq_sp_elx
|
||||||
|
|
||||||
|
vector_entry serror_sp_elx
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry serror_sp_elx
|
||||||
|
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
|
||||||
|
* are handled since TSP does not implement a lower EL
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry sync_exception_aarch64
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry sync_exception_aarch64
|
||||||
|
|
||||||
|
vector_entry irq_aarch64
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry irq_aarch64
|
||||||
|
|
||||||
|
vector_entry fiq_aarch64
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry fiq_aarch64
|
||||||
|
|
||||||
|
vector_entry serror_aarch64
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry serror_aarch64
|
||||||
|
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Lower EL using AArch32 : 0x600 - 0x800. No exceptions
|
||||||
|
* handled since the TSP does not implement a lower EL.
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry sync_exception_aarch32
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry sync_exception_aarch32
|
||||||
|
|
||||||
|
vector_entry irq_aarch32
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry irq_aarch32
|
||||||
|
|
||||||
|
vector_entry fiq_aarch32
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry fiq_aarch32
|
||||||
|
|
||||||
|
vector_entry serror_aarch32
|
||||||
|
b plat_panic_handler
|
||||||
|
end_vector_entry serror_aarch32
|
||||||
30
arm-trusted-firmware/bl32/tsp/aarch64/tsp_request.S
Normal file
30
arm-trusted-firmware/bl32/tsp/aarch64/tsp_request.S
Normal file
@@ -0,0 +1,30 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <bl32/tsp/tsp.h>
|
||||||
|
|
||||||
|
.globl tsp_get_magic
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function raises an SMC to retrieve arguments from secure
|
||||||
|
* monitor/dispatcher, saves the returned arguments the array received in x0,
|
||||||
|
* and then returns to the caller
|
||||||
|
*/
|
||||||
|
func tsp_get_magic
|
||||||
|
/* Load arguments */
|
||||||
|
ldr w0, _tsp_fid_get_magic
|
||||||
|
|
||||||
|
/* Raise SMC */
|
||||||
|
smc #0
|
||||||
|
|
||||||
|
/* Return arguments in x1:x0 */
|
||||||
|
ret
|
||||||
|
endfunc tsp_get_magic
|
||||||
|
|
||||||
|
.align 2
|
||||||
|
_tsp_fid_get_magic:
|
||||||
|
.word TSP_GET_ARGS
|
||||||
250
arm-trusted-firmware/bl32/tsp/ffa_helpers.c
Normal file
250
arm-trusted-firmware/bl32/tsp/ffa_helpers.c
Normal file
@@ -0,0 +1,250 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include "ffa_helpers.h"
|
||||||
|
#include <services/ffa_svc.h>
|
||||||
|
#include "tsp_private.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Wrapper function to send a direct request.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t ffa_msg_send_direct_req(ffa_endpoint_id16_t sender,
|
||||||
|
ffa_endpoint_id16_t receiver,
|
||||||
|
uint32_t arg3,
|
||||||
|
uint32_t arg4,
|
||||||
|
uint32_t arg5,
|
||||||
|
uint32_t arg6,
|
||||||
|
uint32_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t src_dst_ids = (sender << FFA_DIRECT_MSG_SOURCE_SHIFT) |
|
||||||
|
(receiver << FFA_DIRECT_MSG_DESTINATION_SHIFT);
|
||||||
|
|
||||||
|
|
||||||
|
/* Send Direct Request. */
|
||||||
|
return smc_helper(FFA_MSG_SEND_DIRECT_REQ_SMC64, src_dst_ids,
|
||||||
|
0, arg3, arg4, arg5, arg6, arg7);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Wrapper function to send a direct response.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *ffa_msg_send_direct_resp(ffa_endpoint_id16_t sender,
|
||||||
|
ffa_endpoint_id16_t receiver,
|
||||||
|
uint32_t arg3,
|
||||||
|
uint32_t arg4,
|
||||||
|
uint32_t arg5,
|
||||||
|
uint32_t arg6,
|
||||||
|
uint32_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t src_dst_ids = (sender << FFA_DIRECT_MSG_SOURCE_SHIFT) |
|
||||||
|
(receiver << FFA_DIRECT_MSG_DESTINATION_SHIFT);
|
||||||
|
|
||||||
|
return set_smc_args(FFA_MSG_SEND_DIRECT_RESP_SMC64, src_dst_ids,
|
||||||
|
0, arg3, arg4, arg5, arg6, arg7);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Memory Management Helpers.
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Initialises the header of the given `ffa_mtd`, not including the
|
||||||
|
* composite memory region offset.
|
||||||
|
*/
|
||||||
|
static void ffa_memory_region_init_header(
|
||||||
|
struct ffa_mtd *memory_region, ffa_endpoint_id16_t sender,
|
||||||
|
ffa_mem_attr16_t attributes, ffa_mtd_flag32_t flags,
|
||||||
|
uint64_t handle, uint64_t tag, ffa_endpoint_id16_t *receivers,
|
||||||
|
uint32_t receiver_count, ffa_mem_perm8_t permissions)
|
||||||
|
{
|
||||||
|
struct ffa_emad_v1_0 *emad;
|
||||||
|
|
||||||
|
memory_region->emad_offset = sizeof(struct ffa_mtd);
|
||||||
|
memory_region->emad_size = sizeof(struct ffa_emad_v1_0);
|
||||||
|
emad = (struct ffa_emad_v1_0 *)
|
||||||
|
((uint8_t *) memory_region +
|
||||||
|
memory_region->emad_offset);
|
||||||
|
memory_region->sender_id = sender;
|
||||||
|
memory_region->memory_region_attributes = attributes;
|
||||||
|
memory_region->reserved_36_39 = 0;
|
||||||
|
memory_region->flags = flags;
|
||||||
|
memory_region->handle = handle;
|
||||||
|
memory_region->tag = tag;
|
||||||
|
memory_region->reserved_40_47 = 0;
|
||||||
|
memory_region->emad_count = receiver_count;
|
||||||
|
for (uint32_t i = 0U; i < receiver_count; i++) {
|
||||||
|
emad[i].mapd.endpoint_id = receivers[i];
|
||||||
|
emad[i].mapd.memory_access_permissions = permissions;
|
||||||
|
emad[i].mapd.flags = 0;
|
||||||
|
emad[i].comp_mrd_offset = 0;
|
||||||
|
emad[i].reserved_8_15 = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* Initialises the given `ffa_mtd` to be used for an
|
||||||
|
* `FFA_MEM_RETRIEVE_REQ` by the receiver of a memory transaction.
|
||||||
|
* TODO: Support differing attributes per receiver.
|
||||||
|
*
|
||||||
|
* Returns the size of the descriptor written.
|
||||||
|
*/
|
||||||
|
static uint32_t ffa_memory_retrieve_request_init(
|
||||||
|
struct ffa_mtd *memory_region, uint64_t handle,
|
||||||
|
ffa_endpoint_id16_t sender, ffa_endpoint_id16_t *receivers, uint32_t receiver_count,
|
||||||
|
uint64_t tag, ffa_mtd_flag32_t flags,
|
||||||
|
ffa_mem_perm8_t permissions,
|
||||||
|
ffa_mem_attr16_t attributes)
|
||||||
|
{
|
||||||
|
ffa_memory_region_init_header(memory_region, sender, attributes, flags,
|
||||||
|
handle, tag, receivers,
|
||||||
|
receiver_count, permissions);
|
||||||
|
|
||||||
|
return sizeof(struct ffa_mtd) +
|
||||||
|
memory_region->emad_count * sizeof(struct ffa_emad_v1_0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Relinquish access to memory region. */
|
||||||
|
bool ffa_mem_relinquish(void)
|
||||||
|
{
|
||||||
|
smc_args_t ret;
|
||||||
|
|
||||||
|
ret = smc_helper(FFA_MEM_RELINQUISH, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
if (ffa_func_id(ret) != FFA_SUCCESS_SMC32) {
|
||||||
|
ERROR("%s failed to relinquish memory! error: (%x) %x\n",
|
||||||
|
__func__, ffa_func_id(ret), ffa_error_code(ret));
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Retrieve memory shared by another partition. */
|
||||||
|
smc_args_t ffa_mem_retrieve_req(uint32_t descriptor_length,
|
||||||
|
uint32_t fragment_length)
|
||||||
|
{
|
||||||
|
return smc_helper(FFA_MEM_RETRIEVE_REQ_SMC32,
|
||||||
|
descriptor_length,
|
||||||
|
fragment_length,
|
||||||
|
0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Retrieve the next memory descriptor fragment. */
|
||||||
|
smc_args_t ffa_mem_frag_rx(uint64_t handle, uint32_t recv_length)
|
||||||
|
{
|
||||||
|
return smc_helper(FFA_MEM_FRAG_RX,
|
||||||
|
FFA_MEM_HANDLE_LOW(handle),
|
||||||
|
FFA_MEM_HANDLE_HIGH(handle),
|
||||||
|
recv_length,
|
||||||
|
0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool memory_retrieve(struct mailbox *mb,
|
||||||
|
struct ffa_mtd **retrieved,
|
||||||
|
uint64_t handle, ffa_endpoint_id16_t sender,
|
||||||
|
ffa_endpoint_id16_t *receivers, uint32_t receiver_count,
|
||||||
|
ffa_mtd_flag32_t flags, uint32_t *frag_length,
|
||||||
|
uint32_t *total_length)
|
||||||
|
{
|
||||||
|
smc_args_t ret;
|
||||||
|
uint32_t descriptor_size;
|
||||||
|
struct ffa_mtd *memory_region = (struct ffa_mtd *)mb->tx_buffer;
|
||||||
|
|
||||||
|
if (retrieved == NULL || mb == NULL) {
|
||||||
|
ERROR("Invalid parameters!\n");
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear TX buffer. */
|
||||||
|
memset(memory_region, 0, PAGE_SIZE);
|
||||||
|
|
||||||
|
/* Clear local buffer. */
|
||||||
|
memset(mem_region_buffer, 0, REGION_BUF_SIZE);
|
||||||
|
|
||||||
|
descriptor_size = ffa_memory_retrieve_request_init(
|
||||||
|
memory_region, handle, sender, receivers, receiver_count, 0, flags,
|
||||||
|
FFA_MEM_PERM_RW | FFA_MEM_PERM_NX,
|
||||||
|
FFA_MEM_ATTR_NORMAL_MEMORY_CACHED_WB |
|
||||||
|
FFA_MEM_ATTR_INNER_SHAREABLE);
|
||||||
|
|
||||||
|
ret = ffa_mem_retrieve_req(descriptor_size, descriptor_size);
|
||||||
|
|
||||||
|
if (ffa_func_id(ret) == FFA_ERROR) {
|
||||||
|
ERROR("Couldn't retrieve the memory page. Error: %x\n",
|
||||||
|
ffa_error_code(ret));
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Following total_size and fragment_size are useful to keep track
|
||||||
|
* of the state of transaction. When the sum of all fragment_size of all
|
||||||
|
* fragments is equal to total_size, the memory transaction has been
|
||||||
|
* completed.
|
||||||
|
*/
|
||||||
|
*total_length = ret._regs[1];
|
||||||
|
*frag_length = ret._regs[2];
|
||||||
|
|
||||||
|
/* Validate frag_length is less than total_length and mailbox size. */
|
||||||
|
if (*frag_length == 0U || *total_length == 0U ||
|
||||||
|
*frag_length > *total_length || *frag_length > (mb->rxtx_page_count * PAGE_SIZE)) {
|
||||||
|
ERROR("Invalid parameters!\n");
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Copy response to local buffer. */
|
||||||
|
memcpy(mem_region_buffer, mb->rx_buffer, *frag_length);
|
||||||
|
|
||||||
|
if (ffa_rx_release()) {
|
||||||
|
ERROR("Failed to release buffer!\n");
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
*retrieved = (struct ffa_mtd *) mem_region_buffer;
|
||||||
|
|
||||||
|
if ((*retrieved)->emad_count > MAX_MEM_SHARE_RECIPIENTS) {
|
||||||
|
VERBOSE("SPMC memory sharing supports max of %u receivers!\n",
|
||||||
|
MAX_MEM_SHARE_RECIPIENTS);
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We are sharing memory from the normal world therefore validate the NS
|
||||||
|
* bit was set by the SPMC.
|
||||||
|
*/
|
||||||
|
if (((*retrieved)->memory_region_attributes & FFA_MEM_ATTR_NS_BIT) == 0U) {
|
||||||
|
ERROR("SPMC has not set the NS bit! 0x%x\n",
|
||||||
|
(*retrieved)->memory_region_attributes);
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
VERBOSE("Memory Descriptor Retrieved!\n");
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Relinquish the memory region. */
|
||||||
|
bool memory_relinquish(struct ffa_mem_relinquish_descriptor *m, uint64_t handle,
|
||||||
|
ffa_endpoint_id16_t id)
|
||||||
|
{
|
||||||
|
ffa_mem_relinquish_init(m, handle, 0, id);
|
||||||
|
return ffa_mem_relinquish();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Query SPMC that the rx buffer of the partition can be released. */
|
||||||
|
bool ffa_rx_release(void)
|
||||||
|
{
|
||||||
|
smc_args_t ret;
|
||||||
|
|
||||||
|
ret = smc_helper(FFA_RX_RELEASE, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
return ret._regs[SMC_ARG0] != FFA_SUCCESS_SMC32;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Map the provided buffers with the SPMC. */
|
||||||
|
bool ffa_rxtx_map(uintptr_t send, uintptr_t recv, uint32_t pages)
|
||||||
|
{
|
||||||
|
smc_args_t ret;
|
||||||
|
|
||||||
|
ret = smc_helper(FFA_RXTX_MAP_SMC64, send, recv, pages, 0, 0, 0, 0);
|
||||||
|
return ret._regs[0] != FFA_SUCCESS_SMC32;
|
||||||
|
}
|
||||||
116
arm-trusted-firmware/bl32/tsp/ffa_helpers.h
Normal file
116
arm-trusted-firmware/bl32/tsp/ffa_helpers.h
Normal file
@@ -0,0 +1,116 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef FFA_HELPERS_H
|
||||||
|
#define FFA_HELPERS_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include "../../services/std_svc/spm/el3_spmc/spmc.h"
|
||||||
|
#include "../../services/std_svc/spm/el3_spmc/spmc_shared_mem.h"
|
||||||
|
#include <services/el3_spmc_ffa_memory.h>
|
||||||
|
#include <services/ffa_svc.h>
|
||||||
|
#include "tsp_private.h"
|
||||||
|
|
||||||
|
static inline uint32_t ffa_func_id(smc_args_t val)
|
||||||
|
{
|
||||||
|
return (uint32_t) val._regs[0];
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int32_t ffa_error_code(smc_args_t val)
|
||||||
|
{
|
||||||
|
return (uint32_t) val._regs[2];
|
||||||
|
}
|
||||||
|
|
||||||
|
extern uint8_t mem_region_buffer[4096 * 2] __aligned(PAGE_SIZE);
|
||||||
|
#define REGION_BUF_SIZE sizeof(mem_region_buffer)
|
||||||
|
|
||||||
|
/** The maximum number of recipients a memory region may be sent to. */
|
||||||
|
#define MAX_MEM_SHARE_RECIPIENTS 2U
|
||||||
|
|
||||||
|
/* FFA Memory Management mode flags. */
|
||||||
|
#define FFA_FLAG_SHARE_MEMORY (1U << 3)
|
||||||
|
#define FFA_FLAG_LEND_MEMORY (1U << 4)
|
||||||
|
|
||||||
|
#define FFA_FLAG_MEMORY_MASK (3U << 3)
|
||||||
|
|
||||||
|
#define FFA_MEM_HANDLE_LOW(x) (x & 0xFFFFFFFF)
|
||||||
|
#define FFA_MEM_HANDLE_HIGH(x) (x >> 32)
|
||||||
|
|
||||||
|
#define FFA_MEM_PERM_DATA_OFFSET 0
|
||||||
|
#define FFA_MEM_PERM_DATA_MASK 0x3
|
||||||
|
|
||||||
|
static inline uint32_t ffa_mem_relinquish_init(
|
||||||
|
struct ffa_mem_relinquish_descriptor *relinquish_request,
|
||||||
|
uint64_t handle, ffa_mtd_flag32_t flags,
|
||||||
|
ffa_endpoint_id16_t sender)
|
||||||
|
{
|
||||||
|
relinquish_request->handle = handle;
|
||||||
|
relinquish_request->flags = flags;
|
||||||
|
relinquish_request->endpoint_count = 1;
|
||||||
|
relinquish_request->endpoint_array[0] = sender;
|
||||||
|
|
||||||
|
return sizeof(struct ffa_mem_relinquish_descriptor) + sizeof(ffa_endpoint_id16_t);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Gets the `ffa_comp_mrd` for the given receiver from an
|
||||||
|
* `ffa_mtd`, or NULL if it is not valid.
|
||||||
|
*/
|
||||||
|
static inline struct ffa_comp_mrd *
|
||||||
|
ffa_memory_region_get_composite(struct ffa_mtd *memory_region,
|
||||||
|
uint32_t receiver_index)
|
||||||
|
{
|
||||||
|
struct ffa_emad_v1_0 *receivers;
|
||||||
|
uint32_t offset;
|
||||||
|
|
||||||
|
receivers = (struct ffa_emad_v1_0 *)
|
||||||
|
((uint8_t *) memory_region +
|
||||||
|
memory_region->emad_offset +
|
||||||
|
(memory_region->emad_size * receiver_index));
|
||||||
|
offset = receivers->comp_mrd_offset;
|
||||||
|
|
||||||
|
if (offset == 0U) {
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (struct ffa_comp_mrd *)
|
||||||
|
((uint8_t *) memory_region + offset);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline uint32_t ffa_get_data_access_attr(ffa_mem_perm8_t perm)
|
||||||
|
{
|
||||||
|
return ((perm >> FFA_MEM_PERM_DATA_OFFSET) & FFA_MEM_PERM_DATA_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
smc_args_t ffa_mem_frag_rx(uint64_t handle, uint32_t recv_length);
|
||||||
|
bool ffa_mem_relinquish(void);
|
||||||
|
bool ffa_rx_release(void);
|
||||||
|
bool memory_relinquish(struct ffa_mem_relinquish_descriptor *m, uint64_t handle,
|
||||||
|
ffa_endpoint_id16_t id);
|
||||||
|
bool ffa_rxtx_map(uintptr_t send, uintptr_t recv, uint32_t pages);
|
||||||
|
bool memory_retrieve(struct mailbox *mb,
|
||||||
|
struct ffa_mtd **retrieved,
|
||||||
|
uint64_t handle, ffa_endpoint_id16_t sender,
|
||||||
|
ffa_endpoint_id16_t *receivers, uint32_t receiver_count,
|
||||||
|
ffa_mtd_flag32_t flags, uint32_t *frag_length,
|
||||||
|
uint32_t *total_length);
|
||||||
|
|
||||||
|
smc_args_t ffa_msg_send_direct_req(ffa_endpoint_id16_t sender,
|
||||||
|
ffa_endpoint_id16_t receiver,
|
||||||
|
uint32_t arg3,
|
||||||
|
uint32_t arg4,
|
||||||
|
uint32_t arg5,
|
||||||
|
uint32_t arg6,
|
||||||
|
uint32_t arg7);
|
||||||
|
smc_args_t *ffa_msg_send_direct_resp(ffa_endpoint_id16_t sender,
|
||||||
|
ffa_endpoint_id16_t receiver,
|
||||||
|
uint32_t arg3,
|
||||||
|
uint32_t arg4,
|
||||||
|
uint32_t arg5,
|
||||||
|
uint32_t arg6,
|
||||||
|
uint32_t arg7);
|
||||||
|
#endif /* FFA_HELPERS_H */
|
||||||
123
arm-trusted-firmware/bl32/tsp/tsp.ld.S
Normal file
123
arm-trusted-firmware/bl32/tsp/tsp.ld.S
Normal file
@@ -0,0 +1,123 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common/bl_common.ld.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
|
||||||
|
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
|
||||||
|
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
|
||||||
|
ENTRY(tsp_entrypoint)
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY {
|
||||||
|
RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = BL32_BASE;
|
||||||
|
ASSERT(. == ALIGN(PAGE_SIZE),
|
||||||
|
"BL32_BASE address is not aligned on a page boundary.")
|
||||||
|
|
||||||
|
#if SEPARATE_CODE_AND_RODATA
|
||||||
|
.text . : {
|
||||||
|
__TEXT_START__ = .;
|
||||||
|
*tsp_entrypoint.o(.text*)
|
||||||
|
*(.text*)
|
||||||
|
*(.vectors)
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__TEXT_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
.rodata . : {
|
||||||
|
__RODATA_START__ = .;
|
||||||
|
*(.rodata*)
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RODATA_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#else
|
||||||
|
ro . : {
|
||||||
|
__RO_START__ = .;
|
||||||
|
*tsp_entrypoint.o(.text*)
|
||||||
|
*(.text*)
|
||||||
|
*(.rodata*)
|
||||||
|
|
||||||
|
RODATA_COMMON
|
||||||
|
|
||||||
|
*(.vectors)
|
||||||
|
|
||||||
|
__RO_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked as
|
||||||
|
* read-only, executable. No RW data from the next section must
|
||||||
|
* creep in. Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__RO_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark start of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_START__ = . ;
|
||||||
|
|
||||||
|
DATA_SECTION >RAM
|
||||||
|
RELA_SECTION >RAM
|
||||||
|
|
||||||
|
#ifdef TSP_PROGBITS_LIMIT
|
||||||
|
ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
STACK_SECTION >RAM
|
||||||
|
BSS_SECTION >RAM
|
||||||
|
XLAT_TABLE_SECTION >RAM
|
||||||
|
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
/*
|
||||||
|
* The base address of the coherent memory section must be page-aligned (4K)
|
||||||
|
* to guarantee that the coherent data are stored on their own pages and
|
||||||
|
* are not mixed with normal data. This is required to set up the correct
|
||||||
|
* memory attributes for the coherent data page tables.
|
||||||
|
*/
|
||||||
|
coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
|
||||||
|
__COHERENT_RAM_START__ = .;
|
||||||
|
*(tzfw_coherent_mem)
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ = .;
|
||||||
|
/*
|
||||||
|
* Memory page(s) mapped to this section will be marked
|
||||||
|
* as device memory. No other unexpected data must creep in.
|
||||||
|
* Ensure the rest of the current memory page is unused.
|
||||||
|
*/
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
|
__COHERENT_RAM_END__ = .;
|
||||||
|
} >RAM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Define a linker symbol to mark the end of the RW memory area for this
|
||||||
|
* image.
|
||||||
|
*/
|
||||||
|
__RW_END__ = .;
|
||||||
|
__BL32_END__ = .;
|
||||||
|
|
||||||
|
/DISCARD/ : {
|
||||||
|
*(.dynsym .dynstr .hash .gnu.hash)
|
||||||
|
}
|
||||||
|
|
||||||
|
__BSS_SIZE__ = SIZEOF(.bss);
|
||||||
|
#if USE_COHERENT_MEM
|
||||||
|
__COHERENT_RAM_UNALIGNED_SIZE__ =
|
||||||
|
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
|
||||||
|
}
|
||||||
43
arm-trusted-firmware/bl32/tsp/tsp.mk
Normal file
43
arm-trusted-firmware/bl32/tsp/tsp.mk
Normal file
@@ -0,0 +1,43 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
|
||||||
|
INCLUDES += -Iinclude/bl32/tsp
|
||||||
|
|
||||||
|
ifeq (${SPMC_AT_EL3},1)
|
||||||
|
BL32_SOURCES += bl32/tsp/tsp_ffa_main.c \
|
||||||
|
bl32/tsp/ffa_helpers.c
|
||||||
|
else
|
||||||
|
BL32_SOURCES += bl32/tsp/tsp_main.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
BL32_SOURCES += bl32/tsp/aarch64/tsp_entrypoint.S \
|
||||||
|
bl32/tsp/aarch64/tsp_exceptions.S \
|
||||||
|
bl32/tsp/aarch64/tsp_request.S \
|
||||||
|
bl32/tsp/tsp_interrupt.c \
|
||||||
|
bl32/tsp/tsp_timer.c \
|
||||||
|
bl32/tsp/tsp_common.c \
|
||||||
|
common/aarch64/early_exceptions.S \
|
||||||
|
lib/locks/exclusive/aarch64/spinlock.S
|
||||||
|
|
||||||
|
BL32_LINKERFILE := bl32/tsp/tsp.ld.S
|
||||||
|
|
||||||
|
# This flag determines if the TSPD initializes BL32 in tspd_init() (synchronous
|
||||||
|
# method) or configures BL31 to pass control to BL32 instead of BL33
|
||||||
|
# (asynchronous method).
|
||||||
|
TSP_INIT_ASYNC := 0
|
||||||
|
|
||||||
|
$(eval $(call assert_boolean,TSP_INIT_ASYNC))
|
||||||
|
$(eval $(call add_define,TSP_INIT_ASYNC))
|
||||||
|
|
||||||
|
# Include the platform-specific TSP Makefile
|
||||||
|
# If no platform-specific TSP Makefile exists, it means TSP is not supported
|
||||||
|
# on this platform.
|
||||||
|
TSP_PLAT_MAKEFILE := $(wildcard ${PLAT_DIR}/tsp/tsp-${PLAT}.mk)
|
||||||
|
ifeq (,${TSP_PLAT_MAKEFILE})
|
||||||
|
$(error TSP is not supported on platform ${PLAT})
|
||||||
|
else
|
||||||
|
include ${TSP_PLAT_MAKEFILE}
|
||||||
|
endif
|
||||||
156
arm-trusted-firmware/bl32/tsp/tsp_common.c
Normal file
156
arm-trusted-firmware/bl32/tsp/tsp_common.c
Normal file
@@ -0,0 +1,156 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <inttypes.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <arch_features.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <bl32/tsp/tsp.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <lib/spinlock.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
#include <platform_tsp.h>
|
||||||
|
#include "tsp_private.h"
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Per cpu data structure to populate parameters for an SMC in C code and use
|
||||||
|
* a pointer to this structure in assembler code to populate x0-x7.
|
||||||
|
******************************************************************************/
|
||||||
|
static smc_args_t tsp_smc_args[PLATFORM_CORE_COUNT];
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Per cpu data structure to keep track of TSP activity
|
||||||
|
******************************************************************************/
|
||||||
|
work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
|
||||||
|
|
||||||
|
smc_args_t *set_smc_args(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t linear_id;
|
||||||
|
smc_args_t *pcpu_smc_args;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return to Secure Monitor by raising an SMC. The results of the
|
||||||
|
* service are passed as an arguments to the SMC.
|
||||||
|
*/
|
||||||
|
linear_id = plat_my_core_pos();
|
||||||
|
pcpu_smc_args = &tsp_smc_args[linear_id];
|
||||||
|
write_sp_arg(pcpu_smc_args, SMC_ARG0, arg0);
|
||||||
|
write_sp_arg(pcpu_smc_args, SMC_ARG1, arg1);
|
||||||
|
write_sp_arg(pcpu_smc_args, SMC_ARG2, arg2);
|
||||||
|
write_sp_arg(pcpu_smc_args, SMC_ARG3, arg3);
|
||||||
|
write_sp_arg(pcpu_smc_args, SMC_ARG4, arg4);
|
||||||
|
write_sp_arg(pcpu_smc_args, SMC_ARG5, arg5);
|
||||||
|
write_sp_arg(pcpu_smc_args, SMC_ARG6, arg6);
|
||||||
|
write_sp_arg(pcpu_smc_args, SMC_ARG7, arg7);
|
||||||
|
|
||||||
|
return pcpu_smc_args;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Setup function for TSP.
|
||||||
|
******************************************************************************/
|
||||||
|
void tsp_setup(void)
|
||||||
|
{
|
||||||
|
/* Perform early platform-specific setup. */
|
||||||
|
tsp_early_platform_setup();
|
||||||
|
|
||||||
|
/* Perform late platform-specific setup. */
|
||||||
|
tsp_plat_arch_setup();
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/*
|
||||||
|
* Assert that the ARMv8.3-PAuth registers are present or an access
|
||||||
|
* fault will be triggered when they are being saved or restored.
|
||||||
|
*/
|
||||||
|
assert(is_armv8_3_pauth_present());
|
||||||
|
#endif /* ENABLE_PAUTH */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any remaining bookkeeping in the test secure payload
|
||||||
|
* before the system is switched off (in response to a psci SYSTEM_OFF request).
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_system_off_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics. */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr());
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count);
|
||||||
|
|
||||||
|
/* Indicate to the SPD that we have completed this request. */
|
||||||
|
return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any remaining bookkeeping in the test secure payload
|
||||||
|
* before the system is reset (in response to a psci SYSTEM_RESET request).
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_system_reset_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics. */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr());
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count);
|
||||||
|
|
||||||
|
/* Indicate to the SPD that we have completed this request. */
|
||||||
|
return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* TSP smc abort handler. This function is called when aborting a preempted
|
||||||
|
* yielding SMC request. It should cleanup all resources owned by the SMC
|
||||||
|
* handler such as locks or dynamically allocated memory so following SMC
|
||||||
|
* request are executed in a clean environment.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_abort_smc_handler(uint64_t func,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
return set_smc_args(TSP_ABORT_DONE, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
655
arm-trusted-firmware/bl32/tsp/tsp_ffa_main.c
Normal file
655
arm-trusted-firmware/bl32/tsp/tsp_ffa_main.c
Normal file
@@ -0,0 +1,655 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <inttypes.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include "../../services/std_svc/spm/el3_spmc/spmc.h"
|
||||||
|
#include "../../services/std_svc/spm/el3_spmc/spmc_shared_mem.h"
|
||||||
|
#include <arch_features.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <bl32/tsp/tsp.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include "ffa_helpers.h"
|
||||||
|
#include <lib/psci/psci.h>
|
||||||
|
#include <lib/spinlock.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
#include <platform_tsp.h>
|
||||||
|
#include <services/ffa_svc.h>
|
||||||
|
#include "tsp_private.h"
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
static ffa_endpoint_id16_t tsp_id, spmc_id;
|
||||||
|
uint8_t mem_region_buffer[4096 * 2] __aligned(PAGE_SIZE);
|
||||||
|
|
||||||
|
/* Partition Mailbox. */
|
||||||
|
static uint8_t send_page[PAGE_SIZE] __aligned(PAGE_SIZE);
|
||||||
|
static uint8_t recv_page[PAGE_SIZE] __aligned(PAGE_SIZE);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Declare a global mailbox for use within the TSP.
|
||||||
|
* This will be initialized appropriately when the buffers
|
||||||
|
* are mapped with the SPMC.
|
||||||
|
*/
|
||||||
|
static struct mailbox mailbox;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This enum is used to handle test cases driven from the FF-A Test Driver.
|
||||||
|
******************************************************************************/
|
||||||
|
/* Keep in Sync with FF-A Test Driver. */
|
||||||
|
enum message_t {
|
||||||
|
/* Partition Only Messages. */
|
||||||
|
FF_A_RELAY_MESSAGE = 0,
|
||||||
|
|
||||||
|
/* Basic Functionality. */
|
||||||
|
FF_A_ECHO_MESSAGE,
|
||||||
|
FF_A_RELAY_MESSAGE_EL3,
|
||||||
|
|
||||||
|
/* Memory Sharing. */
|
||||||
|
FF_A_MEMORY_SHARE,
|
||||||
|
FF_A_MEMORY_SHARE_FRAGMENTED,
|
||||||
|
FF_A_MEMORY_LEND,
|
||||||
|
FF_A_MEMORY_LEND_FRAGMENTED,
|
||||||
|
|
||||||
|
FF_A_MEMORY_SHARE_MULTI_ENDPOINT,
|
||||||
|
FF_A_MEMORY_LEND_MULTI_ENDPOINT,
|
||||||
|
|
||||||
|
LAST,
|
||||||
|
FF_A_RUN_ALL = 255,
|
||||||
|
FF_A_OP_MAX = 256
|
||||||
|
};
|
||||||
|
|
||||||
|
#if SPMC_AT_EL3
|
||||||
|
extern void tsp_cpu_on_entry(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Test Functions.
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Enable the TSP to forward the received message to another partition and ask
|
||||||
|
* it to echo the value back in order to validate direct messages functionality.
|
||||||
|
******************************************************************************/
|
||||||
|
static int ffa_test_relay(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
smc_args_t ffa_forward_result;
|
||||||
|
ffa_endpoint_id16_t receiver = arg5;
|
||||||
|
|
||||||
|
ffa_forward_result = ffa_msg_send_direct_req(ffa_endpoint_source(arg1),
|
||||||
|
receiver,
|
||||||
|
FF_A_ECHO_MESSAGE, arg4,
|
||||||
|
0, 0, 0);
|
||||||
|
return ffa_forward_result._regs[3];
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function handles memory management tests, currently share and lend.
|
||||||
|
* This test supports the use of FRAG_RX to use memory descriptors that do not
|
||||||
|
* fit in a single 4KB buffer.
|
||||||
|
******************************************************************************/
|
||||||
|
static int test_memory_send(ffa_endpoint_id16_t sender, uint64_t handle,
|
||||||
|
ffa_mtd_flag32_t flags, bool multi_endpoint)
|
||||||
|
{
|
||||||
|
struct ffa_mtd *m;
|
||||||
|
struct ffa_emad_v1_0 *receivers;
|
||||||
|
struct ffa_comp_mrd *composite;
|
||||||
|
int ret, status = 0;
|
||||||
|
unsigned int mem_attrs;
|
||||||
|
char *ptr;
|
||||||
|
ffa_endpoint_id16_t source = sender;
|
||||||
|
uint32_t total_length, recv_length = 0;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* In the case that we're testing multiple endpoints choose a partition
|
||||||
|
* ID that resides in the normal world so the SPMC won't detect it as
|
||||||
|
* invalid.
|
||||||
|
* TODO: Should get endpoint receiver id and flag as input from NWd.
|
||||||
|
*/
|
||||||
|
uint32_t receiver_count = multi_endpoint ? 2 : 1;
|
||||||
|
ffa_endpoint_id16_t test_receivers[2] = { tsp_id, 0x10 };
|
||||||
|
|
||||||
|
/* Ensure that the sender ID resides in the normal world. */
|
||||||
|
if (ffa_is_secure_world_id(sender)) {
|
||||||
|
ERROR("Invalid sender ID 0x%x.\n", sender);
|
||||||
|
return FFA_ERROR_DENIED;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!memory_retrieve(&mailbox, &m, handle, source, test_receivers,
|
||||||
|
receiver_count, flags, &recv_length,
|
||||||
|
&total_length)) {
|
||||||
|
return FFA_ERROR_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
|
||||||
|
receivers = (struct ffa_emad_v1_0 *)
|
||||||
|
((uint8_t *) m + m->emad_offset);
|
||||||
|
while (total_length != recv_length) {
|
||||||
|
smc_args_t ffa_return;
|
||||||
|
uint32_t frag_length;
|
||||||
|
|
||||||
|
ffa_return = ffa_mem_frag_rx(handle, recv_length);
|
||||||
|
|
||||||
|
if (ffa_return._regs[0] == FFA_ERROR) {
|
||||||
|
WARN("TSP: failed to resume mem with handle %lx\n",
|
||||||
|
handle);
|
||||||
|
return ffa_return._regs[2];
|
||||||
|
}
|
||||||
|
frag_length = ffa_return._regs[3];
|
||||||
|
|
||||||
|
/* Validate frag_length is less than total_length and mailbox size. */
|
||||||
|
if (frag_length > total_length ||
|
||||||
|
frag_length > (mailbox.rxtx_page_count * PAGE_SIZE)) {
|
||||||
|
ERROR("Invalid parameters!\n");
|
||||||
|
return FFA_ERROR_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Validate frag_length is less than remaining mem_region_buffer size. */
|
||||||
|
if (frag_length + recv_length >= REGION_BUF_SIZE) {
|
||||||
|
ERROR("Out of memory!\n");
|
||||||
|
return FFA_ERROR_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
|
||||||
|
memcpy(&mem_region_buffer[recv_length], mailbox.rx_buffer,
|
||||||
|
frag_length);
|
||||||
|
|
||||||
|
if (ffa_rx_release()) {
|
||||||
|
ERROR("Failed to release buffer!\n");
|
||||||
|
return FFA_ERROR_DENIED;
|
||||||
|
}
|
||||||
|
|
||||||
|
recv_length += frag_length;
|
||||||
|
|
||||||
|
assert(recv_length <= total_length);
|
||||||
|
}
|
||||||
|
|
||||||
|
composite = ffa_memory_region_get_composite(m, 0);
|
||||||
|
if (composite == NULL) {
|
||||||
|
WARN("Failed to get composite descriptor!\n");
|
||||||
|
return FFA_ERROR_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
|
||||||
|
VERBOSE("Address: %p; page_count: %x %lx\n",
|
||||||
|
(void *)composite->address_range_array[0].address,
|
||||||
|
composite->address_range_array[0].page_count, PAGE_SIZE);
|
||||||
|
|
||||||
|
/* This test is only concerned with RW permissions. */
|
||||||
|
if (ffa_get_data_access_attr(
|
||||||
|
receivers[0].mapd.memory_access_permissions) != FFA_MEM_PERM_RW) {
|
||||||
|
ERROR("Data permission in retrieve response %x does not match share/lend %x!\n",
|
||||||
|
ffa_get_data_access_attr(receivers[0].mapd.memory_access_permissions),
|
||||||
|
FFA_MEM_PERM_RW);
|
||||||
|
return FFA_ERROR_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
|
||||||
|
mem_attrs = MT_RW_DATA | MT_EXECUTE_NEVER;
|
||||||
|
|
||||||
|
/* Only expecting to be sent memory from NWd so map accordingly. */
|
||||||
|
mem_attrs |= MT_NS;
|
||||||
|
|
||||||
|
for (uint32_t i = 0U; i < composite->address_range_count; i++) {
|
||||||
|
size_t size = composite->address_range_array[i].page_count * PAGE_SIZE;
|
||||||
|
|
||||||
|
ptr = (char *) composite->address_range_array[i].address;
|
||||||
|
ret = mmap_add_dynamic_region(
|
||||||
|
(uint64_t)ptr,
|
||||||
|
(uint64_t)ptr,
|
||||||
|
size, mem_attrs);
|
||||||
|
|
||||||
|
if (ret != 0) {
|
||||||
|
ERROR("Failed [%u] mmap_add_dynamic_region %u (%lx) (%lx) (%x)!\n",
|
||||||
|
i, ret,
|
||||||
|
(uint64_t)composite->address_range_array[i].address,
|
||||||
|
size, mem_attrs);
|
||||||
|
|
||||||
|
/* Remove mappings created in this transaction. */
|
||||||
|
for (i--; i >= 0U; i--) {
|
||||||
|
ret = mmap_remove_dynamic_region(
|
||||||
|
(uint64_t)ptr,
|
||||||
|
composite->address_range_array[i].page_count * PAGE_SIZE);
|
||||||
|
|
||||||
|
if (ret != 0) {
|
||||||
|
ERROR("Failed [%d] mmap_remove_dynamic_region!\n", i);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return FFA_ERROR_NO_MEMORY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Increment memory region for validation purposes. */
|
||||||
|
++(*ptr);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read initial magic number from memory region for
|
||||||
|
* validation purposes.
|
||||||
|
*/
|
||||||
|
if (!i) {
|
||||||
|
status = *ptr;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
for (uint32_t i = 0U; i < composite->address_range_count; i++) {
|
||||||
|
ret = mmap_remove_dynamic_region(
|
||||||
|
(uint64_t)composite->address_range_array[i].address,
|
||||||
|
composite->address_range_array[i].page_count * PAGE_SIZE);
|
||||||
|
|
||||||
|
if (ret != 0) {
|
||||||
|
ERROR("Failed [%d] mmap_remove_dynamic_region!\n", i);
|
||||||
|
return FFA_ERROR_NO_MEMORY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!memory_relinquish((struct ffa_mem_relinquish_descriptor *)mailbox.tx_buffer,
|
||||||
|
m->handle, tsp_id)) {
|
||||||
|
ERROR("Failed to relinquish memory region!\n");
|
||||||
|
return FFA_ERROR_INVALID_PARAMETER;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
static smc_args_t *send_ffa_pm_success(void)
|
||||||
|
{
|
||||||
|
return set_smc_args(FFA_MSG_SEND_DIRECT_RESP_SMC32,
|
||||||
|
((tsp_id & FFA_DIRECT_MSG_ENDPOINT_ID_MASK)
|
||||||
|
<< FFA_DIRECT_MSG_SOURCE_SHIFT) | spmc_id,
|
||||||
|
FFA_FWK_MSG_BIT |
|
||||||
|
(FFA_PM_MSG_PM_RESP & FFA_FWK_MSG_MASK),
|
||||||
|
0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any remaining book keeping in the test secure payload
|
||||||
|
* before this cpu is turned off in response to a psci cpu_off request.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_cpu_off_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This cpu is being turned off, so disable the timer to prevent the
|
||||||
|
* secure timer interrupt from interfering with power down. A pending
|
||||||
|
* interrupt will be lost but we do not care as we are turning off.
|
||||||
|
*/
|
||||||
|
tsp_generic_timer_stop();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics. */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_off_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_off_count);
|
||||||
|
|
||||||
|
return send_ffa_pm_success();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any book keeping in the test secure payload before
|
||||||
|
* this cpu's architectural state is saved in response to an earlier psci
|
||||||
|
* cpu_suspend request.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_cpu_suspend_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Save the time context and disable it to prevent the secure timer
|
||||||
|
* interrupt from interfering with wakeup from the suspend state.
|
||||||
|
*/
|
||||||
|
tsp_generic_timer_save();
|
||||||
|
tsp_generic_timer_stop();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics. */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_suspend_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_suspend_count);
|
||||||
|
|
||||||
|
return send_ffa_pm_success();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any bookkeeping in the test secure payload after this
|
||||||
|
* cpu's architectural state has been restored after wakeup from an earlier psci
|
||||||
|
* cpu_suspend request.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/* Restore the generic timer context. */
|
||||||
|
tsp_generic_timer_restore();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics. */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_resume_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
|
||||||
|
read_mpidr(), max_off_pwrlvl);
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_resume_count);
|
||||||
|
|
||||||
|
return send_ffa_pm_success();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function handles framework messages. Currently only PM.
|
||||||
|
******************************************************************************/
|
||||||
|
static smc_args_t *handle_framework_message(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
/* Check if it is a power management message from the SPMC. */
|
||||||
|
if (ffa_endpoint_source(arg1) != spmc_id) {
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check if it is a PM request message. */
|
||||||
|
if ((arg2 & FFA_FWK_MSG_MASK) == FFA_FWK_MSG_PSCI) {
|
||||||
|
/* Check if it is a PSCI CPU_OFF request. */
|
||||||
|
if (arg3 == PSCI_CPU_OFF) {
|
||||||
|
return tsp_cpu_off_main(arg0, arg1, arg2, arg3,
|
||||||
|
arg4, arg5, arg6, arg7);
|
||||||
|
} else if (arg3 == PSCI_CPU_SUSPEND_AARCH64) {
|
||||||
|
return tsp_cpu_suspend_main(arg0, arg1, arg2, arg3,
|
||||||
|
arg4, arg5, arg6, arg7);
|
||||||
|
}
|
||||||
|
} else if ((arg2 & FFA_FWK_MSG_MASK) == FFA_PM_MSG_WB_REQ) {
|
||||||
|
/* Check it is a PSCI Warm Boot request. */
|
||||||
|
if (arg3 == FFA_WB_TYPE_NOTS2RAM) {
|
||||||
|
return tsp_cpu_resume_main(arg0, arg1, arg2, arg3,
|
||||||
|
arg4, arg5, arg6, arg7);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
err:
|
||||||
|
ERROR("%s: Unknown framework message!\n", __func__);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Handles partition messages. Exercised from the FF-A Test Driver.
|
||||||
|
******************************************************************************/
|
||||||
|
static smc_args_t *handle_partition_message(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint16_t sender = ffa_endpoint_source(arg1);
|
||||||
|
uint16_t receiver = ffa_endpoint_destination(arg1);
|
||||||
|
int status = -1;
|
||||||
|
const bool multi_endpoint = true;
|
||||||
|
|
||||||
|
switch (arg3) {
|
||||||
|
case FF_A_MEMORY_SHARE:
|
||||||
|
INFO("TSP Tests: Memory Share Request--\n");
|
||||||
|
status = test_memory_send(sender, arg4, FFA_FLAG_SHARE_MEMORY, !multi_endpoint);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case FF_A_MEMORY_LEND:
|
||||||
|
INFO("TSP Tests: Memory Lend Request--\n");
|
||||||
|
status = test_memory_send(sender, arg4, FFA_FLAG_LEND_MEMORY, !multi_endpoint);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case FF_A_MEMORY_SHARE_MULTI_ENDPOINT:
|
||||||
|
INFO("TSP Tests: Multi Endpoint Memory Share Request--\n");
|
||||||
|
status = test_memory_send(sender, arg4, FFA_FLAG_SHARE_MEMORY, multi_endpoint);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case FF_A_MEMORY_LEND_MULTI_ENDPOINT:
|
||||||
|
INFO("TSP Tests: Multi Endpoint Memory Lend Request--\n");
|
||||||
|
status = test_memory_send(sender, arg4, FFA_FLAG_LEND_MEMORY, multi_endpoint);
|
||||||
|
break;
|
||||||
|
case FF_A_RELAY_MESSAGE:
|
||||||
|
INFO("TSP Tests: Relaying message--\n");
|
||||||
|
status = ffa_test_relay(arg0, arg1, arg2, arg3, arg4,
|
||||||
|
arg5, arg6, arg7);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case FF_A_ECHO_MESSAGE:
|
||||||
|
INFO("TSP Tests: echo message--\n");
|
||||||
|
status = arg4;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
INFO("TSP Tests: Unknown request ID %d--\n", (int) arg3);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Swap the sender and receiver in the response. */
|
||||||
|
return ffa_msg_send_direct_resp(receiver, sender, status, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function implements the event loop for handling FF-A ABI invocations.
|
||||||
|
******************************************************************************/
|
||||||
|
static smc_args_t *tsp_event_loop(uint64_t smc_fid,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
/* Panic if the SPMC did not forward an FF-A call. */
|
||||||
|
if (!is_ffa_fid(smc_fid)) {
|
||||||
|
ERROR("%s: Unknown SMC FID (0x%lx)\n", __func__, smc_fid);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (smc_fid) {
|
||||||
|
case FFA_INTERRUPT:
|
||||||
|
/*
|
||||||
|
* IRQs were enabled upon re-entry into the TSP. The interrupt
|
||||||
|
* must have been handled by now. Return to the SPMC indicating
|
||||||
|
* the same.
|
||||||
|
*/
|
||||||
|
return set_smc_args(FFA_MSG_WAIT, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
|
||||||
|
case FFA_MSG_SEND_DIRECT_REQ_SMC64:
|
||||||
|
case FFA_MSG_SEND_DIRECT_REQ_SMC32:
|
||||||
|
/* Check if a framework message, handle accordingly. */
|
||||||
|
if ((arg2 & FFA_FWK_MSG_BIT)) {
|
||||||
|
return handle_framework_message(smc_fid, arg1, arg2, arg3,
|
||||||
|
arg4, arg5, arg6, arg7);
|
||||||
|
}
|
||||||
|
return handle_partition_message(smc_fid, arg1, arg2, arg3,
|
||||||
|
arg4, arg5, arg6, arg7);
|
||||||
|
}
|
||||||
|
|
||||||
|
ERROR("%s: Unsupported FF-A FID (0x%lx)\n", __func__, smc_fid);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
static smc_args_t *tsp_loop(smc_args_t *args)
|
||||||
|
{
|
||||||
|
smc_args_t ret;
|
||||||
|
|
||||||
|
do {
|
||||||
|
/* --------------------------------------------
|
||||||
|
* Mask FIQ interrupts to avoid preemption
|
||||||
|
* in case EL3 SPMC delegates an IRQ next or a
|
||||||
|
* managed exit. Lastly, unmask IRQs so that
|
||||||
|
* they can be handled immediately upon re-entry.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
write_daifset(DAIF_FIQ_BIT);
|
||||||
|
write_daifclr(DAIF_IRQ_BIT);
|
||||||
|
ret = smc_helper(args->_regs[0], args->_regs[1], args->_regs[2],
|
||||||
|
args->_regs[3], args->_regs[4], args->_regs[5],
|
||||||
|
args->_regs[6], args->_regs[7]);
|
||||||
|
args = tsp_event_loop(ret._regs[0], ret._regs[1], ret._regs[2],
|
||||||
|
ret._regs[3], ret._regs[4], ret._regs[5],
|
||||||
|
ret._regs[6], ret._regs[7]);
|
||||||
|
} while (1);
|
||||||
|
|
||||||
|
/* Not Reached. */
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* TSP main entry point where it gets the opportunity to initialize its secure
|
||||||
|
* state/applications. Once the state is initialized, it must return to the
|
||||||
|
* SPD with a pointer to the 'tsp_vector_table' jump table.
|
||||||
|
******************************************************************************/
|
||||||
|
uint64_t tsp_main(void)
|
||||||
|
{
|
||||||
|
smc_args_t smc_args = {0};
|
||||||
|
|
||||||
|
NOTICE("TSP: %s\n", version_string);
|
||||||
|
NOTICE("TSP: %s\n", build_message);
|
||||||
|
INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE);
|
||||||
|
INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE);
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/* Initialize the platform. */
|
||||||
|
tsp_platform_setup();
|
||||||
|
|
||||||
|
/* Initialize secure/applications state here. */
|
||||||
|
tsp_generic_timer_start();
|
||||||
|
|
||||||
|
/* Register secondary entrypoint with the SPMC. */
|
||||||
|
smc_args = smc_helper(FFA_SECONDARY_EP_REGISTER_SMC64,
|
||||||
|
(uint64_t) tsp_cpu_on_entry,
|
||||||
|
0, 0, 0, 0, 0, 0);
|
||||||
|
if (smc_args._regs[SMC_ARG0] != FFA_SUCCESS_SMC32) {
|
||||||
|
ERROR("TSP could not register secondary ep (0x%lx)\n",
|
||||||
|
smc_args._regs[2]);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
/* Get TSP's endpoint id. */
|
||||||
|
smc_args = smc_helper(FFA_ID_GET, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
if (smc_args._regs[SMC_ARG0] != FFA_SUCCESS_SMC32) {
|
||||||
|
ERROR("TSP could not get own ID (0x%lx) on core%d\n",
|
||||||
|
smc_args._regs[2], linear_id);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
tsp_id = smc_args._regs[2];
|
||||||
|
INFO("TSP FF-A endpoint id = 0x%x\n", tsp_id);
|
||||||
|
|
||||||
|
/* Get the SPMC ID. */
|
||||||
|
smc_args = smc_helper(FFA_SPM_ID_GET, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
if (smc_args._regs[SMC_ARG0] != FFA_SUCCESS_SMC32) {
|
||||||
|
ERROR("TSP could not get SPMC ID (0x%lx) on core%d\n",
|
||||||
|
smc_args._regs[2], linear_id);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
spmc_id = smc_args._regs[2];
|
||||||
|
|
||||||
|
/* Call RXTX_MAP to map a 4k RX and TX buffer. */
|
||||||
|
if (ffa_rxtx_map((uintptr_t) send_page,
|
||||||
|
(uintptr_t) recv_page, 1)) {
|
||||||
|
ERROR("TSP could not map it's RX/TX Buffers\n");
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
mailbox.tx_buffer = send_page;
|
||||||
|
mailbox.rx_buffer = recv_page;
|
||||||
|
mailbox.rxtx_page_count = 1;
|
||||||
|
|
||||||
|
/* Update this cpu's statistics. */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_on_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_on_count);
|
||||||
|
|
||||||
|
/* Tell SPMD that we are done initialising. */
|
||||||
|
tsp_loop(set_smc_args(FFA_MSG_WAIT, 0, 0, 0, 0, 0, 0, 0));
|
||||||
|
|
||||||
|
/* Not reached. */
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any remaining book keeping in the test secure payload
|
||||||
|
* after this cpu's architectural state has been setup in response to an earlier
|
||||||
|
* psci cpu_on request.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_cpu_on_main(void)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/* Initialize secure/applications state here. */
|
||||||
|
tsp_generic_timer_start();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics. */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_on_count++;
|
||||||
|
INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_on_count);
|
||||||
|
/* ---------------------------------------------
|
||||||
|
* Jump to the main event loop to return to EL3
|
||||||
|
* and be ready for the next request on this cpu.
|
||||||
|
* ---------------------------------------------
|
||||||
|
*/
|
||||||
|
return tsp_loop(set_smc_args(FFA_MSG_WAIT, 0, 0, 0, 0, 0, 0, 0));
|
||||||
|
}
|
||||||
115
arm-trusted-firmware/bl32/tsp/tsp_interrupt.c
Normal file
115
arm-trusted-firmware/bl32/tsp/tsp_interrupt.c
Normal file
@@ -0,0 +1,115 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <inttypes.h>
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <bl32/tsp/tsp.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
#include "tsp_private.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function updates the TSP statistics for S-EL1 interrupts handled
|
||||||
|
* synchronously i.e the ones that have been handed over by the TSPD. It also
|
||||||
|
* keeps count of the number of times control was passed back to the TSPD
|
||||||
|
* after handling the interrupt. In the future it will be possible that the
|
||||||
|
* TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to
|
||||||
|
* return execution. This statistic will be useful to distinguish between these
|
||||||
|
* two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter
|
||||||
|
* contains the address of the instruction in normal world where this S-EL1
|
||||||
|
* interrupt was generated.
|
||||||
|
******************************************************************************/
|
||||||
|
void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
tsp_stats[linear_id].sync_sel1_intr_count++;
|
||||||
|
if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN)
|
||||||
|
tsp_stats[linear_id].sync_sel1_intr_ret_count++;
|
||||||
|
|
||||||
|
VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%" PRIx64 "\n",
|
||||||
|
read_mpidr(), elr_el3);
|
||||||
|
VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests,"
|
||||||
|
" %d sync s-el1 interrupt returns\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].sync_sel1_intr_count,
|
||||||
|
tsp_stats[linear_id].sync_sel1_intr_ret_count);
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* This function is invoked when a non S-EL1 interrupt is received and causes
|
||||||
|
* the preemption of TSP. This function returns TSP_PREEMPTED and results
|
||||||
|
* in the control being handed over to EL3 for handling the interrupt.
|
||||||
|
*****************************************************************************/
|
||||||
|
int32_t tsp_handle_preemption(void)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
tsp_stats[linear_id].preempt_intr_count++;
|
||||||
|
VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n",
|
||||||
|
read_mpidr(), tsp_stats[linear_id].preempt_intr_count);
|
||||||
|
return TSP_PREEMPTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* TSP interrupt handler is called as a part of both synchronous and
|
||||||
|
* asynchronous handling of TSP interrupts. Currently the physical timer
|
||||||
|
* interrupt is the only S-EL1 interrupt that this handler expects. It returns
|
||||||
|
* 0 upon successfully handling the expected interrupt and all other
|
||||||
|
* interrupts are treated as normal world or EL3 interrupts.
|
||||||
|
******************************************************************************/
|
||||||
|
int32_t tsp_common_int_handler(void)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos(), id;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the highest priority pending interrupt id and see if it is the
|
||||||
|
* secure physical generic timer interrupt in which case, handle it.
|
||||||
|
* Otherwise throw this interrupt at the EL3 firmware.
|
||||||
|
*
|
||||||
|
* There is a small time window between reading the highest priority
|
||||||
|
* pending interrupt and acknowledging it during which another
|
||||||
|
* interrupt of higher priority could become the highest pending
|
||||||
|
* interrupt. This is not expected to happen currently for TSP.
|
||||||
|
*/
|
||||||
|
id = plat_ic_get_pending_interrupt_id();
|
||||||
|
|
||||||
|
/* TSP can only handle the secure physical timer interrupt */
|
||||||
|
if (id != TSP_IRQ_SEC_PHY_TIMER) {
|
||||||
|
#if SPMC_AT_EL3
|
||||||
|
/*
|
||||||
|
* With the EL3 FF-A SPMC we expect only Timer secure interrupt to fire in
|
||||||
|
* the TSP, so panic if any other interrupt does.
|
||||||
|
*/
|
||||||
|
ERROR("Unexpected interrupt id %u\n", id);
|
||||||
|
panic();
|
||||||
|
#else
|
||||||
|
return tsp_handle_preemption();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Acknowledge and handle the secure timer interrupt. Also sanity check
|
||||||
|
* if it has been preempted by another interrupt through an assertion.
|
||||||
|
*/
|
||||||
|
id = plat_ic_acknowledge_interrupt();
|
||||||
|
assert(id == TSP_IRQ_SEC_PHY_TIMER);
|
||||||
|
tsp_generic_timer_handler();
|
||||||
|
plat_ic_end_of_interrupt(id);
|
||||||
|
|
||||||
|
/* Update the statistics and print some messages */
|
||||||
|
tsp_stats[linear_id].sel1_intr_count++;
|
||||||
|
VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n",
|
||||||
|
read_mpidr(), id);
|
||||||
|
VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n",
|
||||||
|
read_mpidr(), tsp_stats[linear_id].sel1_intr_count);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
286
arm-trusted-firmware/bl32/tsp/tsp_main.c
Normal file
286
arm-trusted-firmware/bl32/tsp/tsp_main.c
Normal file
@@ -0,0 +1,286 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <inttypes.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <arch_features.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <bl32/tsp/tsp.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <lib/spinlock.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
#include <platform_tsp.h>
|
||||||
|
#include "tsp_private.h"
|
||||||
|
|
||||||
|
#include <platform_def.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* TSP main entry point where it gets the opportunity to initialize its secure
|
||||||
|
* state/applications. Once the state is initialized, it must return to the
|
||||||
|
* SPD with a pointer to the 'tsp_vector_table' jump table.
|
||||||
|
******************************************************************************/
|
||||||
|
uint64_t tsp_main(void)
|
||||||
|
{
|
||||||
|
NOTICE("TSP: %s\n", version_string);
|
||||||
|
NOTICE("TSP: %s\n", build_message);
|
||||||
|
INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE);
|
||||||
|
INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE);
|
||||||
|
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/* Initialize the platform */
|
||||||
|
tsp_platform_setup();
|
||||||
|
|
||||||
|
/* Initialize secure/applications state here */
|
||||||
|
tsp_generic_timer_start();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_on_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_on_count);
|
||||||
|
return (uint64_t) &tsp_vector_table;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any remaining book keeping in the test secure payload
|
||||||
|
* after this cpu's architectural state has been setup in response to an earlier
|
||||||
|
* psci cpu_on request.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_cpu_on_main(void)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/* Initialize secure/applications state here */
|
||||||
|
tsp_generic_timer_start();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_on_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_on_count);
|
||||||
|
/* Indicate to the SPD that we have completed turned ourselves on */
|
||||||
|
return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any remaining book keeping in the test secure payload
|
||||||
|
* before this cpu is turned off in response to a psci cpu_off request.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_cpu_off_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This cpu is being turned off, so disable the timer to prevent the
|
||||||
|
* secure timer interrupt from interfering with power down. A pending
|
||||||
|
* interrupt will be lost but we do not care as we are turning off.
|
||||||
|
*/
|
||||||
|
tsp_generic_timer_stop();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_off_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_off_count);
|
||||||
|
|
||||||
|
/* Indicate to the SPD that we have completed this request */
|
||||||
|
return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any book keeping in the test secure payload before
|
||||||
|
* this cpu's architectural state is saved in response to an earlier psci
|
||||||
|
* cpu_suspend request.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_cpu_suspend_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Save the time context and disable it to prevent the secure timer
|
||||||
|
* interrupt from interfering with wakeup from the suspend state.
|
||||||
|
*/
|
||||||
|
tsp_generic_timer_save();
|
||||||
|
tsp_generic_timer_stop();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_suspend_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_suspend_count);
|
||||||
|
|
||||||
|
/* Indicate to the SPD that we have completed this request */
|
||||||
|
return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function performs any book keeping in the test secure payload after this
|
||||||
|
* cpu's architectural state has been restored after wakeup from an earlier psci
|
||||||
|
* cpu_suspend request.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
/* Restore the generic timer context */
|
||||||
|
tsp_generic_timer_restore();
|
||||||
|
|
||||||
|
/* Update this cpu's statistics */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
tsp_stats[linear_id].cpu_resume_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
|
||||||
|
read_mpidr(), max_off_pwrlvl);
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
|
||||||
|
read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count,
|
||||||
|
tsp_stats[linear_id].cpu_resume_count);
|
||||||
|
/* Indicate to the SPD that we have completed this request */
|
||||||
|
return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* TSP fast smc handler. The secure monitor jumps to this function by
|
||||||
|
* doing the ERET after populating X0-X7 registers. The arguments are received
|
||||||
|
* in the function arguments in order. Once the service is rendered, this
|
||||||
|
* function returns to Secure Monitor by raising SMC.
|
||||||
|
******************************************************************************/
|
||||||
|
smc_args_t *tsp_smc_handler(uint64_t func,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7)
|
||||||
|
{
|
||||||
|
uint128_t service_args;
|
||||||
|
uint64_t service_arg0;
|
||||||
|
uint64_t service_arg1;
|
||||||
|
uint64_t results[2];
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
u_register_t dit;
|
||||||
|
|
||||||
|
/* Update this cpu's statistics */
|
||||||
|
tsp_stats[linear_id].smc_count++;
|
||||||
|
tsp_stats[linear_id].eret_count++;
|
||||||
|
|
||||||
|
INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(),
|
||||||
|
((func >> 31) & 1) == 1 ? "fast" : "yielding",
|
||||||
|
func);
|
||||||
|
INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
|
||||||
|
tsp_stats[linear_id].smc_count,
|
||||||
|
tsp_stats[linear_id].eret_count);
|
||||||
|
|
||||||
|
/* Render secure services and obtain results here */
|
||||||
|
results[0] = arg1;
|
||||||
|
results[1] = arg2;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Request a service back from dispatcher/secure monitor.
|
||||||
|
* This call returns and thereafter resumes execution.
|
||||||
|
*/
|
||||||
|
service_args = tsp_get_magic();
|
||||||
|
service_arg0 = (uint64_t)service_args;
|
||||||
|
service_arg1 = (uint64_t)(service_args >> 64U);
|
||||||
|
|
||||||
|
#if CTX_INCLUDE_MTE_REGS
|
||||||
|
/*
|
||||||
|
* Write a dummy value to an MTE register, to simulate usage in the
|
||||||
|
* secure world
|
||||||
|
*/
|
||||||
|
write_gcr_el1(0x99);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Determine the function to perform based on the function ID */
|
||||||
|
switch (TSP_BARE_FID(func)) {
|
||||||
|
case TSP_ADD:
|
||||||
|
results[0] += service_arg0;
|
||||||
|
results[1] += service_arg1;
|
||||||
|
break;
|
||||||
|
case TSP_SUB:
|
||||||
|
results[0] -= service_arg0;
|
||||||
|
results[1] -= service_arg1;
|
||||||
|
break;
|
||||||
|
case TSP_MUL:
|
||||||
|
results[0] *= service_arg0;
|
||||||
|
results[1] *= service_arg1;
|
||||||
|
break;
|
||||||
|
case TSP_DIV:
|
||||||
|
results[0] /= service_arg0 ? service_arg0 : 1;
|
||||||
|
results[1] /= service_arg1 ? service_arg1 : 1;
|
||||||
|
break;
|
||||||
|
case TSP_CHECK_DIT:
|
||||||
|
if (!is_armv8_4_dit_present()) {
|
||||||
|
ERROR("DIT not supported\n");
|
||||||
|
results[0] = 0;
|
||||||
|
results[1] = 0xffff;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
dit = read_dit();
|
||||||
|
results[0] = dit == service_arg0;
|
||||||
|
results[1] = dit;
|
||||||
|
/* Toggle the dit bit */
|
||||||
|
write_dit(service_arg0 != 0U ? 0 : DIT_BIT);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return set_smc_args(func, 0,
|
||||||
|
results[0],
|
||||||
|
results[1],
|
||||||
|
0, 0, 0, 0);
|
||||||
|
}
|
||||||
145
arm-trusted-firmware/bl32/tsp/tsp_private.h
Normal file
145
arm-trusted-firmware/bl32/tsp/tsp_private.h
Normal file
@@ -0,0 +1,145 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef TSP_PRIVATE_H
|
||||||
|
#define TSP_PRIVATE_H
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* The TSP memory footprint starts at address BL32_BASE and ends with the
|
||||||
|
* linker symbol __BL32_END__. Use these addresses to compute the TSP image
|
||||||
|
* size.
|
||||||
|
******************************************************************************/
|
||||||
|
#define BL32_TOTAL_LIMIT BL32_END
|
||||||
|
#define BL32_TOTAL_SIZE (BL32_TOTAL_LIMIT - (unsigned long) BL32_BASE)
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLER__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <bl32/tsp/tsp.h>
|
||||||
|
#include <lib/cassert.h>
|
||||||
|
#include <lib/spinlock.h>
|
||||||
|
#include <smccc_helpers.h>
|
||||||
|
|
||||||
|
typedef struct work_statistics {
|
||||||
|
/* Number of s-el1 interrupts on this cpu */
|
||||||
|
uint32_t sel1_intr_count;
|
||||||
|
/* Number of non s-el1 interrupts on this cpu which preempted TSP */
|
||||||
|
uint32_t preempt_intr_count;
|
||||||
|
/* Number of sync s-el1 interrupts on this cpu */
|
||||||
|
uint32_t sync_sel1_intr_count;
|
||||||
|
/* Number of s-el1 interrupts returns on this cpu */
|
||||||
|
uint32_t sync_sel1_intr_ret_count;
|
||||||
|
uint32_t smc_count; /* Number of returns on this cpu */
|
||||||
|
uint32_t eret_count; /* Number of entries on this cpu */
|
||||||
|
uint32_t cpu_on_count; /* Number of cpu on requests */
|
||||||
|
uint32_t cpu_off_count; /* Number of cpu off requests */
|
||||||
|
uint32_t cpu_suspend_count; /* Number of cpu suspend requests */
|
||||||
|
uint32_t cpu_resume_count; /* Number of cpu resume requests */
|
||||||
|
} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t;
|
||||||
|
|
||||||
|
/* Macros to access members of the above structure using their offsets */
|
||||||
|
#define read_sp_arg(args, offset) ((args)->_regs[offset >> 3])
|
||||||
|
#define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \
|
||||||
|
= val)
|
||||||
|
|
||||||
|
uint128_t tsp_get_magic(void);
|
||||||
|
|
||||||
|
smc_args_t *set_smc_args(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7);
|
||||||
|
smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7);
|
||||||
|
smc_args_t *tsp_cpu_suspend_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7);
|
||||||
|
smc_args_t *tsp_cpu_on_main(void);
|
||||||
|
smc_args_t *tsp_cpu_off_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7);
|
||||||
|
|
||||||
|
/* Generic Timer functions */
|
||||||
|
void tsp_generic_timer_start(void);
|
||||||
|
void tsp_generic_timer_handler(void);
|
||||||
|
void tsp_generic_timer_stop(void);
|
||||||
|
void tsp_generic_timer_save(void);
|
||||||
|
void tsp_generic_timer_restore(void);
|
||||||
|
|
||||||
|
/* S-EL1 interrupt management functions */
|
||||||
|
void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
|
||||||
|
|
||||||
|
|
||||||
|
/* Data structure to keep track of TSP statistics */
|
||||||
|
extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
|
||||||
|
|
||||||
|
/* Vector table of jumps */
|
||||||
|
extern tsp_vectors_t tsp_vector_table;
|
||||||
|
|
||||||
|
/* functions */
|
||||||
|
int32_t tsp_common_int_handler(void);
|
||||||
|
int32_t tsp_handle_preemption(void);
|
||||||
|
|
||||||
|
smc_args_t *tsp_abort_smc_handler(uint64_t func,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7);
|
||||||
|
|
||||||
|
smc_args_t *tsp_smc_handler(uint64_t func,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7);
|
||||||
|
|
||||||
|
smc_args_t *tsp_system_reset_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7);
|
||||||
|
|
||||||
|
smc_args_t *tsp_system_off_main(uint64_t arg0,
|
||||||
|
uint64_t arg1,
|
||||||
|
uint64_t arg2,
|
||||||
|
uint64_t arg3,
|
||||||
|
uint64_t arg4,
|
||||||
|
uint64_t arg5,
|
||||||
|
uint64_t arg6,
|
||||||
|
uint64_t arg7);
|
||||||
|
|
||||||
|
uint64_t tsp_main(void);
|
||||||
|
#endif /* __ASSEMBLER__ */
|
||||||
|
|
||||||
|
#endif /* TSP_PRIVATE_H */
|
||||||
91
arm-trusted-firmware/bl32/tsp/tsp_timer.c
Normal file
91
arm-trusted-firmware/bl32/tsp/tsp_timer.c
Normal file
@@ -0,0 +1,91 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
#include "tsp_private.h"
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Data structure to keep track of per-cpu secure generic timer context across
|
||||||
|
* power management operations.
|
||||||
|
******************************************************************************/
|
||||||
|
typedef struct timer_context {
|
||||||
|
uint64_t cval;
|
||||||
|
uint32_t ctl;
|
||||||
|
} timer_context_t;
|
||||||
|
|
||||||
|
static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT];
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function initializes the generic timer to fire every 0.5 second
|
||||||
|
******************************************************************************/
|
||||||
|
void tsp_generic_timer_start(void)
|
||||||
|
{
|
||||||
|
uint64_t cval;
|
||||||
|
uint32_t ctl = 0;
|
||||||
|
|
||||||
|
/* The timer will fire every 0.5 second */
|
||||||
|
cval = read_cntpct_el0() + (read_cntfrq_el0() >> 1);
|
||||||
|
write_cntps_cval_el1(cval);
|
||||||
|
|
||||||
|
/* Enable the secure physical timer */
|
||||||
|
set_cntp_ctl_enable(ctl);
|
||||||
|
write_cntps_ctl_el1(ctl);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function deasserts the timer interrupt and sets it up again
|
||||||
|
******************************************************************************/
|
||||||
|
void tsp_generic_timer_handler(void)
|
||||||
|
{
|
||||||
|
/* Ensure that the timer did assert the interrupt */
|
||||||
|
assert(get_cntp_ctl_istatus(read_cntps_ctl_el1()));
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Disable the timer and reprogram it. The barriers ensure that there is
|
||||||
|
* no reordering of instructions around the reprogramming code.
|
||||||
|
*/
|
||||||
|
isb();
|
||||||
|
write_cntps_ctl_el1(0);
|
||||||
|
tsp_generic_timer_start();
|
||||||
|
isb();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function deasserts the timer interrupt prior to cpu power down
|
||||||
|
******************************************************************************/
|
||||||
|
void tsp_generic_timer_stop(void)
|
||||||
|
{
|
||||||
|
/* Disable the timer */
|
||||||
|
write_cntps_ctl_el1(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function saves the timer context prior to cpu suspension
|
||||||
|
******************************************************************************/
|
||||||
|
void tsp_generic_timer_save(void)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
pcpu_timer_context[linear_id].cval = read_cntps_cval_el1();
|
||||||
|
pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1();
|
||||||
|
flush_dcache_range((uint64_t) &pcpu_timer_context[linear_id],
|
||||||
|
sizeof(pcpu_timer_context[linear_id]));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function restores the timer context post cpu resumption
|
||||||
|
******************************************************************************/
|
||||||
|
void tsp_generic_timer_restore(void)
|
||||||
|
{
|
||||||
|
uint32_t linear_id = plat_my_core_pos();
|
||||||
|
|
||||||
|
write_cntps_cval_el1(pcpu_timer_context[linear_id].cval);
|
||||||
|
write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl);
|
||||||
|
}
|
||||||
1289
arm-trusted-firmware/changelog.yaml
Normal file
1289
arm-trusted-firmware/changelog.yaml
Normal file
File diff suppressed because it is too large
Load Diff
239
arm-trusted-firmware/common/aarch32/debug.S
Normal file
239
arm-trusted-firmware/common/aarch32/debug.S
Normal file
@@ -0,0 +1,239 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/debug.h>
|
||||||
|
|
||||||
|
.globl asm_print_str
|
||||||
|
.globl asm_print_hex
|
||||||
|
.globl asm_print_hex_bits
|
||||||
|
.globl asm_assert
|
||||||
|
.globl do_panic
|
||||||
|
.globl report_exception
|
||||||
|
.globl report_prefetch_abort
|
||||||
|
.globl report_data_abort
|
||||||
|
|
||||||
|
/* Since the max decimal input number is 65536 */
|
||||||
|
#define MAX_DEC_DIVISOR 10000
|
||||||
|
/* The offset to add to get ascii for numerals '0 - 9' */
|
||||||
|
#define ASCII_OFFSET_NUM '0'
|
||||||
|
|
||||||
|
#if ENABLE_ASSERTIONS
|
||||||
|
.section .rodata.assert_str, "aS"
|
||||||
|
assert_msg1:
|
||||||
|
.asciz "ASSERT: File "
|
||||||
|
assert_msg2:
|
||||||
|
#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
|
||||||
|
/******************************************************************
|
||||||
|
* Virtualization comes with the UDIV/SDIV instructions. If missing
|
||||||
|
* write file line number in hexadecimal format.
|
||||||
|
******************************************************************/
|
||||||
|
.asciz " Line 0x"
|
||||||
|
#else
|
||||||
|
.asciz " Line "
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This macro is intended to be used to print the
|
||||||
|
* line number in decimal. Used by asm_assert macro.
|
||||||
|
* The max number expected is 65536.
|
||||||
|
* In: r4 = the decimal to print.
|
||||||
|
* Clobber: lr, r0, r1, r2, r5, r6
|
||||||
|
*/
|
||||||
|
.macro asm_print_line_dec
|
||||||
|
mov r6, #10 /* Divide by 10 after every loop iteration */
|
||||||
|
ldr r5, =MAX_DEC_DIVISOR
|
||||||
|
dec_print_loop:
|
||||||
|
udiv r0, r4, r5 /* Get the quotient */
|
||||||
|
mls r4, r0, r5, r4 /* Find the remainder */
|
||||||
|
add r0, r0, #ASCII_OFFSET_NUM /* Convert to ascii */
|
||||||
|
bl plat_crash_console_putc
|
||||||
|
udiv r5, r5, r6 /* Reduce divisor */
|
||||||
|
cmp r5, #0
|
||||||
|
bne dec_print_loop
|
||||||
|
.endm
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------------
|
||||||
|
* Assertion support in assembly.
|
||||||
|
* The below function helps to support assertions in assembly where we do not
|
||||||
|
* have a C runtime stack. Arguments to the function are :
|
||||||
|
* r0 - File name
|
||||||
|
* r1 - Line no
|
||||||
|
* Clobber list : lr, r0 - r6
|
||||||
|
* ---------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
func asm_assert
|
||||||
|
#if LOG_LEVEL >= LOG_LEVEL_INFO
|
||||||
|
/*
|
||||||
|
* Only print the output if LOG_LEVEL is higher or equal to
|
||||||
|
* LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
|
||||||
|
*/
|
||||||
|
/* Stash the parameters already in r0 and r1 */
|
||||||
|
mov r5, r0
|
||||||
|
mov r6, r1
|
||||||
|
|
||||||
|
/* Ensure the console is initialized */
|
||||||
|
bl plat_crash_console_init
|
||||||
|
|
||||||
|
/* Check if the console is initialized */
|
||||||
|
cmp r0, #0
|
||||||
|
beq _assert_loop
|
||||||
|
|
||||||
|
/* The console is initialized */
|
||||||
|
ldr r4, =assert_msg1
|
||||||
|
bl asm_print_str
|
||||||
|
mov r4, r5
|
||||||
|
bl asm_print_str
|
||||||
|
ldr r4, =assert_msg2
|
||||||
|
bl asm_print_str
|
||||||
|
|
||||||
|
/* Check if line number higher than max permitted */
|
||||||
|
ldr r4, =~0xffff
|
||||||
|
tst r6, r4
|
||||||
|
bne _assert_loop
|
||||||
|
mov r4, r6
|
||||||
|
|
||||||
|
#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
|
||||||
|
/******************************************************************
|
||||||
|
* Virtualization comes with the UDIV/SDIV instructions. If missing
|
||||||
|
* write file line number in hexadecimal format.
|
||||||
|
******************************************************************/
|
||||||
|
bl asm_print_hex
|
||||||
|
#else
|
||||||
|
asm_print_line_dec
|
||||||
|
#endif
|
||||||
|
bl plat_crash_console_flush
|
||||||
|
_assert_loop:
|
||||||
|
#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc asm_assert
|
||||||
|
#endif /* ENABLE_ASSERTIONS */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function prints a string from address in r4
|
||||||
|
* Clobber: lr, r0 - r4
|
||||||
|
*/
|
||||||
|
func asm_print_str
|
||||||
|
mov r3, lr
|
||||||
|
1:
|
||||||
|
ldrb r0, [r4], #0x1
|
||||||
|
cmp r0, #0
|
||||||
|
beq 2f
|
||||||
|
bl plat_crash_console_putc
|
||||||
|
b 1b
|
||||||
|
2:
|
||||||
|
bx r3
|
||||||
|
endfunc asm_print_str
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function prints a hexadecimal number in r4.
|
||||||
|
* In: r4 = the hexadecimal to print.
|
||||||
|
* Clobber: lr, r0 - r3, r5
|
||||||
|
*/
|
||||||
|
func asm_print_hex
|
||||||
|
mov r5, #32 /* No of bits to convert to ascii */
|
||||||
|
|
||||||
|
/* Convert to ascii number of bits in r5 */
|
||||||
|
asm_print_hex_bits:
|
||||||
|
mov r3, lr
|
||||||
|
1:
|
||||||
|
sub r5, r5, #4
|
||||||
|
lsr r0, r4, r5
|
||||||
|
and r0, r0, #0xf
|
||||||
|
cmp r0, #0xa
|
||||||
|
blo 2f
|
||||||
|
/* Add by 0x27 in addition to ASCII_OFFSET_NUM
|
||||||
|
* to get ascii for characters 'a - f'.
|
||||||
|
*/
|
||||||
|
add r0, r0, #0x27
|
||||||
|
2:
|
||||||
|
add r0, r0, #ASCII_OFFSET_NUM
|
||||||
|
bl plat_crash_console_putc
|
||||||
|
cmp r5, #0
|
||||||
|
bne 1b
|
||||||
|
bx r3
|
||||||
|
endfunc asm_print_hex
|
||||||
|
|
||||||
|
/***********************************************************
|
||||||
|
* The common implementation of do_panic for all BL stages
|
||||||
|
***********************************************************/
|
||||||
|
|
||||||
|
.section .rodata.panic_str, "aS"
|
||||||
|
panic_msg: .asciz "PANIC at PC : 0x"
|
||||||
|
panic_end: .asciz "\r\n"
|
||||||
|
|
||||||
|
func do_panic
|
||||||
|
/* Have LR copy point to PC at the time of panic */
|
||||||
|
sub r6, lr, #4
|
||||||
|
|
||||||
|
/* Initialize crash console and verify success */
|
||||||
|
bl plat_crash_console_init
|
||||||
|
|
||||||
|
/* Check if the console is initialized */
|
||||||
|
cmp r0, #0
|
||||||
|
beq _panic_handler
|
||||||
|
|
||||||
|
/* The console is initialized */
|
||||||
|
ldr r4, =panic_msg
|
||||||
|
bl asm_print_str
|
||||||
|
|
||||||
|
/* Print LR in hex */
|
||||||
|
mov r4, r6
|
||||||
|
bl asm_print_hex
|
||||||
|
|
||||||
|
/* Print new line */
|
||||||
|
ldr r4, =panic_end
|
||||||
|
bl asm_print_str
|
||||||
|
|
||||||
|
bl plat_crash_console_flush
|
||||||
|
|
||||||
|
_panic_handler:
|
||||||
|
mov lr, r6
|
||||||
|
b plat_panic_handler
|
||||||
|
endfunc do_panic
|
||||||
|
|
||||||
|
/***********************************************************
|
||||||
|
* This function is called from the vector table for
|
||||||
|
* unhandled exceptions. It reads the current mode and
|
||||||
|
* passes it to platform.
|
||||||
|
***********************************************************/
|
||||||
|
func report_exception
|
||||||
|
mrs r0, cpsr
|
||||||
|
and r0, #MODE32_MASK
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc report_exception
|
||||||
|
|
||||||
|
/***********************************************************
|
||||||
|
* This function is called from the vector table for
|
||||||
|
* unhandled exceptions. The lr_abt is given as an
|
||||||
|
* argument to platform handler.
|
||||||
|
***********************************************************/
|
||||||
|
func report_prefetch_abort
|
||||||
|
#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
|
||||||
|
b report_exception
|
||||||
|
#else
|
||||||
|
mrs r0, lr_abt
|
||||||
|
bl plat_report_prefetch_abort
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
#endif
|
||||||
|
endfunc report_prefetch_abort
|
||||||
|
|
||||||
|
/***********************************************************
|
||||||
|
* This function is called from the vector table for
|
||||||
|
* unhandled exceptions. The lr_abt is given as an
|
||||||
|
* argument to platform handler.
|
||||||
|
***********************************************************/
|
||||||
|
func report_data_abort
|
||||||
|
#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
|
||||||
|
b report_exception
|
||||||
|
#else
|
||||||
|
mrs r0, lr_abt
|
||||||
|
bl plat_report_data_abort
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
#endif
|
||||||
|
endfunc report_data_abort
|
||||||
221
arm-trusted-firmware/common/aarch64/debug.S
Normal file
221
arm-trusted-firmware/common/aarch64/debug.S
Normal file
@@ -0,0 +1,221 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/debug.h>
|
||||||
|
|
||||||
|
.globl asm_print_str
|
||||||
|
.globl asm_print_hex
|
||||||
|
.globl asm_print_hex_bits
|
||||||
|
.globl asm_print_newline
|
||||||
|
.globl asm_assert
|
||||||
|
.globl do_panic
|
||||||
|
|
||||||
|
/* Since the max decimal input number is 65536 */
|
||||||
|
#define MAX_DEC_DIVISOR 10000
|
||||||
|
/* The offset to add to get ascii for numerals '0 - 9' */
|
||||||
|
#define ASCII_OFFSET_NUM 0x30
|
||||||
|
|
||||||
|
#if ENABLE_ASSERTIONS
|
||||||
|
.section .rodata.assert_str, "aS"
|
||||||
|
assert_msg1:
|
||||||
|
.asciz "ASSERT: File "
|
||||||
|
assert_msg2:
|
||||||
|
.asciz " Line "
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This macro is intended to be used to print the
|
||||||
|
* line number in decimal. Used by asm_assert macro.
|
||||||
|
* The max number expected is 65536.
|
||||||
|
* In: x4 = the decimal to print.
|
||||||
|
* Clobber: x30, x0, x1, x2, x5, x6
|
||||||
|
*/
|
||||||
|
.macro asm_print_line_dec
|
||||||
|
mov x6, #10 /* Divide by 10 after every loop iteration */
|
||||||
|
mov x5, #MAX_DEC_DIVISOR
|
||||||
|
dec_print_loop:
|
||||||
|
udiv x0, x4, x5 /* Get the quotient */
|
||||||
|
msub x4, x0, x5, x4 /* Find the remainder */
|
||||||
|
add x0, x0, #ASCII_OFFSET_NUM /* Convert to ascii */
|
||||||
|
bl plat_crash_console_putc
|
||||||
|
udiv x5, x5, x6 /* Reduce divisor */
|
||||||
|
cbnz x5, dec_print_loop
|
||||||
|
.endm
|
||||||
|
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------------
|
||||||
|
* Assertion support in assembly.
|
||||||
|
* The below function helps to support assertions in assembly where we do not
|
||||||
|
* have a C runtime stack. Arguments to the function are :
|
||||||
|
* x0 - File name
|
||||||
|
* x1 - Line no
|
||||||
|
* Clobber list : x30, x0, x1, x2, x3, x4, x5, x6.
|
||||||
|
* ---------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
func asm_assert
|
||||||
|
#if LOG_LEVEL >= LOG_LEVEL_INFO
|
||||||
|
/*
|
||||||
|
* Only print the output if LOG_LEVEL is higher or equal to
|
||||||
|
* LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
|
||||||
|
*/
|
||||||
|
mov x5, x0
|
||||||
|
mov x6, x1
|
||||||
|
|
||||||
|
/* Ensure the console is initialized */
|
||||||
|
bl plat_crash_console_init
|
||||||
|
|
||||||
|
/* Check if the console is initialized */
|
||||||
|
cbz x0, _assert_loop
|
||||||
|
|
||||||
|
/* The console is initialized */
|
||||||
|
adr x4, assert_msg1
|
||||||
|
bl asm_print_str
|
||||||
|
mov x4, x5
|
||||||
|
bl asm_print_str
|
||||||
|
adr x4, assert_msg2
|
||||||
|
bl asm_print_str
|
||||||
|
|
||||||
|
/* Check if line number higher than max permitted */
|
||||||
|
tst x6, #~0xffff
|
||||||
|
b.ne _assert_loop
|
||||||
|
mov x4, x6
|
||||||
|
asm_print_line_dec
|
||||||
|
bl plat_crash_console_flush
|
||||||
|
_assert_loop:
|
||||||
|
#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
endfunc asm_assert
|
||||||
|
#endif /* ENABLE_ASSERTIONS */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function prints a string from address in x4.
|
||||||
|
* In: x4 = pointer to string.
|
||||||
|
* Clobber: x30, x0, x1, x2, x3
|
||||||
|
*/
|
||||||
|
func asm_print_str
|
||||||
|
mov x3, x30
|
||||||
|
1:
|
||||||
|
ldrb w0, [x4], #0x1
|
||||||
|
cbz x0, 2f
|
||||||
|
bl plat_crash_console_putc
|
||||||
|
b 1b
|
||||||
|
2:
|
||||||
|
ret x3
|
||||||
|
endfunc asm_print_str
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function prints a hexadecimal number in x4.
|
||||||
|
* In: x4 = the hexadecimal to print.
|
||||||
|
* Clobber: x30, x0 - x3, x5
|
||||||
|
*/
|
||||||
|
func asm_print_hex
|
||||||
|
mov x5, #64 /* No of bits to convert to ascii */
|
||||||
|
|
||||||
|
/* Convert to ascii number of bits in x5 */
|
||||||
|
asm_print_hex_bits:
|
||||||
|
mov x3, x30
|
||||||
|
1:
|
||||||
|
sub x5, x5, #4
|
||||||
|
lsrv x0, x4, x5
|
||||||
|
and x0, x0, #0xf
|
||||||
|
cmp x0, #0xA
|
||||||
|
b.lo 2f
|
||||||
|
/* Add by 0x27 in addition to ASCII_OFFSET_NUM
|
||||||
|
* to get ascii for characters 'a - f'.
|
||||||
|
*/
|
||||||
|
add x0, x0, #0x27
|
||||||
|
2:
|
||||||
|
add x0, x0, #ASCII_OFFSET_NUM
|
||||||
|
bl plat_crash_console_putc
|
||||||
|
cbnz x5, 1b
|
||||||
|
ret x3
|
||||||
|
endfunc asm_print_hex
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Helper function to print newline to console
|
||||||
|
* Clobber: x0
|
||||||
|
*/
|
||||||
|
func asm_print_newline
|
||||||
|
mov x0, '\n'
|
||||||
|
b plat_crash_console_putc
|
||||||
|
endfunc asm_print_newline
|
||||||
|
|
||||||
|
/***********************************************************
|
||||||
|
* The common implementation of do_panic for all BL stages
|
||||||
|
***********************************************************/
|
||||||
|
|
||||||
|
.section .rodata.panic_str, "aS"
|
||||||
|
panic_msg: .asciz "PANIC at PC : 0x"
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------------
|
||||||
|
* do_panic assumes that it is invoked from a C Runtime Environment ie a
|
||||||
|
* valid stack exists. This call will not return.
|
||||||
|
* Clobber list : if CRASH_REPORTING is not enabled then x30, x0 - x6
|
||||||
|
* ---------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* This is for the non el3 BL stages to compile through */
|
||||||
|
.weak el3_panic
|
||||||
|
.weak elx_panic
|
||||||
|
|
||||||
|
func do_panic
|
||||||
|
#if CRASH_REPORTING
|
||||||
|
str x0, [sp, #-0x10]!
|
||||||
|
mrs x0, currentel
|
||||||
|
ubfx x0, x0, #MODE_EL_SHIFT, #MODE_EL_WIDTH
|
||||||
|
cmp x0, #MODE_EL3
|
||||||
|
#if !HANDLE_EA_EL3_FIRST_NS
|
||||||
|
ldr x0, [sp], #0x10
|
||||||
|
b.eq el3_panic
|
||||||
|
#else
|
||||||
|
b.ne to_panic_common
|
||||||
|
|
||||||
|
/* Check EL the exception taken from */
|
||||||
|
mrs x0, spsr_el3
|
||||||
|
ubfx x0, x0, #SPSR_EL_SHIFT, #SPSR_EL_WIDTH
|
||||||
|
cmp x0, #MODE_EL3
|
||||||
|
b.ne elx_panic
|
||||||
|
ldr x0, [sp], #0x10
|
||||||
|
b el3_panic
|
||||||
|
|
||||||
|
to_panic_common:
|
||||||
|
ldr x0, [sp], #0x10
|
||||||
|
#endif /* HANDLE_EA_EL3_FIRST_NS */
|
||||||
|
#endif /* CRASH_REPORTING */
|
||||||
|
|
||||||
|
panic_common:
|
||||||
|
/*
|
||||||
|
* el3_panic will be redefined by the BL31
|
||||||
|
* crash reporting mechanism (if enabled)
|
||||||
|
*/
|
||||||
|
el3_panic:
|
||||||
|
mov x6, x30
|
||||||
|
bl plat_crash_console_init
|
||||||
|
|
||||||
|
/* Check if the console is initialized */
|
||||||
|
cbz x0, _panic_handler
|
||||||
|
|
||||||
|
/* The console is initialized */
|
||||||
|
adr x4, panic_msg
|
||||||
|
bl asm_print_str
|
||||||
|
mov x4, x6
|
||||||
|
|
||||||
|
/* The panic location is lr -4 */
|
||||||
|
sub x4, x4, #4
|
||||||
|
bl asm_print_hex
|
||||||
|
|
||||||
|
/* Print new line */
|
||||||
|
bl asm_print_newline
|
||||||
|
|
||||||
|
bl plat_crash_console_flush
|
||||||
|
|
||||||
|
_panic_handler:
|
||||||
|
/* Pass to plat_panic_handler the address from where el3_panic was
|
||||||
|
* called, not the address of the call from el3_panic. */
|
||||||
|
mov x30, x6
|
||||||
|
b plat_panic_handler
|
||||||
|
endfunc do_panic
|
||||||
129
arm-trusted-firmware/common/aarch64/early_exceptions.S
Normal file
129
arm-trusted-firmware/common/aarch64/early_exceptions.S
Normal file
@@ -0,0 +1,129 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------------------------
|
||||||
|
* Very simple stackless exception handlers used by BL2 and BL31 stages.
|
||||||
|
* BL31 uses them before stacks are setup. BL2 uses them throughout.
|
||||||
|
* -----------------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
.globl early_exceptions
|
||||||
|
|
||||||
|
vector_base early_exceptions
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Current EL with SP0 : 0x0 - 0x200
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionSP0
|
||||||
|
mov x0, #SYNC_EXCEPTION_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionSP0
|
||||||
|
|
||||||
|
vector_entry IrqSP0
|
||||||
|
mov x0, #IRQ_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqSP0
|
||||||
|
|
||||||
|
vector_entry FiqSP0
|
||||||
|
mov x0, #FIQ_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqSP0
|
||||||
|
|
||||||
|
vector_entry SErrorSP0
|
||||||
|
mov x0, #SERROR_SP_EL0
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorSP0
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Current EL with SPx: 0x200 - 0x400
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionSPx
|
||||||
|
mov x0, #SYNC_EXCEPTION_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionSPx
|
||||||
|
|
||||||
|
vector_entry IrqSPx
|
||||||
|
mov x0, #IRQ_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqSPx
|
||||||
|
|
||||||
|
vector_entry FiqSPx
|
||||||
|
mov x0, #FIQ_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqSPx
|
||||||
|
|
||||||
|
vector_entry SErrorSPx
|
||||||
|
mov x0, #SERROR_SP_ELX
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorSPx
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Lower EL using AArch64 : 0x400 - 0x600
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionA64
|
||||||
|
mov x0, #SYNC_EXCEPTION_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionA64
|
||||||
|
|
||||||
|
vector_entry IrqA64
|
||||||
|
mov x0, #IRQ_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqA64
|
||||||
|
|
||||||
|
vector_entry FiqA64
|
||||||
|
mov x0, #FIQ_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqA64
|
||||||
|
|
||||||
|
vector_entry SErrorA64
|
||||||
|
mov x0, #SERROR_AARCH64
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorA64
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Lower EL using AArch32 : 0x600 - 0x800
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
vector_entry SynchronousExceptionA32
|
||||||
|
mov x0, #SYNC_EXCEPTION_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SynchronousExceptionA32
|
||||||
|
|
||||||
|
vector_entry IrqA32
|
||||||
|
mov x0, #IRQ_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry IrqA32
|
||||||
|
|
||||||
|
vector_entry FiqA32
|
||||||
|
mov x0, #FIQ_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry FiqA32
|
||||||
|
|
||||||
|
vector_entry SErrorA32
|
||||||
|
mov x0, #SERROR_AARCH32
|
||||||
|
bl plat_report_exception
|
||||||
|
no_ret plat_panic_handler
|
||||||
|
end_vector_entry SErrorA32
|
||||||
266
arm-trusted-firmware/common/backtrace/backtrace.c
Normal file
266
arm-trusted-firmware/common/backtrace/backtrace.c
Normal file
@@ -0,0 +1,266 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <drivers/console.h>
|
||||||
|
|
||||||
|
/* Maximum number of entries in the backtrace to display */
|
||||||
|
#define UNWIND_LIMIT 20U
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If -fno-omit-frame-pointer is used:
|
||||||
|
*
|
||||||
|
* - AArch64: The AAPCS defines the format of the frame records and mandates the
|
||||||
|
* usage of r29 as frame pointer.
|
||||||
|
*
|
||||||
|
* - AArch32: The format of the frame records is not defined in the AAPCS.
|
||||||
|
* However, at least GCC and Clang use the same format. When they are forced
|
||||||
|
* to only generate A32 code (with -marm), they use r11 as frame pointer and a
|
||||||
|
* similar format as in AArch64. If interworking with T32 is enabled, the
|
||||||
|
* frame pointer is r7 and the format is different. This is not supported by
|
||||||
|
* this implementation of backtrace, so it is needed to use -marm.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Frame records form a linked list in the stack */
|
||||||
|
struct frame_record {
|
||||||
|
/* Previous frame record in the list */
|
||||||
|
struct frame_record *parent;
|
||||||
|
/* Return address of the function at this level */
|
||||||
|
uintptr_t return_addr;
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline uintptr_t extract_address(uintptr_t address)
|
||||||
|
{
|
||||||
|
uintptr_t ret = address;
|
||||||
|
|
||||||
|
#if ENABLE_PAUTH
|
||||||
|
/*
|
||||||
|
* When pointer authentication is enabled, the LR value saved on the
|
||||||
|
* stack contains a PAC. It must be stripped to retrieve the return
|
||||||
|
* address.
|
||||||
|
*/
|
||||||
|
|
||||||
|
xpaci(ret);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Returns true if the address points to a virtual address that can be read at
|
||||||
|
* the current EL, false otherwise.
|
||||||
|
*/
|
||||||
|
#ifdef __aarch64__
|
||||||
|
static bool is_address_readable(uintptr_t address)
|
||||||
|
{
|
||||||
|
unsigned int el = get_current_el();
|
||||||
|
uintptr_t addr = extract_address(address);
|
||||||
|
|
||||||
|
if (el == 3U) {
|
||||||
|
ats1e3r(addr);
|
||||||
|
} else if (el == 2U) {
|
||||||
|
ats1e2r(addr);
|
||||||
|
} else {
|
||||||
|
AT(ats1e1r, addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
isb();
|
||||||
|
|
||||||
|
/* If PAR.F == 1 the address translation was aborted. */
|
||||||
|
if ((read_par_el1() & PAR_F_MASK) != 0U)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
#else /* !__aarch64__ */
|
||||||
|
static bool is_address_readable(uintptr_t addr)
|
||||||
|
{
|
||||||
|
unsigned int el = get_current_el();
|
||||||
|
|
||||||
|
if (el == 3U) {
|
||||||
|
write_ats1cpr(addr);
|
||||||
|
} else if (el == 2U) {
|
||||||
|
write_ats1hr(addr);
|
||||||
|
} else {
|
||||||
|
write_ats1cpr(addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
isb();
|
||||||
|
|
||||||
|
/* If PAR.F == 1 the address translation was aborted. */
|
||||||
|
if ((read64_par() & PAR_F_MASK) != 0U)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
#endif /* __aarch64__ */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Returns true if all the bytes in a given object are in mapped memory and an
|
||||||
|
* LDR using this pointer would succeed, false otherwise.
|
||||||
|
*/
|
||||||
|
static bool is_valid_object(uintptr_t addr, size_t size)
|
||||||
|
{
|
||||||
|
assert(size > 0U);
|
||||||
|
|
||||||
|
if (addr == 0U)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
/* Detect overflows */
|
||||||
|
if ((addr + size) < addr)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
/* A pointer not aligned properly could trigger an alignment fault. */
|
||||||
|
if ((addr & (sizeof(uintptr_t) - 1U)) != 0U)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
/* Check that all the object is readable */
|
||||||
|
for (size_t i = 0; i < size; i++) {
|
||||||
|
if (!is_address_readable(addr + i))
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Returns true if the specified address is correctly aligned and points to a
|
||||||
|
* valid memory region.
|
||||||
|
*/
|
||||||
|
static bool is_valid_jump_address(uintptr_t addr)
|
||||||
|
{
|
||||||
|
if (addr == 0U)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
/* Check alignment. Both A64 and A32 use 32-bit opcodes */
|
||||||
|
if ((addr & (sizeof(uint32_t) - 1U)) != 0U)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
if (!is_address_readable(addr))
|
||||||
|
return false;
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Returns true if the pointer points at a valid frame record, false otherwise.
|
||||||
|
*/
|
||||||
|
static bool is_valid_frame_record(struct frame_record *fr)
|
||||||
|
{
|
||||||
|
return is_valid_object((uintptr_t)fr, sizeof(struct frame_record));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Adjust the frame-pointer-register value by 4 bytes on AArch32 to have the
|
||||||
|
* same layout as AArch64.
|
||||||
|
*/
|
||||||
|
static struct frame_record *adjust_frame_record(struct frame_record *fr)
|
||||||
|
{
|
||||||
|
#ifdef __aarch64__
|
||||||
|
return fr;
|
||||||
|
#else
|
||||||
|
return (struct frame_record *)((uintptr_t)fr - 4U);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
static void unwind_stack(struct frame_record *fr, uintptr_t current_pc,
|
||||||
|
uintptr_t link_register)
|
||||||
|
{
|
||||||
|
uintptr_t call_site;
|
||||||
|
static const char *backtrace_str = "%u: %s: 0x%lx\n";
|
||||||
|
const char *el_str = get_el_str(get_current_el());
|
||||||
|
|
||||||
|
if (!is_valid_frame_record(fr)) {
|
||||||
|
printf("ERROR: Corrupted frame pointer (frame record address = %p)\n",
|
||||||
|
fr);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
call_site = extract_address(fr->return_addr);
|
||||||
|
if (call_site != link_register) {
|
||||||
|
printf("ERROR: Corrupted stack (frame record address = %p)\n",
|
||||||
|
fr);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* The level 0 of the backtrace is the current backtrace function */
|
||||||
|
printf(backtrace_str, 0U, el_str, current_pc);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The last frame record pointer in the linked list at the beginning of
|
||||||
|
* the stack should be NULL unless stack is corrupted.
|
||||||
|
*/
|
||||||
|
for (unsigned int i = 1U; i < UNWIND_LIMIT; i++) {
|
||||||
|
/* If an invalid frame record is found, exit. */
|
||||||
|
if (!is_valid_frame_record(fr))
|
||||||
|
return;
|
||||||
|
/*
|
||||||
|
* A32 and A64 are fixed length so the address from where the
|
||||||
|
* call was made is the instruction before the return address,
|
||||||
|
* which is always 4 bytes before it.
|
||||||
|
*/
|
||||||
|
|
||||||
|
call_site = extract_address(fr->return_addr) - 4U;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If the address is invalid it means that the frame record is
|
||||||
|
* probably corrupted.
|
||||||
|
*/
|
||||||
|
if (!is_valid_jump_address(call_site))
|
||||||
|
return;
|
||||||
|
|
||||||
|
printf(backtrace_str, i, el_str, call_site);
|
||||||
|
|
||||||
|
fr = adjust_frame_record(fr->parent);
|
||||||
|
}
|
||||||
|
|
||||||
|
printf("ERROR: Max backtrace depth reached\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Display a backtrace. The cookie string parameter is displayed along the
|
||||||
|
* trace to help filter the log messages.
|
||||||
|
*
|
||||||
|
* Many things can prevent displaying the expected backtrace. For example,
|
||||||
|
* compiler optimizations can use a branch instead of branch with link when it
|
||||||
|
* detects a tail call. The backtrace level for this caller will not be
|
||||||
|
* displayed, as it does not appear in the call stack anymore. Also, assembly
|
||||||
|
* functions will not be displayed unless they setup AAPCS compliant frame
|
||||||
|
* records on AArch64 and compliant with GCC-specific frame record format on
|
||||||
|
* AArch32.
|
||||||
|
*
|
||||||
|
* Usage of the trace: addr2line can be used to map the addresses to function
|
||||||
|
* and source code location when given the ELF file compiled with debug
|
||||||
|
* information. The "-i" flag is highly recommended to improve display of
|
||||||
|
* inlined function. The *.dump files generated when building each image can
|
||||||
|
* also be used.
|
||||||
|
*
|
||||||
|
* WARNING: In case of corrupted stack, this function could display security
|
||||||
|
* sensitive information past the beginning of the stack so it must not be used
|
||||||
|
* in production build. This function is only compiled in when ENABLE_BACKTRACE
|
||||||
|
* is set to 1.
|
||||||
|
*/
|
||||||
|
void backtrace(const char *cookie)
|
||||||
|
{
|
||||||
|
uintptr_t return_address = (uintptr_t)__builtin_return_address(0U);
|
||||||
|
struct frame_record *fr = __builtin_frame_address(0U);
|
||||||
|
|
||||||
|
/* Printing the backtrace may crash the system, flush before starting */
|
||||||
|
console_flush();
|
||||||
|
|
||||||
|
fr = adjust_frame_record(fr);
|
||||||
|
|
||||||
|
printf("BACKTRACE: START: %s\n", cookie);
|
||||||
|
|
||||||
|
unwind_stack(fr, (uintptr_t)&backtrace, return_address);
|
||||||
|
|
||||||
|
printf("BACKTRACE: END: %s\n", cookie);
|
||||||
|
}
|
||||||
31
arm-trusted-firmware/common/backtrace/backtrace.mk
Normal file
31
arm-trusted-firmware/common/backtrace/backtrace.mk
Normal file
@@ -0,0 +1,31 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
|
||||||
|
# Enable backtrace by default in DEBUG AArch64 builds
|
||||||
|
ifeq (${ARCH},aarch32)
|
||||||
|
ENABLE_BACKTRACE := 0
|
||||||
|
else
|
||||||
|
ENABLE_BACKTRACE := ${DEBUG}
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ENABLE_BACKTRACE},1)
|
||||||
|
# Force the compiler to include the frame pointer
|
||||||
|
TF_CFLAGS += -fno-omit-frame-pointer
|
||||||
|
|
||||||
|
BL_COMMON_SOURCES += common/backtrace/backtrace.c
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq (${ARCH},aarch32)
|
||||||
|
ifeq (${ENABLE_BACKTRACE},1)
|
||||||
|
ifneq (${AARCH32_INSTRUCTION_SET},A32)
|
||||||
|
$(error Error: AARCH32_INSTRUCTION_SET=A32 is needed \
|
||||||
|
for ENABLE_BACKTRACE when compiling for AArch32.)
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(eval $(call assert_boolean,ENABLE_BACKTRACE))
|
||||||
|
$(eval $(call add_define,ENABLE_BACKTRACE))
|
||||||
280
arm-trusted-firmware/common/bl_common.c
Normal file
280
arm-trusted-firmware/common/bl_common.c
Normal file
@@ -0,0 +1,280 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <arch_features.h>
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <drivers/auth/auth_mod.h>
|
||||||
|
#include <drivers/io/io_storage.h>
|
||||||
|
#include <lib/utils.h>
|
||||||
|
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
#if TRUSTED_BOARD_BOOT
|
||||||
|
# ifdef DYN_DISABLE_AUTH
|
||||||
|
static int disable_auth;
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* API to dynamically disable authentication. Only meant for development
|
||||||
|
* systems. This is only invoked if DYN_DISABLE_AUTH is defined.
|
||||||
|
*****************************************************************************/
|
||||||
|
void dyn_disable_auth(void)
|
||||||
|
{
|
||||||
|
INFO("Disabling authentication of images dynamically\n");
|
||||||
|
disable_auth = 1;
|
||||||
|
}
|
||||||
|
# endif /* DYN_DISABLE_AUTH */
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* Function to determine whether the authentication is disabled dynamically.
|
||||||
|
*****************************************************************************/
|
||||||
|
static int dyn_is_auth_disabled(void)
|
||||||
|
{
|
||||||
|
# ifdef DYN_DISABLE_AUTH
|
||||||
|
return disable_auth;
|
||||||
|
# else
|
||||||
|
return 0;
|
||||||
|
# endif
|
||||||
|
}
|
||||||
|
#endif /* TRUSTED_BOARD_BOOT */
|
||||||
|
|
||||||
|
uintptr_t page_align(uintptr_t value, unsigned dir)
|
||||||
|
{
|
||||||
|
/* Round up the limit to the next page boundary */
|
||||||
|
if ((value & PAGE_SIZE_MASK) != 0U) {
|
||||||
|
value &= ~PAGE_SIZE_MASK;
|
||||||
|
if (dir == UP)
|
||||||
|
value += PAGE_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
return value;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Internal function to load an image at a specific address given
|
||||||
|
* an image ID and extents of free memory.
|
||||||
|
*
|
||||||
|
* If the load is successful then the image information is updated.
|
||||||
|
*
|
||||||
|
* Returns 0 on success, a negative error code otherwise.
|
||||||
|
******************************************************************************/
|
||||||
|
static int load_image(unsigned int image_id, image_info_t *image_data)
|
||||||
|
{
|
||||||
|
uintptr_t dev_handle;
|
||||||
|
uintptr_t image_handle;
|
||||||
|
uintptr_t image_spec;
|
||||||
|
uintptr_t image_base;
|
||||||
|
size_t image_size;
|
||||||
|
size_t bytes_read;
|
||||||
|
int io_result;
|
||||||
|
|
||||||
|
assert(image_data != NULL);
|
||||||
|
assert(image_data->h.version >= VERSION_2);
|
||||||
|
|
||||||
|
image_base = image_data->image_base;
|
||||||
|
|
||||||
|
/* Obtain a reference to the image by querying the platform layer */
|
||||||
|
io_result = plat_get_image_source(image_id, &dev_handle, &image_spec);
|
||||||
|
if (io_result != 0) {
|
||||||
|
WARN("Failed to obtain reference to image id=%u (%i)\n",
|
||||||
|
image_id, io_result);
|
||||||
|
return io_result;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Attempt to access the image */
|
||||||
|
io_result = io_open(dev_handle, image_spec, &image_handle);
|
||||||
|
if (io_result != 0) {
|
||||||
|
WARN("Failed to access image id=%u (%i)\n",
|
||||||
|
image_id, io_result);
|
||||||
|
return io_result;
|
||||||
|
}
|
||||||
|
|
||||||
|
INFO("Loading image id=%u at address 0x%lx\n", image_id, image_base);
|
||||||
|
|
||||||
|
/* Find the size of the image */
|
||||||
|
io_result = io_size(image_handle, &image_size);
|
||||||
|
if ((io_result != 0) || (image_size == 0U)) {
|
||||||
|
WARN("Failed to determine the size of the image id=%u (%i)\n",
|
||||||
|
image_id, io_result);
|
||||||
|
goto exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check that the image size to load is within limit */
|
||||||
|
if (image_size > image_data->image_max_size) {
|
||||||
|
WARN("Image id=%u size out of bounds\n", image_id);
|
||||||
|
io_result = -EFBIG;
|
||||||
|
goto exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* image_data->image_max_size is a uint32_t so image_size will always
|
||||||
|
* fit in image_data->image_size.
|
||||||
|
*/
|
||||||
|
image_data->image_size = (uint32_t)image_size;
|
||||||
|
|
||||||
|
/* We have enough space so load the image now */
|
||||||
|
/* TODO: Consider whether to try to recover/retry a partially successful read */
|
||||||
|
io_result = io_read(image_handle, image_base, image_size, &bytes_read);
|
||||||
|
if ((io_result != 0) || (bytes_read < image_size)) {
|
||||||
|
WARN("Failed to load image id=%u (%i)\n", image_id, io_result);
|
||||||
|
goto exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
INFO("Image id=%u loaded: 0x%lx - 0x%lx\n", image_id, image_base,
|
||||||
|
(uintptr_t)(image_base + image_size));
|
||||||
|
|
||||||
|
exit:
|
||||||
|
(void)io_close(image_handle);
|
||||||
|
/* Ignore improbable/unrecoverable error in 'close' */
|
||||||
|
|
||||||
|
/* TODO: Consider maintaining open device connection from this bootloader stage */
|
||||||
|
(void)io_dev_close(dev_handle);
|
||||||
|
/* Ignore improbable/unrecoverable error in 'dev_close' */
|
||||||
|
|
||||||
|
return io_result;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if TRUSTED_BOARD_BOOT
|
||||||
|
/*
|
||||||
|
* This function uses recursion to authenticate the parent images up to the root
|
||||||
|
* of trust.
|
||||||
|
*/
|
||||||
|
static int load_auth_image_recursive(unsigned int image_id,
|
||||||
|
image_info_t *image_data,
|
||||||
|
int is_parent_image)
|
||||||
|
{
|
||||||
|
int rc;
|
||||||
|
unsigned int parent_id;
|
||||||
|
|
||||||
|
/* Use recursion to authenticate parent images */
|
||||||
|
rc = auth_mod_get_parent_id(image_id, &parent_id);
|
||||||
|
if (rc == 0) {
|
||||||
|
rc = load_auth_image_recursive(parent_id, image_data, 1);
|
||||||
|
if (rc != 0) {
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Load the image */
|
||||||
|
rc = load_image(image_id, image_data);
|
||||||
|
if (rc != 0) {
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Authenticate it */
|
||||||
|
rc = auth_mod_verify_img(image_id,
|
||||||
|
(void *)image_data->image_base,
|
||||||
|
image_data->image_size);
|
||||||
|
if (rc != 0) {
|
||||||
|
/* Authentication error, zero memory and flush it right away. */
|
||||||
|
zero_normalmem((void *)image_data->image_base,
|
||||||
|
image_data->image_size);
|
||||||
|
flush_dcache_range(image_data->image_base,
|
||||||
|
image_data->image_size);
|
||||||
|
return -EAUTH;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif /* TRUSTED_BOARD_BOOT */
|
||||||
|
|
||||||
|
static int load_auth_image_internal(unsigned int image_id,
|
||||||
|
image_info_t *image_data)
|
||||||
|
{
|
||||||
|
#if TRUSTED_BOARD_BOOT
|
||||||
|
if (dyn_is_auth_disabled() == 0) {
|
||||||
|
return load_auth_image_recursive(image_id, image_data, 0);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return load_image(image_id, image_data);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Generic function to load and authenticate an image. The image is actually
|
||||||
|
* loaded by calling the 'load_image()' function. Therefore, it returns the
|
||||||
|
* same error codes if the loading operation failed, or -EAUTH if the
|
||||||
|
* authentication failed. In addition, this function uses recursion to
|
||||||
|
* authenticate the parent images up to the root of trust (if TBB is enabled).
|
||||||
|
******************************************************************************/
|
||||||
|
int load_auth_image(unsigned int image_id, image_info_t *image_data)
|
||||||
|
{
|
||||||
|
int err;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* All firmware banks should be part of the same non-volatile storage as per
|
||||||
|
* PSA FWU specification, hence don't check for any alternate boot source
|
||||||
|
* when PSA FWU is enabled.
|
||||||
|
*/
|
||||||
|
#if PSA_FWU_SUPPORT
|
||||||
|
err = load_auth_image_internal(image_id, image_data);
|
||||||
|
#else
|
||||||
|
do {
|
||||||
|
err = load_auth_image_internal(image_id, image_data);
|
||||||
|
} while ((err != 0) && (plat_try_next_boot_source() != 0));
|
||||||
|
#endif /* PSA_FWU_SUPPORT */
|
||||||
|
|
||||||
|
if (err == 0) {
|
||||||
|
/*
|
||||||
|
* If loading of the image gets passed (along with its
|
||||||
|
* authentication in case of Trusted-Boot flow) then measure
|
||||||
|
* it (if MEASURED_BOOT flag is enabled).
|
||||||
|
*/
|
||||||
|
err = plat_mboot_measure_image(image_id, image_data);
|
||||||
|
if (err != 0) {
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Flush the image to main memory so that it can be executed
|
||||||
|
* later by any CPU, regardless of cache and MMU state.
|
||||||
|
*/
|
||||||
|
flush_dcache_range(image_data->image_base,
|
||||||
|
image_data->image_size);
|
||||||
|
}
|
||||||
|
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Print the content of an entry_point_info_t structure.
|
||||||
|
******************************************************************************/
|
||||||
|
void print_entry_point_info(const entry_point_info_t *ep_info)
|
||||||
|
{
|
||||||
|
INFO("Entry point address = 0x%lx\n", ep_info->pc);
|
||||||
|
INFO("SPSR = 0x%x\n", ep_info->spsr);
|
||||||
|
|
||||||
|
#define PRINT_IMAGE_ARG(n) \
|
||||||
|
VERBOSE("Argument #" #n " = 0x%llx\n", \
|
||||||
|
(unsigned long long) ep_info->args.arg##n)
|
||||||
|
|
||||||
|
PRINT_IMAGE_ARG(0);
|
||||||
|
PRINT_IMAGE_ARG(1);
|
||||||
|
PRINT_IMAGE_ARG(2);
|
||||||
|
PRINT_IMAGE_ARG(3);
|
||||||
|
#ifdef __aarch64__
|
||||||
|
PRINT_IMAGE_ARG(4);
|
||||||
|
PRINT_IMAGE_ARG(5);
|
||||||
|
PRINT_IMAGE_ARG(6);
|
||||||
|
PRINT_IMAGE_ARG(7);
|
||||||
|
#endif
|
||||||
|
#undef PRINT_IMAGE_ARG
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function is for returning the TF-A version
|
||||||
|
*/
|
||||||
|
const char *get_version(void)
|
||||||
|
{
|
||||||
|
extern const char version[];
|
||||||
|
return version;
|
||||||
|
}
|
||||||
351
arm-trusted-firmware/common/desc_image_load.c
Normal file
351
arm-trusted-firmware/common/desc_image_load.c
Normal file
@@ -0,0 +1,351 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/desc_image_load.h>
|
||||||
|
#include <common/tbbr/tbbr_img_def.h>
|
||||||
|
|
||||||
|
static bl_load_info_t bl_load_info;
|
||||||
|
static bl_params_t next_bl_params;
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function flushes the data structures so that they are visible
|
||||||
|
* in memory for the next BL image.
|
||||||
|
******************************************************************************/
|
||||||
|
void flush_bl_params_desc(void)
|
||||||
|
{
|
||||||
|
flush_bl_params_desc_args(bl_mem_params_desc_ptr,
|
||||||
|
bl_mem_params_desc_num,
|
||||||
|
&next_bl_params);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function flushes the data structures specified as arguments so that they
|
||||||
|
* are visible in memory for the next BL image.
|
||||||
|
******************************************************************************/
|
||||||
|
void flush_bl_params_desc_args(bl_mem_params_node_t *mem_params_desc_ptr,
|
||||||
|
unsigned int mem_params_desc_num,
|
||||||
|
bl_params_t *next_bl_params_ptr)
|
||||||
|
{
|
||||||
|
assert(mem_params_desc_ptr != NULL);
|
||||||
|
assert(mem_params_desc_num != 0U);
|
||||||
|
assert(next_bl_params_ptr != NULL);
|
||||||
|
|
||||||
|
flush_dcache_range((uintptr_t)mem_params_desc_ptr,
|
||||||
|
sizeof(*mem_params_desc_ptr) * mem_params_desc_num);
|
||||||
|
|
||||||
|
flush_dcache_range((uintptr_t)next_bl_params_ptr,
|
||||||
|
sizeof(*next_bl_params_ptr));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns the index for given image_id, within the
|
||||||
|
* image descriptor array provided by bl_image_info_descs_ptr, if the
|
||||||
|
* image is found else it returns -1.
|
||||||
|
******************************************************************************/
|
||||||
|
int get_bl_params_node_index(unsigned int image_id)
|
||||||
|
{
|
||||||
|
unsigned int index;
|
||||||
|
assert(image_id != INVALID_IMAGE_ID);
|
||||||
|
|
||||||
|
for (index = 0U; index < bl_mem_params_desc_num; index++) {
|
||||||
|
if (bl_mem_params_desc_ptr[index].image_id == image_id)
|
||||||
|
return (int)index;
|
||||||
|
}
|
||||||
|
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function returns the pointer to `bl_mem_params_node_t` object for
|
||||||
|
* given image_id, within the image descriptor array provided by
|
||||||
|
* bl_mem_params_desc_ptr, if the image is found else it returns NULL.
|
||||||
|
******************************************************************************/
|
||||||
|
bl_mem_params_node_t *get_bl_mem_params_node(unsigned int image_id)
|
||||||
|
{
|
||||||
|
int index;
|
||||||
|
assert(image_id != INVALID_IMAGE_ID);
|
||||||
|
|
||||||
|
index = get_bl_params_node_index(image_id);
|
||||||
|
if (index >= 0)
|
||||||
|
return &bl_mem_params_desc_ptr[index];
|
||||||
|
else
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function creates the list of loadable images, by populating and
|
||||||
|
* linking each `bl_load_info_node_t` type node, using the internal array
|
||||||
|
* of image descriptor provided by bl_mem_params_desc_ptr. It also populates
|
||||||
|
* and returns `bl_load_info_t` type structure that contains head of the list
|
||||||
|
* of loadable images.
|
||||||
|
******************************************************************************/
|
||||||
|
bl_load_info_t *get_bl_load_info_from_mem_params_desc(void)
|
||||||
|
{
|
||||||
|
unsigned int index = 0;
|
||||||
|
|
||||||
|
/* If there is no image to start with, return NULL */
|
||||||
|
if (bl_mem_params_desc_num == 0U)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
/* Assign initial data structures */
|
||||||
|
bl_load_info_node_t *bl_node_info =
|
||||||
|
&bl_mem_params_desc_ptr[index].load_node_mem;
|
||||||
|
bl_load_info.head = bl_node_info;
|
||||||
|
SET_PARAM_HEAD(&bl_load_info, PARAM_BL_LOAD_INFO, VERSION_2, 0U);
|
||||||
|
|
||||||
|
/* Go through the image descriptor array and create the list */
|
||||||
|
for (; index < bl_mem_params_desc_num; index++) {
|
||||||
|
|
||||||
|
/* Populate the image information */
|
||||||
|
bl_node_info->image_id = bl_mem_params_desc_ptr[index].image_id;
|
||||||
|
bl_node_info->image_info = &bl_mem_params_desc_ptr[index].image_info;
|
||||||
|
|
||||||
|
/* Link next image if present */
|
||||||
|
if ((index + 1U) < bl_mem_params_desc_num) {
|
||||||
|
/* Get the memory and link the next node */
|
||||||
|
bl_node_info->next_load_info =
|
||||||
|
&bl_mem_params_desc_ptr[index + 1U].load_node_mem;
|
||||||
|
bl_node_info = bl_node_info->next_load_info;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return &bl_load_info;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function creates the list of executable images, by populating and
|
||||||
|
* linking each `bl_params_node_t` type node, using the internal array of
|
||||||
|
* image descriptor provided by bl_mem_params_desc_ptr. It also populates
|
||||||
|
* and returns `bl_params_t` type structure that contains head of the list
|
||||||
|
* of executable images.
|
||||||
|
******************************************************************************/
|
||||||
|
bl_params_t *get_next_bl_params_from_mem_params_desc(void)
|
||||||
|
{
|
||||||
|
unsigned int count;
|
||||||
|
unsigned int img_id = 0U;
|
||||||
|
unsigned int link_index = 0U;
|
||||||
|
bl_params_node_t *bl_current_exec_node = NULL;
|
||||||
|
bl_params_node_t *bl_last_exec_node = NULL;
|
||||||
|
bl_mem_params_node_t *desc_ptr;
|
||||||
|
|
||||||
|
/* If there is no image to start with, return NULL */
|
||||||
|
if (bl_mem_params_desc_num == 0U)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
/* Get the list HEAD */
|
||||||
|
for (count = 0U; count < bl_mem_params_desc_num; count++) {
|
||||||
|
|
||||||
|
desc_ptr = &bl_mem_params_desc_ptr[count];
|
||||||
|
|
||||||
|
if ((EP_GET_EXE(desc_ptr->ep_info.h.attr) == EXECUTABLE) &&
|
||||||
|
(EP_GET_FIRST_EXE(desc_ptr->ep_info.h.attr) == EP_FIRST_EXE)) {
|
||||||
|
next_bl_params.head = &desc_ptr->params_node_mem;
|
||||||
|
link_index = count;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Make sure we have a HEAD node */
|
||||||
|
assert(next_bl_params.head != NULL);
|
||||||
|
|
||||||
|
/* Populate the HEAD information */
|
||||||
|
SET_PARAM_HEAD(&next_bl_params, PARAM_BL_PARAMS, VERSION_2, 0U);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Go through the image descriptor array and create the list.
|
||||||
|
* This bounded loop is to make sure that we are not looping forever.
|
||||||
|
*/
|
||||||
|
for (count = 0U; count < bl_mem_params_desc_num; count++) {
|
||||||
|
|
||||||
|
desc_ptr = &bl_mem_params_desc_ptr[link_index];
|
||||||
|
|
||||||
|
/* Make sure the image is executable */
|
||||||
|
assert(EP_GET_EXE(desc_ptr->ep_info.h.attr) == EXECUTABLE);
|
||||||
|
|
||||||
|
/* Get the memory for current node */
|
||||||
|
bl_current_exec_node = &desc_ptr->params_node_mem;
|
||||||
|
|
||||||
|
/* Populate the image information */
|
||||||
|
bl_current_exec_node->image_id = desc_ptr->image_id;
|
||||||
|
bl_current_exec_node->image_info = &desc_ptr->image_info;
|
||||||
|
bl_current_exec_node->ep_info = &desc_ptr->ep_info;
|
||||||
|
|
||||||
|
if (bl_last_exec_node != NULL) {
|
||||||
|
/* Assert if loop detected */
|
||||||
|
assert(bl_last_exec_node->next_params_info == NULL);
|
||||||
|
|
||||||
|
/* Link the previous node to the current one */
|
||||||
|
bl_last_exec_node->next_params_info = bl_current_exec_node;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the last node */
|
||||||
|
bl_last_exec_node = bl_current_exec_node;
|
||||||
|
|
||||||
|
/* If no next hand-off image then break out */
|
||||||
|
img_id = desc_ptr->next_handoff_image_id;
|
||||||
|
if (img_id == INVALID_IMAGE_ID)
|
||||||
|
break;
|
||||||
|
|
||||||
|
/* Get the index for the next hand-off image */
|
||||||
|
link_index = get_bl_params_node_index(img_id);
|
||||||
|
assert((link_index > 0U) &&
|
||||||
|
(link_index < bl_mem_params_desc_num));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Invalid image is expected to terminate the loop */
|
||||||
|
assert(img_id == INVALID_IMAGE_ID);
|
||||||
|
|
||||||
|
return &next_bl_params;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function populates the entry point information with the corresponding
|
||||||
|
* config file for all executable BL images described in bl_params.
|
||||||
|
******************************************************************************/
|
||||||
|
void populate_next_bl_params_config(bl_params_t *bl2_to_next_bl_params)
|
||||||
|
{
|
||||||
|
bl_params_node_t *params_node;
|
||||||
|
unsigned int fw_config_id;
|
||||||
|
uintptr_t fw_config_base;
|
||||||
|
bl_mem_params_node_t *mem_params;
|
||||||
|
uintptr_t hw_config_base = 0;
|
||||||
|
|
||||||
|
assert(bl2_to_next_bl_params != NULL);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the `bl_mem_params_node_t` corresponding to HW_CONFIG
|
||||||
|
* if available.
|
||||||
|
*/
|
||||||
|
mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
|
||||||
|
|
||||||
|
if (mem_params != NULL)
|
||||||
|
hw_config_base = mem_params->image_info.image_base;
|
||||||
|
|
||||||
|
for (params_node = bl2_to_next_bl_params->head; params_node != NULL;
|
||||||
|
params_node = params_node->next_params_info) {
|
||||||
|
|
||||||
|
fw_config_base = 0;
|
||||||
|
|
||||||
|
switch (params_node->image_id) {
|
||||||
|
case BL31_IMAGE_ID:
|
||||||
|
fw_config_id = SOC_FW_CONFIG_ID;
|
||||||
|
break;
|
||||||
|
case BL32_IMAGE_ID:
|
||||||
|
/*
|
||||||
|
* At the moment, OPTEE cannot accept a DTB in secure memory,
|
||||||
|
* so fall back and use NT_FW_CONFIG instead.
|
||||||
|
* This MUST be fixed as soon as OPTEE has support to
|
||||||
|
* receive DTBs in secure memory.
|
||||||
|
*/
|
||||||
|
#ifndef SPD_opteed
|
||||||
|
fw_config_id = TOS_FW_CONFIG_ID;
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
|
case BL33_IMAGE_ID:
|
||||||
|
fw_config_id = NT_FW_CONFIG_ID;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
fw_config_id = INVALID_IMAGE_ID;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (fw_config_id != INVALID_IMAGE_ID) {
|
||||||
|
mem_params = get_bl_mem_params_node(fw_config_id);
|
||||||
|
if (mem_params != NULL) {
|
||||||
|
fw_config_base = mem_params->image_info.image_base;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef SPD_opteed
|
||||||
|
/*
|
||||||
|
* If SPD_opteed is enabled, arg[0,2] are populated by
|
||||||
|
* parse_optee_header(), which is called by
|
||||||
|
* arm_bl2_handle_post_image_load(). The meaning of the
|
||||||
|
* arguments are:
|
||||||
|
* arg0 <-- MODE_RW
|
||||||
|
* arg1 <-- Paged image base
|
||||||
|
* arg2 <-- Paged image size
|
||||||
|
*/
|
||||||
|
if (params_node->image_id == BL32_IMAGE_ID) {
|
||||||
|
params_node->ep_info->args.arg3 = fw_config_base;
|
||||||
|
} else {
|
||||||
|
#endif
|
||||||
|
/*
|
||||||
|
* Pass hw and tb_fw config addresses to next images.
|
||||||
|
* NOTE - for EL3 runtime images (BL31 for AArch64
|
||||||
|
* and BL32 for AArch32), arg0 is already used by
|
||||||
|
* generic code. Take care of not overwriting the
|
||||||
|
* previous initialisations.
|
||||||
|
*/
|
||||||
|
if (params_node == bl2_to_next_bl_params->head) {
|
||||||
|
if (params_node->ep_info->args.arg1 == 0U)
|
||||||
|
params_node->ep_info->args.arg1 =
|
||||||
|
fw_config_base;
|
||||||
|
if (params_node->ep_info->args.arg2 == 0U)
|
||||||
|
params_node->ep_info->args.arg2 =
|
||||||
|
hw_config_base;
|
||||||
|
} else {
|
||||||
|
if (params_node->ep_info->args.arg0 == 0U)
|
||||||
|
params_node->ep_info->args.arg0 =
|
||||||
|
fw_config_base;
|
||||||
|
if (params_node->ep_info->args.arg1 == 0U)
|
||||||
|
params_node->ep_info->args.arg1 =
|
||||||
|
hw_config_base;
|
||||||
|
}
|
||||||
|
#ifdef SPD_opteed
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Helper to extract BL32/BL33 entry point info from arg0 passed to BL31, for
|
||||||
|
* platforms that are only interested in those. Platforms that need to extract
|
||||||
|
* more information can parse the structures themselves.
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
void bl31_params_parse_helper(u_register_t param,
|
||||||
|
entry_point_info_t *bl32_ep_info_out,
|
||||||
|
entry_point_info_t *bl33_ep_info_out)
|
||||||
|
{
|
||||||
|
bl_params_node_t *node;
|
||||||
|
bl_params_t *v2 = (void *)(uintptr_t)param;
|
||||||
|
|
||||||
|
#if !ERROR_DEPRECATED
|
||||||
|
if (v2->h.version == PARAM_VERSION_1) {
|
||||||
|
struct { /* Deprecated version 1 parameter structure. */
|
||||||
|
param_header_t h;
|
||||||
|
image_info_t *bl31_image_info;
|
||||||
|
entry_point_info_t *bl32_ep_info;
|
||||||
|
image_info_t *bl32_image_info;
|
||||||
|
entry_point_info_t *bl33_ep_info;
|
||||||
|
image_info_t *bl33_image_info;
|
||||||
|
} *v1 = (void *)(uintptr_t)param;
|
||||||
|
assert(v1->h.type == PARAM_BL31);
|
||||||
|
if (bl32_ep_info_out != NULL)
|
||||||
|
*bl32_ep_info_out = *v1->bl32_ep_info;
|
||||||
|
if (bl33_ep_info_out != NULL)
|
||||||
|
*bl33_ep_info_out = *v1->bl33_ep_info;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
#endif /* !ERROR_DEPRECATED */
|
||||||
|
|
||||||
|
assert(v2->h.version == PARAM_VERSION_2);
|
||||||
|
assert(v2->h.type == PARAM_BL_PARAMS);
|
||||||
|
for (node = v2->head; node != NULL; node = node->next_params_info) {
|
||||||
|
if (node->image_id == BL32_IMAGE_ID)
|
||||||
|
if (bl32_ep_info_out != NULL)
|
||||||
|
*bl32_ep_info_out = *node->ep_info;
|
||||||
|
if (node->image_id == BL33_IMAGE_ID)
|
||||||
|
if (bl33_ep_info_out != NULL)
|
||||||
|
*bl33_ep_info_out = *node->ep_info;
|
||||||
|
}
|
||||||
|
}
|
||||||
626
arm-trusted-firmware/common/fdt_fixup.c
Normal file
626
arm-trusted-firmware/common/fdt_fixup.c
Normal file
@@ -0,0 +1,626 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Contains generic routines to fix up the device tree blob passed on to
|
||||||
|
* payloads like BL32 and BL33 (and further down the boot chain).
|
||||||
|
* This allows to easily add PSCI nodes, when the original DT does not have
|
||||||
|
* it or advertises another method.
|
||||||
|
* Also it supports to add reserved memory nodes to describe memory that
|
||||||
|
* is used by the secure world, so that non-secure software avoids using
|
||||||
|
* that.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <errno.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include <libfdt.h>
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <common/fdt_fixup.h>
|
||||||
|
#include <common/fdt_wrappers.h>
|
||||||
|
#include <drivers/console.h>
|
||||||
|
#include <lib/psci/psci.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
|
||||||
|
static int append_psci_compatible(void *fdt, int offs, const char *str)
|
||||||
|
{
|
||||||
|
return fdt_appendprop(fdt, offs, "compatible", str, strlen(str) + 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Those defines are for PSCI v0.1 legacy clients, which we expect to use
|
||||||
|
* the same execution state (AArch32/AArch64) as TF-A.
|
||||||
|
* Kernels running in AArch32 on an AArch64 TF-A should use PSCI v0.2.
|
||||||
|
*/
|
||||||
|
#ifdef __aarch64__
|
||||||
|
#define PSCI_CPU_SUSPEND_FNID PSCI_CPU_SUSPEND_AARCH64
|
||||||
|
#define PSCI_CPU_ON_FNID PSCI_CPU_ON_AARCH64
|
||||||
|
#else
|
||||||
|
#define PSCI_CPU_SUSPEND_FNID PSCI_CPU_SUSPEND_AARCH32
|
||||||
|
#define PSCI_CPU_ON_FNID PSCI_CPU_ON_AARCH32
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* dt_add_psci_node() - Add a PSCI node into an existing device tree
|
||||||
|
* @fdt: pointer to the device tree blob in memory
|
||||||
|
*
|
||||||
|
* Add a device tree node describing PSCI into the root level of an existing
|
||||||
|
* device tree blob in memory.
|
||||||
|
* This will add v0.1, v0.2 and v1.0 compatible strings and the standard
|
||||||
|
* function IDs for v0.1 compatibility.
|
||||||
|
* An existing PSCI node will not be touched, the function will return success
|
||||||
|
* in this case. This function will not touch the /cpus enable methods, use
|
||||||
|
* dt_add_psci_cpu_enable_methods() for that.
|
||||||
|
*
|
||||||
|
* Return: 0 on success, -1 otherwise.
|
||||||
|
******************************************************************************/
|
||||||
|
int dt_add_psci_node(void *fdt)
|
||||||
|
{
|
||||||
|
int offs;
|
||||||
|
|
||||||
|
if (fdt_path_offset(fdt, "/psci") >= 0) {
|
||||||
|
WARN("PSCI Device Tree node already exists!\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
offs = fdt_path_offset(fdt, "/");
|
||||||
|
if (offs < 0)
|
||||||
|
return -1;
|
||||||
|
offs = fdt_add_subnode(fdt, offs, "psci");
|
||||||
|
if (offs < 0)
|
||||||
|
return -1;
|
||||||
|
if (append_psci_compatible(fdt, offs, "arm,psci-1.0"))
|
||||||
|
return -1;
|
||||||
|
if (append_psci_compatible(fdt, offs, "arm,psci-0.2"))
|
||||||
|
return -1;
|
||||||
|
if (append_psci_compatible(fdt, offs, "arm,psci"))
|
||||||
|
return -1;
|
||||||
|
if (fdt_setprop_string(fdt, offs, "method", "smc"))
|
||||||
|
return -1;
|
||||||
|
if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_FNID))
|
||||||
|
return -1;
|
||||||
|
if (fdt_setprop_u32(fdt, offs, "cpu_off", PSCI_CPU_OFF))
|
||||||
|
return -1;
|
||||||
|
if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_FNID))
|
||||||
|
return -1;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Find the first subnode that has a "device_type" property with the value
|
||||||
|
* "cpu" and which's enable-method is not "psci" (yet).
|
||||||
|
* Returns 0 if no such subnode is found, so all have already been patched
|
||||||
|
* or none have to be patched in the first place.
|
||||||
|
* Returns 1 if *one* such subnode has been found and successfully changed
|
||||||
|
* to "psci".
|
||||||
|
* Returns negative values on error.
|
||||||
|
*
|
||||||
|
* Call in a loop until it returns 0. Recalculate the node offset after
|
||||||
|
* it has returned 1.
|
||||||
|
*/
|
||||||
|
static int dt_update_one_cpu_node(void *fdt, int offset)
|
||||||
|
{
|
||||||
|
int offs;
|
||||||
|
|
||||||
|
/* Iterate over all subnodes to find those with device_type = "cpu". */
|
||||||
|
for (offs = fdt_first_subnode(fdt, offset); offs >= 0;
|
||||||
|
offs = fdt_next_subnode(fdt, offs)) {
|
||||||
|
const char *prop;
|
||||||
|
int len;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
prop = fdt_getprop(fdt, offs, "device_type", &len);
|
||||||
|
if (prop == NULL)
|
||||||
|
continue;
|
||||||
|
if ((strcmp(prop, "cpu") != 0) || (len != 4))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
/* Ignore any nodes which already use "psci". */
|
||||||
|
prop = fdt_getprop(fdt, offs, "enable-method", &len);
|
||||||
|
if ((prop != NULL) &&
|
||||||
|
(strcmp(prop, "psci") == 0) && (len == 5))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
ret = fdt_setprop_string(fdt, offs, "enable-method", "psci");
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
/*
|
||||||
|
* Subnode found and patched.
|
||||||
|
* Restart to accommodate potentially changed offsets.
|
||||||
|
*/
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (offs == -FDT_ERR_NOTFOUND)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return offs;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* dt_add_psci_cpu_enable_methods() - switch CPU nodes in DT to use PSCI
|
||||||
|
* @fdt: pointer to the device tree blob in memory
|
||||||
|
*
|
||||||
|
* Iterate over all CPU device tree nodes (/cpus/cpu@x) in memory to change
|
||||||
|
* the enable-method to PSCI. This will add the enable-method properties, if
|
||||||
|
* required, or will change existing properties to read "psci".
|
||||||
|
*
|
||||||
|
* Return: 0 on success, or a negative error value otherwise.
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
int dt_add_psci_cpu_enable_methods(void *fdt)
|
||||||
|
{
|
||||||
|
int offs, ret;
|
||||||
|
|
||||||
|
do {
|
||||||
|
offs = fdt_path_offset(fdt, "/cpus");
|
||||||
|
if (offs < 0)
|
||||||
|
return offs;
|
||||||
|
|
||||||
|
ret = dt_update_one_cpu_node(fdt, offs);
|
||||||
|
} while (ret > 0);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define HIGH_BITS(x) ((sizeof(x) > 4) ? ((x) >> 32) : (typeof(x))0)
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* fdt_add_reserved_memory() - reserve (secure) memory regions in DT
|
||||||
|
* @dtb: pointer to the device tree blob in memory
|
||||||
|
* @node_name: name of the subnode to be used
|
||||||
|
* @base: physical base address of the reserved region
|
||||||
|
* @size: size of the reserved region
|
||||||
|
*
|
||||||
|
* Add a region of memory to the /reserved-memory node in a device tree in
|
||||||
|
* memory, creating that node if required. Each region goes into a subnode
|
||||||
|
* of that node and has a @node_name, a @base address and a @size.
|
||||||
|
* This will prevent any device tree consumer from using that memory. It
|
||||||
|
* can be used to announce secure memory regions, as it adds the "no-map"
|
||||||
|
* property to prevent mapping and speculative operations on that region.
|
||||||
|
*
|
||||||
|
* See reserved-memory/reserved-memory.txt in the (Linux kernel) DT binding
|
||||||
|
* documentation for details.
|
||||||
|
* According to this binding, the address-cells and size-cells must match
|
||||||
|
* those of the root node.
|
||||||
|
*
|
||||||
|
* Return: 0 on success, a negative error value otherwise.
|
||||||
|
******************************************************************************/
|
||||||
|
int fdt_add_reserved_memory(void *dtb, const char *node_name,
|
||||||
|
uintptr_t base, size_t size)
|
||||||
|
{
|
||||||
|
int offs = fdt_path_offset(dtb, "/reserved-memory");
|
||||||
|
uint32_t addresses[4];
|
||||||
|
int ac, sc;
|
||||||
|
unsigned int idx = 0;
|
||||||
|
|
||||||
|
ac = fdt_address_cells(dtb, 0);
|
||||||
|
sc = fdt_size_cells(dtb, 0);
|
||||||
|
if (offs < 0) { /* create if not existing yet */
|
||||||
|
offs = fdt_add_subnode(dtb, 0, "reserved-memory");
|
||||||
|
if (offs < 0) {
|
||||||
|
return offs;
|
||||||
|
}
|
||||||
|
fdt_setprop_u32(dtb, offs, "#address-cells", ac);
|
||||||
|
fdt_setprop_u32(dtb, offs, "#size-cells", sc);
|
||||||
|
fdt_setprop(dtb, offs, "ranges", NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ac > 1) {
|
||||||
|
addresses[idx] = cpu_to_fdt32(HIGH_BITS(base));
|
||||||
|
idx++;
|
||||||
|
}
|
||||||
|
addresses[idx] = cpu_to_fdt32(base & 0xffffffff);
|
||||||
|
idx++;
|
||||||
|
if (sc > 1) {
|
||||||
|
addresses[idx] = cpu_to_fdt32(HIGH_BITS(size));
|
||||||
|
idx++;
|
||||||
|
}
|
||||||
|
addresses[idx] = cpu_to_fdt32(size & 0xffffffff);
|
||||||
|
idx++;
|
||||||
|
offs = fdt_add_subnode(dtb, offs, node_name);
|
||||||
|
fdt_setprop(dtb, offs, "no-map", NULL, 0);
|
||||||
|
fdt_setprop(dtb, offs, "reg", addresses, idx * sizeof(uint32_t));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* fdt_add_cpu() Add a new CPU node to the DT
|
||||||
|
* @dtb: Pointer to the device tree blob in memory
|
||||||
|
* @parent: Offset of the parent node
|
||||||
|
* @mpidr: MPIDR for the current CPU
|
||||||
|
*
|
||||||
|
* Create and add a new cpu node to a DTB.
|
||||||
|
*
|
||||||
|
* Return the offset of the new node or a negative value in case of error
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
static int fdt_add_cpu(void *dtb, int parent, u_register_t mpidr)
|
||||||
|
{
|
||||||
|
int cpu_offs;
|
||||||
|
int err;
|
||||||
|
char snode_name[15];
|
||||||
|
uint64_t reg_prop;
|
||||||
|
|
||||||
|
reg_prop = mpidr & MPID_MASK & ~MPIDR_MT_MASK;
|
||||||
|
|
||||||
|
snprintf(snode_name, sizeof(snode_name), "cpu@%x",
|
||||||
|
(unsigned int)reg_prop);
|
||||||
|
|
||||||
|
cpu_offs = fdt_add_subnode(dtb, parent, snode_name);
|
||||||
|
if (cpu_offs < 0) {
|
||||||
|
ERROR ("FDT: add subnode \"%s\" failed: %i\n",
|
||||||
|
snode_name, cpu_offs);
|
||||||
|
return cpu_offs;
|
||||||
|
}
|
||||||
|
|
||||||
|
err = fdt_setprop_string(dtb, cpu_offs, "compatible", "arm,armv8");
|
||||||
|
if (err < 0) {
|
||||||
|
ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
|
||||||
|
"compatible", cpu_offs);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
err = fdt_setprop_u64(dtb, cpu_offs, "reg", reg_prop);
|
||||||
|
if (err < 0) {
|
||||||
|
ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
|
||||||
|
"reg", cpu_offs);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
err = fdt_setprop_string(dtb, cpu_offs, "device_type", "cpu");
|
||||||
|
if (err < 0) {
|
||||||
|
ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
|
||||||
|
"device_type", cpu_offs);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
err = fdt_setprop_string(dtb, cpu_offs, "enable-method", "psci");
|
||||||
|
if (err < 0) {
|
||||||
|
ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
|
||||||
|
"enable-method", cpu_offs);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
return cpu_offs;
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
* fdt_add_cpus_node() - Add the cpus node to the DTB
|
||||||
|
* @dtb: pointer to the device tree blob in memory
|
||||||
|
* @afflv0: Maximum number of threads per core (affinity level 0).
|
||||||
|
* @afflv1: Maximum number of CPUs per cluster (affinity level 1).
|
||||||
|
* @afflv2: Maximum number of clusters (affinity level 2).
|
||||||
|
*
|
||||||
|
* Iterate over all the possible MPIDs given the maximum affinity levels and
|
||||||
|
* add a cpus node to the DTB with all the valid CPUs on the system.
|
||||||
|
* If there is already a /cpus node, exit gracefully
|
||||||
|
*
|
||||||
|
* A system with two CPUs would generate a node equivalent or similar to:
|
||||||
|
*
|
||||||
|
* cpus {
|
||||||
|
* #address-cells = <2>;
|
||||||
|
* #size-cells = <0>;
|
||||||
|
*
|
||||||
|
* cpu0: cpu@0 {
|
||||||
|
* compatible = "arm,armv8";
|
||||||
|
* reg = <0x0 0x0>;
|
||||||
|
* device_type = "cpu";
|
||||||
|
* enable-method = "psci";
|
||||||
|
* };
|
||||||
|
* cpu1: cpu@10000 {
|
||||||
|
* compatible = "arm,armv8";
|
||||||
|
* reg = <0x0 0x100>;
|
||||||
|
* device_type = "cpu";
|
||||||
|
* enable-method = "psci";
|
||||||
|
* };
|
||||||
|
* };
|
||||||
|
*
|
||||||
|
* Full documentation about the CPU bindings can be found at:
|
||||||
|
* https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt
|
||||||
|
*
|
||||||
|
* Return the offset of the node or a negative value on error.
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
int fdt_add_cpus_node(void *dtb, unsigned int afflv0,
|
||||||
|
unsigned int afflv1, unsigned int afflv2)
|
||||||
|
{
|
||||||
|
int offs;
|
||||||
|
int err;
|
||||||
|
unsigned int i, j, k;
|
||||||
|
u_register_t mpidr;
|
||||||
|
int cpuid;
|
||||||
|
|
||||||
|
if (fdt_path_offset(dtb, "/cpus") >= 0) {
|
||||||
|
return -EEXIST;
|
||||||
|
}
|
||||||
|
|
||||||
|
offs = fdt_add_subnode(dtb, 0, "cpus");
|
||||||
|
if (offs < 0) {
|
||||||
|
ERROR ("FDT: add subnode \"cpus\" node to parent node failed");
|
||||||
|
return offs;
|
||||||
|
}
|
||||||
|
|
||||||
|
err = fdt_setprop_u32(dtb, offs, "#address-cells", 2);
|
||||||
|
if (err < 0) {
|
||||||
|
ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
|
||||||
|
"#address-cells", offs);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
err = fdt_setprop_u32(dtb, offs, "#size-cells", 0);
|
||||||
|
if (err < 0) {
|
||||||
|
ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
|
||||||
|
"#size-cells", offs);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Populate the node with the CPUs.
|
||||||
|
* As libfdt prepends subnodes within a node, reverse the index count
|
||||||
|
* so the CPU nodes would be better ordered.
|
||||||
|
*/
|
||||||
|
for (i = afflv2; i > 0U; i--) {
|
||||||
|
for (j = afflv1; j > 0U; j--) {
|
||||||
|
for (k = afflv0; k > 0U; k--) {
|
||||||
|
mpidr = ((i - 1) << MPIDR_AFF2_SHIFT) |
|
||||||
|
((j - 1) << MPIDR_AFF1_SHIFT) |
|
||||||
|
((k - 1) << MPIDR_AFF0_SHIFT) |
|
||||||
|
(read_mpidr_el1() & MPIDR_MT_MASK);
|
||||||
|
|
||||||
|
cpuid = plat_core_pos_by_mpidr(mpidr);
|
||||||
|
if (cpuid >= 0) {
|
||||||
|
/* Valid MPID found */
|
||||||
|
err = fdt_add_cpu(dtb, offs, mpidr);
|
||||||
|
if (err < 0) {
|
||||||
|
ERROR ("FDT: %s 0x%08x\n",
|
||||||
|
"error adding CPU",
|
||||||
|
(uint32_t)mpidr);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return offs;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* fdt_add_cpu_idle_states() - add PSCI CPU idle states to cpu nodes in the DT
|
||||||
|
* @dtb: pointer to the device tree blob in memory
|
||||||
|
* @states: array of idle state descriptions, ending with empty element
|
||||||
|
*
|
||||||
|
* Add information about CPU idle states to the devicetree. This function
|
||||||
|
* assumes that CPU idle states are not already present in the devicetree, and
|
||||||
|
* that all CPU states are equally applicable to all CPUs.
|
||||||
|
*
|
||||||
|
* See arm/idle-states.yaml and arm/psci.yaml in the (Linux kernel) DT binding
|
||||||
|
* documentation for more details.
|
||||||
|
*
|
||||||
|
* Return: 0 on success, a negative error value otherwise.
|
||||||
|
******************************************************************************/
|
||||||
|
int fdt_add_cpu_idle_states(void *dtb, const struct psci_cpu_idle_state *state)
|
||||||
|
{
|
||||||
|
int cpu_node, cpus_node, idle_states_node, ret;
|
||||||
|
uint32_t count, phandle;
|
||||||
|
|
||||||
|
ret = fdt_find_max_phandle(dtb, &phandle);
|
||||||
|
phandle++;
|
||||||
|
if (ret < 0) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
cpus_node = fdt_path_offset(dtb, "/cpus");
|
||||||
|
if (cpus_node < 0) {
|
||||||
|
return cpus_node;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Create the idle-states node and its child nodes. */
|
||||||
|
idle_states_node = fdt_add_subnode(dtb, cpus_node, "idle-states");
|
||||||
|
if (idle_states_node < 0) {
|
||||||
|
return idle_states_node;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = fdt_setprop_string(dtb, idle_states_node, "entry-method", "psci");
|
||||||
|
if (ret < 0) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (count = 0U; state->name != NULL; count++, phandle++, state++) {
|
||||||
|
int idle_state_node;
|
||||||
|
|
||||||
|
idle_state_node = fdt_add_subnode(dtb, idle_states_node,
|
||||||
|
state->name);
|
||||||
|
if (idle_state_node < 0) {
|
||||||
|
return idle_state_node;
|
||||||
|
}
|
||||||
|
|
||||||
|
fdt_setprop_string(dtb, idle_state_node, "compatible",
|
||||||
|
"arm,idle-state");
|
||||||
|
fdt_setprop_u32(dtb, idle_state_node, "arm,psci-suspend-param",
|
||||||
|
state->power_state);
|
||||||
|
if (state->local_timer_stop) {
|
||||||
|
fdt_setprop_empty(dtb, idle_state_node,
|
||||||
|
"local-timer-stop");
|
||||||
|
}
|
||||||
|
fdt_setprop_u32(dtb, idle_state_node, "entry-latency-us",
|
||||||
|
state->entry_latency_us);
|
||||||
|
fdt_setprop_u32(dtb, idle_state_node, "exit-latency-us",
|
||||||
|
state->exit_latency_us);
|
||||||
|
fdt_setprop_u32(dtb, idle_state_node, "min-residency-us",
|
||||||
|
state->min_residency_us);
|
||||||
|
if (state->wakeup_latency_us) {
|
||||||
|
fdt_setprop_u32(dtb, idle_state_node,
|
||||||
|
"wakeup-latency-us",
|
||||||
|
state->wakeup_latency_us);
|
||||||
|
}
|
||||||
|
fdt_setprop_u32(dtb, idle_state_node, "phandle", phandle);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (count == 0U) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Link each cpu node to the idle state nodes. */
|
||||||
|
fdt_for_each_subnode(cpu_node, dtb, cpus_node) {
|
||||||
|
const char *device_type;
|
||||||
|
fdt32_t *value;
|
||||||
|
|
||||||
|
/* Only process child nodes with device_type = "cpu". */
|
||||||
|
device_type = fdt_getprop(dtb, cpu_node, "device_type", NULL);
|
||||||
|
if (device_type == NULL || strcmp(device_type, "cpu") != 0) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Allocate space for the list of phandles. */
|
||||||
|
ret = fdt_setprop_placeholder(dtb, cpu_node, "cpu-idle-states",
|
||||||
|
count * sizeof(phandle),
|
||||||
|
(void **)&value);
|
||||||
|
if (ret < 0) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Fill in the phandles of the idle state nodes. */
|
||||||
|
for (uint32_t i = 0U; i < count; ++i) {
|
||||||
|
value[i] = cpu_to_fdt32(phandle - count + i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* fdt_adjust_gic_redist() - Adjust GICv3 redistributor size
|
||||||
|
* @dtb: Pointer to the DT blob in memory
|
||||||
|
* @nr_cores: Number of CPU cores on this system.
|
||||||
|
* @gicr_base: Base address of the first GICR frame, or ~0 if unchanged
|
||||||
|
* @gicr_frame_size: Size of the GICR frame per core
|
||||||
|
*
|
||||||
|
* On a GICv3 compatible interrupt controller, the redistributor provides
|
||||||
|
* a number of 64k pages per each supported core. So with a dynamic topology,
|
||||||
|
* this size cannot be known upfront and thus can't be hardcoded into the DTB.
|
||||||
|
*
|
||||||
|
* Find the DT node describing the GICv3 interrupt controller, and adjust
|
||||||
|
* the size of the redistributor to match the number of actual cores on
|
||||||
|
* this system.
|
||||||
|
* A GICv4 compatible redistributor uses four 64K pages per core, whereas GICs
|
||||||
|
* without support for direct injection of virtual interrupts use two 64K pages.
|
||||||
|
* The @gicr_frame_size parameter should be 262144 and 131072, respectively.
|
||||||
|
* Also optionally allow adjusting the GICR frame base address, when this is
|
||||||
|
* different due to ITS frames between distributor and redistributor.
|
||||||
|
*
|
||||||
|
* Return: 0 on success, negative error value otherwise.
|
||||||
|
*/
|
||||||
|
int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores,
|
||||||
|
uintptr_t gicr_base, unsigned int gicr_frame_size)
|
||||||
|
{
|
||||||
|
int offset = fdt_node_offset_by_compatible(dtb, 0, "arm,gic-v3");
|
||||||
|
uint64_t reg_64;
|
||||||
|
uint32_t reg_32;
|
||||||
|
void *val;
|
||||||
|
int parent, ret;
|
||||||
|
int ac, sc;
|
||||||
|
|
||||||
|
if (offset < 0) {
|
||||||
|
return offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
parent = fdt_parent_offset(dtb, offset);
|
||||||
|
if (parent < 0) {
|
||||||
|
return parent;
|
||||||
|
}
|
||||||
|
ac = fdt_address_cells(dtb, parent);
|
||||||
|
sc = fdt_size_cells(dtb, parent);
|
||||||
|
if (ac < 0 || sc < 0) {
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (gicr_base != INVALID_BASE_ADDR) {
|
||||||
|
if (ac == 1) {
|
||||||
|
reg_32 = cpu_to_fdt32(gicr_base);
|
||||||
|
val = ®_32;
|
||||||
|
} else {
|
||||||
|
reg_64 = cpu_to_fdt64(gicr_base);
|
||||||
|
val = ®_64;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* The redistributor base address is the second address in
|
||||||
|
* the "reg" entry, so we have to skip one address and one
|
||||||
|
* size cell.
|
||||||
|
*/
|
||||||
|
ret = fdt_setprop_inplace_namelen_partial(dtb, offset,
|
||||||
|
"reg", 3,
|
||||||
|
(ac + sc) * 4,
|
||||||
|
val, ac * 4);
|
||||||
|
if (ret < 0) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (sc == 1) {
|
||||||
|
reg_32 = cpu_to_fdt32(nr_cores * gicr_frame_size);
|
||||||
|
val = ®_32;
|
||||||
|
} else {
|
||||||
|
reg_64 = cpu_to_fdt64(nr_cores * (uint64_t)gicr_frame_size);
|
||||||
|
val = ®_64;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The redistributor is described in the second "reg" entry.
|
||||||
|
* So we have to skip one address and one size cell, then another
|
||||||
|
* address cell to get to the second size cell.
|
||||||
|
*/
|
||||||
|
return fdt_setprop_inplace_namelen_partial(dtb, offset, "reg", 3,
|
||||||
|
(ac + sc + ac) * 4,
|
||||||
|
val, sc * 4);
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* fdt_set_mac_address () - store MAC address in device tree
|
||||||
|
* @dtb: pointer to the device tree blob in memory
|
||||||
|
* @eth_idx: number of Ethernet interface in /aliases node
|
||||||
|
* @mac_addr: pointer to 6 byte MAC address to store
|
||||||
|
*
|
||||||
|
* Use the generic local-mac-address property in a network device DT node
|
||||||
|
* to define the MAC address this device should be using. Many platform
|
||||||
|
* network devices lack device-specific non-volatile storage to hold this
|
||||||
|
* address, and leave it up to firmware to find and store a unique MAC
|
||||||
|
* address in the DT.
|
||||||
|
* The MAC address could be read from some board or firmware defined storage,
|
||||||
|
* or could be derived from some other unique property like a serial number.
|
||||||
|
*
|
||||||
|
* Return: 0 on success, a negative libfdt error value otherwise.
|
||||||
|
*/
|
||||||
|
int fdt_set_mac_address(void *dtb, unsigned int ethernet_idx,
|
||||||
|
const uint8_t *mac_addr)
|
||||||
|
{
|
||||||
|
char eth_alias[12];
|
||||||
|
const char *path;
|
||||||
|
int node;
|
||||||
|
|
||||||
|
if (ethernet_idx > 9U) {
|
||||||
|
return -FDT_ERR_BADVALUE;
|
||||||
|
}
|
||||||
|
snprintf(eth_alias, sizeof(eth_alias), "ethernet%d", ethernet_idx);
|
||||||
|
|
||||||
|
path = fdt_get_alias(dtb, eth_alias);
|
||||||
|
if (path == NULL) {
|
||||||
|
return -FDT_ERR_NOTFOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
node = fdt_path_offset(dtb, path);
|
||||||
|
if (node < 0) {
|
||||||
|
ERROR("Path \"%s\" not found in DT: %d\n", path, node);
|
||||||
|
return node;
|
||||||
|
}
|
||||||
|
|
||||||
|
return fdt_setprop(dtb, node, "local-mac-address", mac_addr, 6);
|
||||||
|
}
|
||||||
641
arm-trusted-firmware/common/fdt_wrappers.c
Normal file
641
arm-trusted-firmware/common/fdt_wrappers.c
Normal file
@@ -0,0 +1,641 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Helper functions to offer easier navigation of Device Tree Blob */
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <inttypes.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include <libfdt.h>
|
||||||
|
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <common/fdt_wrappers.h>
|
||||||
|
#include <common/uuid.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read cells from a given property of the given node. Any number of 32-bit
|
||||||
|
* cells of the property can be read. Returns 0 on success, or a negative
|
||||||
|
* FDT error value otherwise.
|
||||||
|
*/
|
||||||
|
int fdt_read_uint32_array(const void *dtb, int node, const char *prop_name,
|
||||||
|
unsigned int cells, uint32_t *value)
|
||||||
|
{
|
||||||
|
const fdt32_t *prop;
|
||||||
|
int value_len;
|
||||||
|
|
||||||
|
assert(dtb != NULL);
|
||||||
|
assert(prop_name != NULL);
|
||||||
|
assert(value != NULL);
|
||||||
|
assert(node >= 0);
|
||||||
|
|
||||||
|
/* Access property and obtain its length (in bytes) */
|
||||||
|
prop = fdt_getprop(dtb, node, prop_name, &value_len);
|
||||||
|
if (prop == NULL) {
|
||||||
|
VERBOSE("Couldn't find property %s in dtb\n", prop_name);
|
||||||
|
return -FDT_ERR_NOTFOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Verify that property length can fill the entire array. */
|
||||||
|
if (NCELLS((unsigned int)value_len) < cells) {
|
||||||
|
WARN("Property length mismatch\n");
|
||||||
|
return -FDT_ERR_BADVALUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (unsigned int i = 0U; i < cells; i++) {
|
||||||
|
value[i] = fdt32_to_cpu(prop[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fdt_read_uint32(const void *dtb, int node, const char *prop_name,
|
||||||
|
uint32_t *value)
|
||||||
|
{
|
||||||
|
return fdt_read_uint32_array(dtb, node, prop_name, 1, value);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t fdt_read_uint32_default(const void *dtb, int node,
|
||||||
|
const char *prop_name, uint32_t dflt_value)
|
||||||
|
{
|
||||||
|
uint32_t ret = dflt_value;
|
||||||
|
int err = fdt_read_uint32(dtb, node, prop_name, &ret);
|
||||||
|
|
||||||
|
if (err < 0) {
|
||||||
|
return dflt_value;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fdt_read_uint64(const void *dtb, int node, const char *prop_name,
|
||||||
|
uint64_t *value)
|
||||||
|
{
|
||||||
|
uint32_t array[2] = {0, 0};
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = fdt_read_uint32_array(dtb, node, prop_name, 2, array);
|
||||||
|
if (ret < 0) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
*value = ((uint64_t)array[0] << 32) | array[1];
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read bytes from a given property of the given node. Any number of
|
||||||
|
* bytes of the property can be read. The fdt pointer is updated.
|
||||||
|
* Returns 0 on success, and -1 on error.
|
||||||
|
*/
|
||||||
|
int fdtw_read_bytes(const void *dtb, int node, const char *prop,
|
||||||
|
unsigned int length, void *value)
|
||||||
|
{
|
||||||
|
const void *ptr;
|
||||||
|
int value_len;
|
||||||
|
|
||||||
|
assert(dtb != NULL);
|
||||||
|
assert(prop != NULL);
|
||||||
|
assert(value != NULL);
|
||||||
|
assert(node >= 0);
|
||||||
|
|
||||||
|
/* Access property and obtain its length (in bytes) */
|
||||||
|
ptr = fdt_getprop_namelen(dtb, node, prop, (int)strlen(prop),
|
||||||
|
&value_len);
|
||||||
|
if (ptr == NULL) {
|
||||||
|
WARN("Couldn't find property %s in dtb\n", prop);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Verify that property length is not less than number of bytes */
|
||||||
|
if ((unsigned int)value_len < length) {
|
||||||
|
WARN("Property length mismatch\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
(void)memcpy(value, ptr, length);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read string from a given property of the given node. Up to 'size - 1'
|
||||||
|
* characters are read, and a NUL terminator is added. Returns 0 on success,
|
||||||
|
* and -1 upon error.
|
||||||
|
*/
|
||||||
|
int fdtw_read_string(const void *dtb, int node, const char *prop,
|
||||||
|
char *str, size_t size)
|
||||||
|
{
|
||||||
|
const char *ptr;
|
||||||
|
size_t len;
|
||||||
|
|
||||||
|
assert(dtb != NULL);
|
||||||
|
assert(node >= 0);
|
||||||
|
assert(prop != NULL);
|
||||||
|
assert(str != NULL);
|
||||||
|
assert(size > 0U);
|
||||||
|
|
||||||
|
ptr = fdt_getprop_namelen(dtb, node, prop, (int)strlen(prop), NULL);
|
||||||
|
if (ptr == NULL) {
|
||||||
|
WARN("Couldn't find property %s in dtb\n", prop);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
len = strlcpy(str, ptr, size);
|
||||||
|
if (len >= size) {
|
||||||
|
WARN("String of property %s in dtb has been truncated\n", prop);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read UUID from a given property of the given node. Returns 0 on success,
|
||||||
|
* and a negative value upon error.
|
||||||
|
*/
|
||||||
|
int fdtw_read_uuid(const void *dtb, int node, const char *prop,
|
||||||
|
unsigned int length, uint8_t *uuid)
|
||||||
|
{
|
||||||
|
/* Buffer for UUID string (plus NUL terminator) */
|
||||||
|
char uuid_string[UUID_STRING_LENGTH + 1U];
|
||||||
|
int err;
|
||||||
|
|
||||||
|
assert(dtb != NULL);
|
||||||
|
assert(prop != NULL);
|
||||||
|
assert(uuid != NULL);
|
||||||
|
assert(node >= 0);
|
||||||
|
|
||||||
|
if (length < UUID_BYTES_LENGTH) {
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
err = fdtw_read_string(dtb, node, prop, uuid_string,
|
||||||
|
UUID_STRING_LENGTH + 1U);
|
||||||
|
if (err != 0) {
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (read_uuid(uuid, uuid_string) != 0) {
|
||||||
|
return -FDT_ERR_BADVALUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Write cells in place to a given property of the given node. At most 2 cells
|
||||||
|
* of the property are written. Returns 0 on success, and -1 upon error.
|
||||||
|
*/
|
||||||
|
int fdtw_write_inplace_cells(void *dtb, int node, const char *prop,
|
||||||
|
unsigned int cells, void *value)
|
||||||
|
{
|
||||||
|
int err, len;
|
||||||
|
|
||||||
|
assert(dtb != NULL);
|
||||||
|
assert(prop != NULL);
|
||||||
|
assert(value != NULL);
|
||||||
|
assert(node >= 0);
|
||||||
|
|
||||||
|
/* We expect either 1 or 2 cell property */
|
||||||
|
assert(cells <= 2U);
|
||||||
|
|
||||||
|
if (cells == 2U)
|
||||||
|
*(uint64_t *)value = cpu_to_fdt64(*(uint64_t *)value);
|
||||||
|
else
|
||||||
|
*(uint32_t *)value = cpu_to_fdt32(*(uint32_t *)value);
|
||||||
|
|
||||||
|
len = (int)cells * 4;
|
||||||
|
|
||||||
|
/* Set property value in place */
|
||||||
|
err = fdt_setprop_inplace(dtb, node, prop, value, len);
|
||||||
|
if (err != 0) {
|
||||||
|
WARN("Modify property %s failed with error %d\n", prop, err);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Write bytes in place to a given property of the given node.
|
||||||
|
* Any number of bytes of the property can be written.
|
||||||
|
* Returns 0 on success, and < 0 on error.
|
||||||
|
*/
|
||||||
|
int fdtw_write_inplace_bytes(void *dtb, int node, const char *prop,
|
||||||
|
unsigned int length, const void *data)
|
||||||
|
{
|
||||||
|
const void *ptr;
|
||||||
|
int namelen, value_len, err;
|
||||||
|
|
||||||
|
assert(dtb != NULL);
|
||||||
|
assert(prop != NULL);
|
||||||
|
assert(data != NULL);
|
||||||
|
assert(node >= 0);
|
||||||
|
|
||||||
|
namelen = (int)strlen(prop);
|
||||||
|
|
||||||
|
/* Access property and obtain its length in bytes */
|
||||||
|
ptr = fdt_getprop_namelen(dtb, node, prop, namelen, &value_len);
|
||||||
|
if (ptr == NULL) {
|
||||||
|
WARN("Couldn't find property %s in dtb\n", prop);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Verify that property length is not less than number of bytes */
|
||||||
|
if ((unsigned int)value_len < length) {
|
||||||
|
WARN("Property length mismatch\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set property value in place */
|
||||||
|
err = fdt_setprop_inplace_namelen_partial(dtb, node, prop,
|
||||||
|
namelen, 0,
|
||||||
|
data, (int)length);
|
||||||
|
if (err != 0) {
|
||||||
|
WARN("Set property %s failed with error %d\n", prop, err);
|
||||||
|
}
|
||||||
|
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint64_t fdt_read_prop_cells(const fdt32_t *prop, int nr_cells)
|
||||||
|
{
|
||||||
|
uint64_t reg = fdt32_to_cpu(prop[0]);
|
||||||
|
|
||||||
|
if (nr_cells > 1) {
|
||||||
|
reg = (reg << 32) | fdt32_to_cpu(prop[1]);
|
||||||
|
}
|
||||||
|
|
||||||
|
return reg;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fdt_get_reg_props_by_index(const void *dtb, int node, int index,
|
||||||
|
uintptr_t *base, size_t *size)
|
||||||
|
{
|
||||||
|
const fdt32_t *prop;
|
||||||
|
int parent, len;
|
||||||
|
int ac, sc;
|
||||||
|
int cell;
|
||||||
|
|
||||||
|
parent = fdt_parent_offset(dtb, node);
|
||||||
|
if (parent < 0) {
|
||||||
|
return -FDT_ERR_BADOFFSET;
|
||||||
|
}
|
||||||
|
|
||||||
|
ac = fdt_address_cells(dtb, parent);
|
||||||
|
sc = fdt_size_cells(dtb, parent);
|
||||||
|
|
||||||
|
cell = index * (ac + sc);
|
||||||
|
|
||||||
|
prop = fdt_getprop(dtb, node, "reg", &len);
|
||||||
|
if (prop == NULL) {
|
||||||
|
WARN("Couldn't find \"reg\" property in dtb\n");
|
||||||
|
return -FDT_ERR_NOTFOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (((cell + ac + sc) * (int)sizeof(uint32_t)) > len) {
|
||||||
|
return -FDT_ERR_BADVALUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (base != NULL) {
|
||||||
|
*base = (uintptr_t)fdt_read_prop_cells(&prop[cell], ac);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (size != NULL) {
|
||||||
|
*size = (size_t)fdt_read_prop_cells(&prop[cell + ac], sc);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function fills reg node info (base & size) with an index found by
|
||||||
|
* checking the reg-names node.
|
||||||
|
* Returns 0 on success and a negative FDT error code on failure.
|
||||||
|
******************************************************************************/
|
||||||
|
int fdt_get_reg_props_by_name(const void *dtb, int node, const char *name,
|
||||||
|
uintptr_t *base, size_t *size)
|
||||||
|
{
|
||||||
|
int index;
|
||||||
|
|
||||||
|
index = fdt_stringlist_search(dtb, node, "reg-names", name);
|
||||||
|
if (index < 0) {
|
||||||
|
return index;
|
||||||
|
}
|
||||||
|
|
||||||
|
return fdt_get_reg_props_by_index(dtb, node, index, base, size);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function gets the stdout path node.
|
||||||
|
* It reads the value indicated inside the device tree.
|
||||||
|
* Returns node offset on success and a negative FDT error code on failure.
|
||||||
|
******************************************************************************/
|
||||||
|
int fdt_get_stdout_node_offset(const void *dtb)
|
||||||
|
{
|
||||||
|
int node;
|
||||||
|
const char *prop, *path;
|
||||||
|
int len;
|
||||||
|
|
||||||
|
/* The /secure-chosen node takes precedence over the standard one. */
|
||||||
|
node = fdt_path_offset(dtb, "/secure-chosen");
|
||||||
|
if (node < 0) {
|
||||||
|
node = fdt_path_offset(dtb, "/chosen");
|
||||||
|
if (node < 0) {
|
||||||
|
return -FDT_ERR_NOTFOUND;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
prop = fdt_getprop(dtb, node, "stdout-path", NULL);
|
||||||
|
if (prop == NULL) {
|
||||||
|
return -FDT_ERR_NOTFOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Determine the actual path length, as a colon terminates the path. */
|
||||||
|
path = strchr(prop, ':');
|
||||||
|
if (path == NULL) {
|
||||||
|
len = strlen(prop);
|
||||||
|
} else {
|
||||||
|
len = path - prop;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Aliases cannot start with a '/', so it must be the actual path. */
|
||||||
|
if (prop[0] == '/') {
|
||||||
|
return fdt_path_offset_namelen(dtb, prop, len);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Lookup the alias, as this contains the actual path. */
|
||||||
|
path = fdt_get_alias_namelen(dtb, prop, len);
|
||||||
|
if (path == NULL) {
|
||||||
|
return -FDT_ERR_NOTFOUND;
|
||||||
|
}
|
||||||
|
|
||||||
|
return fdt_path_offset(dtb, path);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Only devices which are direct children of root node use CPU address domain.
|
||||||
|
* All other devices use addresses that are local to the device node and cannot
|
||||||
|
* directly used by CPU. Device tree provides an address translation mechanism
|
||||||
|
* through "ranges" property which provides mappings from local address space to
|
||||||
|
* parent address space. Since a device could be a child of a child node to the
|
||||||
|
* root node, there can be more than one level of address translation needed to
|
||||||
|
* map the device local address space to CPU address space.
|
||||||
|
* fdtw_translate_address() API performs address translation of a local address
|
||||||
|
* to a global address with help of various helper functions.
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
static bool fdtw_xlat_hit(const uint32_t *value, int child_addr_size,
|
||||||
|
int parent_addr_size, int range_size, uint64_t base_address,
|
||||||
|
uint64_t *translated_addr)
|
||||||
|
{
|
||||||
|
uint64_t local_address, parent_address, addr_range;
|
||||||
|
|
||||||
|
local_address = fdt_read_prop_cells(value, child_addr_size);
|
||||||
|
parent_address = fdt_read_prop_cells(value + child_addr_size,
|
||||||
|
parent_addr_size);
|
||||||
|
addr_range = fdt_read_prop_cells(value + child_addr_size +
|
||||||
|
parent_addr_size,
|
||||||
|
range_size);
|
||||||
|
VERBOSE("DT: Address %" PRIx64 " mapped to %" PRIx64 " with range %" PRIx64 "\n",
|
||||||
|
local_address, parent_address, addr_range);
|
||||||
|
|
||||||
|
/* Perform range check */
|
||||||
|
if ((base_address < local_address) ||
|
||||||
|
(base_address >= local_address + addr_range)) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Found hit for the addr range that needs to be translated */
|
||||||
|
*translated_addr = parent_address + (base_address - local_address);
|
||||||
|
VERBOSE("DT: child address %" PRIx64 "mapped to %" PRIx64 " in parent bus\n",
|
||||||
|
local_address, parent_address);
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define ILLEGAL_ADDR ULL(~0)
|
||||||
|
|
||||||
|
static uint64_t fdtw_search_all_xlat_entries(const void *dtb,
|
||||||
|
const struct fdt_property *ranges_prop,
|
||||||
|
int local_bus, uint64_t base_address)
|
||||||
|
{
|
||||||
|
uint64_t translated_addr;
|
||||||
|
const uint32_t *next_entry;
|
||||||
|
int parent_bus_node, nxlat_entries, length;
|
||||||
|
int self_addr_cells, parent_addr_cells, self_size_cells, ncells_xlat;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The number of cells in one translation entry in ranges is the sum of
|
||||||
|
* the following values:
|
||||||
|
* self#address-cells + parent#address-cells + self#size-cells
|
||||||
|
* Ex: the iofpga ranges property has one translation entry with 4 cells
|
||||||
|
* They represent iofpga#addr-cells + motherboard#addr-cells + iofpga#size-cells
|
||||||
|
* = 1 + 2 + 1
|
||||||
|
*/
|
||||||
|
|
||||||
|
parent_bus_node = fdt_parent_offset(dtb, local_bus);
|
||||||
|
self_addr_cells = fdt_address_cells(dtb, local_bus);
|
||||||
|
self_size_cells = fdt_size_cells(dtb, local_bus);
|
||||||
|
parent_addr_cells = fdt_address_cells(dtb, parent_bus_node);
|
||||||
|
|
||||||
|
/* Number of cells per translation entry i.e., mapping */
|
||||||
|
ncells_xlat = self_addr_cells + parent_addr_cells + self_size_cells;
|
||||||
|
|
||||||
|
assert(ncells_xlat > 0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Find the number of translations(mappings) specified in the current
|
||||||
|
* `ranges` property. Note that length represents number of bytes and
|
||||||
|
* is stored in big endian mode.
|
||||||
|
*/
|
||||||
|
length = fdt32_to_cpu(ranges_prop->len);
|
||||||
|
nxlat_entries = (length/sizeof(uint32_t))/ncells_xlat;
|
||||||
|
|
||||||
|
assert(nxlat_entries > 0);
|
||||||
|
|
||||||
|
next_entry = (const uint32_t *)ranges_prop->data;
|
||||||
|
|
||||||
|
/* Iterate over the entries in the "ranges" */
|
||||||
|
for (int i = 0; i < nxlat_entries; i++) {
|
||||||
|
if (fdtw_xlat_hit(next_entry, self_addr_cells,
|
||||||
|
parent_addr_cells, self_size_cells, base_address,
|
||||||
|
&translated_addr)){
|
||||||
|
return translated_addr;
|
||||||
|
}
|
||||||
|
next_entry = next_entry + ncells_xlat;
|
||||||
|
}
|
||||||
|
|
||||||
|
INFO("DT: No translation found for address %" PRIx64 " in node %s\n",
|
||||||
|
base_address, fdt_get_name(dtb, local_bus, NULL));
|
||||||
|
return ILLEGAL_ADDR;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* address mapping needs to be done recursively starting from current node to
|
||||||
|
* root node through all intermediate parent nodes.
|
||||||
|
* Sample device tree is shown here:
|
||||||
|
|
||||||
|
smb@0,0 {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||||
|
<1 0 0 0x14000000 0x04000000>,
|
||||||
|
<2 0 0 0x18000000 0x04000000>,
|
||||||
|
<3 0 0 0x1c000000 0x04000000>,
|
||||||
|
<4 0 0 0x0c000000 0x04000000>,
|
||||||
|
<5 0 0 0x10000000 0x04000000>;
|
||||||
|
|
||||||
|
motherboard {
|
||||||
|
arm,v2m-memory-map = "rs1";
|
||||||
|
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
iofpga@3,00000000 {
|
||||||
|
compatible = "arm,amba-bus", "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 3 0 0x200000>;
|
||||||
|
v2m_serial1: uart@a0000 {
|
||||||
|
compatible = "arm,pl011", "arm,primecell";
|
||||||
|
reg = <0x0a0000 0x1000>;
|
||||||
|
interrupts = <0 6 4>;
|
||||||
|
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||||
|
clock-names = "uartclk", "apb_pclk";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
* As seen above, there are 3 levels of address translations needed. An empty
|
||||||
|
* `ranges` property denotes identity mapping (as seen in `motherboard` node).
|
||||||
|
* Each ranges property can map a set of child addresses to parent bus. Hence
|
||||||
|
* there can be more than 1 (translation) entry in the ranges property as seen
|
||||||
|
* in the `smb` node which has 6 translation entries.
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/* Recursive implementation */
|
||||||
|
uint64_t fdtw_translate_address(const void *dtb, int node,
|
||||||
|
uint64_t base_address)
|
||||||
|
{
|
||||||
|
int length, local_bus_node;
|
||||||
|
const char *node_name;
|
||||||
|
uint64_t global_address;
|
||||||
|
|
||||||
|
local_bus_node = fdt_parent_offset(dtb, node);
|
||||||
|
node_name = fdt_get_name(dtb, local_bus_node, NULL);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* In the example given above, starting from the leaf node:
|
||||||
|
* uart@a000 represents the current node
|
||||||
|
* iofpga@3,00000000 represents the local bus
|
||||||
|
* motherboard represents the parent bus
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Read the ranges property */
|
||||||
|
const struct fdt_property *property = fdt_get_property(dtb,
|
||||||
|
local_bus_node, "ranges", &length);
|
||||||
|
|
||||||
|
if (property == NULL) {
|
||||||
|
if (local_bus_node == 0) {
|
||||||
|
/*
|
||||||
|
* root node doesn't have range property as addresses
|
||||||
|
* are in CPU address space.
|
||||||
|
*/
|
||||||
|
return base_address;
|
||||||
|
}
|
||||||
|
INFO("DT: Couldn't find ranges property in node %s\n",
|
||||||
|
node_name);
|
||||||
|
return ILLEGAL_ADDR;
|
||||||
|
} else if (length == 0) {
|
||||||
|
/* empty ranges indicates identity map to parent bus */
|
||||||
|
return fdtw_translate_address(dtb, local_bus_node, base_address);
|
||||||
|
}
|
||||||
|
|
||||||
|
VERBOSE("DT: Translation lookup in node %s at offset %d\n", node_name,
|
||||||
|
local_bus_node);
|
||||||
|
global_address = fdtw_search_all_xlat_entries(dtb, property,
|
||||||
|
local_bus_node, base_address);
|
||||||
|
|
||||||
|
if (global_address == ILLEGAL_ADDR) {
|
||||||
|
return ILLEGAL_ADDR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Translate the local device address recursively */
|
||||||
|
return fdtw_translate_address(dtb, local_bus_node, global_address);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For every CPU node (`/cpus/cpu@n`) in an FDT, execute a callback passing a
|
||||||
|
* pointer to the FDT and the offset of the CPU node. If the return value of the
|
||||||
|
* callback is negative, it is treated as an error and the loop is aborted. In
|
||||||
|
* this situation, the value of the callback is returned from the function.
|
||||||
|
*
|
||||||
|
* Returns `0` on success, or a negative integer representing an error code.
|
||||||
|
*/
|
||||||
|
int fdtw_for_each_cpu(const void *dtb,
|
||||||
|
int (*callback)(const void *dtb, int node, uintptr_t mpidr))
|
||||||
|
{
|
||||||
|
int ret = 0;
|
||||||
|
int parent, node = 0;
|
||||||
|
|
||||||
|
parent = fdt_path_offset(dtb, "/cpus");
|
||||||
|
if (parent < 0) {
|
||||||
|
return parent;
|
||||||
|
}
|
||||||
|
|
||||||
|
fdt_for_each_subnode(node, dtb, parent) {
|
||||||
|
const char *name;
|
||||||
|
int len;
|
||||||
|
|
||||||
|
uintptr_t mpidr = 0U;
|
||||||
|
|
||||||
|
name = fdt_get_name(dtb, node, &len);
|
||||||
|
if (strncmp(name, "cpu@", 4) != 0) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = fdt_get_reg_props_by_index(dtb, node, 0, &mpidr, NULL);
|
||||||
|
if (ret < 0) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = callback(dtb, node, mpidr);
|
||||||
|
if (ret < 0) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Find a given node in device tree. If not present, add it.
|
||||||
|
* Returns offset of node found/added on success, and < 0 on error.
|
||||||
|
*/
|
||||||
|
int fdtw_find_or_add_subnode(void *fdt, int parentoffset, const char *name)
|
||||||
|
{
|
||||||
|
int offset;
|
||||||
|
|
||||||
|
offset = fdt_subnode_offset(fdt, parentoffset, name);
|
||||||
|
|
||||||
|
if (offset == -FDT_ERR_NOTFOUND) {
|
||||||
|
offset = fdt_add_subnode(fdt, parentoffset, name);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (offset < 0) {
|
||||||
|
ERROR("%s: %s: %s\n", __func__, name, fdt_strerror(offset));
|
||||||
|
}
|
||||||
|
|
||||||
|
return offset;
|
||||||
|
}
|
||||||
7
arm-trusted-firmware/common/fdt_wrappers.mk
Normal file
7
arm-trusted-firmware/common/fdt_wrappers.mk
Normal file
@@ -0,0 +1,7 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
|
||||||
|
FDT_WRAPPERS_SOURCES := common/fdt_wrappers.c
|
||||||
334
arm-trusted-firmware/common/feat_detect.c
Normal file
334
arm-trusted-firmware/common/feat_detect.c
Normal file
@@ -0,0 +1,334 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common/feat_detect.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This section lists the wrapper modules for each feature to evaluate the
|
||||||
|
* feature states (FEAT_STATE_1 and FEAT_STATE_2) and perform necessary action
|
||||||
|
* as below:
|
||||||
|
*
|
||||||
|
* It verifies whether the FEAT_XXX (eg: FEAT_SB) is supported by the PE or not.
|
||||||
|
* Without this check an exception would occur during context save/restore
|
||||||
|
* routines, if the feature is enabled but not supported by PE.
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/******************************************
|
||||||
|
* Feature : FEAT_SB (Speculation Barrier)
|
||||||
|
*****************************************/
|
||||||
|
static void read_feat_sb(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_SB == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_0_feat_sb_present(), "SB");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************
|
||||||
|
* Feature : FEAT_CSV2_2 (Cache Speculation Variant 2)
|
||||||
|
*****************************************************/
|
||||||
|
static void read_feat_csv2_2(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_0_feat_csv2_2_present(), "CSV2_2");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/***********************************************
|
||||||
|
* Feature : FEAT_PAN (Privileged Access Never)
|
||||||
|
**********************************************/
|
||||||
|
static void read_feat_pan(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_PAN == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_1_pan_present(), "PAN");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************
|
||||||
|
* Feature : FEAT_VHE (Virtualization Host Extensions)
|
||||||
|
*****************************************************/
|
||||||
|
static void read_feat_vhe(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_VHE == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_1_vhe_present(), "VHE");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Feature : FEAT_RAS (Reliability, Availability, and Serviceability Extension)
|
||||||
|
******************************************************************************/
|
||||||
|
static void read_feat_ras(void)
|
||||||
|
{
|
||||||
|
#if (RAS_EXTENSION == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_2_feat_ras_present(), "RAS");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/************************************************
|
||||||
|
* Feature : FEAT_PAUTH (Pointer Authentication)
|
||||||
|
***********************************************/
|
||||||
|
static void read_feat_pauth(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_PAUTH == FEAT_STATE_1) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_3_pauth_present(), "PAUTH");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/************************************************************
|
||||||
|
* Feature : FEAT_DIT (Data Independent Timing Instructions)
|
||||||
|
***********************************************************/
|
||||||
|
static void read_feat_dit(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_DIT == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_4_feat_dit_present(), "DIT");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************
|
||||||
|
* Feature : FEAT_AMUv1 (Activity Monitors Extensions v1)
|
||||||
|
********************************************************/
|
||||||
|
static void read_feat_amuv1(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_AMUv1 == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_4_feat_amuv1_present(), "AMUv1");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Feature : FEAT_MPAM (Memory Partitioning and Monitoring (MPAM) Extension)
|
||||||
|
***************************************************************************/
|
||||||
|
static void read_feat_mpam(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(get_mpam_version() != 0U, "MPAM");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************
|
||||||
|
* Feature : FEAT_NV2 (Enhanced Nested Virtualization Support)
|
||||||
|
*************************************************************/
|
||||||
|
static void read_feat_nv2(void)
|
||||||
|
{
|
||||||
|
#if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_1)
|
||||||
|
unsigned int nv = get_armv8_4_feat_nv_support();
|
||||||
|
|
||||||
|
feat_detect_panic((nv == ID_AA64MMFR2_EL1_NV2_SUPPORTED), "NV2");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/***********************************
|
||||||
|
* Feature : FEAT_SEL2 (Secure EL2)
|
||||||
|
**********************************/
|
||||||
|
static void read_feat_sel2(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_SEL2 == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_4_sel2_present(), "SEL2");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/****************************************************
|
||||||
|
* Feature : FEAT_TRF (Self-hosted Trace Extensions)
|
||||||
|
***************************************************/
|
||||||
|
static void read_feat_trf(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_TRF_FOR_NS == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_arm8_4_feat_trf_present(), "TRF");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/************************************************
|
||||||
|
* Feature : FEAT_MTE (Memory Tagging Extension)
|
||||||
|
***********************************************/
|
||||||
|
static void read_feat_mte(void)
|
||||||
|
{
|
||||||
|
#if (CTX_INCLUDE_MTE_REGS == FEAT_STATE_1)
|
||||||
|
unsigned int mte = get_armv8_5_mte_support();
|
||||||
|
|
||||||
|
feat_detect_panic((mte != MTE_UNIMPLEMENTED), "MTE");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/***********************************************
|
||||||
|
* Feature : FEAT_RNG (Random Number Generator)
|
||||||
|
**********************************************/
|
||||||
|
static void read_feat_rng(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_RNG == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_5_rng_present(), "RNG");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/****************************************************
|
||||||
|
* Feature : FEAT_BTI (Branch Target Identification)
|
||||||
|
***************************************************/
|
||||||
|
static void read_feat_bti(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_BTI == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_5_bti_present(), "BTI");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/****************************************
|
||||||
|
* Feature : FEAT_FGT (Fine Grain Traps)
|
||||||
|
***************************************/
|
||||||
|
static void read_feat_fgt(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_FGT == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_6_fgt_present(), "FGT");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/***********************************************
|
||||||
|
* Feature : FEAT_AMUv1p1 (AMU Extensions v1.1)
|
||||||
|
**********************************************/
|
||||||
|
static void read_feat_amuv1p1(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_6_feat_amuv1p1_present(), "AMUv1p1");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************
|
||||||
|
* Feature : FEAT_ECV (Enhanced Counter Virtualization)
|
||||||
|
******************************************************/
|
||||||
|
static void read_feat_ecv(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_ECV == FEAT_STATE_1)
|
||||||
|
unsigned int ecv = get_armv8_6_ecv_support();
|
||||||
|
|
||||||
|
feat_detect_panic(((ecv == ID_AA64MMFR0_EL1_ECV_SUPPORTED) ||
|
||||||
|
(ecv == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH)), "ECV");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/***********************************************************
|
||||||
|
* Feature : FEAT_TWED (Delayed Trapping of WFE Instruction)
|
||||||
|
**********************************************************/
|
||||||
|
static void read_feat_twed(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_TWED == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_armv8_6_twed_present(), "TWED");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************
|
||||||
|
* Feature : FEAT_HCX (Extended Hypervisor Configuration Register)
|
||||||
|
*****************************************************************/
|
||||||
|
static void read_feat_hcx(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_HCX == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_feat_hcx_present(), "HCX");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************
|
||||||
|
* Feature : FEAT_RME (Realm Management Extension)
|
||||||
|
*************************************************/
|
||||||
|
static void read_feat_rme(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_RME == FEAT_STATE_1)
|
||||||
|
feat_detect_panic((get_armv9_2_feat_rme_support() !=
|
||||||
|
ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED), "RME");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************
|
||||||
|
* Feature : FEAT_BRBE (Branch Record Buffer Extension)
|
||||||
|
*****************************************************/
|
||||||
|
static void read_feat_brbe(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_BRBE_FOR_NS == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_feat_brbe_present(), "BRBE");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************
|
||||||
|
* Feature : FEAT_TRBE (Trace Buffer Extension)
|
||||||
|
*****************************************************/
|
||||||
|
static void read_feat_trbe(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_TRBE_FOR_NS == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_feat_trbe_present(), "TRBE");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************
|
||||||
|
* Feature : FEAT_RNG_TRAP (Trapping support for RNDR/RNDRRS)
|
||||||
|
*****************************************************************/
|
||||||
|
static void read_feat_rng_trap(void)
|
||||||
|
{
|
||||||
|
#if (ENABLE_FEAT_RNG_TRAP == FEAT_STATE_1)
|
||||||
|
feat_detect_panic(is_feat_rng_trap_present(), "RNG_TRAP");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/***********************************************************************************
|
||||||
|
* TF-A supports many Arm architectural features starting from arch version
|
||||||
|
* (8.0 till 8.7+). These features are mostly enabled through build flags. This
|
||||||
|
* mechanism helps in validating these build flags in the early boot phase
|
||||||
|
* either in BL1 or BL31 depending on the platform and assists in identifying
|
||||||
|
* and notifying the features which are enabled but not supported by the PE.
|
||||||
|
*
|
||||||
|
* It reads all the enabled features ID-registers and ensures the features
|
||||||
|
* are supported by the PE.
|
||||||
|
* In case if they aren't it stops booting at an early phase and logs the error
|
||||||
|
* messages, notifying the platforms about the features that are not supported.
|
||||||
|
*
|
||||||
|
* Further the procedure is implemented with a tri-state approach for each feature:
|
||||||
|
* ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time
|
||||||
|
* ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware.
|
||||||
|
* There will be panic if feature is not present at cold boot.
|
||||||
|
* ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime
|
||||||
|
* depending on hardware capability.
|
||||||
|
*
|
||||||
|
* For better readability, state values are defined with macros namely:
|
||||||
|
* { FEAT_STATE_0, FEAT_STATE_1, FEAT_STATE_2 } taking values as their naming.
|
||||||
|
**********************************************************************************/
|
||||||
|
void detect_arch_features(void)
|
||||||
|
{
|
||||||
|
/* v8.0 features */
|
||||||
|
read_feat_sb();
|
||||||
|
read_feat_csv2_2();
|
||||||
|
|
||||||
|
/* v8.1 features */
|
||||||
|
read_feat_pan();
|
||||||
|
read_feat_vhe();
|
||||||
|
|
||||||
|
/* v8.2 features */
|
||||||
|
read_feat_ras();
|
||||||
|
|
||||||
|
/* v8.3 features */
|
||||||
|
read_feat_pauth();
|
||||||
|
|
||||||
|
/* v8.4 features */
|
||||||
|
read_feat_dit();
|
||||||
|
read_feat_amuv1();
|
||||||
|
read_feat_mpam();
|
||||||
|
read_feat_nv2();
|
||||||
|
read_feat_sel2();
|
||||||
|
read_feat_trf();
|
||||||
|
|
||||||
|
/* v8.5 features */
|
||||||
|
read_feat_mte();
|
||||||
|
read_feat_rng();
|
||||||
|
read_feat_bti();
|
||||||
|
read_feat_rng_trap();
|
||||||
|
|
||||||
|
/* v8.6 features */
|
||||||
|
read_feat_amuv1p1();
|
||||||
|
read_feat_fgt();
|
||||||
|
read_feat_ecv();
|
||||||
|
read_feat_twed();
|
||||||
|
|
||||||
|
/* v8.7 features */
|
||||||
|
read_feat_hcx();
|
||||||
|
|
||||||
|
/* v9.0 features */
|
||||||
|
read_feat_brbe();
|
||||||
|
read_feat_trbe();
|
||||||
|
|
||||||
|
/* v9.2 features */
|
||||||
|
read_feat_rme();
|
||||||
|
}
|
||||||
80
arm-trusted-firmware/common/image_decompress.c
Normal file
80
arm-trusted-firmware/common/image_decompress.c
Normal file
@@ -0,0 +1,80 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include <arch_helpers.h>
|
||||||
|
#include <common/bl_common.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <common/image_decompress.h>
|
||||||
|
|
||||||
|
static uintptr_t decompressor_buf_base;
|
||||||
|
static uint32_t decompressor_buf_size;
|
||||||
|
static decompressor_t *decompressor;
|
||||||
|
static struct image_info saved_image_info;
|
||||||
|
|
||||||
|
void image_decompress_init(uintptr_t buf_base, uint32_t buf_size,
|
||||||
|
decompressor_t *_decompressor)
|
||||||
|
{
|
||||||
|
decompressor_buf_base = buf_base;
|
||||||
|
decompressor_buf_size = buf_size;
|
||||||
|
decompressor = _decompressor;
|
||||||
|
}
|
||||||
|
|
||||||
|
void image_decompress_prepare(struct image_info *info)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* If the image is compressed, it should be loaded into the temporary
|
||||||
|
* buffer instead of its final destination. We save image_info, then
|
||||||
|
* override ->image_base and ->image_max_size so that load_image() will
|
||||||
|
* transfer the compressed data to the temporary buffer.
|
||||||
|
*/
|
||||||
|
saved_image_info = *info;
|
||||||
|
info->image_base = decompressor_buf_base;
|
||||||
|
info->image_max_size = decompressor_buf_size;
|
||||||
|
}
|
||||||
|
|
||||||
|
int image_decompress(struct image_info *info)
|
||||||
|
{
|
||||||
|
uintptr_t compressed_image_base, image_base, work_base;
|
||||||
|
uint32_t compressed_image_size, work_size;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The size of compressed data has been filled by load_image().
|
||||||
|
* Read it out before restoring image_info.
|
||||||
|
*/
|
||||||
|
compressed_image_size = info->image_size;
|
||||||
|
compressed_image_base = info->image_base;
|
||||||
|
*info = saved_image_info;
|
||||||
|
|
||||||
|
assert(compressed_image_size <= decompressor_buf_size);
|
||||||
|
|
||||||
|
image_base = info->image_base;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Use the rest of the temporary buffer as workspace of the
|
||||||
|
* decompressor since the decompressor may need additional memory.
|
||||||
|
*/
|
||||||
|
work_base = compressed_image_base + compressed_image_size;
|
||||||
|
work_size = decompressor_buf_size - compressed_image_size;
|
||||||
|
|
||||||
|
ret = decompressor(&compressed_image_base, compressed_image_size,
|
||||||
|
&image_base, info->image_max_size,
|
||||||
|
work_base, work_size);
|
||||||
|
if (ret) {
|
||||||
|
ERROR("Failed to decompress image (err=%d)\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* image_base is updated to the final pos when decompressor() exits. */
|
||||||
|
info->image_size = image_base - info->image_base;
|
||||||
|
|
||||||
|
flush_dcache_range(info->image_base, info->image_size);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
154
arm-trusted-firmware/common/runtime_svc.c
Normal file
154
arm-trusted-firmware/common/runtime_svc.c
Normal file
@@ -0,0 +1,154 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <common/runtime_svc.h>
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* The 'rt_svc_descs' array holds the runtime service descriptors exported by
|
||||||
|
* services by placing them in the 'rt_svc_descs' linker section.
|
||||||
|
* The 'rt_svc_descs_indices' array holds the index of a descriptor in the
|
||||||
|
* 'rt_svc_descs' array. When an SMC arrives, the OEN[29:24] bits and the call
|
||||||
|
* type[31] bit in the function id are combined to get an index into the
|
||||||
|
* 'rt_svc_descs_indices' array. This gives the index of the descriptor in the
|
||||||
|
* 'rt_svc_descs' array which contains the SMC handler.
|
||||||
|
******************************************************************************/
|
||||||
|
uint8_t rt_svc_descs_indices[MAX_RT_SVCS];
|
||||||
|
|
||||||
|
#define RT_SVC_DECS_NUM ((RT_SVC_DESCS_END - RT_SVC_DESCS_START)\
|
||||||
|
/ sizeof(rt_svc_desc_t))
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Function to invoke the registered `handle` corresponding to the smc_fid in
|
||||||
|
* AArch32 mode.
|
||||||
|
******************************************************************************/
|
||||||
|
uintptr_t handle_runtime_svc(uint32_t smc_fid,
|
||||||
|
void *cookie,
|
||||||
|
void *handle,
|
||||||
|
unsigned int flags)
|
||||||
|
{
|
||||||
|
u_register_t x1, x2, x3, x4;
|
||||||
|
unsigned int index;
|
||||||
|
unsigned int idx;
|
||||||
|
const rt_svc_desc_t *rt_svc_descs;
|
||||||
|
|
||||||
|
assert(handle != NULL);
|
||||||
|
idx = get_unique_oen_from_smc_fid(smc_fid);
|
||||||
|
assert(idx < MAX_RT_SVCS);
|
||||||
|
|
||||||
|
index = rt_svc_descs_indices[idx];
|
||||||
|
if (index >= RT_SVC_DECS_NUM)
|
||||||
|
SMC_RET1(handle, SMC_UNK);
|
||||||
|
|
||||||
|
rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START;
|
||||||
|
|
||||||
|
get_smc_params_from_ctx(handle, x1, x2, x3, x4);
|
||||||
|
|
||||||
|
return rt_svc_descs[index].handle(smc_fid, x1, x2, x3, x4, cookie,
|
||||||
|
handle, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Simple routine to sanity check a runtime service descriptor before using it
|
||||||
|
******************************************************************************/
|
||||||
|
static int32_t validate_rt_svc_desc(const rt_svc_desc_t *desc)
|
||||||
|
{
|
||||||
|
if (desc == NULL)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (desc->start_oen > desc->end_oen)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (desc->end_oen >= OEN_LIMIT)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if ((desc->call_type != SMC_TYPE_FAST) &&
|
||||||
|
(desc->call_type != SMC_TYPE_YIELD))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
/* A runtime service having no init or handle function doesn't make sense */
|
||||||
|
if ((desc->init == NULL) && (desc->handle == NULL))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* This function calls the initialisation routine in the descriptor exported by
|
||||||
|
* a runtime service. Once a descriptor has been validated, its start & end
|
||||||
|
* owning entity numbers and the call type are combined to form a unique oen.
|
||||||
|
* The unique oen is used as an index into the 'rt_svc_descs_indices' array.
|
||||||
|
* The index of the runtime service descriptor is stored at this index.
|
||||||
|
******************************************************************************/
|
||||||
|
void __init runtime_svc_init(void)
|
||||||
|
{
|
||||||
|
int rc = 0;
|
||||||
|
uint8_t index, start_idx, end_idx;
|
||||||
|
rt_svc_desc_t *rt_svc_descs;
|
||||||
|
|
||||||
|
/* Assert the number of descriptors detected are less than maximum indices */
|
||||||
|
assert((RT_SVC_DESCS_END >= RT_SVC_DESCS_START) &&
|
||||||
|
(RT_SVC_DECS_NUM < MAX_RT_SVCS));
|
||||||
|
|
||||||
|
/* If no runtime services are implemented then simply bail out */
|
||||||
|
if (RT_SVC_DECS_NUM == 0U)
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* Initialise internal variables to invalid state */
|
||||||
|
(void)memset(rt_svc_descs_indices, -1, sizeof(rt_svc_descs_indices));
|
||||||
|
|
||||||
|
rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START;
|
||||||
|
for (index = 0U; index < RT_SVC_DECS_NUM; index++) {
|
||||||
|
rt_svc_desc_t *service = &rt_svc_descs[index];
|
||||||
|
|
||||||
|
/*
|
||||||
|
* An invalid descriptor is an error condition since it is
|
||||||
|
* difficult to predict the system behaviour in the absence
|
||||||
|
* of this service.
|
||||||
|
*/
|
||||||
|
rc = validate_rt_svc_desc(service);
|
||||||
|
if (rc != 0) {
|
||||||
|
ERROR("Invalid runtime service descriptor %p\n",
|
||||||
|
(void *) service);
|
||||||
|
panic();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The runtime service may have separate rt_svc_desc_t
|
||||||
|
* for its fast smc and yielding smc. Since the service itself
|
||||||
|
* need to be initialized only once, only one of them will have
|
||||||
|
* an initialisation routine defined. Call the initialisation
|
||||||
|
* routine for this runtime service, if it is defined.
|
||||||
|
*/
|
||||||
|
if (service->init != NULL) {
|
||||||
|
rc = service->init();
|
||||||
|
if (rc != 0) {
|
||||||
|
ERROR("Error initializing runtime service %s\n",
|
||||||
|
service->name);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Fill the indices corresponding to the start and end
|
||||||
|
* owning entity numbers with the index of the
|
||||||
|
* descriptor which will handle the SMCs for this owning
|
||||||
|
* entity range.
|
||||||
|
*/
|
||||||
|
start_idx = (uint8_t)get_unique_oen(service->start_oen,
|
||||||
|
service->call_type);
|
||||||
|
end_idx = (uint8_t)get_unique_oen(service->end_oen,
|
||||||
|
service->call_type);
|
||||||
|
assert(start_idx <= end_idx);
|
||||||
|
assert(end_idx < MAX_RT_SVCS);
|
||||||
|
for (; start_idx <= end_idx; start_idx++)
|
||||||
|
rt_svc_descs_indices[start_idx] = index;
|
||||||
|
}
|
||||||
|
}
|
||||||
45
arm-trusted-firmware/common/tf_crc32.c
Normal file
45
arm-trusted-firmware/common/tf_crc32.c
Normal file
@@ -0,0 +1,45 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdarg.h>
|
||||||
|
#include <assert.h>
|
||||||
|
|
||||||
|
#include <arm_acle.h>
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <common/tf_crc32.h>
|
||||||
|
|
||||||
|
/* compute CRC using Arm intrinsic function
|
||||||
|
*
|
||||||
|
* This function is useful for the platforms with the CPU ARMv8.0
|
||||||
|
* (with CRC instructions supported), and onwards.
|
||||||
|
* Platforms with CPU ARMv8.0 should make sure to add a compile switch
|
||||||
|
* '-march=armv8-a+crc" for successful compilation of this file.
|
||||||
|
*
|
||||||
|
* @crc: previous accumulated CRC
|
||||||
|
* @buf: buffer base address
|
||||||
|
* @size: the size of the buffer
|
||||||
|
*
|
||||||
|
* Return calculated CRC value
|
||||||
|
*/
|
||||||
|
uint32_t tf_crc32(uint32_t crc, const unsigned char *buf, size_t size)
|
||||||
|
{
|
||||||
|
assert(buf != NULL);
|
||||||
|
|
||||||
|
uint32_t calc_crc = ~crc;
|
||||||
|
const unsigned char *local_buf = buf;
|
||||||
|
size_t local_size = size;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* calculate CRC over byte data
|
||||||
|
*/
|
||||||
|
while (local_size != 0UL) {
|
||||||
|
calc_crc = __crc32b(calc_crc, *local_buf);
|
||||||
|
local_buf++;
|
||||||
|
local_size--;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ~calc_crc;
|
||||||
|
}
|
||||||
79
arm-trusted-firmware/common/tf_log.c
Normal file
79
arm-trusted-firmware/common/tf_log.c
Normal file
@@ -0,0 +1,79 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdarg.h>
|
||||||
|
#include <assert.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <plat/common/platform.h>
|
||||||
|
|
||||||
|
/* Set the default maximum log level to the `LOG_LEVEL` build flag */
|
||||||
|
static unsigned int max_log_level = LOG_LEVEL;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The common log function which is invoked by TF-A code.
|
||||||
|
* This function should not be directly invoked and is meant to be
|
||||||
|
* only used by the log macros defined in debug.h. The function
|
||||||
|
* expects the first character in the format string to be one of the
|
||||||
|
* LOG_MARKER_* macros defined in debug.h.
|
||||||
|
*/
|
||||||
|
void tf_log(const char *fmt, ...)
|
||||||
|
{
|
||||||
|
unsigned int log_level;
|
||||||
|
va_list args;
|
||||||
|
const char *prefix_str;
|
||||||
|
|
||||||
|
/* We expect the LOG_MARKER_* macro as the first character */
|
||||||
|
log_level = fmt[0];
|
||||||
|
|
||||||
|
/* Verify that log_level is one of LOG_MARKER_* macro defined in debug.h */
|
||||||
|
assert((log_level > 0U) && (log_level <= LOG_LEVEL_VERBOSE));
|
||||||
|
assert((log_level % 10U) == 0U);
|
||||||
|
|
||||||
|
if (log_level > max_log_level)
|
||||||
|
return;
|
||||||
|
|
||||||
|
prefix_str = plat_log_get_prefix(log_level);
|
||||||
|
|
||||||
|
while (*prefix_str != '\0') {
|
||||||
|
(void)putchar(*prefix_str);
|
||||||
|
prefix_str++;
|
||||||
|
}
|
||||||
|
|
||||||
|
va_start(args, fmt);
|
||||||
|
(void)vprintf(fmt + 1, args);
|
||||||
|
va_end(args);
|
||||||
|
}
|
||||||
|
|
||||||
|
void tf_log_newline(const char log_fmt[2])
|
||||||
|
{
|
||||||
|
unsigned int log_level = log_fmt[0];
|
||||||
|
|
||||||
|
/* Verify that log_level is one of LOG_MARKER_* macro defined in debug.h */
|
||||||
|
assert((log_level > 0U) && (log_level <= LOG_LEVEL_VERBOSE));
|
||||||
|
assert((log_level % 10U) == 0U);
|
||||||
|
|
||||||
|
if (log_level > max_log_level)
|
||||||
|
return;
|
||||||
|
|
||||||
|
putchar('\n');
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The helper function to set the log level dynamically by platform. The
|
||||||
|
* maximum log level is determined by `LOG_LEVEL` build flag at compile time
|
||||||
|
* and this helper can set a lower (or equal) log level than the one at compile.
|
||||||
|
*/
|
||||||
|
void tf_log_set_max_level(unsigned int log_level)
|
||||||
|
{
|
||||||
|
assert(log_level <= LOG_LEVEL_VERBOSE);
|
||||||
|
assert((log_level % 10U) == 0U);
|
||||||
|
|
||||||
|
/* Cap log_level to the compile time maximum. */
|
||||||
|
if (log_level <= (unsigned int)LOG_LEVEL)
|
||||||
|
max_log_level = log_level;
|
||||||
|
}
|
||||||
158
arm-trusted-firmware/common/uuid.c
Normal file
158
arm-trusted-firmware/common/uuid.c
Normal file
@@ -0,0 +1,158 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <common/uuid.h>
|
||||||
|
|
||||||
|
/* Return the hex nibble value of a char */
|
||||||
|
static int8_t hex_val(char hex)
|
||||||
|
{
|
||||||
|
int8_t val = 0;
|
||||||
|
|
||||||
|
if ((hex >= '0') && (hex <= '9')) {
|
||||||
|
val = (int8_t)(hex - '0');
|
||||||
|
} else if ((hex >= 'a') && (hex <= 'f')) {
|
||||||
|
val = (int8_t)(hex - 'a' + 0xa);
|
||||||
|
} else if ((hex >= 'A') && (hex <= 'F')) {
|
||||||
|
val = (int8_t)(hex - 'A' + 0xa);
|
||||||
|
} else {
|
||||||
|
val = -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read hex_src_len hex characters from hex_src, convert to bytes and
|
||||||
|
* store in buffer pointed to by dest
|
||||||
|
*/
|
||||||
|
static int read_hex(uint8_t *dest, char *hex_src, unsigned int hex_src_len)
|
||||||
|
{
|
||||||
|
int8_t nibble;
|
||||||
|
uint8_t byte;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The string length must be a multiple of 2 to represent an
|
||||||
|
* exact number of bytes.
|
||||||
|
*/
|
||||||
|
assert((hex_src_len % 2U) == 0U);
|
||||||
|
|
||||||
|
for (unsigned int i = 0U; i < (hex_src_len / 2U); i++) {
|
||||||
|
nibble = 0;
|
||||||
|
byte = 0U;
|
||||||
|
|
||||||
|
nibble = hex_val(hex_src[2U * i]);
|
||||||
|
if (nibble < 0) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
byte = (uint8_t)nibble;
|
||||||
|
byte <<= 4U;
|
||||||
|
|
||||||
|
nibble = hex_val(hex_src[(2U * i) + 1U]);
|
||||||
|
if (nibble < 0) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
byte |= (uint8_t)nibble;
|
||||||
|
|
||||||
|
*dest = byte;
|
||||||
|
dest++;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Parse UUIDs of the form aabbccdd-eeff-4099-8877-665544332211 */
|
||||||
|
int read_uuid(uint8_t *dest, char *uuid)
|
||||||
|
{
|
||||||
|
int err;
|
||||||
|
uint8_t *dest_start = dest;
|
||||||
|
|
||||||
|
/* Check that we have enough characters */
|
||||||
|
if (strnlen(uuid, UUID_STRING_LENGTH) != UUID_STRING_LENGTH) {
|
||||||
|
WARN("UUID string is too short\n");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* aabbccdd */
|
||||||
|
err = read_hex(dest, uuid, 8);
|
||||||
|
uuid += 8;
|
||||||
|
dest += 4;
|
||||||
|
|
||||||
|
/* Check for '-' */
|
||||||
|
err |= ((*uuid == '-') ? 0 : -1);
|
||||||
|
uuid++;
|
||||||
|
|
||||||
|
/* eeff */
|
||||||
|
err |= read_hex(dest, uuid, 4);
|
||||||
|
uuid += 4;
|
||||||
|
dest += 2;
|
||||||
|
|
||||||
|
/* Check for '-' */
|
||||||
|
err |= ((*uuid == '-') ? 0 : -1);
|
||||||
|
uuid++;
|
||||||
|
|
||||||
|
/* 4099 */
|
||||||
|
err |= read_hex(dest, uuid, 4);
|
||||||
|
uuid += 4;
|
||||||
|
dest += 2;
|
||||||
|
|
||||||
|
/* Check for '-' */
|
||||||
|
err |= ((*uuid == '-') ? 0 : -1);
|
||||||
|
uuid++;
|
||||||
|
|
||||||
|
/* 8877 */
|
||||||
|
err |= read_hex(dest, uuid, 4);
|
||||||
|
uuid += 4;
|
||||||
|
dest += 2;
|
||||||
|
|
||||||
|
/* Check for '-' */
|
||||||
|
err |= ((*uuid == '-') ? 0 : -1);
|
||||||
|
uuid++;
|
||||||
|
|
||||||
|
/* 665544332211 */
|
||||||
|
err |= read_hex(dest, uuid, 12);
|
||||||
|
uuid += 12;
|
||||||
|
dest += 6;
|
||||||
|
|
||||||
|
if (err < 0) {
|
||||||
|
WARN("Error parsing UUID\n");
|
||||||
|
/* Clear the buffer on error */
|
||||||
|
memset((void *)dest_start, '\0', UUID_BYTES_LENGTH * sizeof(uint8_t));
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Helper function to check if 2 UUIDs match.
|
||||||
|
*/
|
||||||
|
bool uuid_match(uint32_t *uuid1, uint32_t *uuid2)
|
||||||
|
{
|
||||||
|
return !memcmp(uuid1, uuid2, sizeof(uint32_t) * 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Helper function to copy from one UUID struct to another.
|
||||||
|
*/
|
||||||
|
void copy_uuid(uint32_t *to_uuid, uint32_t *from_uuid)
|
||||||
|
{
|
||||||
|
to_uuid[0] = from_uuid[0];
|
||||||
|
to_uuid[1] = from_uuid[1];
|
||||||
|
to_uuid[2] = from_uuid[2];
|
||||||
|
to_uuid[3] = from_uuid[3];
|
||||||
|
}
|
||||||
|
|
||||||
|
bool is_null_uuid(uint32_t *uuid)
|
||||||
|
{
|
||||||
|
return (uuid[0] == 0 && uuid[1] == 0 &&
|
||||||
|
uuid[2] == 0 && uuid[3] == 0);
|
||||||
|
}
|
||||||
37
arm-trusted-firmware/dco.txt
Normal file
37
arm-trusted-firmware/dco.txt
Normal file
@@ -0,0 +1,37 @@
|
|||||||
|
Developer Certificate of Origin
|
||||||
|
Version 1.1
|
||||||
|
|
||||||
|
Copyright (C) 2004, 2006 The Linux Foundation and its contributors.
|
||||||
|
1 Letterman Drive
|
||||||
|
Suite D4700
|
||||||
|
San Francisco, CA, 94129
|
||||||
|
|
||||||
|
Everyone is permitted to copy and distribute verbatim copies of this
|
||||||
|
license document, but changing it is not allowed.
|
||||||
|
|
||||||
|
|
||||||
|
Developer's Certificate of Origin 1.1
|
||||||
|
|
||||||
|
By making a contribution to this project, I certify that:
|
||||||
|
|
||||||
|
(a) The contribution was created in whole or in part by me and I
|
||||||
|
have the right to submit it under the open source license
|
||||||
|
indicated in the file; or
|
||||||
|
|
||||||
|
(b) The contribution is based upon previous work that, to the best
|
||||||
|
of my knowledge, is covered under an appropriate open source
|
||||||
|
license and I have the right under that license to submit that
|
||||||
|
work with modifications, whether created in whole or in part
|
||||||
|
by me, under the same open source license (unless I am
|
||||||
|
permitted to submit under a different license), as indicated
|
||||||
|
in the file; or
|
||||||
|
|
||||||
|
(c) The contribution was provided directly to me by some other
|
||||||
|
person who certified (a), (b) or (c) and I have not modified
|
||||||
|
it.
|
||||||
|
|
||||||
|
(d) I understand and agree that this project and the contribution
|
||||||
|
are public and that a record of the contribution (including all
|
||||||
|
personal information I submit with it, including my sign-off) is
|
||||||
|
maintained indefinitely and may be redistributed consistent with
|
||||||
|
this project or the open source license(s) involved.
|
||||||
25
arm-trusted-firmware/docs/Makefile
Normal file
25
arm-trusted-firmware/docs/Makefile
Normal file
@@ -0,0 +1,25 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2019-2020, ARM Limited. All rights reserved.
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
#
|
||||||
|
# Minimal makefile for Sphinx documentation
|
||||||
|
#
|
||||||
|
|
||||||
|
# You can set these variables from the command line.
|
||||||
|
SPHINXOPTS = -W
|
||||||
|
SPHINXBUILD = sphinx-build
|
||||||
|
SPHINXPROJ = TrustedFirmware-A
|
||||||
|
SOURCEDIR = .
|
||||||
|
BUILDDIR = build
|
||||||
|
|
||||||
|
# Put it first so that "make" without argument is like "make help".
|
||||||
|
help:
|
||||||
|
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
|
||||||
|
|
||||||
|
.PHONY: help Makefile
|
||||||
|
|
||||||
|
# Catch-all target: route all unknown targets to Sphinx using the new
|
||||||
|
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
|
||||||
|
%: Makefile
|
||||||
|
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user