diff --git a/drivers/tegra/hwpm/Makefile.th500.soc.sources b/drivers/tegra/hwpm/Makefile.th500.soc.sources index 7d68fb7..c222174 100644 --- a/drivers/tegra/hwpm/Makefile.th500.soc.sources +++ b/drivers/tegra/hwpm/Makefile.th500.soc.sources @@ -43,4 +43,7 @@ nvhwpm-th500-soc-objs += hal/th500/soc/ip/mss_channel/th500_mss_channel.o ccflags-y += -DCONFIG_TH500_HWPM_IP_C2C nvhwpm-th500-objs += hal/th500/soc/ip/c2c/th500_c2c.o +ccflags-y += -DCONFIG_TH500_HWPM_IP_SMMU +nvhwpm-th500-soc-objs += hal/th500/soc/ip/smmu/th500_smmu.o + endif diff --git a/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h b/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h index 778a7e8..ee37d6b 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h +++ b/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h @@ -288,12 +288,16 @@ #define addr_map_rpg_pm_smmu3_limit_r() (0x13e67fffU) #define addr_map_rpg_pm_smmu4_base_r() (0x13e68000U) #define addr_map_rpg_pm_smmu4_limit_r() (0x13e68fffU) -#define addr_map_smmu0_base_r() (0x11000000U) -#define addr_map_smmu0_limit_r() (0x11ffffffU) -#define addr_map_smmu1_base_r() (0x12000000U) -#define addr_map_smmu1_limit_r() (0x12ffffffU) -#define addr_map_smmu2_base_r() (0x15000000U) -#define addr_map_smmu2_limit_r() (0x15ffffffU) +#define addr_map_smmu0_base_r() (0x11a30000U) +#define addr_map_smmu0_limit_r() (0x11a3ffffU) +#define addr_map_smmu1_base_r() (0x12a30000U) +#define addr_map_smmu1_limit_r() (0x12a3ffffU) +#define addr_map_smmu2_base_r() (0x15a30000U) +#define addr_map_smmu2_limit_r() (0x15a3ffffU) +#define addr_map_smmu3_base_r() (0x16a30000U) +#define addr_map_smmu3_limit_r() (0x16a3ffffU) +#define addr_map_smmu4_base_r() (0x05a30000U) +#define addr_map_smmu4_limit_r() (0x05a3ffffU) #define addr_map_rpg_pm_msshub0_base_r() (0x13e69000U) #define addr_map_rpg_pm_msshub0_limit_r() (0x13e69fffU) #define addr_map_rpg_pm_msshub1_base_r() (0x13e6a000U) diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/smmu/th500_smmu.c b/drivers/tegra/hwpm/hal/th500/soc/ip/smmu/th500_smmu.c new file mode 100644 index 0000000..a520a79 --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/smmu/th500_smmu.c @@ -0,0 +1,605 @@ +// SPDX-License-Identifier: MIT +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#include "th500_smmu.h" + +#include +#include +#include +#include + +static struct hwpm_ip_aperture th500_smmu_inst0_perfmon_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_smmu0", + .device_index = TH500_SMMU0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_smmu0_base_r(), + .end_abs_pa = addr_map_rpg_pm_smmu0_limit_r(), + .start_pa = addr_map_rpg_pm_smmu0_base_r(), + .end_pa = addr_map_rpg_pm_smmu0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_smmu_inst1_perfmon_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_smmu1", + .device_index = TH500_SMMU1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_smmu1_base_r(), + .end_abs_pa = addr_map_rpg_pm_smmu1_limit_r(), + .start_pa = addr_map_rpg_pm_smmu1_base_r(), + .end_pa = addr_map_rpg_pm_smmu1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_smmu_inst2_perfmon_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_smmu2", + .device_index = TH500_SMMU2_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_smmu2_base_r(), + .end_abs_pa = addr_map_rpg_pm_smmu2_limit_r(), + .start_pa = addr_map_rpg_pm_smmu2_base_r(), + .end_pa = addr_map_rpg_pm_smmu2_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_smmu_inst3_perfmon_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_smmu3", + .device_index = TH500_SMMU3_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_smmu3_base_r(), + .end_abs_pa = addr_map_rpg_pm_smmu3_limit_r(), + .start_pa = addr_map_rpg_pm_smmu3_base_r(), + .end_pa = addr_map_rpg_pm_smmu3_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_smmu_inst4_perfmon_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_smmu4", + .device_index = TH500_SMMU4_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_smmu4_base_r(), + .end_abs_pa = addr_map_rpg_pm_smmu4_limit_r(), + .start_pa = addr_map_rpg_pm_smmu4_base_r(), + .end_pa = addr_map_rpg_pm_smmu4_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_smmu_inst0_perfmux_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_smmu0_base_r(), + .end_abs_pa = addr_map_smmu0_limit_r(), + .start_pa = addr_map_smmu0_base_r(), + .end_pa = addr_map_smmu0_limit_r(), + .base_pa = 0ULL, + .alist = th500_smmu_alist, + .alist_size = ARRAY_SIZE(th500_smmu_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_smmu_inst1_perfmux_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_smmu1_base_r(), + .end_abs_pa = addr_map_smmu1_limit_r(), + .start_pa = addr_map_smmu1_base_r(), + .end_pa = addr_map_smmu1_limit_r(), + .base_pa = 0ULL, + .alist = th500_smmu_alist, + .alist_size = ARRAY_SIZE(th500_smmu_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_smmu_inst2_perfmux_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_smmu2_base_r(), + .end_abs_pa = addr_map_smmu2_limit_r(), + .start_pa = addr_map_smmu2_base_r(), + .end_pa = addr_map_smmu2_limit_r(), + .base_pa = 0ULL, + .alist = th500_smmu_alist, + .alist_size = ARRAY_SIZE(th500_smmu_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_smmu_inst3_perfmux_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_smmu3_base_r(), + .end_abs_pa = addr_map_smmu3_limit_r(), + .start_pa = addr_map_smmu3_base_r(), + .end_pa = addr_map_smmu3_limit_r(), + .base_pa = 0ULL, + .alist = th500_smmu_alist, + .alist_size = ARRAY_SIZE(th500_smmu_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_smmu_inst4_perfmux_element_static_array[ + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_smmu4_base_r(), + .end_abs_pa = addr_map_smmu4_limit_r(), + .start_pa = addr_map_smmu4_base_r(), + .end_pa = addr_map_smmu4_limit_r(), + .base_pa = 0ULL, + .alist = th500_smmu_alist, + .alist_size = ARRAY_SIZE(th500_smmu_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +static struct hwpm_ip_inst th500_smmu_inst_static_array[ + TH500_HWPM_IP_SMMU_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .num_core_elements_per_inst = + TH500_HWPM_IP_SMMU_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_smmu_inst0_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_smmu0_base_r(), + .range_end = addr_map_smmu0_limit_r(), + .element_stride = addr_map_smmu0_limit_r() - + addr_map_smmu0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST, + .element_static_array = + th500_smmu_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_smmu0_base_r(), + .range_end = addr_map_rpg_pm_smmu0_limit_r(), + .element_stride = addr_map_rpg_pm_smmu0_limit_r() - + addr_map_rpg_pm_smmu0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(1), + .num_core_elements_per_inst = + TH500_HWPM_IP_SMMU_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_smmu_inst1_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_smmu1_base_r(), + .range_end = addr_map_smmu1_limit_r(), + .element_stride = addr_map_smmu1_limit_r() - + addr_map_smmu1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST, + .element_static_array = + th500_smmu_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_smmu1_base_r(), + .range_end = addr_map_rpg_pm_smmu1_limit_r(), + .element_stride = addr_map_rpg_pm_smmu1_limit_r() - + addr_map_rpg_pm_smmu1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(2), + .num_core_elements_per_inst = + TH500_HWPM_IP_SMMU_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_smmu_inst2_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_smmu2_base_r(), + .range_end = addr_map_smmu2_limit_r(), + .element_stride = addr_map_smmu2_limit_r() - + addr_map_smmu2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST, + .element_static_array = + th500_smmu_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_smmu2_base_r(), + .range_end = addr_map_rpg_pm_smmu2_limit_r(), + .element_stride = addr_map_rpg_pm_smmu2_limit_r() - + addr_map_rpg_pm_smmu2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(3), + .num_core_elements_per_inst = + TH500_HWPM_IP_SMMU_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_smmu_inst3_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_smmu3_base_r(), + .range_end = addr_map_smmu3_limit_r(), + .element_stride = addr_map_smmu3_limit_r() - + addr_map_smmu3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST, + .element_static_array = + th500_smmu_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_smmu3_base_r(), + .range_end = addr_map_rpg_pm_smmu3_limit_r(), + .element_stride = addr_map_rpg_pm_smmu3_limit_r() - + addr_map_rpg_pm_smmu3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(4), + .num_core_elements_per_inst = + TH500_HWPM_IP_SMMU_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_smmu_inst4_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_smmu4_base_r(), + .range_end = addr_map_smmu4_limit_r(), + .element_stride = addr_map_smmu4_limit_r() - + addr_map_smmu4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST, + .element_static_array = + th500_smmu_inst4_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_smmu4_base_r(), + .range_end = addr_map_rpg_pm_smmu4_limit_r(), + .element_stride = addr_map_rpg_pm_smmu4_limit_r() - + addr_map_rpg_pm_smmu4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, +}; + +/* IP structure */ +struct hwpm_ip th500_hwpm_ip_smmu = { + .num_instances = TH500_HWPM_IP_SMMU_NUM_INSTANCES, + .ip_inst_static_array = th500_smmu_inst_static_array, + + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + /* NOTE: range should be in ascending order */ + .range_start = addr_map_smmu4_base_r(), + .range_end = addr_map_smmu3_limit_r(), + .inst_stride = addr_map_smmu0_limit_r() - + addr_map_smmu0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_smmu0_base_r(), + .range_end = addr_map_rpg_pm_smmu4_limit_r(), + .inst_stride = addr_map_rpg_pm_smmu0_limit_r() - + addr_map_rpg_pm_smmu0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, + + .dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK, + .override_enable = false, + .inst_fs_mask = 0U, + .resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID, + .reserved = false, +}; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/smmu/th500_smmu.h b/drivers/tegra/hwpm/hal/th500/soc/ip/smmu/th500_smmu.h new file mode 100644 index 0000000..14921e0 --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/smmu/th500_smmu.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#ifndef TH500_HWPM_IP_SMMU_H +#define TH500_HWPM_IP_SMMU_H + +#if defined(CONFIG_TH500_HWPM_IP_SMMU) +#define TH500_HWPM_ACTIVE_IP_SMMU TH500_HWPM_IP_SMMU, + +/* This data should ideally be available in HW headers */ +#define TH500_HWPM_IP_SMMU_NUM_INSTANCES 5U +#define TH500_HWPM_IP_SMMU_NUM_CORE_ELEMENT_PER_INST 1U +#define TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST 1U +#define TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST 1U +#define TH500_HWPM_IP_SMMU_NUM_BROADCAST_PER_INST 0U + +extern struct hwpm_ip th500_hwpm_ip_smmu; + +#else +#define TH500_HWPM_ACTIVE_IP_SMMU +#endif + +#endif /* TH500_HWPM_IP_SMMU_H */ diff --git a/drivers/tegra/hwpm/hal/th500/th500_internal.h b/drivers/tegra/hwpm/hal/th500/th500_internal.h index 9c8302e..6ad6d30 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_internal.h +++ b/drivers/tegra/hwpm/hal/th500/th500_internal.h @@ -27,6 +27,7 @@ #include #include #include +#include #define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX @@ -35,6 +36,7 @@ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PMA) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_CHANNEL) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_C2C) \ + DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_SMMU) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX) #undef DEFINE_SOC_HWPM_ACTIVE_IP diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h index 68f8474..2622f4e 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm.h @@ -78,6 +78,7 @@ enum tegra_hwpm_ip_enum { TEGRA_HWPM_IP_MSS_MCF, TEGRA_HWPM_IP_APE, TEGRA_HWPM_IP_C2C, + TEGRA_HWPM_IP_SMMU, TERGA_HWPM_NUM_IPS }; @@ -107,6 +108,7 @@ enum tegra_hwpm_resource_enum { TEGRA_HWPM_RESOURCE_CMD_SLICE_RTR, TEGRA_HWPM_RESOURCE_APE, TEGRA_HWPM_RESOURCE_C2C, + TEGRA_HWPM_RESOURCE_SMMU, TERGA_HWPM_NUM_RESOURCES }; diff --git a/drivers/tegra/hwpm/os/linux/ip_utils.c b/drivers/tegra/hwpm/os/linux/ip_utils.c index 9c01b8d..31640dd 100644 --- a/drivers/tegra/hwpm/os/linux/ip_utils.c +++ b/drivers/tegra/hwpm/os/linux/ip_utils.c @@ -90,6 +90,9 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_IP_C2C: ip_enum_idx = TEGRA_HWPM_IP_C2C; break; + case TEGRA_SOC_HWPM_IP_SMMU: + ip_enum_idx = TEGRA_HWPM_IP_SMMU; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_ip %d is invalid", @@ -195,6 +198,9 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_RESOURCE_C2C: res_enum_idx = TEGRA_HWPM_RESOURCE_C2C; break; + case TEGRA_SOC_HWPM_RESOURCE_SMMU: + res_enum_idx = TEGRA_HWPM_RESOURCE_SMMU; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_resource %d is invalid", diff --git a/include/uapi/linux/tegra-soc-hwpm-uapi.h b/include/uapi/linux/tegra-soc-hwpm-uapi.h index 4ef52e7..d591fc3 100644 --- a/include/uapi/linux/tegra-soc-hwpm-uapi.h +++ b/include/uapi/linux/tegra-soc-hwpm-uapi.h @@ -45,6 +45,7 @@ enum tegra_soc_hwpm_ip { TEGRA_SOC_HWPM_IP_MSS_MCF, TEGRA_SOC_HWPM_IP_APE, TEGRA_SOC_HWPM_IP_C2C, + TEGRA_SOC_HWPM_IP_SMMU, TERGA_SOC_HWPM_NUM_IPS }; @@ -112,6 +113,7 @@ enum tegra_soc_hwpm_resource { TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR, TEGRA_SOC_HWPM_RESOURCE_APE, TEGRA_SOC_HWPM_RESOURCE_C2C, + TEGRA_SOC_HWPM_RESOURCE_SMMU, TERGA_SOC_HWPM_NUM_RESOURCES };