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tegra: hwpm: use kstable available APIS
- Some of the APIs are not available on stable kernel. Use kstable specific APIs with LINUX_KERNEL macro condition. - Temporarily comment functions that are not available on Kstable. - Next chip headers are renamed to accommodate more than one next chip. Update next chip includes in init.c and driver.c files. - Rename TEGRA_SOC_HWPM_IP_INACTIVE to TEGRA_HWPM_IP_INACTIVE to follow other macro/enum naming convention. - Use is_resource_active() HAL instead of chip specific function. - Create clock reset functions that will allow us to handle change in APIs on kstable. Jira THWPM-41 Change-Id: I55f58fa51cf9ae96ee9a9565942e68b3b2bb76ee Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2764840 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
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Vedashree Vidwans
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195
os/linux/clk_rst_utils.c
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195
os/linux/clk_rst_utils.c
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/reset.h>
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#include <linux/clk.h>
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#include <tegra_hwpm.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_soc.h>
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#include <tegra_hwpm_clk_rst.h>
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#include <os/linux/driver.h>
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#define LA_CLK_RATE 625000000UL
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int tegra_hwpm_clk_rst_prepare_impl(struct tegra_hwpm_os_linux *hwpm_linux)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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/*
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* Starting OOT config, clocks and resets are handled by UEFI layer
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* Hence, do nothing.
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*/
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return 0;
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#else
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int ret = 0;
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struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm;
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if (tegra_hwpm_is_platform_silicon()) {
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hwpm_linux->la_clk = devm_clk_get(hwpm_linux->dev, "la");
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if (IS_ERR(hwpm_linux->la_clk)) {
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tegra_hwpm_err(hwpm, "Missing la clock");
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ret = PTR_ERR(hwpm_linux->la_clk);
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goto fail;
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}
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hwpm_linux->la_parent_clk =
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devm_clk_get(hwpm_linux->dev, "parent");
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if (IS_ERR(hwpm_linux->la_parent_clk)) {
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tegra_hwpm_err(hwpm, "Missing la parent clk");
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ret = PTR_ERR(hwpm_linux->la_parent_clk);
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goto fail;
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}
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hwpm_linux->la_rst =
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devm_reset_control_get(hwpm_linux->dev, "la");
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if (IS_ERR(hwpm_linux->la_rst)) {
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tegra_hwpm_err(hwpm, "Missing la reset");
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ret = PTR_ERR(hwpm_linux->la_rst);
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goto fail;
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}
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hwpm_linux->hwpm_rst =
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devm_reset_control_get(hwpm_linux->dev, "hwpm");
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if (IS_ERR(hwpm_linux->hwpm_rst)) {
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tegra_hwpm_err(hwpm, "Missing hwpm reset");
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ret = PTR_ERR(hwpm_linux->hwpm_rst);
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goto fail;
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}
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}
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fail:
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return ret;
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#endif
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}
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int tegra_hwpm_clk_rst_set_rate_enable_impl(
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struct tegra_hwpm_os_linux *hwpm_linux)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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/*
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* Starting OOT config, clocks and resets are handled by UEFI layer
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* Hence, do nothing.
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*/
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return 0;
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#else
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int ret = 0;
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struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm;
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if (tegra_hwpm_is_platform_silicon()) {
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ret = reset_control_assert(hwpm_linux->hwpm_rst);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "hwpm reset assert failed");
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goto fail;
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}
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ret = reset_control_assert(hwpm_linux->la_rst);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "la reset assert failed");
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goto fail;
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}
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/* Set required parent for la_clk */
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if (hwpm_linux->la_clk && hwpm_linux->la_parent_clk) {
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ret = clk_set_parent(
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hwpm_linux->la_clk, hwpm_linux->la_parent_clk);
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if (ret < 0) {
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tegra_hwpm_err(hwpm,
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"la clk set parent failed");
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goto fail;
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}
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}
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/* set la_clk rate to 625 MHZ */
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ret = clk_set_rate(hwpm_linux->la_clk, LA_CLK_RATE);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "la clock set rate failed");
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goto fail;
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}
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ret = clk_prepare_enable(hwpm_linux->la_clk);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "la clock enable failed");
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goto fail;
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}
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ret = reset_control_deassert(hwpm_linux->la_rst);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "la reset deassert failed");
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goto fail;
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}
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ret = reset_control_deassert(hwpm_linux->hwpm_rst);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "hwpm reset deassert failed");
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goto fail;
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}
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}
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fail:
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return ret;
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#endif
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}
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int tegra_hwpm_clk_rst_disable_impl(struct tegra_hwpm_os_linux *hwpm_linux)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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/*
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* Starting OOT config, clocks and resets are handled by UEFI layer
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* Hence, do nothing.
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*/
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return 0;
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#else
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int ret = 0;
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struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm;
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if (tegra_hwpm_is_platform_silicon()) {
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ret = reset_control_assert(hwpm_linux->hwpm_rst);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "hwpm reset assert failed");
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goto fail;
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}
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ret = reset_control_assert(hwpm_linux->la_rst);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "la reset assert failed");
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goto fail;
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}
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clk_disable_unprepare(hwpm_linux->la_clk);
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}
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fail:
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return ret;
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#endif
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}
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void tegra_hwpm_clk_rst_release_impl(struct tegra_hwpm_os_linux *hwpm_linux)
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{
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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/*
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* Starting OOT config, clocks and resets are handled by UEFI layer
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* Hence, do nothing.
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*/
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#else
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if (tegra_hwpm_is_platform_silicon()) {
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if (hwpm_linux->la_clk) {
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devm_clk_put(hwpm_linux->dev, hwpm_linux->la_clk);
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}
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if (hwpm_linux->la_parent_clk) {
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devm_clk_put(hwpm_linux->dev,
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hwpm_linux->la_parent_clk);
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}
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if (hwpm_linux->la_rst) {
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reset_control_assert(hwpm_linux->la_rst);
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}
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if (hwpm_linux->hwpm_rst) {
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reset_control_assert(hwpm_linux->hwpm_rst);
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}
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}
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#endif
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}
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