From 1b8fd6fc4b402addcaca1fcd3964743e62a778b3 Mon Sep 17 00:00:00 2001 From: Vishal Aslot Date: Mon, 2 Oct 2023 23:08:37 +0000 Subject: [PATCH] tegra: hwpm: th500: Add support for PCIE This patch adds support for PCIE XTLQ, XTLRC, and XALRC performance monitoring in the driver. Bug 4287384 Signed-off-by: Vishal Aslot Change-Id: I0c07a6eb879b1bdc8d80bb085ef2bf58afbbd94b Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2990011 Reviewed-by: Vedashree Vidwans Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit --- drivers/tegra/hwpm/Makefile.th500.soc.sources | 5 + .../th500/soc/hw/th500_addr_map_soc_hwpm.h | 80 +- .../hal/th500/soc/ip/pcie/th500_pcie_xalrc.c | 1120 +++++++++++++++++ .../hal/th500/soc/ip/pcie/th500_pcie_xalrc.h | 48 + .../hal/th500/soc/ip/pcie/th500_pcie_xtlq.c | 1120 +++++++++++++++++ .../hal/th500/soc/ip/pcie/th500_pcie_xtlq.h | 48 + .../hal/th500/soc/ip/pcie/th500_pcie_xtlrc.c | 1120 +++++++++++++++++ .../hal/th500/soc/ip/pcie/th500_pcie_xtlrc.h | 48 + .../th500/soc/th500_soc_regops_allowlist.c | 10 +- .../th500/soc/th500_soc_regops_allowlist.h | 4 +- .../tegra/hwpm/hal/th500/th500_interface.c | 24 +- drivers/tegra/hwpm/hal/th500/th500_internal.h | 6 + drivers/tegra/hwpm/hal/th500/th500_ip.c | 4 +- drivers/tegra/hwpm/include/tegra_hwpm.h | 6 + drivers/tegra/hwpm/os/linux/ip_utils.c | 18 + include/uapi/linux/tegra-soc-hwpm-uapi.h | 6 + 16 files changed, 3639 insertions(+), 28 deletions(-) create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.c create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.h create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.c create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.h create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.c create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.h diff --git a/drivers/tegra/hwpm/Makefile.th500.soc.sources b/drivers/tegra/hwpm/Makefile.th500.soc.sources index 7a762e4..008b6b5 100644 --- a/drivers/tegra/hwpm/Makefile.th500.soc.sources +++ b/drivers/tegra/hwpm/Makefile.th500.soc.sources @@ -72,4 +72,9 @@ nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_clink/th500_mcf_clink.o ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_CORE nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_core/th500_mcf_core.o +ccflags-y += -DCONFIG_TH500_HWPM_IP_PCIE +nvhwpm-th500-soc-objs += hal/th500/soc/ip/pcie/th500_pcie_xalrc.o +nvhwpm-th500-soc-objs += hal/th500/soc/ip/pcie/th500_pcie_xtlrc.o +nvhwpm-th500-soc-objs += hal/th500/soc/ip/pcie/th500_pcie_xtlq.o + endif diff --git a/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h b/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h index d365910..3267b90 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h +++ b/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h @@ -486,26 +486,66 @@ #define addr_map_rpg_pm_xtlq8_limit_r() (0x13e1cfffU) #define addr_map_rpg_pm_xtlq9_base_r() (0x13e1d000U) #define addr_map_rpg_pm_xtlq9_limit_r() (0x13e1dfffU) -#define addr_map_pcie_c0_ctl0_base_r() (0x14080000U) -#define addr_map_pcie_c0_ctl0_limit_r() (0x1408ffffU) -#define addr_map_pcie_c1_ctl0_base_r() (0x140a0000U) -#define addr_map_pcie_c1_ctl0_limit_r() (0x140affffU) -#define addr_map_pcie_c2_ctl0_base_r() (0x140c0000U) -#define addr_map_pcie_c2_ctl0_limit_r() (0x140cffffU) -#define addr_map_pcie_c3_ctl0_base_r() (0x140e0000U) -#define addr_map_pcie_c3_ctl0_limit_r() (0x140effffU) -#define addr_map_pcie_c4_ctl0_base_r() (0x14100000U) -#define addr_map_pcie_c4_ctl0_limit_r() (0x1410ffffU) -#define addr_map_pcie_c5_ctl0_base_r() (0x14120000U) -#define addr_map_pcie_c5_ctl0_limit_r() (0x1412ffffU) -#define addr_map_pcie_c6_ctl0_base_r() (0x14140000U) -#define addr_map_pcie_c6_ctl0_limit_r() (0x1414ffffU) -#define addr_map_pcie_c7_ctl0_base_r() (0x14160000U) -#define addr_map_pcie_c7_ctl0_limit_r() (0x1416ffffU) -#define addr_map_pcie_c8_ctl0_base_r() (0x14180000U) -#define addr_map_pcie_c8_ctl0_limit_r() (0x1418ffffU) -#define addr_map_pcie_c9_ctl0_base_r() (0x141a0000U) -#define addr_map_pcie_c9_ctl0_limit_r() (0x141affffU) +#define addr_map_pcie_c0_ctl0_xalrc_base_r() (0x14080000U) +#define addr_map_pcie_c0_ctl0_xalrc_limit_r() (0x1408ffffU) +#define addr_map_pcie_c0_ctl1_xtlq_base_r() (0x14090000U) +#define addr_map_pcie_c0_ctl1_xtlq_limit_r() (0x1409ffffU) +#define addr_map_pcie_c1_ctl0_xalrc_base_r() (0x140a0000U) +#define addr_map_pcie_c1_ctl0_xalrc_limit_r() (0x140affffU) +#define addr_map_pcie_c1_ctl1_xtlq_base_r() (0x140b0000U) +#define addr_map_pcie_c1_ctl1_xtlq_limit_r() (0x140bffffU) +#define addr_map_pcie_c2_ctl0_xalrc_base_r() (0x140c0000U) +#define addr_map_pcie_c2_ctl0_xalrc_limit_r() (0x140cffffU) +#define addr_map_pcie_c2_ctl1_xtlq_base_r() (0x140d0000U) +#define addr_map_pcie_c2_ctl1_xtlq_limit_r() (0x140dffffU) +#define addr_map_pcie_c3_ctl0_xalrc_base_r() (0x140e0000U) +#define addr_map_pcie_c3_ctl0_xalrc_limit_r() (0x140effffU) +#define addr_map_pcie_c3_ctl1_xtlq_base_r() (0x140f0000U) +#define addr_map_pcie_c3_ctl1_xtlq_limit_r() (0x140fffffU) +#define addr_map_pcie_c4_ctl0_xalrc_base_r() (0x14100000U) +#define addr_map_pcie_c4_ctl0_xalrc_limit_r() (0x1410ffffU) +#define addr_map_pcie_c4_ctl1_xtlq_base_r() (0x14110000U) +#define addr_map_pcie_c4_ctl1_xtlq_limit_r() (0x1411ffffU) +#define addr_map_pcie_c5_ctl0_xalrc_base_r() (0x14120000U) +#define addr_map_pcie_c5_ctl0_xalrc_limit_r() (0x1412ffffU) +#define addr_map_pcie_c5_ctl1_xtlq_base_r() (0x14130000U) +#define addr_map_pcie_c5_ctl1_xtlq_limit_r() (0x1413ffffU) +#define addr_map_pcie_c6_ctl0_xalrc_base_r() (0x14140000U) +#define addr_map_pcie_c6_ctl0_xalrc_limit_r() (0x1414ffffU) +#define addr_map_pcie_c6_ctl1_xtlq_base_r() (0x14150000U) +#define addr_map_pcie_c6_ctl1_xtlq_limit_r() (0x1415ffffU) +#define addr_map_pcie_c7_ctl0_xalrc_base_r() (0x14160000U) +#define addr_map_pcie_c7_ctl0_xalrc_limit_r() (0x1416ffffU) +#define addr_map_pcie_c7_ctl1_xtlq_base_r() (0x14170000U) +#define addr_map_pcie_c7_ctl1_xtlq_limit_r() (0x1417ffffU) +#define addr_map_pcie_c8_ctl0_xalrc_base_r() (0x14180000U) +#define addr_map_pcie_c8_ctl0_xalrc_limit_r() (0x1418ffffU) +#define addr_map_pcie_c8_ctl1_xtlq_base_r() (0x14190000U) +#define addr_map_pcie_c8_ctl1_xtlq_limit_r() (0x1419ffffU) +#define addr_map_pcie_c9_ctl0_xalrc_base_r() (0x141a0000U) +#define addr_map_pcie_c9_ctl0_xalrc_limit_r() (0x141affffU) +#define addr_map_pcie_c9_ctl1_xtlq_base_r() (0x141b0000U) +#define addr_map_pcie_c9_ctl1_xtlq_limit_r() (0x141bffffU) +#define addr_map_pcie_c0_ctl0_xtlrc_base_r() (0x14083000U) +#define addr_map_pcie_c0_ctl0_xtlrc_limit_r() (0x14083fffU) +#define addr_map_pcie_c1_ctl0_xtlrc_base_r() (0x140a3000U) +#define addr_map_pcie_c1_ctl0_xtlrc_limit_r() (0x140a3fffU) +#define addr_map_pcie_c2_ctl0_xtlrc_base_r() (0x140c3000U) +#define addr_map_pcie_c2_ctl0_xtlrc_limit_r() (0x140c3fffU) +#define addr_map_pcie_c3_ctl0_xtlrc_base_r() (0x140e3000U) +#define addr_map_pcie_c3_ctl0_xtlrc_limit_r() (0x140e3fffU) +#define addr_map_pcie_c4_ctl0_xtlrc_base_r() (0x14103000U) +#define addr_map_pcie_c4_ctl0_xtlrc_limit_r() (0x14103fffU) +#define addr_map_pcie_c5_ctl0_xtlrc_base_r() (0x14123000U) +#define addr_map_pcie_c5_ctl0_xtlrc_limit_r() (0x14123fffU) +#define addr_map_pcie_c6_ctl0_xtlrc_base_r() (0x14143000U) +#define addr_map_pcie_c6_ctl0_xtlrc_limit_r() (0x14143fffU) +#define addr_map_pcie_c7_ctl0_xtlrc_base_r() (0x14163000U) +#define addr_map_pcie_c7_ctl0_xtlrc_limit_r() (0x14163fffU) +#define addr_map_pcie_c8_ctl0_xtlrc_base_r() (0x14183000U) +#define addr_map_pcie_c8_ctl0_xtlrc_limit_r() (0x14183fffU) +#define addr_map_pcie_c9_ctl0_xtlrc_base_r() (0x141a3000U) +#define addr_map_pcie_c9_ctl0_xtlrc_limit_r() (0x141a3fffU) #define addr_map_rpg_pm_ctc0_base_r() (0x13e8d000U) #define addr_map_rpg_pm_ctc0_limit_r() (0x13e8dfffU) #define addr_map_rpg_pm_ctc1_base_r() (0x13e8e000U) diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.c b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.c new file mode 100644 index 0000000..61b881c --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.c @@ -0,0 +1,1120 @@ +// SPDX-License-Identifier: MIT +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#include "th500_pcie_xalrc.h" + +#include +#include +#include +#include + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst0_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc0", + .device_index = TH500_XALRC0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc0_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc0_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc0_base_r(), + .end_pa = addr_map_rpg_pm_xalrc0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst1_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc1", + .device_index = TH500_XALRC1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc1_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc1_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc1_base_r(), + .end_pa = addr_map_rpg_pm_xalrc1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst2_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc2", + .device_index = TH500_XALRC2_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc2_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc2_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc2_base_r(), + .end_pa = addr_map_rpg_pm_xalrc2_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst3_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc3", + .device_index = TH500_XALRC3_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc3_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc3_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc3_base_r(), + .end_pa = addr_map_rpg_pm_xalrc3_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst4_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc4", + .device_index = TH500_XALRC4_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc4_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc4_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc4_base_r(), + .end_pa = addr_map_rpg_pm_xalrc4_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst5_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc5", + .device_index = TH500_XALRC5_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc5_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc5_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc5_base_r(), + .end_pa = addr_map_rpg_pm_xalrc5_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst6_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc6", + .device_index = TH500_XALRC6_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc6_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc6_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc6_base_r(), + .end_pa = addr_map_rpg_pm_xalrc6_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst7_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc7", + .device_index = TH500_XALRC7_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc7_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc7_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc7_base_r(), + .end_pa = addr_map_rpg_pm_xalrc7_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst8_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc8", + .device_index = TH500_XALRC8_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc8_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc8_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc8_base_r(), + .end_pa = addr_map_rpg_pm_xalrc8_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst9_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xalrc9", + .device_index = TH500_XALRC9_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xalrc9_base_r(), + .end_abs_pa = addr_map_rpg_pm_xalrc9_limit_r(), + .start_pa = addr_map_rpg_pm_xalrc9_base_r(), + .end_pa = addr_map_rpg_pm_xalrc9_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst0_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c0_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c0_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c0_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c0_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst1_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c1_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c1_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c1_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c1_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst2_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c2_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c2_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c2_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c2_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst3_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c3_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c3_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c3_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c3_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst4_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c4_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c4_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c4_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c4_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst5_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c5_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c5_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c5_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c5_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst6_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c6_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c6_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c6_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c6_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst7_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c7_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c7_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c7_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c7_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst8_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c8_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c8_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c8_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c8_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xalrc_inst9_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c9_ctl0_xalrc_base_r(), + .end_abs_pa = addr_map_pcie_c9_ctl0_xalrc_limit_r(), + .start_pa = addr_map_pcie_c9_ctl0_xalrc_base_r(), + .end_pa = addr_map_pcie_c9_ctl0_xalrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xalrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xalrc_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +static struct hwpm_ip_inst th500_pcie_xalrc_inst_static_array[ + TH500_HWPM_IP_PCIE_XALRC_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst0_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c0_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c0_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c0_ctl0_xalrc_limit_r() - + addr_map_pcie_c0_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc0_base_r(), + .range_end = addr_map_rpg_pm_xalrc0_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc0_limit_r() - + addr_map_rpg_pm_xalrc0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(1), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst1_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c1_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c1_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c1_ctl0_xalrc_limit_r() - + addr_map_pcie_c1_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc1_base_r(), + .range_end = addr_map_rpg_pm_xalrc1_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc1_limit_r() - + addr_map_rpg_pm_xalrc1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(2), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst2_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c2_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c2_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c2_ctl0_xalrc_limit_r() - + addr_map_pcie_c2_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc2_base_r(), + .range_end = addr_map_rpg_pm_xalrc2_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc2_limit_r() - + addr_map_rpg_pm_xalrc2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(3), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst3_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c3_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c3_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c3_ctl0_xalrc_limit_r() - + addr_map_pcie_c3_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc3_base_r(), + .range_end = addr_map_rpg_pm_xalrc3_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc3_limit_r() - + addr_map_rpg_pm_xalrc3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(4), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst4_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c4_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c4_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c4_ctl0_xalrc_limit_r() - + addr_map_pcie_c4_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst4_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc4_base_r(), + .range_end = addr_map_rpg_pm_xalrc4_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc4_limit_r() - + addr_map_rpg_pm_xalrc4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(5), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst5_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c5_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c5_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c5_ctl0_xalrc_limit_r() - + addr_map_pcie_c5_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst5_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc5_base_r(), + .range_end = addr_map_rpg_pm_xalrc5_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc5_limit_r() - + addr_map_rpg_pm_xalrc5_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(6), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst6_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c6_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c6_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c6_ctl0_xalrc_limit_r() - + addr_map_pcie_c6_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst6_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc6_base_r(), + .range_end = addr_map_rpg_pm_xalrc6_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc6_limit_r() - + addr_map_rpg_pm_xalrc6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(7), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst7_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c7_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c7_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c7_ctl0_xalrc_limit_r() - + addr_map_pcie_c7_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst7_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc7_base_r(), + .range_end = addr_map_rpg_pm_xalrc7_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc7_limit_r() - + addr_map_rpg_pm_xalrc7_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(8), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst8_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c8_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c8_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c8_ctl0_xalrc_limit_r() - + addr_map_pcie_c8_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst8_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc8_base_r(), + .range_end = addr_map_rpg_pm_xalrc8_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc8_limit_r() - + addr_map_rpg_pm_xalrc8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(9), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst9_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c9_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c9_ctl0_xalrc_limit_r(), + .element_stride = addr_map_pcie_c9_ctl0_xalrc_limit_r() - + addr_map_pcie_c9_ctl0_xalrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xalrc_inst9_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xalrc9_base_r(), + .range_end = addr_map_rpg_pm_xalrc9_limit_r(), + .element_stride = addr_map_rpg_pm_xalrc9_limit_r() - + addr_map_rpg_pm_xalrc9_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, +}; + +/* IP structure */ +struct hwpm_ip th500_hwpm_ip_pcie_xalrc = { + .num_instances = TH500_HWPM_IP_PCIE_XALRC_NUM_INSTANCES, + .ip_inst_static_array = th500_pcie_xalrc_inst_static_array, + + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c0_ctl0_xalrc_base_r(), + .range_end = addr_map_pcie_c9_ctl0_xalrc_limit_r(), + .inst_stride = addr_map_pcie_c0_ctl0_xalrc_limit_r() - + addr_map_pcie_c0_ctl0_xalrc_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_xalrc0_base_r(), + .range_end = addr_map_rpg_pm_xalrc9_limit_r(), + .inst_stride = addr_map_rpg_pm_xalrc0_limit_r() - + addr_map_rpg_pm_xalrc0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, + + .dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK, + .override_enable = false, + .inst_fs_mask = 0U, + .resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID, + .reserved = false, +}; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.h b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.h new file mode 100644 index 0000000..732fdb4 --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#ifndef TH500_HWPM_IP_PCIE_XALRC_H +#define TH500_HWPM_IP_PCIE_XALRC_H + +#if defined(CONFIG_TH500_HWPM_IP_PCIE) +#define TH500_HWPM_ACTIVE_IP_PCIE_XALRC TH500_HWPM_IP_PCIE_XALRC, + +/* This data should ideally be available in HW headers */ +#define TH500_HWPM_IP_PCIE_XALRC_NUM_INSTANCES 10U +#define TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST 1U +#define TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST 1U +#define TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST 1U +#define TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST 0U + +extern struct hwpm_ip th500_hwpm_ip_pcie_xalrc; + +#else +#define TH500_HWPM_ACTIVE_IP_PCIE_XALRC +#endif + +#endif /* TH500_HWPM_IP_PCIE_XALRC_H */ diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.c b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.c new file mode 100644 index 0000000..f9d229b --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.c @@ -0,0 +1,1120 @@ +// SPDX-License-Identifier: MIT +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#include "th500_pcie_xtlq.h" + +#include +#include +#include +#include + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst0_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq0", + .device_index = TH500_XTLQ0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq0_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq0_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq0_base_r(), + .end_pa = addr_map_rpg_pm_xtlq0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst1_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq1", + .device_index = TH500_XTLQ1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq1_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq1_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq1_base_r(), + .end_pa = addr_map_rpg_pm_xtlq1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst2_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq2", + .device_index = TH500_XTLQ2_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq2_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq2_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq2_base_r(), + .end_pa = addr_map_rpg_pm_xtlq2_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst3_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq3", + .device_index = TH500_XTLQ3_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq3_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq3_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq3_base_r(), + .end_pa = addr_map_rpg_pm_xtlq3_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst4_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq4", + .device_index = TH500_XTLQ4_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq4_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq4_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq4_base_r(), + .end_pa = addr_map_rpg_pm_xtlq4_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst5_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq5", + .device_index = TH500_XTLQ5_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq5_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq5_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq5_base_r(), + .end_pa = addr_map_rpg_pm_xtlq5_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst6_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq6", + .device_index = TH500_XTLQ6_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq6_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq6_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq6_base_r(), + .end_pa = addr_map_rpg_pm_xtlq6_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst7_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq7", + .device_index = TH500_XTLQ7_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq7_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq7_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq7_base_r(), + .end_pa = addr_map_rpg_pm_xtlq7_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst8_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq8", + .device_index = TH500_XTLQ8_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq8_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq8_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq8_base_r(), + .end_pa = addr_map_rpg_pm_xtlq8_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst9_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlq9", + .device_index = TH500_XTLQ9_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlq9_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlq9_limit_r(), + .start_pa = addr_map_rpg_pm_xtlq9_base_r(), + .end_pa = addr_map_rpg_pm_xtlq9_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst0_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c0_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c0_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c0_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c0_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst1_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c1_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c1_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c1_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c1_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst2_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c2_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c2_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c2_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c2_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst3_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c3_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c3_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c3_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c3_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst4_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c4_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c4_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c4_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c4_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst5_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c5_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c5_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c5_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c5_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst6_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c6_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c6_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c6_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c6_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst7_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c7_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c7_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c7_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c7_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst8_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c8_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c8_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c8_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c8_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlq_inst9_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c9_ctl1_xtlq_base_r(), + .end_abs_pa = addr_map_pcie_c9_ctl1_xtlq_limit_r(), + .start_pa = addr_map_pcie_c9_ctl1_xtlq_base_r(), + .end_pa = addr_map_pcie_c9_ctl1_xtlq_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlq_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlq_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +static struct hwpm_ip_inst th500_pcie_xtlq_inst_static_array[ + TH500_HWPM_IP_PCIE_XTLQ_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst0_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c0_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c0_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c0_ctl1_xtlq_limit_r() - + addr_map_pcie_c0_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq0_base_r(), + .range_end = addr_map_rpg_pm_xtlq0_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq0_limit_r() - + addr_map_rpg_pm_xtlq0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(1), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst1_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c1_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c1_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c1_ctl1_xtlq_limit_r() - + addr_map_pcie_c1_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq1_base_r(), + .range_end = addr_map_rpg_pm_xtlq1_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq1_limit_r() - + addr_map_rpg_pm_xtlq1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(2), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst2_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c2_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c2_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c2_ctl1_xtlq_limit_r() - + addr_map_pcie_c2_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq2_base_r(), + .range_end = addr_map_rpg_pm_xtlq2_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq2_limit_r() - + addr_map_rpg_pm_xtlq2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(3), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst3_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c3_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c3_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c3_ctl1_xtlq_limit_r() - + addr_map_pcie_c3_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq3_base_r(), + .range_end = addr_map_rpg_pm_xtlq3_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq3_limit_r() - + addr_map_rpg_pm_xtlq3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(4), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst4_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c4_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c4_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c4_ctl1_xtlq_limit_r() - + addr_map_pcie_c4_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst4_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq4_base_r(), + .range_end = addr_map_rpg_pm_xtlq4_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq4_limit_r() - + addr_map_rpg_pm_xtlq4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(5), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst5_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c5_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c5_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c5_ctl1_xtlq_limit_r() - + addr_map_pcie_c5_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst5_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq5_base_r(), + .range_end = addr_map_rpg_pm_xtlq5_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq5_limit_r() - + addr_map_rpg_pm_xtlq5_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(6), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst6_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c6_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c6_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c6_ctl1_xtlq_limit_r() - + addr_map_pcie_c6_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst6_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq6_base_r(), + .range_end = addr_map_rpg_pm_xtlq6_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq6_limit_r() - + addr_map_rpg_pm_xtlq6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(7), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst7_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c7_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c7_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c7_ctl1_xtlq_limit_r() - + addr_map_pcie_c7_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst7_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq7_base_r(), + .range_end = addr_map_rpg_pm_xtlq7_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq7_limit_r() - + addr_map_rpg_pm_xtlq7_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(8), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst8_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c8_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c8_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c8_ctl1_xtlq_limit_r() - + addr_map_pcie_c8_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst8_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq8_base_r(), + .range_end = addr_map_rpg_pm_xtlq8_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq8_limit_r() - + addr_map_rpg_pm_xtlq8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(9), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst9_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c9_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c9_ctl1_xtlq_limit_r(), + .element_stride = addr_map_pcie_c9_ctl1_xtlq_limit_r() - + addr_map_pcie_c9_ctl1_xtlq_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlq_inst9_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlq9_base_r(), + .range_end = addr_map_rpg_pm_xtlq9_limit_r(), + .element_stride = addr_map_rpg_pm_xtlq9_limit_r() - + addr_map_rpg_pm_xtlq9_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, +}; + +/* IP structure */ +struct hwpm_ip th500_hwpm_ip_pcie_xtlq = { + .num_instances = TH500_HWPM_IP_PCIE_XTLQ_NUM_INSTANCES, + .ip_inst_static_array = th500_pcie_xtlq_inst_static_array, + + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c0_ctl1_xtlq_base_r(), + .range_end = addr_map_pcie_c9_ctl1_xtlq_limit_r(), + .inst_stride = addr_map_pcie_c0_ctl1_xtlq_limit_r() - + addr_map_pcie_c0_ctl1_xtlq_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_xtlq0_base_r(), + .range_end = addr_map_rpg_pm_xtlq9_limit_r(), + .inst_stride = addr_map_rpg_pm_xtlq0_limit_r() - + addr_map_rpg_pm_xtlq0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, + + .dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK, + .override_enable = false, + .inst_fs_mask = 0U, + .resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID, + .reserved = false, +}; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.h b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.h new file mode 100644 index 0000000..caa87d0 --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#ifndef TH500_HWPM_IP_PCIE_XTLQ_H +#define TH500_HWPM_IP_PCIE_XTLQ_H + +#if defined(CONFIG_TH500_HWPM_IP_PCIE) +#define TH500_HWPM_ACTIVE_IP_PCIE_XTLQ TH500_HWPM_IP_PCIE_XTLQ, + +/* This data should ideally be available in HW headers */ +#define TH500_HWPM_IP_PCIE_XTLQ_NUM_INSTANCES 10U +#define TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST 1U +#define TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST 1U +#define TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST 1U +#define TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST 0U + +extern struct hwpm_ip th500_hwpm_ip_pcie_xtlq; + +#else +#define TH500_HWPM_ACTIVE_IP_PCIE_XTLQ +#endif + +#endif /* TH500_HWPM_IP_PCIE_XTLQ_H */ diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.c b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.c new file mode 100644 index 0000000..84aa635 --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.c @@ -0,0 +1,1120 @@ +// SPDX-License-Identifier: MIT +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#include "th500_pcie_xtlrc.h" + +#include +#include +#include +#include + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst0_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc0", + .device_index = TH500_XTLRC0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc0_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc0_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc0_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst1_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc1", + .device_index = TH500_XTLRC1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc1_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc1_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc1_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst2_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc2", + .device_index = TH500_XTLRC2_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc2_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc2_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc2_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc2_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst3_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc3", + .device_index = TH500_XTLRC3_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc3_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc3_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc3_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc3_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst4_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc4", + .device_index = TH500_XTLRC4_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc4_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc4_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc4_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc4_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst5_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc5", + .device_index = TH500_XTLRC5_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc5_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc5_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc5_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc5_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst6_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc6", + .device_index = TH500_XTLRC6_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc6_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc6_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc6_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc6_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst7_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc7", + .device_index = TH500_XTLRC7_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc7_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc7_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc7_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc7_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst8_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc8", + .device_index = TH500_XTLRC8_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc8_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc8_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc8_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc8_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst9_perfmon_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_pcie_xtlrc9", + .device_index = TH500_XTLRC9_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_xtlrc9_base_r(), + .end_abs_pa = addr_map_rpg_pm_xtlrc9_limit_r(), + .start_pa = addr_map_rpg_pm_xtlrc9_base_r(), + .end_pa = addr_map_rpg_pm_xtlrc9_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst0_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c0_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c0_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c0_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c0_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst1_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c1_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c1_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c1_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c1_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst2_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c2_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c2_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c2_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c2_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst3_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c3_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c3_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c3_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c3_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst4_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c4_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c4_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c4_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c4_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst5_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c5_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c5_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c5_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c5_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst6_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c6_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c6_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c6_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c6_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst7_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c7_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c7_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c7_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c7_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst8_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c8_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c8_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c8_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c8_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_pcie_xtlrc_inst9_perfmux_element_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c9_ctl0_xtlrc_base_r(), + .end_abs_pa = addr_map_pcie_c9_ctl0_xtlrc_limit_r(), + .start_pa = addr_map_pcie_c9_ctl0_xtlrc_base_r(), + .end_pa = addr_map_pcie_c9_ctl0_xtlrc_limit_r(), + .base_pa = 0ULL, + .alist = th500_pcie_xtlrc_alist, + .alist_size = ARRAY_SIZE(th500_pcie_xtlrc_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +static struct hwpm_ip_inst th500_pcie_xtlrc_inst_static_array[ + TH500_HWPM_IP_PCIE_XTLRC_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst0_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c0_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c0_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c0_ctl0_xtlrc_limit_r() - + addr_map_pcie_c0_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc0_base_r(), + .range_end = addr_map_rpg_pm_xtlrc0_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc0_limit_r() - + addr_map_rpg_pm_xtlrc0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(1), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst1_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c1_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c1_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c1_ctl0_xtlrc_limit_r() - + addr_map_pcie_c1_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc1_base_r(), + .range_end = addr_map_rpg_pm_xtlrc1_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc1_limit_r() - + addr_map_rpg_pm_xtlrc1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(2), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst2_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c2_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c2_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c2_ctl0_xtlrc_limit_r() - + addr_map_pcie_c2_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc2_base_r(), + .range_end = addr_map_rpg_pm_xtlrc2_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc2_limit_r() - + addr_map_rpg_pm_xtlrc2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(3), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst3_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c3_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c3_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c3_ctl0_xtlrc_limit_r() - + addr_map_pcie_c3_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc3_base_r(), + .range_end = addr_map_rpg_pm_xtlrc3_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc3_limit_r() - + addr_map_rpg_pm_xtlrc3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(4), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst4_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c4_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c4_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c4_ctl0_xtlrc_limit_r() - + addr_map_pcie_c4_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst4_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc4_base_r(), + .range_end = addr_map_rpg_pm_xtlrc4_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc4_limit_r() - + addr_map_rpg_pm_xtlrc4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(5), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst5_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c5_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c5_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c5_ctl0_xtlrc_limit_r() - + addr_map_pcie_c5_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst5_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc5_base_r(), + .range_end = addr_map_rpg_pm_xtlrc5_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc5_limit_r() - + addr_map_rpg_pm_xtlrc5_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(6), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst6_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c6_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c6_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c6_ctl0_xtlrc_limit_r() - + addr_map_pcie_c6_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst6_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc6_base_r(), + .range_end = addr_map_rpg_pm_xtlrc6_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc6_limit_r() - + addr_map_rpg_pm_xtlrc6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(7), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst7_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c7_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c7_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c7_ctl0_xtlrc_limit_r() - + addr_map_pcie_c7_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst7_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc7_base_r(), + .range_end = addr_map_rpg_pm_xtlrc7_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc7_limit_r() - + addr_map_rpg_pm_xtlrc7_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(8), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst8_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c8_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c8_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c8_ctl0_xtlrc_limit_r() - + addr_map_pcie_c8_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst8_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc8_base_r(), + .range_end = addr_map_rpg_pm_xtlrc8_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc8_limit_r() - + addr_map_rpg_pm_xtlrc8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(9), + .num_core_elements_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst9_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c9_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c9_ctl0_xtlrc_limit_r(), + .element_stride = addr_map_pcie_c9_ctl0_xtlrc_limit_r() - + addr_map_pcie_c9_ctl0_xtlrc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST, + .element_static_array = + th500_pcie_xtlrc_inst9_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_xtlrc9_base_r(), + .range_end = addr_map_rpg_pm_xtlrc9_limit_r(), + .element_stride = addr_map_rpg_pm_xtlrc9_limit_r() - + addr_map_rpg_pm_xtlrc9_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, +}; + +/* IP structure */ +struct hwpm_ip th500_hwpm_ip_pcie_xtlrc = { + .num_instances = TH500_HWPM_IP_PCIE_XTLRC_NUM_INSTANCES, + .ip_inst_static_array = th500_pcie_xtlrc_inst_static_array, + + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + /* NOTE: range should be in ascending order */ + .range_start = addr_map_pcie_c0_ctl0_xtlrc_base_r(), + .range_end = addr_map_pcie_c9_ctl0_xtlrc_limit_r(), + .inst_stride = addr_map_pcie_c0_ctl0_xtlrc_limit_r() - + addr_map_pcie_c0_ctl0_xtlrc_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_xtlrc0_base_r(), + .range_end = addr_map_rpg_pm_xtlrc9_limit_r(), + .inst_stride = addr_map_rpg_pm_xtlrc0_limit_r() - + addr_map_rpg_pm_xtlrc0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, + + .dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK, + .override_enable = false, + .inst_fs_mask = 0U, + .resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID, + .reserved = false, +}; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.h b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.h new file mode 100644 index 0000000..4cf3207 --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#ifndef TH500_HWPM_IP_PCIE_XTLRC_H +#define TH500_HWPM_IP_PCIE_XTLRC_H + +#if defined(CONFIG_TH500_HWPM_IP_PCIE) +#define TH500_HWPM_ACTIVE_IP_PCIE_XTLRC TH500_HWPM_IP_PCIE_XTLRC, + +/* This data should ideally be available in HW headers */ +#define TH500_HWPM_IP_PCIE_XTLRC_NUM_INSTANCES 10U +#define TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST 1U +#define TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST 1U +#define TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST 1U +#define TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST 0U + +extern struct hwpm_ip th500_hwpm_ip_pcie_xtlrc; + +#else +#define TH500_HWPM_ACTIVE_IP_PCIE_XTLRC +#endif + +#endif /* TH500_HWPM_IP_PCIE_XTLRC_H */ diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c index 51bd89a..6f75620 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c @@ -225,7 +225,15 @@ struct allowlist th500_c2c_alist[52] = { {0x0000b0fc, false}, }; -struct allowlist th500_pcie_alist[1] = { +struct allowlist th500_pcie_xtlq_alist[1] = { + {0x000039e0, true}, +}; + +struct allowlist th500_pcie_xtlrc_alist[1] = { + {0x000004e0, true}, +}; + +struct allowlist th500_pcie_xalrc_alist[1] = { {0x00000470, true}, }; diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h index b1412be..158302e 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h @@ -30,7 +30,9 @@ extern struct allowlist th500_nvltx_alist[3]; extern struct allowlist th500_nvlctrl_alist[2]; extern struct allowlist th500_smmu_alist[1]; extern struct allowlist th500_c2c_alist[52]; -extern struct allowlist th500_pcie_alist[1]; +extern struct allowlist th500_pcie_xtlq_alist[1]; +extern struct allowlist th500_pcie_xtlrc_alist[1]; +extern struct allowlist th500_pcie_xalrc_alist[1]; extern struct allowlist th500_mss_channel_alist[2]; extern struct allowlist th500_mcf_core_alist[2]; extern struct allowlist th500_mcf_clink_alist[3]; diff --git a/drivers/tegra/hwpm/hal/th500/th500_interface.c b/drivers/tegra/hwpm/hal/th500/th500_interface.c index 68fc722..2242151 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_interface.c +++ b/drivers/tegra/hwpm/hal/th500/th500_interface.c @@ -175,8 +175,14 @@ bool th500_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm, break; #endif #if defined(CONFIG_TH500_HWPM_IP_PCIE) - case TEGRA_HWPM_IP_PCIE: - config_ip = TH500_HWPM_IP_PCIE; + case TEGRA_HWPM_IP_PCIE_XTLQ: + config_ip = TH500_HWPM_IP_PCIE_XTLQ; + break; + case TEGRA_HWPM_IP_PCIE_XTLRC: + config_ip = TH500_HWPM_IP_PCIE_XTLRC; + break; + case TEGRA_HWPM_IP_PCIE_XALRC: + config_ip = TH500_HWPM_IP_PCIE_XALRC; break; #endif #if defined(CONFIG_TH500_HWPM_IP_C2C) @@ -257,8 +263,14 @@ bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm, break; #endif #if defined(CONFIG_TH500_HWPM_IP_PCIE) - case TEGRA_HWPM_RESOURCE_PCIE: - config_ip = TH500_HWPM_IP_PCIE; + case TEGRA_HWPM_RESOURCE_PCIE_XTLQ: + config_ip = TH500_HWPM_IP_PCIE_XTLQ; + break; + case TEGRA_HWPM_RESOURCE_PCIE_XTLRC: + config_ip = TH500_HWPM_IP_PCIE_XTLRC; + break; + case TEGRA_HWPM_RESOURCE_PCIE_XALRC: + config_ip = TH500_HWPM_IP_PCIE_XALRC; break; #endif #if defined(CONFIG_TH500_HWPM_IP_C2C) @@ -348,7 +360,9 @@ int th500_hwpm_init_chip_info(struct tegra_soc_hwpm *hwpm) th500_active_ip_info[TH500_HWPM_IP_NVLTX] = &th500_hwpm_ip_nvltx; #endif #if defined(CONFIG_TH500_HWPM_IP_PCIE) - th500_active_ip_info[TH500_HWPM_IP_PCIE] = &th500_hwpm_ip_pcie; + th500_active_ip_info[TH500_HWPM_IP_PCIE_XTLQ] = &th500_hwpm_ip_pcie_xtlq; + th500_active_ip_info[TH500_HWPM_IP_PCIE_XTLRC] = &th500_hwpm_ip_pcie_xtlrc; + th500_active_ip_info[TH500_HWPM_IP_PCIE_XALRC] = &th500_hwpm_ip_pcie_xalrc; #endif #if defined(CONFIG_TH500_HWPM_IP_C2C) th500_active_ip_info[TH500_HWPM_IP_C2C] = &th500_hwpm_ip_c2c; diff --git a/drivers/tegra/hwpm/hal/th500/th500_internal.h b/drivers/tegra/hwpm/hal/th500/th500_internal.h index c9a620a..e6859eb 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_internal.h +++ b/drivers/tegra/hwpm/hal/th500/th500_internal.h @@ -38,6 +38,9 @@ #include #include #include +#include +#include +#include #define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX @@ -57,6 +60,9 @@ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_IOBHX) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_CLINK) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_CORE) \ + DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XTLQ) \ + DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XTLRC) \ + DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XALRC) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX) #undef DEFINE_SOC_HWPM_ACTIVE_IP diff --git a/drivers/tegra/hwpm/hal/th500/th500_ip.c b/drivers/tegra/hwpm/hal/th500/th500_ip.c index b755719..3ff2e18 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_ip.c +++ b/drivers/tegra/hwpm/hal/th500/th500_ip.c @@ -70,7 +70,9 @@ int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, case TH500_HWPM_IP_NVLTX: #endif #if defined(CONFIG_TH500_HWPM_IP_PCIE) - case TH500_HWPM_IP_PCIE: + case TH500_HWPM_IP_PCIE_XTLQ: + case TH500_HWPM_IP_PCIE_XTLRC: + case TH500_HWPM_IP_PCIE_XALRC: #endif #if defined(CONFIG_TH500_HWPM_IP_C2C) case TH500_HWPM_IP_C2C: diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h index 4c1dc38..337be5c 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm.h @@ -89,6 +89,9 @@ enum tegra_hwpm_ip_enum { TEGRA_HWPM_IP_MCF_C2C, TEGRA_HWPM_IP_MCF_CLINK, TEGRA_HWPM_IP_MCF_CORE, + TEGRA_HWPM_IP_PCIE_XTLQ, + TEGRA_HWPM_IP_PCIE_XTLRC, + TEGRA_HWPM_IP_PCIE_XALRC, TERGA_HWPM_NUM_IPS }; @@ -129,6 +132,9 @@ enum tegra_hwpm_resource_enum { TEGRA_HWPM_RESOURCE_MCF_C2C, TEGRA_HWPM_RESOURCE_MCF_CLINK, TEGRA_HWPM_RESOURCE_MCF_CORE, + TEGRA_HWPM_RESOURCE_PCIE_XTLQ, + TEGRA_HWPM_RESOURCE_PCIE_XTLRC, + TEGRA_HWPM_RESOURCE_PCIE_XALRC, TERGA_HWPM_NUM_RESOURCES }; diff --git a/drivers/tegra/hwpm/os/linux/ip_utils.c b/drivers/tegra/hwpm/os/linux/ip_utils.c index 485fec1..a216956 100644 --- a/drivers/tegra/hwpm/os/linux/ip_utils.c +++ b/drivers/tegra/hwpm/os/linux/ip_utils.c @@ -123,6 +123,15 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_IP_MCF_CORE: ip_enum_idx = TEGRA_HWPM_IP_MCF_CORE; break; + case TEGRA_SOC_HWPM_IP_PCIE_XTLQ: + ip_enum_idx = TEGRA_HWPM_IP_PCIE_XTLQ; + break; + case TEGRA_SOC_HWPM_IP_PCIE_XTLRC: + ip_enum_idx = TEGRA_HWPM_IP_PCIE_XTLRC; + break; + case TEGRA_SOC_HWPM_IP_PCIE_XALRC: + ip_enum_idx = TEGRA_HWPM_IP_PCIE_XALRC; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_ip %d is invalid", @@ -261,6 +270,15 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_RESOURCE_MCF_CORE: res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_CORE; break; + case TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLQ: + res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE_XTLQ; + break; + case TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLRC: + res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE_XTLRC; + break; + case TEGRA_SOC_HWPM_RESOURCE_PCIE_XALRC: + res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE_XALRC; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_resource %d is invalid", diff --git a/include/uapi/linux/tegra-soc-hwpm-uapi.h b/include/uapi/linux/tegra-soc-hwpm-uapi.h index 8b7b055..15280a2 100644 --- a/include/uapi/linux/tegra-soc-hwpm-uapi.h +++ b/include/uapi/linux/tegra-soc-hwpm-uapi.h @@ -56,6 +56,9 @@ enum tegra_soc_hwpm_ip { TEGRA_SOC_HWPM_IP_MCF_C2C, TEGRA_SOC_HWPM_IP_MCF_CLINK, TEGRA_SOC_HWPM_IP_MCF_CORE, + TEGRA_SOC_HWPM_IP_PCIE_XTLQ, + TEGRA_SOC_HWPM_IP_PCIE_XTLRC, + TEGRA_SOC_HWPM_IP_PCIE_XALRC, TERGA_SOC_HWPM_NUM_IPS }; @@ -134,6 +137,9 @@ enum tegra_soc_hwpm_resource { TEGRA_SOC_HWPM_RESOURCE_MCF_C2C, TEGRA_SOC_HWPM_RESOURCE_MCF_CLINK, TEGRA_SOC_HWPM_RESOURCE_MCF_CORE, + TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLQ, + TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLRC, + TEGRA_SOC_HWPM_RESOURCE_PCIE_XALRC, TERGA_SOC_HWPM_NUM_RESOURCES };