From 1ff862c00ae6148b3a0c622501af1d7dcc2a80f9 Mon Sep 17 00:00:00 2001 From: vasukis Date: Tue, 23 Apr 2024 22:03:54 +0000 Subject: [PATCH] th500: hwpm: Fix EMC Fuse Mask calculation. A recent change has led to EMC fuse mask calculation regression. This is being corrected in this patch. The emc_fuse_disable mask is set in such a way that, each bit corresponds to 4 MSS Channels. For example, emc_fuse_disable mask=1100, corresponds to MSS_Channel0 to MSS_Channel7 being present, while MSS_Channel8 to MSS_Channel15 are floorswept. However, in HWPM Driver, the logic to represent a floorswept IP element is indicated by '1'. Correct the logic to indicate this. Bug 4490868 Change-Id: Id83d9e1d983c3fbf8f58cef3a1ff45334d7eadd6 Signed-off-by: vasukis Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3122752 Reviewed-by: Vedashree Vidwans Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit --- drivers/tegra/hwpm/hal/th500/th500_ip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tegra/hwpm/hal/th500/th500_ip.c b/drivers/tegra/hwpm/hal/th500/th500_ip.c index cca6a16..3a1ce35 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_ip.c +++ b/drivers/tegra/hwpm/hal/th500/th500_ip.c @@ -328,7 +328,7 @@ static int th500_hwpm_validate_emc_config(struct tegra_soc_hwpm *hwpm) * Convert floorsweep fuse value to available EMC elements. */ do { - if (emc_disable_fuse_val & (0x1U << emc_disable_fuse_bit_idx)) { + if (!(emc_disable_fuse_val & (0x1U << emc_disable_fuse_bit_idx))) { emc_element_floorsweep_mask |= (0xFU << (emc_disable_fuse_bit_idx * 4U)); }