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tegra: hwpm: combine common functionality
- Many HWPM functions are performed on all apertures of all instances of all IPs. Define below resource utility functions to perform a task on all IPs, instances and apertures: - tegra_hwpm_func_all_IPs - tegra_hwpm_func_single_ip - tegra_hwpm_func_all_instance - tegra_hwpm_func_single_instance - tegra_hwpm_func_all_perfmuxes - tegra_hwpm_func_all_perfmons - tegra_hwpm_func_single_aperture - Modify below functions to use above mentioned utility functions: - get allowlist size - combine allowlist - reserve resources - bind resources - release resources This will make code more legible and maintainable. This patch also defines new function that validates all HAL initializations for the chip. Jira THWPM-41 Change-Id: Icaeba4d94187b97022c0a6626584e7d61ab6d0e4 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2705524 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
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Vedashree Vidwans
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@@ -28,92 +28,6 @@
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#include <tegra_hwpm_common.h>
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#include <tegra_hwpm_static_analysis.h>
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static int tegra_hwpm_get_alist_size(struct tegra_soc_hwpm *hwpm)
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{
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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u32 ip_idx;
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u32 perfmux_idx, perfmon_idx;
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unsigned long inst_idx = 0UL;
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unsigned long floorsweep_info = 0UL;
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struct hwpm_ip *chip_ip = NULL;
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hwpm_ip_perfmux *perfmux = NULL;
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hwpm_ip_perfmon *perfmon = NULL;
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tegra_hwpm_fn(hwpm, " ");
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for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(hwpm);
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ip_idx++) {
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chip_ip = active_chip->chip_ips[ip_idx];
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/* Skip unavailable IPs */
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if (!chip_ip->reserved) {
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continue;
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}
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if (chip_ip->fs_mask == 0U) {
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/* No IP instance is available */
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continue;
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}
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floorsweep_info = (unsigned long)chip_ip->fs_mask;
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for_each_set_bit(inst_idx, &floorsweep_info, 32U) {
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/* Add perfmux alist size to full alist size */
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for (perfmux_idx = 0U;
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perfmux_idx < chip_ip->num_perfmux_slots;
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perfmux_idx++) {
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perfmux = chip_ip->ip_perfmux[perfmux_idx];
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if (perfmux == NULL) {
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continue;
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}
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if (perfmux->hw_inst_mask != BIT(inst_idx)) {
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continue;
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}
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if (perfmux->alist) {
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hwpm->full_alist_size =
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tegra_hwpm_safe_add_u64(
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hwpm->full_alist_size,
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perfmux->alist_size);
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} else {
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tegra_hwpm_err(hwpm, "IP %d"
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" perfmux %d NULL alist",
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ip_idx, perfmux_idx);
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}
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}
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/* Add perfmon alist size to full alist size */
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for (perfmon_idx = 0U;
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perfmon_idx < chip_ip->num_perfmon_slots;
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perfmon_idx++) {
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perfmon = chip_ip->ip_perfmon[perfmon_idx];
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if (perfmon == NULL) {
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continue;
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}
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if (perfmon->hw_inst_mask != BIT(inst_idx)) {
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continue;
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}
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if (perfmon->alist) {
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hwpm->full_alist_size =
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tegra_hwpm_safe_add_u64(
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hwpm->full_alist_size,
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perfmon->alist_size);
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} else {
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tegra_hwpm_err(hwpm, "IP %d"
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" perfmon %d NULL alist",
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ip_idx, perfmon_idx);
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}
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}
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}
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}
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return 0;
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}
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int tegra_hwpm_get_allowlist_size(struct tegra_soc_hwpm *hwpm)
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{
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@@ -123,7 +37,7 @@ int tegra_hwpm_get_allowlist_size(struct tegra_soc_hwpm *hwpm)
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tegra_hwpm_fn(hwpm, " ");
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ret = tegra_hwpm_get_alist_size(hwpm);
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ret = tegra_hwpm_func_all_ip(hwpm, NULL, TEGRA_HWPM_GET_ALIST_SIZE);
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if (ret != 0) {
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tegra_hwpm_err(hwpm, "get_alist_size failed");
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return ret;
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@@ -134,100 +48,29 @@ int tegra_hwpm_get_allowlist_size(struct tegra_soc_hwpm *hwpm)
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static int tegra_hwpm_combine_alist(struct tegra_soc_hwpm *hwpm, u64 *alist)
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{
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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u32 ip_idx;
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u32 perfmux_idx, perfmon_idx;
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unsigned long inst_idx = 0UL;
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unsigned long floorsweep_info = 0UL;
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struct hwpm_ip *chip_ip = NULL;
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hwpm_ip_perfmux *perfmux = NULL;
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hwpm_ip_perfmon *perfmon = NULL;
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u64 full_alist_idx = 0;
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struct tegra_hwpm_func_args func_args;
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int err = 0;
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tegra_hwpm_fn(hwpm, " ");
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for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(hwpm);
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ip_idx++) {
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chip_ip = active_chip->chip_ips[ip_idx];
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func_args.alist = alist;
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func_args.full_alist_idx = 0ULL;
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/* Skip unavailable IPs */
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if (!chip_ip->reserved) {
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continue;
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}
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if (chip_ip->fs_mask == 0U) {
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/* No IP instance is available */
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continue;
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}
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if (hwpm->active_chip->copy_alist == NULL) {
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tegra_hwpm_err(hwpm, "copy_alist uninitialized");
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return -ENODEV;
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}
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floorsweep_info = (unsigned long)chip_ip->fs_mask;
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for_each_set_bit(inst_idx, &floorsweep_info, 32U) {
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/* Copy perfmux alist to full alist array */
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for (perfmux_idx = 0U;
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perfmux_idx < chip_ip->num_perfmux_slots;
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perfmux_idx++) {
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perfmux = chip_ip->ip_perfmux[perfmux_idx];
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if (perfmux == NULL) {
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continue;
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}
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if (perfmux->hw_inst_mask != BIT(inst_idx)) {
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continue;
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}
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err = hwpm->active_chip->copy_alist(hwpm,
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perfmux, alist, &full_alist_idx);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "IP %d"
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" perfmux %d alist copy failed",
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ip_idx, perfmux_idx);
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goto fail;
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}
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}
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/* Copy perfmon alist to full alist array */
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for (perfmon_idx = 0U;
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perfmon_idx < chip_ip->num_perfmon_slots;
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perfmon_idx++) {
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perfmon = chip_ip->ip_perfmon[perfmon_idx];
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if (perfmon == NULL) {
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continue;
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}
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if (perfmon->hw_inst_mask != BIT(inst_idx)) {
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continue;
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}
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err = hwpm->active_chip->copy_alist(hwpm,
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perfmon, alist, &full_alist_idx);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "IP %d"
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" perfmon %d alist copy failed",
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ip_idx, perfmon_idx);
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goto fail;
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}
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}
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}
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err = tegra_hwpm_func_all_ip(hwpm, &func_args,
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TEGRA_HWPM_COMBINE_ALIST);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "combine alist failed");
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return err;
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}
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/* Check size of full alist with hwpm->full_alist_size*/
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if (full_alist_idx != hwpm->full_alist_size) {
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if (func_args.full_alist_idx != hwpm->full_alist_size) {
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tegra_hwpm_err(hwpm, "full_alist_size 0x%llx doesn't match "
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"max full_alist_idx 0x%llx",
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hwpm->full_alist_size, full_alist_idx);
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hwpm->full_alist_size, func_args.full_alist_idx);
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err = -EINVAL;
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}
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fail:
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return err;
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}
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@@ -253,10 +96,7 @@ int tegra_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm,
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tegra_hwpm_err(hwpm, "Invalid allowlist size");
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return -EINVAL;
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}
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if (hwpm->active_chip->get_alist_buf_size == NULL) {
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tegra_hwpm_err(hwpm, "alist_buf_size uninitialized");
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return -ENODEV;
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}
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alist_buf_size = tegra_hwpm_safe_mult_u64(hwpm->full_alist_size,
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hwpm->active_chip->get_alist_buf_size(hwpm));
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