tegra: hwpm: redefine uapi enums for internal use

- To make HWPM driver OS agnostic, redefine UAPI IP and resource enums in HWPM header file. The redefined enums will be used internally in driver logic. - Rename force enable IP flag to include chip name. This will allow IPs to be force enabled corresponding to the chip. Jira THWPM-60 Change-Id: Ibe7ce6666b0e009e5183d591591f393037818052 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2747680 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2025-12-22 17:30:40 +03:00 · 2022-07-18 22:37:52 -07:00
parent ed6dd8af44
commit 2dd64aec0b
8 changed files with 280 additions and 84 deletions
--- a/17
+++ b/17
@@ -46,6 +46,21 @@ obj-y += hal/t234/ip/rtr/t234_rtr.o
 # IP config flag and IP specific .o file.
 #

+#
+# One of the HWPM components is a perfmux. Perfmux registers belong to the
+# IP domain. There are 2 ways of accessing perfmux registers
+# - option 1: implement HWPM <-> IP interface. IP drivers register with HWPM
+#             driver and share required function pointers
+# - option 2: map perfmux register address in HWPM driver
+# Option 1 is a preferred solution. However, IP drivers have yet to
+# implement the interface. Such IPs can be force enabled from HWPM driver
+# perspective. However, forcing an IP will enable all instances of the IP.
+# Hence, IP force enable should only be done on full chip config.
+# Note as power management API is not available, unpowergating the IP via
+# command line is required.
+#
+##define CONFIG_T234_HWPM_ALLOW_FORCE_ENABLE
+
 #
 # Define a Minimal IP config flag
 # Enable only MSS_Channel, NVDLA and PVA IPs
@@ -54,7 +69,7 @@ obj-y += hal/t234/ip/rtr/t234_rtr.o
 CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE=y

 ifeq ($(CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE),y)
-ccflags-y += -DCONFIG_HWPM_ALLOW_FORCE_ENABLE
+ccflags-y += -DCONFIG_T234_HWPM_ALLOW_FORCE_ENABLE
 endif

 ifeq ($(CONFIG_TEGRA_GRHOST_NVDLA),y)
--- a/hal/t234/t234_interface.c
+++ b/hal/t234/t234_interface.c
@@ -229,89 +229,89 @@ bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
 	u32 config_ip = TEGRA_SOC_HWPM_IP_INACTIVE;

 	switch (ip_enum) {
-	case TEGRA_SOC_HWPM_IP_VI:
+	case TEGRA_HWPM_IP_VI:
 #if defined(CONFIG_T234_HWPM_IP_VI)
 		config_ip = T234_HWPM_IP_VI;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_ISP:
+	case TEGRA_HWPM_IP_ISP:
 #if defined(CONFIG_T234_HWPM_IP_ISP)
 		config_ip = T234_HWPM_IP_ISP;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_VIC:
+	case TEGRA_HWPM_IP_VIC:
 #if defined(CONFIG_T234_HWPM_IP_VIC)
 		config_ip = T234_HWPM_IP_VIC;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_OFA:
+	case TEGRA_HWPM_IP_OFA:
 #if defined(CONFIG_T234_HWPM_IP_OFA)
 		config_ip = T234_HWPM_IP_OFA;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_PVA:
+	case TEGRA_HWPM_IP_PVA:
 #if defined(CONFIG_T234_HWPM_IP_PVA)
 		config_ip = T234_HWPM_IP_PVA;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_NVDLA:
+	case TEGRA_HWPM_IP_NVDLA:
 #if defined(CONFIG_T234_HWPM_IP_NVDLA)
 		config_ip = T234_HWPM_IP_NVDLA;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_MGBE:
+	case TEGRA_HWPM_IP_MGBE:
 #if defined(CONFIG_T234_HWPM_IP_MGBE)
 		config_ip = T234_HWPM_IP_MGBE;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_SCF:
+	case TEGRA_HWPM_IP_SCF:
 #if defined(CONFIG_T234_HWPM_IP_SCF)
 		config_ip = T234_HWPM_IP_SCF;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_NVDEC:
+	case TEGRA_HWPM_IP_NVDEC:
 #if defined(CONFIG_T234_HWPM_IP_NVDEC)
 		config_ip = T234_HWPM_IP_NVDEC;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_NVENC:
+	case TEGRA_HWPM_IP_NVENC:
 #if defined(CONFIG_T234_HWPM_IP_NVENC)
 		config_ip = T234_HWPM_IP_NVENC;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_PCIE:
+	case TEGRA_HWPM_IP_PCIE:
 #if defined(CONFIG_T234_HWPM_IP_PCIE)
 		config_ip = T234_HWPM_IP_PCIE;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_DISPLAY:
+	case TEGRA_HWPM_IP_DISPLAY:
 #if defined(CONFIG_T234_HWPM_IP_DISPLAY)
 		config_ip = T234_HWPM_IP_DISPLAY;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_MSS_CHANNEL:
+	case TEGRA_HWPM_IP_MSS_CHANNEL:
 #if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL)
 		config_ip = T234_HWPM_IP_MSS_CHANNEL;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_MSS_GPU_HUB:
+	case TEGRA_HWPM_IP_MSS_GPU_HUB:
 #if defined(CONFIG_T234_HWPM_IP_MSS_GPU_HUB)
 		config_ip = T234_HWPM_IP_MSS_GPU_HUB;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS:
+	case TEGRA_HWPM_IP_MSS_ISO_NISO_HUBS:
 #if defined(CONFIG_T234_HWPM_IP_MSS_ISO_NISO_HUBS)
 		config_ip = T234_HWPM_IP_MSS_ISO_NISO_HUBS;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_IP_MSS_MCF:
+	case TEGRA_HWPM_IP_MSS_MCF:
 #if defined(CONFIG_T234_HWPM_IP_MSS_MCF)
 		config_ip = T234_HWPM_IP_MSS_MCF;
 #endif
 		break;
 	default:
 		tegra_hwpm_err(hwpm,
-			"Queried enum tegra_soc_hwpm_ip %d invalid", ip_enum);
+			"Queried enum tegra_hwpm_ip %d invalid", ip_enum);
 		break;
 	}

@@ -320,100 +320,100 @@ bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
 }

 bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
-	u32 res_index, u32 *config_ip_index)
+	u32 res_enum, u32 *config_ip_index)
 {
 	u32 config_ip = TEGRA_SOC_HWPM_IP_INACTIVE;

-	switch (res_index) {
-	case TEGRA_SOC_HWPM_RESOURCE_VI:
+	switch (res_enum) {
+	case TEGRA_HWPM_RESOURCE_VI:
 #if defined(CONFIG_T234_HWPM_IP_VI)
 		config_ip = T234_HWPM_IP_VI;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_ISP:
+	case TEGRA_HWPM_RESOURCE_ISP:
 #if defined(CONFIG_T234_HWPM_IP_ISP)
 		config_ip = T234_HWPM_IP_ISP;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_VIC:
+	case TEGRA_HWPM_RESOURCE_VIC:
 #if defined(CONFIG_T234_HWPM_IP_VIC)
 		config_ip = T234_HWPM_IP_VIC;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_OFA:
+	case TEGRA_HWPM_RESOURCE_OFA:
 #if defined(CONFIG_T234_HWPM_IP_OFA)
 		config_ip = T234_HWPM_IP_OFA;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_PVA:
+	case TEGRA_HWPM_RESOURCE_PVA:
 #if defined(CONFIG_T234_HWPM_IP_PVA)
 		config_ip = T234_HWPM_IP_PVA;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_NVDLA:
+	case TEGRA_HWPM_RESOURCE_NVDLA:
 #if defined(CONFIG_T234_HWPM_IP_NVDLA)
 		config_ip = T234_HWPM_IP_NVDLA;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_MGBE:
+	case TEGRA_HWPM_RESOURCE_MGBE:
 #if defined(CONFIG_T234_HWPM_IP_MGBE)
 		config_ip = T234_HWPM_IP_MGBE;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_SCF:
+	case TEGRA_HWPM_RESOURCE_SCF:
 #if defined(CONFIG_T234_HWPM_IP_SCF)
 		config_ip = T234_HWPM_IP_SCF;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_NVDEC:
+	case TEGRA_HWPM_RESOURCE_NVDEC:
 #if defined(CONFIG_T234_HWPM_IP_NVDEC)
 		config_ip = T234_HWPM_IP_NVDEC;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_NVENC:
+	case TEGRA_HWPM_RESOURCE_NVENC:
 #if defined(CONFIG_T234_HWPM_IP_NVENC)
 		config_ip = T234_HWPM_IP_NVENC;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_PCIE:
+	case TEGRA_HWPM_RESOURCE_PCIE:
 #if defined(CONFIG_T234_HWPM_IP_PCIE)
 		config_ip = T234_HWPM_IP_PCIE;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_DISPLAY:
+	case TEGRA_HWPM_RESOURCE_DISPLAY:
 #if defined(CONFIG_T234_HWPM_IP_DISPLAY)
 		config_ip = T234_HWPM_IP_DISPLAY;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL:
+	case TEGRA_HWPM_RESOURCE_MSS_CHANNEL:
 #if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL)
 		config_ip = T234_HWPM_IP_MSS_CHANNEL;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_MSS_GPU_HUB:
+	case TEGRA_HWPM_RESOURCE_MSS_GPU_HUB:
 #if defined(CONFIG_T234_HWPM_IP_MSS_GPU_HUB)
 		config_ip = T234_HWPM_IP_MSS_GPU_HUB;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_MSS_ISO_NISO_HUBS:
+	case TEGRA_HWPM_RESOURCE_MSS_ISO_NISO_HUBS:
 #if defined(CONFIG_T234_HWPM_IP_MSS_ISO_NISO_HUBS)
 		config_ip = T234_HWPM_IP_MSS_ISO_NISO_HUBS;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_MSS_MCF:
+	case TEGRA_HWPM_RESOURCE_MSS_MCF:
 #if defined(CONFIG_T234_HWPM_IP_MSS_MCF)
 		config_ip = T234_HWPM_IP_MSS_MCF;
 #endif
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_PMA:
+	case TEGRA_HWPM_RESOURCE_PMA:
 		config_ip = T234_HWPM_IP_PMA;
 		break;
-	case TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR:
+	case TEGRA_HWPM_RESOURCE_CMD_SLICE_RTR:
 		config_ip = T234_HWPM_IP_RTR;
 		break;
 	default:
 		tegra_hwpm_err(hwpm, "Queried resource %d invalid",
-			res_index);
+			res_enum);
 		break;
 	}

--- a/hal/t234/t234_internal.h
+++ b/hal/t234/t234_internal.h
@@ -69,9 +69,9 @@ struct tegra_soc_hwpm;
 struct hwpm_ip_aperture;

 bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
-	u32 ip_index, u32 *config_ip_index);
+	u32 ip_enum, u32 *config_ip_index);
 bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
-	u32 res_index, u32 *config_ip_index);
+	u32 res_enum, u32 *config_ip_index);

 u32 t234_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm);
 u32 t234_get_ip_max_idx(struct tegra_soc_hwpm *hwpm);
--- a/hal/t234/t234_ip.c
+++ b/hal/t234/t234_ip.c
@@ -289,11 +289,10 @@ int t234_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm)

 int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
 {
-
 	int ret = 0;

 	tegra_hwpm_fn(hwpm, " ");
-#if defined(CONFIG_HWPM_ALLOW_FORCE_ENABLE)
+#if defined(CONFIG_T234_HWPM_ALLOW_FORCE_ENABLE)

 #if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL)
 	/* MSS CHANNEL */
@@ -477,7 +476,7 @@ int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,
 				}
 			}
 			*fs_mask = floorsweep;
-			*ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID;
+			*ip_status = TEGRA_HWPM_IP_STATUS_VALID;

 			return 0;
 		}
@@ -486,7 +485,7 @@ int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,
 	tegra_hwpm_dbg(hwpm, hwpm_dbg_floorsweep_info,
 		"SOC hwpm IP %d is unavailable", ip_enum);

-	*ip_status = TEGRA_SOC_HWPM_IP_STATUS_INVALID;
+	*ip_status = TEGRA_HWPM_IP_STATUS_INVALID;
 	*fs_mask = 0ULL;

 	return 0;
--- a/include/tegra_hwpm.h
+++ b/include/tegra_hwpm.h
@@ -21,18 +21,84 @@

 #include <uapi/linux/tegra-soc-hwpm-uapi.h>

-#undef BIT
-#define BIT(x) (0x1U << (u32)(x))
-
-#undef ARRAY_SIZE
-#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0]))
+#include <tegra_hwpm_types.h>

 #define TEGRA_SOC_HWPM_IP_INACTIVE	~(0U)

+/* These macro values should match TEGRA_SOC_HWPM_IP_STATUS_* */
+#define TEGRA_HWPM_IP_STATUS_VALID	0U
+#define TEGRA_HWPM_IP_STATUS_INVALID	1U
+
+/* These macro values should match TEGRA_SOC_HWPM_RESOURCE_STATUS_* */
+#define TEGRA_HWPM_RESOURCE_STATUS_INVALID	0U
+#define TEGRA_HWPM_RESOURCE_STATUS_VALID	1U
+
+#define TEGRA_HWPM_FUSE_PRODUCTION_MODE_MASK		BIT(0)
+#define TEGRA_HWPM_FUSE_SECURITY_MODE_MASK		BIT(1)
+#define TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK	BIT(2)
+
+struct tegra_hwpm_mem_mgmt;
+struct tegra_hwpm_allowlist_map;
+enum tegra_soc_hwpm_ip_reg_op;
+
+/*
+ * This is a copy of enum tegra_soc_hwpm_ip uapi structure.
+ * It is not a hard requirement as tegra_soc_hwpm_ip is translated to
+ * tegra_hwpm_ip_enum before each use.
+ */
+enum tegra_hwpm_ip_enum {
+	TEGRA_HWPM_IP_VI,
+	TEGRA_HWPM_IP_ISP,
+	TEGRA_HWPM_IP_VIC,
+	TEGRA_HWPM_IP_OFA,
+	TEGRA_HWPM_IP_PVA,
+	TEGRA_HWPM_IP_NVDLA,
+	TEGRA_HWPM_IP_MGBE,
+	TEGRA_HWPM_IP_SCF,
+	TEGRA_HWPM_IP_NVDEC,
+	TEGRA_HWPM_IP_NVENC,
+	TEGRA_HWPM_IP_PCIE,
+	TEGRA_HWPM_IP_DISPLAY,
+	TEGRA_HWPM_IP_MSS_CHANNEL,
+	TEGRA_HWPM_IP_MSS_GPU_HUB,
+	TEGRA_HWPM_IP_MSS_ISO_NISO_HUBS,
+	TEGRA_HWPM_IP_MSS_MCF,
+	TEGRA_HWPM_IP_APE,
+	TERGA_HWPM_NUM_IPS
+};
+
+/*
+ * This is a copy of enum tegra_soc_hwpm_resource uapi structure.
+ * It is not a hard requirement as tegra_soc_hwpm_resource is translated to
+ * tegra_hwpm_resource_enum before each use.
+ */
+enum tegra_hwpm_resource_enum {
+	TEGRA_HWPM_RESOURCE_VI,
+	TEGRA_HWPM_RESOURCE_ISP,
+	TEGRA_HWPM_RESOURCE_VIC,
+	TEGRA_HWPM_RESOURCE_OFA,
+	TEGRA_HWPM_RESOURCE_PVA,
+	TEGRA_HWPM_RESOURCE_NVDLA,
+	TEGRA_HWPM_RESOURCE_MGBE,
+	TEGRA_HWPM_RESOURCE_SCF,
+	TEGRA_HWPM_RESOURCE_NVDEC,
+	TEGRA_HWPM_RESOURCE_NVENC,
+	TEGRA_HWPM_RESOURCE_PCIE,
+	TEGRA_HWPM_RESOURCE_DISPLAY,
+	TEGRA_HWPM_RESOURCE_MSS_CHANNEL,
+	TEGRA_HWPM_RESOURCE_MSS_GPU_HUB,
+	TEGRA_HWPM_RESOURCE_MSS_ISO_NISO_HUBS,
+	TEGRA_HWPM_RESOURCE_MSS_MCF,
+	TEGRA_HWPM_RESOURCE_PMA,
+	TEGRA_HWPM_RESOURCE_CMD_SLICE_RTR,
+	TEGRA_HWPM_RESOURCE_APE,
+	TERGA_HWPM_NUM_RESOURCES
+};
+
 /*
 * This structure is copy of struct tegra_soc_hwpm_ip_ops uapi structure.
- * This is not a hard requirement as tegra_hwpm_validate_ip_ops conversion
- * function.
+ * This is not a hard requirement as each value from tegra_soc_hwpm_ip_ops
+ * is copied to struct tegra_hwpm_ip_ops.
 */
 struct tegra_hwpm_ip_ops {
 	/*
@@ -76,36 +142,12 @@ struct tegra_hwpm_ip_ops {
 				u32 *reg_data);
 };

-/*
- * One of the HWPM components is a perfmux. Perfmux registers belong to the
- * IP domain. There are 2 ways of accessing perfmux registers
- * - option 1: implement HWPM <-> IP interface. IP drivers register with HWPM
- *             driver and share required function pointers
- * - option 2: map perfmux register address in HWPM driver
- * Option 1 is a preferred solution. However, IP drivers have yet to
- * implement the interface. Such IPs can be force enabled from HWPM driver
- * perspective. However, forcing an IP will enable all instances of the IP.
- * Hence, IP force enable should only be done on full chip config.
- * Note as power management API is not available, unpowergating the IP via
- * command line is required.
- */
-/*#define CONFIG_HWPM_ALLOW_FORCE_ENABLE*/
-
 /* There are 3 types of HWPM components/apertures */
 #define TEGRA_HWPM_APERTURE_TYPE_PERFMUX	0U
 #define TEGRA_HWPM_APERTURE_TYPE_BROADCAST	1U
 #define TEGRA_HWPM_APERTURE_TYPE_PERFMON	2U
 #define TEGRA_HWPM_APERTURE_TYPE_MAX		3U

-#define TEGRA_HWPM_RESOURCE_STATUS_INVALID	\
-		TEGRA_SOC_HWPM_RESOURCE_STATUS_INVALID
-#define TEGRA_HWPM_RESOURCE_STATUS_VALID	\
-		TEGRA_SOC_HWPM_RESOURCE_STATUS_VALID
-
-#define TEGRA_HWPM_FUSE_PRODUCTION_MODE_MASK		BIT(0)
-#define TEGRA_HWPM_FUSE_SECURITY_MODE_MASK		BIT(1)
-#define TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK	BIT(2)
-
 /*
 * Devices handled by HWPM driver can be divided into 2 categories
 * - HWPM : Components in HWPM device address space
@@ -337,9 +379,9 @@ struct tegra_soc_hwpm_chip {

 	/* Chip HALs */
 	bool (*is_ip_active)(struct tegra_soc_hwpm *hwpm,
-	u32 ip_index, u32 *config_ip_index);
+	u32 ip_enum, u32 *config_ip_index);
 	bool (*is_resource_active)(struct tegra_soc_hwpm *hwpm,
-	u32 res_index, u32 *config_ip_index);
+	u32 res_enum, u32 *config_ip_index);

 	u32 (*get_rtr_int_idx)(struct tegra_soc_hwpm *hwpm);
 	u32 (*get_ip_max_idx)(struct tegra_soc_hwpm *hwpm);
--- a/os/linux/ioctl.c
+++ b/os/linux/ioctl.c
@@ -83,7 +83,6 @@ static int tegra_hwpm_get_resource_info_ioctl(struct tegra_soc_hwpm *hwpm,
 	}

 	return tegra_hwpm_get_resource_info(hwpm, rsrc_info);
-
 }

 static int tegra_hwpm_reserve_resource_ioctl(struct tegra_soc_hwpm *hwpm,
@@ -106,7 +105,8 @@ static int tegra_hwpm_reserve_resource_ioctl(struct tegra_soc_hwpm *hwpm,
 		return -EINVAL;
 	}

-	ret = tegra_hwpm_reserve_resource(hwpm, resource);
+	ret = tegra_hwpm_reserve_resource(hwpm,
+		tegra_hwpm_translate_soc_hwpm_resource(hwpm, resource));
 	if (ret < 0) {
 		tegra_hwpm_err(hwpm, "Failed to reserve resource %d", resource);
 	}
--- a/os/linux/ip_utils.c
+++ b/os/linux/ip_utils.c
@@ -192,6 +192,73 @@ int tegra_hwpm_complete_ip_register_impl(struct tegra_soc_hwpm *hwpm)
 	return ret;
 }

+static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm,
+	enum tegra_soc_hwpm_ip ip_enum)
+{
+	u32 ip_enum_idx = TEGRA_SOC_HWPM_IP_INACTIVE;
+
+	switch (ip_enum) {
+	case TEGRA_SOC_HWPM_IP_VI:
+		ip_enum_idx = TEGRA_HWPM_IP_VI;
+		break;
+	case TEGRA_SOC_HWPM_IP_ISP:
+		ip_enum_idx = TEGRA_HWPM_IP_ISP;
+		break;
+	case TEGRA_SOC_HWPM_IP_VIC:
+		ip_enum_idx = TEGRA_HWPM_IP_VIC;
+		break;
+	case TEGRA_SOC_HWPM_IP_OFA:
+		ip_enum_idx = TEGRA_HWPM_IP_OFA;
+		break;
+	case TEGRA_SOC_HWPM_IP_PVA:
+		ip_enum_idx = TEGRA_HWPM_IP_PVA;
+		break;
+	case TEGRA_SOC_HWPM_IP_NVDLA:
+		ip_enum_idx = TEGRA_HWPM_IP_NVDLA;
+		break;
+	case TEGRA_SOC_HWPM_IP_MGBE:
+		ip_enum_idx = TEGRA_HWPM_IP_MGBE;
+		break;
+	case TEGRA_SOC_HWPM_IP_SCF:
+		ip_enum_idx = TEGRA_HWPM_IP_SCF;
+		break;
+	case TEGRA_SOC_HWPM_IP_NVDEC:
+		ip_enum_idx = TEGRA_HWPM_IP_NVDEC;
+		break;
+	case TEGRA_SOC_HWPM_IP_NVENC:
+		ip_enum_idx = TEGRA_HWPM_IP_NVENC;
+		break;
+	case TEGRA_SOC_HWPM_IP_PCIE:
+		ip_enum_idx = TEGRA_HWPM_IP_PCIE;
+		break;
+	case TEGRA_SOC_HWPM_IP_DISPLAY:
+		ip_enum_idx = TEGRA_HWPM_IP_DISPLAY;
+		break;
+	case TEGRA_SOC_HWPM_IP_MSS_CHANNEL:
+		ip_enum_idx = TEGRA_HWPM_IP_MSS_CHANNEL;
+		break;
+	case TEGRA_SOC_HWPM_IP_MSS_GPU_HUB:
+		ip_enum_idx = TEGRA_HWPM_IP_MSS_GPU_HUB;
+		break;
+	case TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS:
+		ip_enum_idx = TEGRA_HWPM_IP_MSS_ISO_NISO_HUBS;
+		break;
+	case TEGRA_SOC_HWPM_IP_MSS_MCF:
+		ip_enum_idx = TEGRA_HWPM_IP_MSS_MCF;
+		break;
+	case TEGRA_SOC_HWPM_IP_APE:
+		ip_enum_idx = TEGRA_HWPM_IP_APE;
+		break;
+	default:
+		tegra_hwpm_err(hwpm,
+			"Queried enum tegra_soc_hwpm_ip %d is invalid",
+			ip_enum);
+		break;
+	}
+
+	return ip_enum_idx;
+}
+
 int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
 	struct tegra_soc_hwpm_ip_floorsweep_info *fs_info)
 {
@@ -201,8 +268,9 @@ int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
 	tegra_hwpm_fn(hwpm, " ");

 	for (i = 0U; i < fs_info->num_queries; i++) {
-		ret = hwpm->active_chip->get_fs_info(
-			hwpm, (u32)fs_info->ip_fsinfo[i].ip,
+		ret = hwpm->active_chip->get_fs_info(hwpm,
+			tegra_hwpm_translate_soc_hwpm_ip(
+				hwpm, fs_info->ip_fsinfo[i].ip),
 			&fs_info->ip_fsinfo[i].ip_inst_mask,
 			&fs_info->ip_fsinfo[i].status);
 		if (ret < 0) {
@@ -211,7 +279,8 @@ int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
 		}

 		tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_floorsweep_info,
-			"Query %d: ip %d: ip_status: %d inst_mask 0x%llx",
+			"Query %d: tegra_soc_hwpm_ip %d: ip_status: %d"
+			" inst_mask 0x%llx",
 			i, fs_info->ip_fsinfo[i].ip,
 			fs_info->ip_fsinfo[i].status,
 			fs_info->ip_fsinfo[i].ip_inst_mask);
@@ -219,6 +288,73 @@ int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
 	return ret;
 }

+u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
+	enum tegra_soc_hwpm_resource res_enum)
+{
+	u32 res_enum_idx = TEGRA_SOC_HWPM_IP_INACTIVE;
+
+	switch (res_enum) {
+	case TEGRA_SOC_HWPM_RESOURCE_VI:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_VI;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_ISP:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_ISP;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_VIC:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_VIC;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_OFA:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_OFA;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_PVA:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_PVA;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_NVDLA:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_NVDLA;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_MGBE:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_MGBE;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_SCF:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_SCF;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_NVDEC:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_NVDEC;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_NVENC:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_NVENC;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_PCIE:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_DISPLAY:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_DISPLAY;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_CHANNEL;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_MSS_GPU_HUB:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_GPU_HUB;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_MSS_ISO_NISO_HUBS:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_ISO_NISO_HUBS;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_MSS_MCF:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_MCF;
+		break;
+	case TEGRA_SOC_HWPM_RESOURCE_APE:
+		res_enum_idx = TEGRA_HWPM_RESOURCE_APE;
+		break;
+	default:
+		tegra_hwpm_err(hwpm,
+			"Queried enum tegra_soc_hwpm_resource %d is invalid",
+			res_enum);
+		break;
+	}
+
+	return res_enum_idx;
+}
+
 int tegra_hwpm_get_resource_info(struct tegra_soc_hwpm *hwpm,
 	struct tegra_soc_hwpm_resource_info *rsrc_info)
 {
@@ -229,7 +365,8 @@ int tegra_hwpm_get_resource_info(struct tegra_soc_hwpm *hwpm,

 	for (i = 0U; i < rsrc_info->num_queries; i++) {
 		ret = hwpm->active_chip->get_resource_info(
-			hwpm, (u32)rsrc_info->resource_info[i].resource,
+			hwpm, tegra_hwpm_translate_soc_hwpm_resource(
+				hwpm, rsrc_info->resource_info[i].resource),
 			&rsrc_info->resource_info[i].status);
 		if (ret < 0) {
 			/* Print error for debug purpose. */
--- a/os/linux/ip_utils.h
+++ b/os/linux/ip_utils.h
@@ -14,11 +14,14 @@
 #ifndef TEGRA_HWPM_OS_LINUX_IP_UTILS_H
 #define TEGRA_HWPM_OS_LINUX_IP_UTILS_H

+enum tegra_soc_hwpm_resource;
 struct tegra_soc_hwpm;
 struct tegra_soc_hwpm_ip_floorsweep_info;
 struct tegra_soc_hwpm_resource_info;

 int tegra_hwpm_complete_ip_register_impl(struct tegra_soc_hwpm *hwpm);
+u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
+	enum tegra_soc_hwpm_resource res_enum);
 int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
 	struct tegra_soc_hwpm_ip_floorsweep_info *fs_info);
 int tegra_hwpm_get_resource_info(struct tegra_soc_hwpm *hwpm,