From 2e41e3a5bdeaaf8aa0f8c05f26efc9500e65ad14 Mon Sep 17 00:00:00 2001 From: Vishal Aslot Date: Tue, 26 Sep 2023 19:59:29 +0000 Subject: [PATCH] tegra: hwpm: th500: Add support for MCF CLINK This patch adds support for MCF CLINK performance monitoring in the driver. Bug 4287384 Signed-off-by: Vishal Aslot Change-Id: I6d28bb911b3d2b1623bce9a5d46dc0160570c8ec Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2986107 GVS: Gerrit_Virtual_Submit Reviewed-by: Vedashree Vidwans --- drivers/tegra/hwpm/Makefile.th500.soc.sources | 3 + .../th500/soc/ip/mcf_clink/th500_mcf_clink.c | 396 ++++++++++++++++++ .../th500/soc/ip/mcf_clink/th500_mcf_clink.h | 48 +++ drivers/tegra/hwpm/hal/th500/th500_internal.h | 2 + drivers/tegra/hwpm/include/tegra_hwpm.h | 2 + drivers/tegra/hwpm/os/linux/ip_utils.c | 6 + include/uapi/linux/tegra-soc-hwpm-uapi.h | 2 + 7 files changed, 459 insertions(+) create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h diff --git a/drivers/tegra/hwpm/Makefile.th500.soc.sources b/drivers/tegra/hwpm/Makefile.th500.soc.sources index d6b7146..6d00cb5 100644 --- a/drivers/tegra/hwpm/Makefile.th500.soc.sources +++ b/drivers/tegra/hwpm/Makefile.th500.soc.sources @@ -66,4 +66,7 @@ nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.o ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_C2C nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.o +ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_CLINK +nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_clink/th500_mcf_clink.o + endif diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c new file mode 100644 index 0000000..035a9bc --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: MIT +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#include "th500_mcf_clink.h" + +#include +#include +#include +#include + +static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmon_element_static_array[ + TH500_HWPM_IP_MCF_CLINK_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_mcfsys0", + .device_index = TH500_MCFSYS0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_mcfsys0_base_r(), + .end_abs_pa = addr_map_rpg_pm_mcfsys0_limit_r(), + .start_pa = addr_map_rpg_pm_mcfsys0_base_r(), + .end_pa = addr_map_rpg_pm_mcfsys0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_mcfsys1", + .device_index = TH500_MCFSYS1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_mcfsys1_base_r(), + .end_abs_pa = addr_map_rpg_pm_mcfsys1_limit_r(), + .start_pa = addr_map_rpg_pm_mcfsys1_base_r(), + .end_pa = addr_map_rpg_pm_mcfsys1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_array[ + TH500_HWPM_IP_MCF_CLINK_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 11U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc10_base_r(), + .end_abs_pa = addr_map_mc10_limit_r(), + .start_pa = addr_map_mc10_base_r(), + .end_pa = addr_map_mc10_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(1), + .element_index = 12U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc11_base_r(), + .end_abs_pa = addr_map_mc11_limit_r(), + .start_pa = addr_map_mc11_base_r(), + .end_pa = addr_map_mc11_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(2), + .element_index = 13U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc12_base_r(), + .end_abs_pa = addr_map_mc12_limit_r(), + .start_pa = addr_map_mc12_base_r(), + .end_pa = addr_map_mc12_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(3), + .element_index = 14U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc13_base_r(), + .end_abs_pa = addr_map_mc13_limit_r(), + .start_pa = addr_map_mc13_base_r(), + .end_pa = addr_map_mc13_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(4), + .element_index = 15U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc14_base_r(), + .end_abs_pa = addr_map_mc14_limit_r(), + .start_pa = addr_map_mc14_base_r(), + .end_pa = addr_map_mc14_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(5), + .element_index = 16U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc15_base_r(), + .end_abs_pa = addr_map_mc15_limit_r(), + .start_pa = addr_map_mc15_base_r(), + .end_pa = addr_map_mc15_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(6), + .element_index = 17U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc16_base_r(), + .end_abs_pa = addr_map_mc16_limit_r(), + .start_pa = addr_map_mc16_base_r(), + .end_pa = addr_map_mc16_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(7), + .element_index = 18U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc17_base_r(), + .end_abs_pa = addr_map_mc17_limit_r(), + .start_pa = addr_map_mc17_base_r(), + .end_pa = addr_map_mc17_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(8), + .element_index = 19U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc18_base_r(), + .end_abs_pa = addr_map_mc18_limit_r(), + .start_pa = addr_map_mc18_base_r(), + .end_pa = addr_map_mc18_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(9), + .element_index = 20U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc19_base_r(), + .end_abs_pa = addr_map_mc19_limit_r(), + .start_pa = addr_map_mc19_base_r(), + .end_pa = addr_map_mc19_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(10), + .element_index = 21U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc20_base_r(), + .end_abs_pa = addr_map_mc20_limit_r(), + .start_pa = addr_map_mc20_base_r(), + .end_pa = addr_map_mc20_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(11), + .element_index = 22U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc21_base_r(), + .end_abs_pa = addr_map_mc21_limit_r(), + .start_pa = addr_map_mc21_base_r(), + .end_pa = addr_map_mc21_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mcf_clink_inst0_broadcast_element_static_array[ + TH500_HWPM_IP_MCF_CLINK_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +static struct hwpm_ip_inst th500_mcf_clink_inst_static_array[ + TH500_HWPM_IP_MCF_CLINK_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .num_core_elements_per_inst = + TH500_HWPM_IP_MCF_CLINK_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CLINK_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mcf_clink_inst0_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc10_base_r(), + .range_end = addr_map_mc21_limit_r(), + .element_stride = addr_map_mc10_limit_r() - + addr_map_mc10_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CLINK_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mcf_clink_inst0_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CLINK_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mcf_clink_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mcfsys0_base_r(), + .range_end = addr_map_rpg_pm_mcfsys1_limit_r(), + .element_stride = addr_map_rpg_pm_mcfsys0_limit_r() - + addr_map_rpg_pm_mcfsys0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, +}; + +/* IP structure */ +struct hwpm_ip th500_hwpm_ip_mcf_clink = { + .num_instances = TH500_HWPM_IP_MCF_CLINK_NUM_INSTANCES, + .ip_inst_static_array = th500_mcf_clink_inst_static_array, + + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc10_base_r(), + .range_end = addr_map_mc21_limit_r(), + .inst_stride = addr_map_mc21_limit_r() - + addr_map_mc10_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .inst_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_mcfsys0_base_r(), + .range_end = addr_map_rpg_pm_mcfsys1_limit_r(), + .inst_stride = addr_map_rpg_pm_mcfsys1_limit_r() - + addr_map_rpg_pm_mcfsys0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, + + .dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK, + .override_enable = false, + .inst_fs_mask = 0U, + .resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID, + .reserved = false, +}; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h new file mode 100644 index 0000000..e88d3bd --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#ifndef TH500_HWPM_IP_MCF_CLINK_H +#define TH500_HWPM_IP_MCF_CLINK_H + +#if defined(CONFIG_TH500_HWPM_IP_MCF_CLINK) +#define TH500_HWPM_ACTIVE_IP_MCF_CLINK TH500_HWPM_IP_MCF_CLINK, + +/* This data should ideally be available in HW headers */ +#define TH500_HWPM_IP_MCF_CLINK_NUM_INSTANCES 1U +#define TH500_HWPM_IP_MCF_CLINK_NUM_CORE_ELEMENT_PER_INST 12U +#define TH500_HWPM_IP_MCF_CLINK_NUM_PERFMON_PER_INST 2U +#define TH500_HWPM_IP_MCF_CLINK_NUM_PERFMUX_PER_INST 12U +#define TH500_HWPM_IP_MCF_CLINK_NUM_BROADCAST_PER_INST 1U + +extern struct hwpm_ip th500_hwpm_ip_mcf_clink; + +#else +#define TH500_HWPM_ACTIVE_IP_MCF_CLINK +#endif + +#endif /* TH500_HWPM_IP_MCF_CLINK_H */ diff --git a/drivers/tegra/hwpm/hal/th500/th500_internal.h b/drivers/tegra/hwpm/hal/th500/th500_internal.h index a1fa37f..58fd003 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_internal.h +++ b/drivers/tegra/hwpm/hal/th500/th500_internal.h @@ -36,6 +36,7 @@ #include #include #include +#include #define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX @@ -53,6 +54,7 @@ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_HUB) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_OCU) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_IOBHX) \ + DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_CLINK) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX) #undef DEFINE_SOC_HWPM_ACTIVE_IP diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h index 1d858d1..62be9b3 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm.h @@ -87,6 +87,7 @@ enum tegra_hwpm_ip_enum { TEGRA_HWPM_IP_MCF_OCU, TEGRA_HWPM_IP_MCF_IOBHX, TEGRA_HWPM_IP_MCF_C2C, + TEGRA_HWPM_IP_MCF_CLINK, TERGA_HWPM_NUM_IPS }; @@ -125,6 +126,7 @@ enum tegra_hwpm_resource_enum { TEGRA_HWPM_RESOURCE_MCF_OCU, TEGRA_HWPM_RESOURCE_MCF_IOBHX, TEGRA_HWPM_RESOURCE_MCF_C2C, + TEGRA_HWPM_RESOURCE_MCF_CLINK, TERGA_HWPM_NUM_RESOURCES }; diff --git a/drivers/tegra/hwpm/os/linux/ip_utils.c b/drivers/tegra/hwpm/os/linux/ip_utils.c index a45d416..9560045 100644 --- a/drivers/tegra/hwpm/os/linux/ip_utils.c +++ b/drivers/tegra/hwpm/os/linux/ip_utils.c @@ -117,6 +117,9 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_IP_MCF_C2C: ip_enum_idx = TEGRA_HWPM_IP_MCF_C2C; break; + case TEGRA_SOC_HWPM_IP_MCF_CLINK: + ip_enum_idx = TEGRA_HWPM_IP_MCF_CLINK; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_ip %d is invalid", @@ -249,6 +252,9 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_RESOURCE_MCF_C2C: res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_C2C; break; + case TEGRA_SOC_HWPM_RESOURCE_MCF_CLINK: + res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_CLINK; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_resource %d is invalid", diff --git a/include/uapi/linux/tegra-soc-hwpm-uapi.h b/include/uapi/linux/tegra-soc-hwpm-uapi.h index 8c0284e..31cfeaa 100644 --- a/include/uapi/linux/tegra-soc-hwpm-uapi.h +++ b/include/uapi/linux/tegra-soc-hwpm-uapi.h @@ -54,6 +54,7 @@ enum tegra_soc_hwpm_ip { TEGRA_SOC_HWPM_IP_MCF_OCU, TEGRA_SOC_HWPM_IP_MCF_IOBHX, TEGRA_SOC_HWPM_IP_MCF_C2C, + TEGRA_SOC_HWPM_IP_MCF_CLINK, TERGA_SOC_HWPM_NUM_IPS }; @@ -130,6 +131,7 @@ enum tegra_soc_hwpm_resource { TEGRA_SOC_HWPM_RESOURCE_MCF_OCU, TEGRA_SOC_HWPM_RESOURCE_MCF_IOBHX, TEGRA_SOC_HWPM_RESOURCE_MCF_C2C, + TEGRA_SOC_HWPM_RESOURCE_MCF_CLINK, TERGA_SOC_HWPM_NUM_RESOURCES };