diff --git a/Makefile b/Makefile index a4a30d7..44d67a8 100644 --- a/Makefile +++ b/Makefile @@ -49,7 +49,6 @@ obj-y += hal/t234/t234_hwpm_aperture_utils.o obj-y += hal/t234/t234_hwpm_interface_utils.o obj-y += hal/t234/t234_hwpm_ip_utils.o obj-y += hal/t234/t234_hwpm_mem_buf_utils.o -obj-y += hal/t234/t234_hwpm_regops_utils.o obj-y += hal/t234/t234_hwpm_regops_allowlist.o obj-y += hal/t234/t234_hwpm_resource_utils.o diff --git a/common/tegra_hwpm_aperture_utils.c b/common/tegra_hwpm_aperture_utils.c index 25e5773..04cca0f 100644 --- a/common/tegra_hwpm_aperture_utils.c +++ b/common/tegra_hwpm_aperture_utils.c @@ -15,12 +15,13 @@ #include #include +#include #include #include #include -int tegra_hwpm_perfmon_reserve(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon) +static int tegra_hwpm_perfmon_reserve(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *perfmon) { struct resource *res = NULL; @@ -60,8 +61,87 @@ int tegra_hwpm_perfmon_reserve(struct tegra_soc_hwpm *hwpm, return 0; } -int tegra_hwpm_perfmon_release(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon) +static int tegra_hwpm_perfmux_reserve(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *perfmux) +{ + u32 val = 0U; + + tegra_hwpm_fn(hwpm, " "); + + perfmux->start_pa = perfmux->start_abs_pa; + perfmux->end_pa = perfmux->end_abs_pa; + + /* Allocate fake registers */ + if (hwpm->fake_registers_enabled) { + u64 address_range = tegra_hwpm_safe_add_u64( + tegra_hwpm_safe_sub_u64( + perfmux->end_pa, perfmux->start_pa), 1ULL); + u64 num_regs = address_range / sizeof(u32); + + perfmux->fake_registers = + kcalloc(num_regs, sizeof(u32), GFP_KERNEL); + if (perfmux->fake_registers == NULL) { + tegra_hwpm_err(hwpm, "Aperture(0x%llx - 0x%llx):" + " Couldn't allocate memory for fake registers", + perfmux->start_pa, perfmux->end_pa); + return -ENOMEM; + } + } + + /* Validate perfmux availability by reading 1st alist offset */ + val = tegra_hwpm_regops_readl(hwpm, + tegra_hwpm_safe_add_u64(perfmux->start_abs_pa, + perfmux->alist[0U].reg_offset), ip_inst, perfmux); + if (val < 0U) { + tegra_hwpm_dbg(hwpm, hwpm_info, + "perfmux start_abs_pa 0x%llx unavailable", + perfmux->start_abs_pa); + + ip_inst->element_fs_mask &= ~(perfmux->element_index_mask); + } + + return 0; +} + +int tegra_hwpm_element_reserve(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *element) +{ + int err = 0; + + tegra_hwpm_fn(hwpm, " "); + + switch (element->element_type) { + case HWPM_ELEMENT_PERFMON: + case HWPM_ELEMENT_PERFMUX: + err = tegra_hwpm_perfmon_reserve(hwpm, ip_inst, element); + if (err != 0) { + tegra_hwpm_err(hwpm, "Element mask 0x%x reserve failed", + element->element_index_mask); + goto fail; + } + break; + case IP_ELEMENT_PERFMUX: + case IP_ELEMENT_BROADCAST: + err = tegra_hwpm_perfmux_reserve(hwpm, ip_inst, element); + if (err != 0) { + tegra_hwpm_err(hwpm, "Element mask 0x%x reserve failed", + element->element_index_mask); + goto fail; + } + break; + case HWPM_ELEMENT_INVALID: + default: + tegra_hwpm_err(hwpm, "Invalid element type %d", + element->element_type); + return -EINVAL; + } + +fail: + return err; +} + +static int tegra_hwpm_perfmon_release(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_aperture *perfmon) { tegra_hwpm_fn(hwpm, " "); @@ -81,63 +161,14 @@ int tegra_hwpm_perfmon_release(struct tegra_soc_hwpm *hwpm, return 0; } -int tegra_hwpm_perfmux_reserve(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmux *perfmux) -{ - int err = 0; - int ret = 0; - - tegra_hwpm_fn(hwpm, " "); - - /* - * Indicate that HWPM driver is initializing monitoring. - * Since perfmux is controlled by IP, indicate monitoring enabled - * by disabling IP power management. - */ - /* Make sure that ip_ops are initialized */ - if ((perfmux->ip_ops.ip_dev != NULL) && - (perfmux->ip_ops.hwpm_ip_pm != NULL)) { - err = (*perfmux->ip_ops.hwpm_ip_pm)( - perfmux->ip_ops.ip_dev, true); - if (err != 0) { - tegra_hwpm_err(hwpm, "Runtime PM disable failed"); - } - } else { - tegra_hwpm_dbg(hwpm, hwpm_verbose, "Runtime PM not configured"); - } - - perfmux->start_pa = perfmux->start_abs_pa; - perfmux->end_pa = perfmux->end_abs_pa; - - /* Allocate fake registers */ - if (hwpm->fake_registers_enabled) { - u64 address_range = tegra_hwpm_safe_add_u64( - tegra_hwpm_safe_sub_u64( - perfmux->end_pa, perfmux->start_pa), 1ULL); - u64 num_regs = address_range / sizeof(u32); - perfmux->fake_registers = (u32 *)kzalloc( - sizeof(u32) * num_regs, GFP_KERNEL); - if (perfmux->fake_registers == NULL) { - tegra_hwpm_err(hwpm, "Aperture(0x%llx - 0x%llx):" - " Couldn't allocate memory for fake registers", - perfmux->start_pa, perfmux->end_pa); - ret = -ENOMEM; - goto fail; - } - } - -fail: - return ret; -} - -int tegra_hwpm_perfmux_release(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmux *perfmux) +static int tegra_hwpm_perfmux_release(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_aperture *perfmux) { tegra_hwpm_fn(hwpm, " "); /* * Release - * This is only required for for fake registers + * This is only required for fake registers */ if (perfmux->fake_registers) { kfree(perfmux->fake_registers); @@ -147,91 +178,635 @@ int tegra_hwpm_perfmux_release(struct tegra_soc_hwpm *hwpm, return 0; } -int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm) +int tegra_hwpm_element_release(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_aperture *element) { - int ret = 0; - u32 perfmux_idx = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip_rtr = NULL; - hwpm_ip_perfmux *rtr_perfmux = NULL; + int err = 0; tegra_hwpm_fn(hwpm, " "); - chip_ip_rtr = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)]; - - /* Make sure that RTR is not already reserved */ - if (chip_ip_rtr->reserved == true) { - tegra_hwpm_err(hwpm, "RTR already reserved, ignoring"); - return 0; - } - - /* Reserve RTR perfmuxes */ - for (perfmux_idx = 0U; perfmux_idx < chip_ip_rtr->num_perfmux_slots; - perfmux_idx++) { - rtr_perfmux = chip_ip_rtr->ip_perfmux[perfmux_idx]; - - if (rtr_perfmux == NULL) { - continue; + switch (element->element_type) { + case HWPM_ELEMENT_PERFMON: + case HWPM_ELEMENT_PERFMUX: + err = hwpm->active_chip->perfmon_disable(hwpm, element); + if (err != 0) { + tegra_hwpm_err(hwpm, "Element mask 0x%x disable failed", + element->element_index_mask); + goto fail; } - /* Since RTR is hwpm component, use perfmon reserve function */ - ret = tegra_hwpm_perfmon_reserve(hwpm, rtr_perfmux); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "RTR perfmux %d reserve failed", - perfmux_idx); - return ret; + err = tegra_hwpm_perfmon_release(hwpm, element); + if (err != 0) { + tegra_hwpm_err(hwpm, "Element mask 0x%x release failed", + element->element_index_mask); + goto fail; + } + break; + case IP_ELEMENT_PERFMUX: + case IP_ELEMENT_BROADCAST: + err = hwpm->active_chip->perfmux_disable(hwpm, element); + if (err != 0) { + tegra_hwpm_err(hwpm, "Element mask 0x%x disable failed", + element->element_index_mask); + goto fail; } - chip_ip_rtr->fs_mask |= rtr_perfmux->hw_inst_mask; + err = tegra_hwpm_perfmux_release(hwpm, element); + if (err != 0) { + tegra_hwpm_err(hwpm, "Element mask 0x%x release failed", + element->element_index_mask); + goto fail; + } + break; + case HWPM_ELEMENT_INVALID: + default: + tegra_hwpm_err(hwpm, "Invalid element type %d", + element->element_type); + return -EINVAL; } - /* No perfmons in RTR */ - - chip_ip_rtr->reserved = true; - - return ret; +fail: + return err; } -int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm) +static void tegra_hwpm_free_dynamic_inst_array(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, + u32 ip_idx, struct hwpm_ip *chip_ip) { - int ret = 0; - u32 perfmux_idx; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip_rtr = NULL; - hwpm_ip_perfmux *rtr_perfmux = NULL; + u32 a_type; tegra_hwpm_fn(hwpm, " "); - chip_ip_rtr = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)]; + /* Do this for all aperture types */ + for (a_type = 0U; a_type < TEGRA_HWPM_APERTURE_TYPE_MAX; a_type++) { + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; - if (!chip_ip_rtr->reserved) { - tegra_hwpm_dbg(hwpm, hwpm_info, "RTR wasn't mapped, ignoring."); - return 0; - } - - /* Release RTR perfmux */ - for (perfmux_idx = 0U; perfmux_idx < chip_ip_rtr->num_perfmux_slots; - perfmux_idx++) { - rtr_perfmux = chip_ip_rtr->ip_perfmux[perfmux_idx]; - - if (rtr_perfmux == NULL) { + if (inst_a_info->inst_arr == NULL) { + /* No a_type elements in the IP */ continue; } - /* RTR is hwpm component, use perfmon release func */ - ret = tegra_hwpm_perfmon_release(hwpm, rtr_perfmux); - if (ret != 0) { - tegra_hwpm_err(hwpm, "RTR perfmux %d release failed", - perfmux_idx); - return ret; - } + kfree(inst_a_info->inst_arr); + } +} - chip_ip_rtr->fs_mask &= ~(rtr_perfmux->hw_inst_mask); +static int tegra_hwpm_alloc_dynamic_inst_element_array( + struct tegra_soc_hwpm *hwpm, struct hwpm_ip *chip_ip, u32 a_type) +{ + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; + u64 ip_element_range = 0ULL; + u32 idx; + + tegra_hwpm_fn(hwpm, " "); + + if (inst_a_info->range_start == 0ULL) { + /* No a_type elements in the IP */ + return 0; } - /* No perfmons in RTR */ + ip_element_range = tegra_hwpm_safe_add_u64( + tegra_hwpm_safe_sub_u64(inst_a_info->range_end, + inst_a_info->range_start), 1ULL); + inst_a_info->inst_slots = tegra_hwpm_safe_cast_u64_to_u32( + ip_element_range / inst_a_info->inst_stride); + + inst_a_info->inst_arr = kcalloc(inst_a_info->inst_slots, + sizeof(struct hwpm_ip_inst *), GFP_KERNEL); + if (inst_a_info->inst_arr == NULL) { + tegra_hwpm_err(hwpm, + "a_type %d instance array alloc failed", + a_type); + return -ENOMEM; + } + + for (idx = 0U; idx < inst_a_info->inst_slots; idx++) { + inst_a_info->inst_arr[idx] = NULL; + } - chip_ip_rtr->reserved = false; return 0; -} \ No newline at end of file +} + +static int tegra_hwpm_alloc_dynamic_inst_array(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, enum tegra_hwpm_funcs iia_func, + u32 ip_idx, struct hwpm_ip *chip_ip) +{ + int err = 0; + u32 a_type; + + tegra_hwpm_fn(hwpm, " "); + + /* Do this for all aperture types */ + for (a_type = 0U; a_type < TEGRA_HWPM_APERTURE_TYPE_MAX; a_type++) { + err = tegra_hwpm_alloc_dynamic_inst_element_array( + hwpm, chip_ip, a_type); + if (err != 0) { + tegra_hwpm_err(hwpm, "IP %d a_type %d" + "dynamic_inst_perfmon_array alloc failed", + ip_idx, a_type); + goto fail; + } + } + +fail: + return err; +} + +static int tegra_hwpm_func_single_element(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, + enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, + u32 static_inst_idx, u32 a_type, u32 static_aperture_idx) +{ + int err = 0, ret = 0; + struct hwpm_ip_inst *ip_inst = + &chip_ip->ip_inst_static_array[static_inst_idx]; + struct hwpm_ip_element_info *e_info = &ip_inst->element_info[a_type]; + struct hwpm_ip_aperture *element = + &e_info->element_static_array[static_aperture_idx]; + u64 element_offset = 0ULL; + u32 idx = 0U; + + tegra_hwpm_fn(hwpm, " "); + + switch (iia_func) { + case TEGRA_HWPM_INIT_IP_STRUCTURES: + /* Compute element offset from element range start */ + element_offset = tegra_hwpm_safe_sub_u64( + element->start_abs_pa, e_info->range_start); + + /* Compute element's slot index */ + idx = tegra_hwpm_safe_cast_u64_to_u32( + element_offset / e_info->element_stride); + + tegra_hwpm_dbg(hwpm, hwpm_info, + "IP %d inst %d a_type %d element type %d" + " start_addr 0x%llx static idx %d == dynamic idx %d", + ip_idx, static_inst_idx, a_type, element->element_type, + element->start_abs_pa, static_aperture_idx, idx); + + /* Set perfmux slot pointer */ + e_info->element_arr[idx] = element; + break; + case TEGRA_HWPM_GET_ALIST_SIZE: + if ((element->element_index_mask & + ip_inst->element_fs_mask) == 0U) { + return 0; + } + if (element->alist) { + hwpm->full_alist_size = tegra_hwpm_safe_add_u64( + hwpm->full_alist_size, element->alist_size); + } else { + tegra_hwpm_err(hwpm, "IP %d" + " element type %d static_idx %d NULL alist", + ip_idx, a_type, static_aperture_idx); + } + break; + case TEGRA_HWPM_COMBINE_ALIST: + if ((element->element_index_mask & + ip_inst->element_fs_mask) == 0U) { + return 0; + } + err = hwpm->active_chip->copy_alist(hwpm, + element, func_args->alist, &func_args->full_alist_idx); + if (err != 0) { + tegra_hwpm_err(hwpm, + "IP %d element type %d static_idx %d" + " alist copy failed", + ip_idx, a_type, static_aperture_idx); + return err; + } + break; + case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE: + if ((element->element_index_mask & + ip_inst->element_fs_mask) == 0U) { + return 0; + } + err = tegra_hwpm_element_reserve(hwpm, ip_inst, element); + if (err != 0) { + tegra_hwpm_err(hwpm, "IP %d element" + " type %d static_idx %d reserve failed", + ip_idx, a_type, static_aperture_idx); + goto fail; + } + break; + case TEGRA_HWPM_RELEASE_RESOURCES: + case TEGRA_HWPM_RELEASE_ROUTER: + if ((element->element_index_mask & + ip_inst->element_fs_mask) == 0U) { + return 0; + } + ret = tegra_hwpm_element_release(hwpm, element); + if (ret != 0) { + tegra_hwpm_err(hwpm, "IP %d element" + " type %d idx %d release failed", + ip_idx, a_type, static_aperture_idx); + } + break; + case TEGRA_HWPM_BIND_RESOURCES: + if ((element->element_index_mask & + ip_inst->element_fs_mask) == 0U) { + return 0; + } + err = hwpm->active_chip->zero_alist_regs( + hwpm, ip_inst, element); + if (err != 0) { + tegra_hwpm_err(hwpm, "IP %d element" + " type %d idx %d zero regs failed", + ip_idx, a_type, static_aperture_idx); + goto fail; + } + if (element->element_type == HWPM_ELEMENT_PERFMON) { + err = hwpm->active_chip->perfmon_enable(hwpm, element); + if (err != 0) { + tegra_hwpm_err(hwpm, "IP %d element" + " type %d idx %d enable failed", + ip_idx, a_type, static_aperture_idx); + goto fail; + } + } + break; + case TEGRA_HWPM_RELEASE_IP_STRUCTURES: + if ((element->element_index_mask & + ip_inst->element_fs_mask) == 0U) { + return 0; + } + break; + default: + tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func); + return -EINVAL; + break; + } + + return 0; +fail: + return err; +} + +static int tegra_hwpm_func_all_elements_of_type(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, + enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, + u32 static_inst_idx, u32 a_type) +{ + u32 static_idx = 0U, idx = 0U; + u64 inst_element_range = 0ULL; + int err = 0; + struct hwpm_ip_inst *ip_inst = + &chip_ip->ip_inst_static_array[static_inst_idx]; + struct hwpm_ip_element_info *e_info = &ip_inst->element_info[a_type]; + + tegra_hwpm_fn(hwpm, " "); + + if (iia_func == TEGRA_HWPM_INIT_IP_STRUCTURES) { + if (e_info->num_element_per_inst == 0U) { + /* no a_type elements in this IP */ + return 0; + } + + inst_element_range = tegra_hwpm_safe_add_u64( + tegra_hwpm_safe_sub_u64(e_info->range_end, + e_info->range_start), 1ULL); + e_info->element_slots = tegra_hwpm_safe_cast_u64_to_u32( + inst_element_range / e_info->element_stride); + + e_info->element_arr = kcalloc(e_info->element_slots, + sizeof(struct hwpm_ip_aperture *), GFP_KERNEL); + if (e_info->element_arr == NULL) { + tegra_hwpm_err(hwpm, + "a_type %d element array alloc failed", a_type); + return -ENOMEM; + } + + for (idx = 0U; idx < e_info->element_slots; idx++) { + e_info->element_arr[idx] = NULL; + } + } + + for (static_idx = 0U; static_idx < e_info->num_element_per_inst; + static_idx++) { + err = tegra_hwpm_func_single_element( + hwpm, func_args, iia_func, ip_idx, + chip_ip, static_inst_idx, a_type, static_idx); + if (err != 0) { + tegra_hwpm_err(hwpm, + "IP %d inst %d a_type %d idx %d func %d failed", + ip_idx, static_inst_idx, a_type, + static_idx, iia_func); + goto fail; + } + } + + if (iia_func == TEGRA_HWPM_RELEASE_IP_STRUCTURES) { + if (e_info->element_arr != NULL) { + kfree(e_info->element_arr); + } + } + + return 0; +fail: + return err; +} + +static int tegra_hwpm_func_all_elements(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, + enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, + u32 static_inst_idx) +{ + u32 a_type; + int err = 0; + + tegra_hwpm_fn(hwpm, " "); + + for (a_type = 0U; a_type < TEGRA_HWPM_APERTURE_TYPE_MAX; a_type++) { + err = tegra_hwpm_func_all_elements_of_type(hwpm, func_args, + iia_func, ip_idx, chip_ip, static_inst_idx, a_type); + if (err != 0) { + tegra_hwpm_err(hwpm, + "IP %d inst %d a_type %d func %d failed", + ip_idx, static_inst_idx, a_type, iia_func); + goto fail; + } + } + + return 0; +fail: + return err; +} + +static int tegra_hwpm_func_single_inst(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, + enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, + u32 static_inst_idx) +{ + int err = 0; + u32 a_type, idx = 0U; + u64 inst_offset = 0ULL; + struct hwpm_ip_inst *ip_inst = + &chip_ip->ip_inst_static_array[static_inst_idx]; + struct hwpm_ip_inst_per_aperture_info *inst_a_info = NULL; + struct hwpm_ip_element_info *e_info = NULL; + + tegra_hwpm_fn(hwpm, " "); + + if (iia_func == TEGRA_HWPM_INIT_IP_STRUCTURES) { + for (a_type = 0U; a_type < TEGRA_HWPM_APERTURE_TYPE_MAX; + a_type++) { + inst_a_info = &chip_ip->inst_aperture_info[a_type]; + e_info = &ip_inst->element_info[a_type]; + + if (inst_a_info->range_start == 0ULL) { + /* No a_type elements in the IP */ + continue; + } + + /* Compute element offset from element range start */ + inst_offset = tegra_hwpm_safe_sub_u64( + e_info->range_start, inst_a_info->range_start); + + /* Compute element's slot index */ + idx = tegra_hwpm_safe_cast_u64_to_u32( + inst_offset / inst_a_info->inst_stride); + + tegra_hwpm_dbg(hwpm, hwpm_info, "IP %d a_type %d " + " static inst idx %d == dynamic idx %d", + ip_idx, a_type, static_inst_idx, idx); + + /* Set perfmux slot pointer */ + inst_a_info->inst_arr[idx] = ip_inst; + } + } + + if (iia_func == TEGRA_HWPM_RESERVE_GIVEN_RESOURCE) { + /* + * Disable IP power management indicating + * start of profiling session + */ + err = tegra_hwpm_ip_handle_power_mgmt(hwpm, ip_inst, true); + if (err != 0) { + tegra_hwpm_err(hwpm, + "IP %d inst %d power mgmt disable failed", + ip_idx, static_inst_idx); + goto fail; + } + } + + /* Continue functionality for all apertures */ + err = tegra_hwpm_func_all_elements(hwpm, func_args, iia_func, + ip_idx, chip_ip, static_inst_idx); + if (err != 0) { + tegra_hwpm_err(hwpm, "IP %d inst %d func 0x%x failed", + ip_idx, static_inst_idx, iia_func); + goto fail; + } + + if (iia_func == TEGRA_HWPM_RELEASE_RESOURCES) { + /* + * Enable IP power management indicating + * end of profiling session + */ + err = tegra_hwpm_ip_handle_power_mgmt(hwpm, ip_inst, false); + if (err != 0) { + tegra_hwpm_err(hwpm, + "IP %d inst %d power mgmt enable failed", + ip_idx, static_inst_idx); + goto fail; + } + } + +fail: + return err; +} + +static int tegra_hwpm_func_all_inst(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, + enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip) +{ + int err = 0, ret = 0; + u32 inst_idx = 0U; + unsigned long reserved_insts = 0UL, idx = 0UL; + + tegra_hwpm_fn(hwpm, " "); + + for (inst_idx = 0U; inst_idx < chip_ip->num_instances; inst_idx++) { + err = tegra_hwpm_func_single_inst(hwpm, func_args, iia_func, + ip_idx, chip_ip, inst_idx); + if (err != 0) { + tegra_hwpm_err(hwpm, "IP %d inst %d func 0x%x failed", + ip_idx, inst_idx, iia_func); + goto fail; + } + + if (iia_func == TEGRA_HWPM_RESERVE_GIVEN_RESOURCE) { + reserved_insts |= BIT(inst_idx); + } + } + + return 0; + +fail: + if (iia_func == TEGRA_HWPM_RESERVE_GIVEN_RESOURCE) { + /* Revert previously reserved instances of this IP */ + for_each_set_bit(idx, &reserved_insts, 32U) { + /* Release all apertures belonging to this instance */ + ret = tegra_hwpm_func_single_inst(hwpm, func_args, + TEGRA_HWPM_RELEASE_RESOURCES, + ip_idx, chip_ip, idx); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "IP %d inst %d func 0x%x failed", + ip_idx, idx, + TEGRA_HWPM_RELEASE_RESOURCES); + } + } + } + /* Return previous error */ + return err; +} + +int tegra_hwpm_func_single_ip(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, + enum tegra_hwpm_funcs iia_func, u32 ip_idx) +{ + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_idx]; + int err = 0; + + tegra_hwpm_fn(hwpm, " "); + + if (chip_ip == NULL) { + tegra_hwpm_err(hwpm, "IP %d not populated", ip_idx); + return -ENODEV; + } + + switch (iia_func) { + case TEGRA_HWPM_GET_ALIST_SIZE: + case TEGRA_HWPM_COMBINE_ALIST: + case TEGRA_HWPM_BIND_RESOURCES: + /* Skip unavailable IPs */ + if (!chip_ip->reserved) { + return 0; + } + + if (chip_ip->inst_fs_mask == 0U) { + /* No IP instance is available */ + return 0; + } + break; + case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE: + /* Skip IPs which are already reserved */ + if (chip_ip->reserved) { + tegra_hwpm_dbg(hwpm, hwpm_info, + "Chip IP %d already reserved", ip_idx); + return 0; + } + + /* Make sure IP override is not enabled */ + if (chip_ip->override_enable) { + tegra_hwpm_dbg(hwpm, hwpm_info, + "Chip IP %d not available", ip_idx); + return 0; + } + + if (chip_ip->inst_fs_mask == 0U) { + /* No IP instance is available to reserve */ + return 0; + } + break; + case TEGRA_HWPM_RELEASE_RESOURCES: + /* RTR will be released later */ + if (ip_idx == active_chip->get_rtr_int_idx(hwpm)) { + return 0; + } + /* Skip unavailable IPs */ + if (!chip_ip->reserved) { + return 0; + } + + if (chip_ip->inst_fs_mask == 0U) { + /* No IP instance is available to release */ + return 0; + } + break; + case TEGRA_HWPM_RELEASE_ROUTER: + /* Skip unavailable IPs */ + if (!chip_ip->reserved) { + return 0; + } + + if (chip_ip->inst_fs_mask == 0U) { + /* No IP instance is available to release */ + return 0; + } + break; + case TEGRA_HWPM_INIT_IP_STRUCTURES: + err = tegra_hwpm_alloc_dynamic_inst_array( + hwpm, func_args, iia_func, ip_idx, chip_ip); + if (err != 0) { + tegra_hwpm_err(hwpm, "IP %d func 0x%x failed", + ip_idx, iia_func); + goto fail; + } + break; + case TEGRA_HWPM_RELEASE_IP_STRUCTURES: + break; + default: + tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func); + goto fail; + break; + } + + /* Continue functionality for all instances in this IP */ + err = tegra_hwpm_func_all_inst(hwpm, func_args, iia_func, + ip_idx, chip_ip); + if (err != 0) { + tegra_hwpm_err(hwpm, "IP %d func 0x%x failed", + ip_idx, iia_func); + goto fail; + } + + /* Post execute functionality */ + if (iia_func == TEGRA_HWPM_RESERVE_GIVEN_RESOURCE) { + chip_ip->reserved = true; + } + if ((iia_func == TEGRA_HWPM_RELEASE_RESOURCES) || + (iia_func == TEGRA_HWPM_RELEASE_ROUTER)) { + chip_ip->reserved = false; + } + if (iia_func == TEGRA_HWPM_RELEASE_IP_STRUCTURES) { + tegra_hwpm_free_dynamic_inst_array(hwpm, NULL, ip_idx, chip_ip); + } + + return 0; +fail: + return err; +} + +int tegra_hwpm_func_all_ip(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, + enum tegra_hwpm_funcs iia_func) +{ + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + u32 ip_idx; + int err = 0; + + tegra_hwpm_fn(hwpm, " "); + + if (iia_func == TEGRA_HWPM_COMBINE_ALIST) { + /* Start from zeroth index */ + func_args->full_alist_idx = 0ULL; + } + + for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(hwpm); + ip_idx++) { + + err = tegra_hwpm_func_single_ip( + hwpm, func_args, iia_func, ip_idx); + if (err != 0) { + tegra_hwpm_err(hwpm, "IP %d func 0x%x failed", + ip_idx, iia_func); + return err; + } + } + + return 0; +} diff --git a/common/tegra_hwpm_init.c b/common/tegra_hwpm_init.c index 5766fe7..b210163 100644 --- a/common/tegra_hwpm_init.c +++ b/common/tegra_hwpm_init.c @@ -71,22 +71,45 @@ static int tegra_hwpm_init_chip_info(struct tegra_soc_hwpm *hwpm) return err; } +static int tegra_hwpm_init_chip_ip_structures(struct tegra_soc_hwpm *hwpm) +{ + int err = 0; + + tegra_hwpm_fn(hwpm, " "); + + err = tegra_hwpm_func_all_ip(hwpm, NULL, TEGRA_HWPM_INIT_IP_STRUCTURES); + if (err != 0) { + tegra_hwpm_err(hwpm, "failed init IP structures"); + return err; + } + + return err; +} + int tegra_hwpm_init_sw_components(struct tegra_soc_hwpm *hwpm) { int err = 0; + tegra_hwpm_fn(hwpm, " "); + err = tegra_hwpm_init_chip_info(hwpm); if (err != 0) { tegra_hwpm_err(hwpm, "Failed to initialize current chip info."); return err; } - err = hwpm->active_chip->init_chip_ip_structures(hwpm); + err = tegra_hwpm_init_chip_ip_structures(hwpm); if (err != 0) { tegra_hwpm_err(hwpm, "IP structure init failed"); return err; } + err = tegra_hwpm_finalize_chip_info(hwpm); + if (err < 0) { + tegra_hwpm_err(hwpm, "Unable to initialize chip fs_info"); + return err; + } + return 0; } @@ -112,24 +135,13 @@ void tegra_hwpm_release_sw_components(struct tegra_soc_hwpm *hwpm) int tegra_hwpm_setup_sw(struct tegra_soc_hwpm *hwpm) { - int ret = 0; - tegra_hwpm_fn(hwpm, " "); - ret = tegra_hwpm_finalize_chip_info(hwpm); - if (ret < 0) { - tegra_hwpm_err(hwpm, "Unable to initialize chip fs_info"); - goto fail; - } - /* Initialize SW state */ hwpm->bind_completed = false; hwpm->full_alist_size = 0; return 0; - -fail: - return ret; } int tegra_hwpm_setup_hw(struct tegra_soc_hwpm *hwpm) @@ -208,23 +220,16 @@ fail: void tegra_hwpm_release_sw_setup(struct tegra_soc_hwpm *hwpm) { - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = NULL; - u32 ip_idx; + int err = 0; - for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(hwpm); - ip_idx++) { - chip_ip = active_chip->chip_ips[ip_idx]; + tegra_hwpm_fn(hwpm, " "); - /* Release perfmux array */ - if (chip_ip->num_perfmux_per_inst != 0U) { - kfree(chip_ip->ip_perfmux); - } - - /* Release perfmon array */ - if (chip_ip->num_perfmon_per_inst != 0U) { - kfree(chip_ip->ip_perfmon); - } + err = tegra_hwpm_func_all_ip(hwpm, NULL, + TEGRA_HWPM_RELEASE_IP_STRUCTURES); + if (err != 0) { + tegra_hwpm_err(hwpm, "failed release IP structures"); + return; } + return; } diff --git a/common/tegra_hwpm_ip_utils.c b/common/tegra_hwpm_ip_utils.c index 2e114bb..1a69d4e 100644 --- a/common/tegra_hwpm_ip_utils.c +++ b/common/tegra_hwpm_ip_utils.c @@ -15,343 +15,107 @@ #include #include +#include #include #include #include -static int tegra_hwpm_init_ip_perfmux_apertures(struct tegra_soc_hwpm *hwpm, - struct hwpm_ip *chip_ip) +int tegra_hwpm_ip_handle_power_mgmt(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_inst *ip_inst, bool disable) { - u32 idx = 0U, perfmux_idx = 0U, max_perfmux = 0U; - u64 perfmux_address_range = 0ULL, perfmux_offset = 0ULL; - hwpm_ip_perfmux *perfmux = NULL; - - /* Initialize perfmux array */ - if (chip_ip->num_perfmux_per_inst == 0U) { - /* no perfmux in this IP */ - return 0; - } - - perfmux_address_range = tegra_hwpm_safe_add_u64( - tegra_hwpm_safe_sub_u64(chip_ip->perfmux_range_end, - chip_ip->perfmux_range_start), 1ULL); - chip_ip->num_perfmux_slots = tegra_hwpm_safe_cast_u64_to_u32( - perfmux_address_range / chip_ip->inst_perfmux_stride); - - chip_ip->ip_perfmux = kzalloc( - sizeof(hwpm_ip_perfmux *) * chip_ip->num_perfmux_slots, - GFP_KERNEL); - if (chip_ip->ip_perfmux == NULL) { - tegra_hwpm_err(hwpm, "Perfmux pointer array allocation failed"); - return -ENOMEM; - } - - /* Set all perfmux slot pointers to NULL */ - for (idx = 0U; idx < chip_ip->num_perfmux_slots; idx++) { - chip_ip->ip_perfmux[idx] = NULL; - } - - /* Assign valid perfmuxes to corresponding slot pointers */ - max_perfmux = chip_ip->num_instances * chip_ip->num_perfmux_per_inst; - for (perfmux_idx = 0U; perfmux_idx < max_perfmux; perfmux_idx++) { - perfmux = &chip_ip->perfmux_static_array[perfmux_idx]; - - /* Compute perfmux offset from perfmux range start */ - perfmux_offset = tegra_hwpm_safe_sub_u64( - perfmux->start_abs_pa, chip_ip->perfmux_range_start); - - /* Compute perfmux slot index */ - idx = tegra_hwpm_safe_cast_u64_to_u32( - perfmux_offset / chip_ip->inst_perfmux_stride); - - /* Set perfmux slot pointer */ - chip_ip->ip_perfmux[idx] = perfmux; - } - - return 0; -} - -static int tegra_hwpm_init_ip_perfmon_apertures(struct tegra_soc_hwpm *hwpm, - struct hwpm_ip *chip_ip) -{ - u32 idx = 0U, perfmon_idx = 0U, max_perfmon = 0U; - u64 perfmon_address_range = 0ULL, perfmon_offset = 0ULL; - hwpm_ip_perfmon *perfmon = NULL; - - /* Initialize perfmon array */ - if (chip_ip->num_perfmon_per_inst == 0U) { - /* no perfmons in this IP */ - return 0; - } - - perfmon_address_range = tegra_hwpm_safe_add_u64( - tegra_hwpm_safe_sub_u64(chip_ip->perfmon_range_end, - chip_ip->perfmon_range_start), 1ULL); - chip_ip->num_perfmon_slots = tegra_hwpm_safe_cast_u64_to_u32( - perfmon_address_range / chip_ip->inst_perfmon_stride); - - chip_ip->ip_perfmon = kzalloc( - sizeof(hwpm_ip_perfmon *) * chip_ip->num_perfmon_slots, - GFP_KERNEL); - if (chip_ip->ip_perfmon == NULL) { - tegra_hwpm_err(hwpm, "Perfmon pointer array allocation failed"); - return -ENOMEM; - } - - /* Set all perfmon slot pointers to NULL */ - for (idx = 0U; idx < chip_ip->num_perfmon_slots; idx++) { - chip_ip->ip_perfmon[idx] = NULL; - } - - /* Assign valid perfmuxes to corresponding slot pointers */ - max_perfmon = chip_ip->num_instances * chip_ip->num_perfmon_per_inst; - for (perfmon_idx = 0U; perfmon_idx < max_perfmon; perfmon_idx++) { - perfmon = &chip_ip->perfmon_static_array[perfmon_idx]; - - /* Compute perfmon offset from perfmon range start */ - perfmon_offset = tegra_hwpm_safe_sub_u64( - perfmon->start_abs_pa, chip_ip->perfmon_range_start); - - /* Compute perfmon slot index */ - idx = tegra_hwpm_safe_cast_u64_to_u32( - perfmon_offset / chip_ip->inst_perfmon_stride); - - /* Set perfmon slot pointer */ - chip_ip->ip_perfmon[idx] = perfmon; - } - - return 0; -} - -int tegra_hwpm_init_chip_ip_structures(struct tegra_soc_hwpm *hwpm) -{ - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = NULL; - u32 ip_idx; - int ret = 0; - - for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(hwpm); - ip_idx++) { - chip_ip = active_chip->chip_ips[ip_idx]; - - ret = tegra_hwpm_init_ip_perfmon_apertures(hwpm, chip_ip); - if (ret != 0) { - tegra_hwpm_err(hwpm, "IP %d perfmon alloc failed", - ip_idx); - return ret; - } - - ret = tegra_hwpm_init_ip_perfmux_apertures(hwpm, chip_ip); - if (ret != 0) { - tegra_hwpm_err(hwpm, "IP %d perfmux alloc failed", - ip_idx); - return ret; - } - } - - return 0; -} - -/* - * This function finds the IP perfmon index corresponding to given base address. - * Perfmon aperture belongs to IP domain and contains IP instance info - * wrt base address. - * Return instance index - */ -static int tegra_hwpm_find_ip_perfmon_index(struct tegra_soc_hwpm *hwpm, - u64 base_addr, u32 ip_index, u32 *ip_perfmon_idx) -{ - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_index]; - u32 perfmon_idx; - u64 addr_offset = 0ULL; - hwpm_ip_perfmon *perfmon = NULL; - - tegra_hwpm_fn(hwpm, " "); - - if (ip_perfmon_idx == NULL) { - tegra_hwpm_err(hwpm, "pointer for ip_perfmon_idx is NULL"); - return -EINVAL; - } - - /* Validate phys_addr falls in IP address range */ - if ((base_addr < chip_ip->perfmon_range_start) || - (base_addr > chip_ip->perfmon_range_end)) { - tegra_hwpm_dbg(hwpm, hwpm_info, - "phys address 0x%llx not in IP %d", - base_addr, ip_index); - return -ENODEV; - } - - /* Find IP instance for given phys_address */ + int err = 0; /* - * Since all IP instances are configured to be in consecutive memory, - * instance index can be found using instance physical address stride. + * Since perfmux is controlled by IP, indicate monitoring enabled + * by disabling IP power management. + * disable = false: start of profiling session + * disable = true: end of profiling session */ - addr_offset = tegra_hwpm_safe_sub_u64( - base_addr, chip_ip->perfmon_range_start); - perfmon_idx = tegra_hwpm_safe_cast_u64_to_u32( - addr_offset / chip_ip->inst_perfmon_stride); - - /* Make sure instance index is valid */ - if (perfmon_idx >= chip_ip->num_perfmon_slots) { - tegra_hwpm_err(hwpm, - "IP:%d -> base addr 0x%llx is out of bounds", - ip_index, base_addr); - return -EINVAL; + /* Make sure that ip_ops are initialized */ + if ((ip_inst->ip_ops.ip_dev != NULL) && + (ip_inst->ip_ops.hwpm_ip_pm != NULL)) { + err = (*ip_inst->ip_ops.hwpm_ip_pm)( + ip_inst->ip_ops.ip_dev, disable); + if (err != 0) { + tegra_hwpm_err(hwpm, "Runtime PM %s failed", + disable == true ? "disable" : "enable"); + } + } else { + tegra_hwpm_dbg(hwpm, hwpm_verbose, "Runtime PM not configured"); } - /* Validate IP instance perfmon start address = given phys addr */ - perfmon = chip_ip->ip_perfmon[perfmon_idx]; - - if (perfmon == NULL) { - /* - * This a valid case. For example, not all MSS base addresses - * are shared between MSS IPs. - */ - tegra_hwpm_dbg(hwpm, hwpm_info, - "For addr 0x%llx IP %d perfmon_idx %d not populated", - base_addr, ip_index, perfmon_idx); - return -ENODEV; - } - - if (base_addr != perfmon->start_abs_pa) { - tegra_hwpm_dbg(hwpm, hwpm_info, - "base addr 0x%llx != perfmon abs addr", base_addr); - return -EINVAL; - } - - *ip_perfmon_idx = perfmon_idx; - - return 0; + return err; } -/* - * This function finds the IP perfmux index corresponding to given base address. - * Perfmux aperture belongs to IP domain and contains IP instance info - * wrt base address. - * Return instance index - */ -static int tegra_hwpm_find_ip_perfmux_index(struct tegra_soc_hwpm *hwpm, - u64 base_addr, u32 ip_index, u32 *ip_perfmux_idx) -{ - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_index]; - u32 perfmux_idx; - u64 addr_offset = 0ULL; - hwpm_ip_perfmux *perfmux = NULL; - - tegra_hwpm_fn(hwpm, " "); - - if (ip_perfmux_idx == NULL) { - tegra_hwpm_err(hwpm, "pointer for ip_perfmux_idx is NULL"); - return -EINVAL; - } - - /* Validate phys_addr falls in IP address range */ - if ((base_addr < chip_ip->perfmux_range_start) || - (base_addr > chip_ip->perfmux_range_end)) { - tegra_hwpm_dbg(hwpm, hwpm_info, - "phys address 0x%llx not in IP %d", - base_addr, ip_index); - return -ENODEV; - } - - /* Find IP instance for given phys_address */ - /* - * Since all IP instances are configured to be in consecutive memory, - * instance index can be found using instance physical address stride. - */ - addr_offset = tegra_hwpm_safe_sub_u64( - base_addr, chip_ip->perfmux_range_start); - perfmux_idx = tegra_hwpm_safe_cast_u64_to_u32( - addr_offset / chip_ip->inst_perfmux_stride); - - /* Make sure instance index is valid */ - if (perfmux_idx >= chip_ip->num_perfmux_slots) { - tegra_hwpm_err(hwpm, - "IP:%d -> base addr 0x%llx is out of bounds", - ip_index, base_addr); - return -EINVAL; - } - - /* Validate IP instance perfmux start address = given phys addr */ - perfmux = chip_ip->ip_perfmux[perfmux_idx]; - - if (perfmux == NULL) { - /* - * This a valid case. For example, not all MSS base addresses - * are shared between MSS IPs. - */ - tegra_hwpm_dbg(hwpm, hwpm_info, - "For addr 0x%llx IP %d perfmux_idx %d not populated", - base_addr, ip_index, perfmux_idx); - return -ENODEV; - } - - if (base_addr != perfmux->start_abs_pa) { - tegra_hwpm_dbg(hwpm, hwpm_info, - "base addr 0x%llx != perfmux abs addr", base_addr); - return -EINVAL; - } - - *ip_perfmux_idx = perfmux_idx; - - return 0; -} - -static int tegra_hwpm_update_ip_floorsweep_mask(struct tegra_soc_hwpm *hwpm, - u32 ip_idx, u32 hw_inst_mask, bool available) +static int tegra_hwpm_update_ip_inst_element_fs_mask( + struct tegra_soc_hwpm *hwpm, + u32 ip_idx, u32 a_type, u32 inst_idx, bool available) { struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_idx]; + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; + struct hwpm_ip_inst *ip_inst = inst_a_info->inst_arr[inst_idx]; + struct hwpm_ip_element_info *perfmux_info = + &ip_inst->element_info[TEGRA_HWPM_APERTURE_TYPE_PERFMUX]; + struct hwpm_ip_aperture *perfmux = NULL; + u32 idx = 0U; tegra_hwpm_fn(hwpm, " "); - /* Update floorsweep info */ - if (available) { - chip_ip->fs_mask |= hw_inst_mask; - } else { - chip_ip->fs_mask &= ~(hw_inst_mask); + /* Only perfmuxes are essential for element_fs_mask */ + for (idx = 0U; idx < perfmux_info->num_element_per_inst; idx++) { + perfmux = &perfmux_info->element_static_array[idx]; + + ip_inst->element_fs_mask |= perfmux->element_index_mask; } return 0; } +static int tegra_hwpm_update_ip_inst_fs_mask(struct tegra_soc_hwpm *hwpm, + u32 ip_idx, u32 a_type, u32 inst_idx, bool available) +{ + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_idx]; + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; + struct hwpm_ip_inst *ip_inst = inst_a_info->inst_arr[inst_idx]; + + tegra_hwpm_fn(hwpm, " "); + + /* Update inst fs info */ + if (available) { + chip_ip->inst_fs_mask |= ip_inst->hw_inst_mask; + } else { + chip_ip->inst_fs_mask &= ~(ip_inst->hw_inst_mask); + } + + return tegra_hwpm_update_ip_inst_element_fs_mask(hwpm, ip_idx, + a_type, inst_idx, available); +} + static int tegra_hwpm_update_ip_ops_info(struct tegra_soc_hwpm *hwpm, struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops, - u32 ip_idx, u32 ip_perfmux_idx, bool available) + u32 ip_idx, u32 a_type, u32 inst_idx, bool available) { - u32 perfmux_idx, max_num_perfmux = 0U; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_idx]; - struct tegra_hwpm_ip_ops *ip_ops; - hwpm_ip_perfmux *given_perfmux = chip_ip->ip_perfmux[ip_perfmux_idx]; - hwpm_ip_perfmux *perfmux = NULL; + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; + struct hwpm_ip_inst *ip_inst = inst_a_info->inst_arr[inst_idx]; + /* Update IP ops info for the instance */ + struct tegra_hwpm_ip_ops *ip_ops = &ip_inst->ip_ops; tegra_hwpm_fn(hwpm, " "); - /* Update IP ops info for all perfmuxes in the instance */ - max_num_perfmux = tegra_hwpm_safe_mult_u32( - chip_ip->num_instances, chip_ip->num_perfmux_per_inst); - for (perfmux_idx = 0U; perfmux_idx < max_num_perfmux; perfmux_idx++) { - perfmux = &chip_ip->perfmux_static_array[perfmux_idx]; - - if (perfmux->hw_inst_mask != given_perfmux->hw_inst_mask) { - continue; - } - - ip_ops = &perfmux->ip_ops; - - if (available) { - ip_ops->ip_dev = hwpm_ip_ops->ip_dev; - ip_ops->hwpm_ip_pm = hwpm_ip_ops->hwpm_ip_pm; - ip_ops->hwpm_ip_reg_op = hwpm_ip_ops->hwpm_ip_reg_op; - } else { - ip_ops->ip_dev = NULL; - ip_ops->hwpm_ip_pm = NULL; - ip_ops->hwpm_ip_reg_op = NULL; - } + if (available) { + ip_ops->ip_dev = hwpm_ip_ops->ip_dev; + ip_ops->hwpm_ip_pm = hwpm_ip_ops->hwpm_ip_pm; + ip_ops->hwpm_ip_reg_op = hwpm_ip_ops->hwpm_ip_reg_op; + } else { + ip_ops->ip_dev = NULL; + ip_ops->hwpm_ip_pm = NULL; + ip_ops->hwpm_ip_reg_op = NULL; } return 0; @@ -365,92 +129,63 @@ int tegra_hwpm_set_fs_info_ip_ops(struct tegra_soc_hwpm *hwpm, u64 base_address, u32 ip_idx, bool available) { int ret = 0; - u32 perfmux_idx = 0U, perfmon_idx = 0U; - struct tegra_soc_hwpm_chip *active_chip = NULL; - struct hwpm_ip *chip_ip = NULL; - hwpm_ip_perfmux *perfmux = NULL; - hwpm_ip_perfmon *perfmon = NULL; + bool found = false; + u32 idx = ip_idx; + u32 inst_idx = 0U, element_idx = 0U; + u32 a_type = 0U; + enum tegra_hwpm_element_type element_type = HWPM_ELEMENT_INVALID; tegra_hwpm_fn(hwpm, " "); - if (hwpm->active_chip == NULL) { - tegra_hwpm_err(hwpm, "chip struct not populated"); - return -ENODEV; - } - - active_chip = hwpm->active_chip; - - if (ip_idx == TEGRA_SOC_HWPM_IP_INACTIVE) { - tegra_hwpm_err(hwpm, "invalid ip_idx %d", ip_idx); + /* Find IP aperture containing phys_addr in allowlist */ + found = tegra_hwpm_aperture_for_address(hwpm, + TEGRA_HWPM_MATCH_BASE_ADDRESS, base_address, + &idx, &inst_idx, &element_idx, &element_type); + if (!found) { + tegra_hwpm_err(hwpm, "Base addr 0x%llx not in IP %d", + base_address, idx); return -EINVAL; } - chip_ip = active_chip->chip_ips[ip_idx]; + tegra_hwpm_dbg(hwpm, hwpm_verbose, + "Found addr 0x%llx IP %d inst_idx %d element_idx %d e_type %d", + base_address, idx, inst_idx, element_idx, element_type); - if (chip_ip == NULL) { - tegra_hwpm_err(hwpm, "IP %d not populated", ip_idx); - return -ENODEV; + switch (element_type) { + case HWPM_ELEMENT_PERFMON: + a_type = TEGRA_HWPM_APERTURE_TYPE_PERFMON; + break; + case HWPM_ELEMENT_PERFMUX: + case IP_ELEMENT_PERFMUX: + a_type = TEGRA_HWPM_APERTURE_TYPE_PERFMUX; + break; + case IP_ELEMENT_BROADCAST: + a_type = TEGRA_HWPM_APERTURE_TYPE_BROADCAST; + break; + case HWPM_ELEMENT_INVALID: + default: + tegra_hwpm_err(hwpm, "Invalid element type %d", element_type); } - if (chip_ip->override_enable) { - /* This IP should not be configured for HWPM */ - tegra_hwpm_dbg(hwpm, hwpm_info, - "IP %d enable override", ip_idx); - return 0; /* Should this be notified to caller or ignored */ + if (hwpm_ip_ops != NULL) { + /* Update IP ops */ + ret = tegra_hwpm_update_ip_ops_info(hwpm, hwpm_ip_ops, + ip_idx, a_type, inst_idx, available); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "IP %d inst_idx %d: Failed to update ip_ops", + ip_idx, inst_idx); + goto fail; + } } - if (chip_ip->num_perfmux_per_inst != 0U) { - /* Step 1: find IP hw instance mask using perfmux */ - ret = tegra_hwpm_find_ip_perfmux_index(hwpm, - base_address, ip_idx, &perfmux_idx); - if (ret != 0) { - /* Error will be printed handled by parent function */ - goto fail; - } - - perfmux = chip_ip->ip_perfmux[perfmux_idx]; - - /* Step 2: Update IP floorsweep info */ - ret = tegra_hwpm_update_ip_floorsweep_mask( - hwpm, ip_idx, perfmux->hw_inst_mask, available); - if (ret != 0) { - tegra_hwpm_err(hwpm, "IP %d perfmux %d base 0x%llx: " - "FS mask update failed", - ip_idx, perfmux_idx, base_address); - goto fail; - } - - if (hwpm_ip_ops != NULL) { - /* Update IP ops */ - ret = tegra_hwpm_update_ip_ops_info(hwpm, hwpm_ip_ops, - ip_idx, perfmux_idx, available); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "IP %d perfmux %d: Failed to update ip_ops", - ip_idx, perfmux_idx); - goto fail; - } - } - } else { - /* Step 1: find IP hw instance mask using perfmon */ - ret = tegra_hwpm_find_ip_perfmon_index(hwpm, - base_address, ip_idx, &perfmon_idx); - if (ret != 0) { - /* Error will be printed handled by parent function */ - goto fail; - } - - perfmon = chip_ip->ip_perfmon[perfmon_idx]; - - /* Step 2: Update IP floorsweep info */ - ret = tegra_hwpm_update_ip_floorsweep_mask( - hwpm, ip_idx, perfmon->hw_inst_mask, available); - if (ret != 0) { - tegra_hwpm_err(hwpm, "IP %d perfmon %d base 0x%llx: " - "FS mask update failed", - ip_idx, perfmon_idx, base_address); - goto fail; - } + ret = tegra_hwpm_update_ip_inst_fs_mask(hwpm, ip_idx, a_type, + inst_idx, available); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "IP %d inst_idx %d: Failed to update fs_info", + ip_idx, inst_idx); + goto fail; } fail: @@ -510,3 +245,336 @@ int tegra_hwpm_finalize_chip_info(struct tegra_soc_hwpm *hwpm) return ret; } + +static bool tegra_hwpm_addr_in_single_element(struct tegra_soc_hwpm *hwpm, + enum tegra_hwpm_funcs iia_func, + u64 find_addr, u32 *ip_idx, u32 *inst_idx, u32 *element_idx, + enum tegra_hwpm_element_type *element_type, u32 a_type) +{ + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + struct hwpm_ip *chip_ip = active_chip->chip_ips[*ip_idx]; + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; + struct hwpm_ip_inst *ip_inst = inst_a_info->inst_arr[*inst_idx]; + struct hwpm_ip_element_info *e_info = &ip_inst->element_info[a_type]; + struct hwpm_ip_aperture *element = e_info->element_arr[*element_idx]; + + if (element == NULL) { + tegra_hwpm_dbg(hwpm, hwpm_info, "IP %d addr 0x%llx inst_idx %d " + "a_type %d: element_idx %d not populated", + *ip_idx, find_addr, *inst_idx, a_type, *element_idx); + return false; + } + + if (iia_func == TEGRA_HWPM_FIND_GIVEN_ADDRESS) { + /* Make sure this instance is available */ + if ((element->element_index_mask & + ip_inst->element_fs_mask) == 0U) { + tegra_hwpm_dbg(hwpm, hwpm_info, + "IP %d addr 0x%llx inst_idx %d " + "a_type %d: element_idx %d: not available", + *ip_idx, find_addr, *inst_idx, a_type, + *element_idx); + return false; + } + + /* Make sure phys addr belongs to this element */ + if ((find_addr < element->start_abs_pa) || + (find_addr > element->end_abs_pa)) { + tegra_hwpm_err(hwpm, "IP %d addr 0x%llx inst_idx %d " + "a_type %d element_idx %d: out of bounds", + *ip_idx, find_addr, *inst_idx, a_type, + *element_idx); + return false; + } + + if (hwpm->active_chip->check_alist(hwpm, element, find_addr)) { + *element_type = element->element_type; + return true; + } + + tegra_hwpm_dbg(hwpm, hwpm_verbose, + "IP %d addr 0x%llx inst_idx %d " + "a_type %d element_idx %d address not in alist", + *ip_idx, find_addr, *inst_idx, a_type, + *element_idx); + return false; + } + + if (iia_func == TEGRA_HWPM_MATCH_BASE_ADDRESS) { + /* Confirm that given addr is base address of this element */ + if (find_addr != element->start_abs_pa) { + tegra_hwpm_dbg(hwpm, hwpm_info, + "IP %d addr 0x%llx inst_idx %d " + "a_type %d element_idx %d: addr != start addr", + *ip_idx, find_addr, *inst_idx, a_type, + *element_idx); + return false; + } + *element_type = element->element_type; + return true; + } + + /* All cases handled, execution shouldn't reach here */ + return false; +} + +static bool tegra_hwpm_addr_in_all_elements(struct tegra_soc_hwpm *hwpm, + enum tegra_hwpm_funcs iia_func, + u64 find_addr, u32 *ip_idx, u32 *inst_idx, u32 *element_idx, + enum tegra_hwpm_element_type *element_type, u32 a_type) +{ + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + struct hwpm_ip *chip_ip = active_chip->chip_ips[*ip_idx]; + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; + struct hwpm_ip_inst *ip_inst = inst_a_info->inst_arr[*inst_idx]; + struct hwpm_ip_element_info *e_info = &ip_inst->element_info[a_type]; + u64 element_offset = 0ULL; + u32 idx; + + /* Make sure address falls in elements of a_type */ + if (e_info->num_element_per_inst == 0U) { + tegra_hwpm_dbg(hwpm, hwpm_info, + "IP %d addr 0x%llx: inst_idx %d no type %d elements", + *ip_idx, find_addr, *inst_idx, a_type); + return false; + } + + if ((find_addr < e_info->range_start) || + (find_addr > e_info->range_end)) { + /* Address not in this instance corresponding to a_type */ + return false; + } + + /* Find element index to which address belongs to */ + element_offset = tegra_hwpm_safe_sub_u64( + find_addr, e_info->range_start); + idx = tegra_hwpm_safe_cast_u64_to_u32( + element_offset / e_info->element_stride); + + /* Make sure element index is valid */ + if (idx >= e_info->element_slots) { + tegra_hwpm_err(hwpm, "IP %d addr 0x%llx inst_idx %d a_type %d: " + "element_idx %d out of bounds", + *ip_idx, find_addr, *inst_idx, a_type, idx); + return false; + } + + *element_idx = idx; + + /* Process further and return */ + return tegra_hwpm_addr_in_single_element(hwpm, iia_func, + find_addr, ip_idx, inst_idx, element_idx, element_type, a_type); +} + +static bool tegra_hwpm_addr_in_single_instance(struct tegra_soc_hwpm *hwpm, + enum tegra_hwpm_funcs iia_func, + u64 find_addr, u32 *ip_idx, u32 *inst_idx, u32 *element_idx, + enum tegra_hwpm_element_type *element_type, u32 a_type) +{ + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + struct hwpm_ip *chip_ip = active_chip->chip_ips[*ip_idx]; + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; + struct hwpm_ip_inst *ip_inst = inst_a_info->inst_arr[*inst_idx]; + + tegra_hwpm_fn(hwpm, " "); + + if (ip_inst == NULL) { + tegra_hwpm_dbg(hwpm, hwpm_info, "IP %d addr 0x%llx: " + "a_type %d inst_idx %d not populated", + *ip_idx, find_addr, a_type, *inst_idx); + return false; + } + + if (iia_func == TEGRA_HWPM_FIND_GIVEN_ADDRESS) { + /* Make sure this instance is available */ + if ((chip_ip->inst_fs_mask & ip_inst->hw_inst_mask) == 0U) { + tegra_hwpm_dbg(hwpm, hwpm_info, "IP %d addr 0x%llx: " + "a_type %d inst_idx %d not available", + *ip_idx, find_addr, a_type, *inst_idx); + return false; + } + } + + /* Process further and return */ + return tegra_hwpm_addr_in_all_elements(hwpm, iia_func, + find_addr, ip_idx, inst_idx, element_idx, element_type, a_type); +} + +static bool tegra_hwpm_addr_in_all_instances(struct tegra_soc_hwpm *hwpm, + enum tegra_hwpm_funcs iia_func, + u64 find_addr, u32 *ip_idx, u32 *inst_idx, u32 *element_idx, + enum tegra_hwpm_element_type *element_type, u32 a_type) +{ + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + struct hwpm_ip *chip_ip = active_chip->chip_ips[*ip_idx]; + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; + u64 inst_offset = 0ULL; + u32 idx = 0U; + + tegra_hwpm_fn(hwpm, " "); + + /* Find instance to which address belongs to */ + inst_offset = tegra_hwpm_safe_sub_u64( + find_addr, inst_a_info->range_start); + idx = tegra_hwpm_safe_cast_u64_to_u32( + inst_offset / inst_a_info->inst_stride); + + /* Make sure instance index is valid */ + if (idx >= inst_a_info->inst_slots) { + tegra_hwpm_err(hwpm, "IP %d addr 0x%llx a_type %d: " + "inst_idx %d out of bounds", + *ip_idx, find_addr, a_type, idx); + return false; + } + + *inst_idx = idx; + + /* Process further and return */ + return tegra_hwpm_addr_in_single_instance(hwpm, iia_func, + find_addr, ip_idx, inst_idx, element_idx, + element_type, a_type); +} + +static bool tegra_hwpm_addr_in_single_ip(struct tegra_soc_hwpm *hwpm, + enum tegra_hwpm_funcs iia_func, + u64 find_addr, u32 *ip_idx, u32 *inst_idx, u32 *element_idx, + enum tegra_hwpm_element_type *element_type) +{ + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + struct hwpm_ip *chip_ip = active_chip->chip_ips[*ip_idx]; + u32 a_type; + bool found = false; + + tegra_hwpm_fn(hwpm, " "); + + if (chip_ip == NULL) { + tegra_hwpm_err(hwpm, "IP %d not populated as expected", *ip_idx); + return false; + } + + if (chip_ip->override_enable) { + /* This IP should not be configured for HWPM */ + tegra_hwpm_dbg(hwpm, hwpm_info, "IP %d override enabled", + *ip_idx); + return false; + } + + if (iia_func == TEGRA_HWPM_FIND_GIVEN_ADDRESS) { + /* Make sure this instance is available */ + if (!chip_ip->reserved) { + tegra_hwpm_dbg(hwpm, hwpm_info, "IP %d not reserved", + *ip_idx); + return false; + } + } + + if (chip_ip->num_instances == 0U) { + /* No instances in this IP */ + tegra_hwpm_dbg(hwpm, hwpm_info, "IP %d no instances", *ip_idx); + return false; + } + + /* Figure out which aperture type this address belongs to */ + for (a_type = 0U; a_type < TEGRA_HWPM_APERTURE_TYPE_MAX; a_type++) { + struct hwpm_ip_inst_per_aperture_info *inst_a_info = + &chip_ip->inst_aperture_info[a_type]; + + if ((find_addr < inst_a_info->range_start) || + (find_addr > inst_a_info->range_end)) { + /* Address not in this IP for this a_type */ + continue; + } + + /* Process further and return */ + found = tegra_hwpm_addr_in_all_instances(hwpm, iia_func, + find_addr, ip_idx, inst_idx, element_idx, + element_type, a_type); + if (found) { + break; + } + /* + * Address can belong to other type. + * For example, for MC IPs, broadcast aperture base address + * falls between perfmux address range. And, element + * corresponding to broadcast address in perfmux array is + * set to NULL. + */ + } + return found; +} + +static bool tegra_hwpm_addr_in_all_ip(struct tegra_soc_hwpm *hwpm, + enum tegra_hwpm_funcs iia_func, + u64 find_addr, u32 *ip_idx, u32 *inst_idx, u32 *element_idx, + enum tegra_hwpm_element_type *element_type) +{ + u32 idx; + bool found = false; + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + + tegra_hwpm_fn(hwpm, " "); + + for (idx = 0U; idx < active_chip->get_ip_max_idx(hwpm); idx++) { + struct hwpm_ip *chip_ip = active_chip->chip_ips[idx]; + + if (chip_ip == NULL) { + tegra_hwpm_err(hwpm, "IP %d not populated as expected", + idx); + return false; + } + + if (!chip_ip->reserved) { + continue; + } + + found = tegra_hwpm_addr_in_single_ip(hwpm, iia_func, find_addr, + &idx, inst_idx, element_idx, element_type); + if (found) { + *ip_idx = idx; + return true; + } + } + + return found; +} + +bool tegra_hwpm_aperture_for_address(struct tegra_soc_hwpm *hwpm, + enum tegra_hwpm_funcs iia_func, + u64 find_addr, u32 *ip_idx, u32 *inst_idx, u32 *element_idx, + enum tegra_hwpm_element_type *element_type) +{ + bool found = false; + + tegra_hwpm_fn(hwpm, " "); + + if ((ip_idx == NULL) || (inst_idx == NULL) || + (element_idx == NULL) || (element_type == NULL)) { + tegra_hwpm_err(hwpm, "NULL index pointer"); + return false; + } + + if (iia_func == TEGRA_HWPM_FIND_GIVEN_ADDRESS) { + /* IP index is not known, search in all IPs */ + found = tegra_hwpm_addr_in_all_ip(hwpm, iia_func, find_addr, + ip_idx, inst_idx, element_idx, element_type); + if (!found) { + tegra_hwpm_err(hwpm, "Address not in any IP"); + return found; + } + } + + if (iia_func == TEGRA_HWPM_MATCH_BASE_ADDRESS) { + found = tegra_hwpm_addr_in_single_ip(hwpm, iia_func, find_addr, + ip_idx, inst_idx, element_idx, element_type); + if (!found) { + tegra_hwpm_err(hwpm, "Address not in IP %d", *ip_idx); + return found; + } + } + + return found; +} diff --git a/common/tegra_hwpm_regops_utils.c b/common/tegra_hwpm_regops_utils.c index 9dc3959..a271dd9 100644 --- a/common/tegra_hwpm_regops_utils.c +++ b/common/tegra_hwpm_regops_utils.c @@ -15,17 +15,136 @@ #include -#include #include +#include +#include #include +#include + +static int tegra_hwpm_exec_reg_ops(struct tegra_soc_hwpm *hwpm, + struct tegra_soc_hwpm_reg_op *reg_op) +{ + bool found = false; + u32 ip_idx = TEGRA_SOC_HWPM_IP_INACTIVE; + u32 inst_idx = 0U, element_idx = 0U; + u32 a_type = 0U; + u32 reg_val = 0U; + u64 addr_hi = 0ULL; + enum tegra_hwpm_element_type element_type = HWPM_ELEMENT_INVALID; + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + struct hwpm_ip *chip_ip = NULL; + struct hwpm_ip_inst_per_aperture_info *inst_a_info = NULL; + struct hwpm_ip_inst *ip_inst = NULL; + struct hwpm_ip_element_info *e_info = NULL; + struct hwpm_ip_aperture *element = NULL; + + tegra_hwpm_fn(hwpm, " "); + + /* Find IP aperture containing phys_addr in allowlist */ + found = tegra_hwpm_aperture_for_address(hwpm, + TEGRA_HWPM_FIND_GIVEN_ADDRESS, reg_op->phys_addr, + &ip_idx, &inst_idx, &element_idx, &element_type); + if (!found) { + /* Silent failure as regops can continue on error */ + tegra_hwpm_dbg(hwpm, hwpm_verbose, + "Phys addr 0x%llx not available in any IP", + reg_op->phys_addr); + reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_INVALID_ADDR; + return -EINVAL; + } + + tegra_hwpm_dbg(hwpm, hwpm_verbose, + "Found addr 0x%llx IP %d inst_idx %d element_idx %d e_type %d", + reg_op->phys_addr, ip_idx, inst_idx, element_idx, element_type); + + switch (element_type) { + case HWPM_ELEMENT_PERFMON: + a_type = TEGRA_HWPM_APERTURE_TYPE_PERFMON; + break; + case HWPM_ELEMENT_PERFMUX: + case IP_ELEMENT_PERFMUX: + a_type = TEGRA_HWPM_APERTURE_TYPE_PERFMUX; + break; + case IP_ELEMENT_BROADCAST: + a_type = TEGRA_HWPM_APERTURE_TYPE_BROADCAST; + break; + case HWPM_ELEMENT_INVALID: + default: + tegra_hwpm_err(hwpm, "Invalid element type %d", element_type); + return -EINVAL; + } + + chip_ip = active_chip->chip_ips[ip_idx]; + inst_a_info = &chip_ip->inst_aperture_info[a_type]; + ip_inst = inst_a_info->inst_arr[inst_idx]; + e_info = &ip_inst->element_info[a_type]; + element = e_info->element_arr[element_idx]; + + switch (reg_op->cmd) { + case TEGRA_SOC_HWPM_REG_OP_CMD_RD32: + reg_op->reg_val_lo = tegra_hwpm_regops_readl(hwpm, + reg_op->phys_addr, ip_inst, element); + reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS; + break; + + case TEGRA_SOC_HWPM_REG_OP_CMD_RD64: + addr_hi = tegra_hwpm_safe_add_u64(reg_op->phys_addr, 4ULL); + reg_op->reg_val_lo = tegra_hwpm_regops_readl(hwpm, + reg_op->phys_addr, ip_inst, element); + reg_op->reg_val_hi = tegra_hwpm_regops_readl(hwpm, + addr_hi, ip_inst, element); + reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS; + break; + + /* Read Modify Write operation */ + case TEGRA_SOC_HWPM_REG_OP_CMD_WR32: + reg_val = tegra_hwpm_regops_readl(hwpm, + reg_op->phys_addr, ip_inst, element); + reg_val = set_field(reg_val, reg_op->mask_lo, + reg_op->reg_val_lo); + tegra_hwpm_regops_writel(hwpm, + reg_op->phys_addr, reg_val, ip_inst, element); + reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS; + break; + + /* Read Modify Write operation */ + case TEGRA_SOC_HWPM_REG_OP_CMD_WR64: + addr_hi = tegra_hwpm_safe_add_u64(reg_op->phys_addr, 4ULL); + + /* Lower 32 bits */ + reg_val = tegra_hwpm_regops_readl(hwpm, + reg_op->phys_addr, ip_inst, element); + reg_val = set_field(reg_val, reg_op->mask_lo, + reg_op->reg_val_lo); + tegra_hwpm_regops_writel(hwpm, + reg_op->phys_addr, reg_val, ip_inst, element); + + /* Upper 32 bits */ + reg_val = tegra_hwpm_regops_readl(hwpm, + addr_hi, ip_inst, element); + reg_val = set_field(reg_val, reg_op->mask_hi, + reg_op->reg_val_hi); + tegra_hwpm_regops_writel(hwpm, + reg_op->phys_addr, reg_val, ip_inst, element); + reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS; + break; + + default: + tegra_hwpm_err(hwpm, "Invalid reg op command(%u)", reg_op->cmd); + reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_INVALID_CMD; + return -EINVAL; + break; + } + + return 0; +} int tegra_hwpm_exec_regops(struct tegra_soc_hwpm *hwpm, struct tegra_soc_hwpm_exec_reg_ops *exec_reg_ops) { - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; int op_idx = 0; - struct tegra_soc_hwpm_reg_op *reg_op = NULL; int ret = 0; + struct tegra_soc_hwpm_reg_op *reg_op = NULL; tegra_hwpm_fn(hwpm, " "); @@ -46,11 +165,6 @@ int tegra_hwpm_exec_regops(struct tegra_soc_hwpm *hwpm, return -EINVAL; } - if (active_chip->exec_reg_ops == NULL) { - tegra_hwpm_err(hwpm, "exec_reg_ops uninitialized"); - return -ENODEV; - } - /* * Initialize flag to true assuming all regops will pass * If any regop fails, the flag will be reset to false. @@ -63,7 +177,7 @@ int tegra_hwpm_exec_regops(struct tegra_soc_hwpm *hwpm, "reg op: idx(%d), phys(0x%llx), cmd(%u)", op_idx, reg_op->phys_addr, reg_op->cmd); - ret = active_chip->exec_reg_ops(hwpm, reg_op); + ret = tegra_hwpm_exec_reg_ops(hwpm, reg_op); if (ret < 0) { tegra_hwpm_err(hwpm, "exec_reg_ops %d failed", op_idx); exec_reg_ops->b_all_reg_ops_passed = false; diff --git a/common/tegra_hwpm_resource_utils.c b/common/tegra_hwpm_resource_utils.c index 3ad8f11..57c2023 100644 --- a/common/tegra_hwpm_resource_utils.c +++ b/common/tegra_hwpm_resource_utils.c @@ -19,409 +19,40 @@ #include #include -int tegra_hwpm_func_single_aperture(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, - u32 inst_idx, u32 aperture_idx, enum hwpm_aperture_type a_type) +int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm) { - struct hwpm_ip_aperture *aperture = NULL; - int err = 0, ret = 0; - - if (a_type == HWPM_APERTURE_PERFMUX) { - aperture = chip_ip->ip_perfmux[aperture_idx]; - } else if (a_type == HWPM_APERTURE_PERFMON) { - aperture = chip_ip->ip_perfmon[aperture_idx]; - } else { - tegra_hwpm_err(hwpm, "INVALID a_type %d", a_type); - return -EINVAL; - } - - if (aperture == NULL) { - return 0; - } - - if (aperture->hw_inst_mask != BIT(inst_idx)) { - return 0; - } - - switch (iia_func) { - case TEGRA_HWPM_GET_ALIST_SIZE: - if (aperture->alist) { - hwpm->full_alist_size = - tegra_hwpm_safe_add_u64( - hwpm->full_alist_size, - aperture->alist_size); - } else { - tegra_hwpm_err(hwpm, "IP %d" - " aperture type %d idx %d NULL alist", - ip_idx, a_type, aperture_idx); - } - break; - case TEGRA_HWPM_COMBINE_ALIST: - err = hwpm->active_chip->copy_alist(hwpm, - aperture, func_args->alist, &func_args->full_alist_idx); - if (err != 0) { - tegra_hwpm_err(hwpm, "IP %d" - " aperture type %d idx %d alist copy failed", - ip_idx, a_type, aperture_idx); - return err; - } - break; - case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE: - if (a_type == HWPM_APERTURE_PERFMUX) { - err = tegra_hwpm_perfmux_reserve(hwpm, aperture); - if (err != 0) { - tegra_hwpm_err(hwpm, "IP %d aperture" - " type %d idx %d reserve failed", - ip_idx, aperture_idx); - goto fail; - } - } else if (a_type == HWPM_APERTURE_PERFMON) { - err = tegra_hwpm_perfmon_reserve(hwpm, aperture); - if (err != 0) { - tegra_hwpm_err(hwpm, "IP %d aperture" - " type %d idx %d reserve failed", - ip_idx, aperture_idx); - goto fail; - } - } - break; - case TEGRA_HWPM_RELEASE_RESOURCES: - if (a_type == HWPM_APERTURE_PERFMUX) { - ret = hwpm->active_chip->perfmux_disable(hwpm, aperture); - if (ret != 0) { - tegra_hwpm_err(hwpm, "IP %d aperture" - " type %d idx %d disable failed", - ip_idx, aperture_idx); - } - - ret = tegra_hwpm_perfmux_release(hwpm, aperture); - if (ret != 0) { - tegra_hwpm_err(hwpm, "IP %d aperture" - " type %d idx %d release failed", - ip_idx, aperture_idx); - } - } else if (a_type == HWPM_APERTURE_PERFMON) { - ret = hwpm->active_chip->perfmon_disable(hwpm, aperture); - if (ret != 0) { - tegra_hwpm_err(hwpm, "IP %d aperture" - " type %d idx %d disable failed", - ip_idx, aperture_idx); - } - - ret = tegra_hwpm_perfmon_release(hwpm, aperture); - if (ret != 0) { - tegra_hwpm_err(hwpm, "IP %d aperture" - " type %d idx %d release failed", - ip_idx, aperture_idx); - } - } - break; - case TEGRA_HWPM_BIND_RESOURCES: - err = hwpm->active_chip->zero_alist_regs(hwpm, aperture); - if (err != 0) { - tegra_hwpm_err(hwpm, "IP %d aperture" - " type %d idx %d zero regs failed", - ip_idx, aperture_idx); - goto fail; - } - if (a_type == HWPM_APERTURE_PERFMON) { - err = hwpm->active_chip->perfmon_enable(hwpm, aperture); - if (err != 0) { - tegra_hwpm_err(hwpm, "IP %d aperture" - " type %d idx %d enable failed", - ip_idx, aperture_idx); - goto fail; - } - } - break; - default: - tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func); - return -EINVAL; - break; - } - - return 0; -fail: - return err; -} - -int tegra_hwpm_func_all_perfmons(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, - u32 inst_idx) -{ - u32 perfmon_idx; int err = 0; - for (perfmon_idx = 0U; perfmon_idx < chip_ip->num_perfmon_slots; - perfmon_idx++) { - err = tegra_hwpm_func_single_aperture( - hwpm, func_args, iia_func, ip_idx, - chip_ip, inst_idx, perfmon_idx, HWPM_APERTURE_PERFMON); - if (err < 0) { - tegra_hwpm_err(hwpm, - "IP %d inst %d perfmon %d func 0x%x failed", - ip_idx, inst_idx, perfmon_idx, iia_func); - goto fail; - } - } - - return 0; -fail: - return err; -} - -int tegra_hwpm_func_all_perfmuxes(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, - u32 inst_idx) -{ - u32 perfmux_idx; - int err = 0; - - for (perfmux_idx = 0U; perfmux_idx < chip_ip->num_perfmux_slots; - perfmux_idx++) { - err = tegra_hwpm_func_single_aperture( - hwpm, func_args, iia_func, ip_idx, - chip_ip, inst_idx, perfmux_idx, HWPM_APERTURE_PERFMUX); - if (err < 0) { - tegra_hwpm_err(hwpm, - "IP %d inst %d perfmux %d func 0x%x failed", - ip_idx, inst_idx, perfmux_idx, iia_func); - goto fail; - } - } - - return 0; -fail: - return err; -} - -int tegra_hwpm_func_all_inst(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip) -{ - unsigned long inst_idx = 0UL; - unsigned long floorsweep_info = 0UL; - unsigned long reserved_insts = 0UL; - int err = 0; - - /* Execute tasks for all instances if any */ - floorsweep_info = (unsigned long)chip_ip->fs_mask; - - for_each_set_bit(inst_idx, &floorsweep_info, 32U) { - switch (iia_func) { - case TEGRA_HWPM_GET_ALIST_SIZE: - /* do nothing, continue to apertures */ - break; - case TEGRA_HWPM_COMBINE_ALIST: - func_args->full_alist_idx = 0ULL; - break; - case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE: - /* do nothing, continue to apertures */ - break; - case TEGRA_HWPM_BIND_RESOURCES: - /* do nothing, continue to instances */ - break; - case TEGRA_HWPM_RELEASE_RESOURCES: - /* do nothing, continue to instances */ - break; - default: - tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func); - goto fail; - break; - } - - /* Continue functionality for all apertures */ - err = tegra_hwpm_func_all_perfmuxes( - hwpm, func_args, iia_func, ip_idx, chip_ip, inst_idx); - if (err < 0) { - tegra_hwpm_err(hwpm, "IP %d inst %d func 0x%x failed", - ip_idx, inst_idx, iia_func); - goto fail; - } - - err = tegra_hwpm_func_all_perfmons( - hwpm, func_args, iia_func, ip_idx, chip_ip, inst_idx); - if (err < 0) { - tegra_hwpm_err(hwpm, "IP %d inst %d func 0x%x failed", - ip_idx, inst_idx, iia_func); - goto fail; - } - - /* Post execute functionality */ - switch (iia_func) { - case TEGRA_HWPM_GET_ALIST_SIZE: - /* do nothing, continue to apertures */ - break; - case TEGRA_HWPM_COMBINE_ALIST: - /* do nothing, continue to apertures */ - break; - case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE: - reserved_insts |= BIT(inst_idx); - break; - case TEGRA_HWPM_BIND_RESOURCES: - /* do nothing, continue to instances */ - break; - case TEGRA_HWPM_RELEASE_RESOURCES: - /* do nothing, continue to instances */ - break; - default: - tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func); - goto fail; - break; - } - } - - return 0; - -fail: - if (iia_func == TEGRA_HWPM_RESERVE_GIVEN_RESOURCE) { - /* Revert previously reserved instances of this IP */ - for_each_set_bit(inst_idx, &reserved_insts, 32U) { - /* Release all apertures belonging to this instance */ - err = tegra_hwpm_func_all_perfmuxes(hwpm, func_args, - TEGRA_HWPM_RELEASE_RESOURCES, ip_idx, - chip_ip, inst_idx); - if (err < 0) { - tegra_hwpm_err(hwpm, - "IP %d inst %d func 0x%x failed", - ip_idx, inst_idx, iia_func); - return err; - } - - err = tegra_hwpm_func_all_perfmons(hwpm, func_args, - TEGRA_HWPM_RELEASE_RESOURCES, ip_idx, - chip_ip, inst_idx); - if (err < 0) { - tegra_hwpm_err(hwpm, - "IP %d inst %d func 0x%x failed", - ip_idx, inst_idx, iia_func); - return err; - } - } - } - - return err; -} - -int tegra_hwpm_func_single_ip(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx) -{ struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_idx]; - int err = 0; tegra_hwpm_fn(hwpm, " "); - if (chip_ip == NULL) { - tegra_hwpm_err(hwpm, "IP %d not populated", ip_idx); - return -ENODEV; + err = tegra_hwpm_func_single_ip(hwpm, NULL, + TEGRA_HWPM_RESERVE_GIVEN_RESOURCE, + active_chip->get_rtr_int_idx(hwpm)); + if (err != 0) { + tegra_hwpm_err(hwpm, "failed to reserve IP %d", + active_chip->get_rtr_int_idx(hwpm)); + return err; } - - switch (iia_func) { - case TEGRA_HWPM_GET_ALIST_SIZE: - case TEGRA_HWPM_COMBINE_ALIST: - case TEGRA_HWPM_BIND_RESOURCES: - /* Skip unavailable IPs */ - if (!chip_ip->reserved) { - return 0; - } - - if (chip_ip->fs_mask == 0U) { - /* No IP instance is available */ - return 0; - } - break; - case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE: - /* PMA and RTR are already reserved */ - if (ip_idx == active_chip->get_rtr_int_idx(hwpm)) { - return 0; - } - /* Skip IPs which are already reserved */ - if (chip_ip->reserved) { - tegra_hwpm_dbg(hwpm, hwpm_info, - "Chip IP %d already reserved", ip_idx); - return 0; - } - - /* Make sure IP override is not enabled */ - if (chip_ip->override_enable) { - tegra_hwpm_dbg(hwpm, hwpm_info, - "Chip IP %d not available", ip_idx); - return 0; - } - - break; - case TEGRA_HWPM_RELEASE_RESOURCES: - /* PMA and RTR will be released later */ - if (ip_idx == active_chip->get_rtr_int_idx(hwpm)) { - return 0; - } - /* Skip unavailable IPs */ - if (!chip_ip->reserved) { - return 0; - } - - if (chip_ip->fs_mask == 0U) { - /* No IP instance is available */ - return 0; - } - break; - default: - tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func); - goto fail; - break; - } - - /* Continue functionality for all instances in this IP */ - err = tegra_hwpm_func_all_inst(hwpm, func_args, iia_func, - ip_idx, chip_ip); - if (err < 0) { - tegra_hwpm_err(hwpm, "IP %d func 0x%x failed", - ip_idx, iia_func); - goto fail; - } - - /* Post execute functionality */ - if (iia_func == TEGRA_HWPM_RESERVE_GIVEN_RESOURCE) { - chip_ip->reserved = true; - } - if (iia_func == TEGRA_HWPM_RELEASE_RESOURCES) { - chip_ip->reserved = false; - } - - return 0; -fail: return err; } -int tegra_hwpm_func_all_ip(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func) +int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm) { - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - u32 ip_idx; int err = 0; + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; tegra_hwpm_fn(hwpm, " "); - for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(hwpm); - ip_idx++) { - - err = tegra_hwpm_func_single_ip( - hwpm, func_args, iia_func, ip_idx); - if (err < 0) { - tegra_hwpm_err(hwpm, "IP %d func 0x%x failed", - ip_idx, iia_func); - goto fail; - } + err = tegra_hwpm_func_single_ip(hwpm, NULL, + TEGRA_HWPM_RELEASE_RESOURCES, + active_chip->get_rtr_int_idx(hwpm)); + if (err != 0) { + tegra_hwpm_err(hwpm, "failed to release IP %d", + active_chip->get_rtr_int_idx(hwpm)); + return err; } - - return 0; -fail: return err; } @@ -471,7 +102,7 @@ int tegra_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm) return err; } - return 0; + return err; } int tegra_hwpm_release_resources(struct tegra_soc_hwpm *hwpm) diff --git a/hal/t234/ip/display/t234_hwpm_ip_display.c b/hal/t234/ip/display/t234_hwpm_ip_display.c index 746038d..1bb39ee 100644 --- a/hal/t234/ip/display/t234_hwpm_ip_display.c +++ b/hal/t234/ip/display/t234_hwpm_ip_display.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_display_perfmon_static_array[ - T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST * - T234_HWPM_IP_DISPLAY_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_display_inst0_perfmon_element_static_array[ + T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_nvdisplay0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_disp_base_r(), .end_abs_pa = addr_map_rpg_pm_disp_limit_r(), .start_pa = 0ULL, @@ -41,19 +36,14 @@ hwpm_ip_perfmon t234_display_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_display_perfmux_static_array[ - T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_DISPLAY_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_display_inst0_perfmux_element_static_array[ + T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_disp_base_r(), .end_abs_pa = addr_map_disp_limit_r(), .start_pa = 0ULL, @@ -65,28 +55,116 @@ hwpm_ip_perfmux t234_display_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_display_inst_static_array[ + T234_HWPM_IP_DISPLAY_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_display_inst0_perfmux_element_static_array, + .range_start = addr_map_disp_base_r(), + .range_end = addr_map_disp_limit_r(), + .element_stride = + addr_map_disp_limit_r() - + addr_map_disp_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_DISPLAY_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST, + .element_static_array = + t234_display_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_disp_base_r(), + .range_end = addr_map_rpg_pm_disp_limit_r(), + .element_stride = + addr_map_rpg_pm_disp_limit_r() - + addr_map_rpg_pm_disp_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_display = { .num_instances = T234_HWPM_IP_DISPLAY_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_display_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_disp_base_r(), - .perfmon_range_end = addr_map_rpg_pm_disp_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_disp_limit_r() - - addr_map_rpg_pm_disp_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_disp_base_r(), - .perfmux_range_end = addr_map_disp_limit_r(), - .inst_perfmux_stride = addr_map_disp_limit_r() - - addr_map_disp_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_disp_base_r(), + .range_end = addr_map_disp_limit_r(), + .inst_stride = addr_map_disp_limit_r() - + addr_map_disp_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_disp_base_r(), + .range_end = addr_map_rpg_pm_disp_limit_r(), + .inst_stride = addr_map_rpg_pm_disp_limit_r() - + addr_map_rpg_pm_disp_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_display_perfmon_static_array, - .perfmux_static_array = t234_display_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/display/t234_hwpm_ip_display.h b/hal/t234/ip/display/t234_hwpm_ip_display.h index 33ea99c..11aecf6 100644 --- a/hal/t234/ip/display/t234_hwpm_ip_display.h +++ b/hal/t234/ip/display/t234_hwpm_ip_display.h @@ -21,6 +21,7 @@ #define T234_HWPM_IP_DISPLAY_NUM_INSTANCES 1U #define T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST 1U #define T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_DISPLAY_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_display; diff --git a/hal/t234/ip/isp/t234_hwpm_ip_isp.c b/hal/t234/ip/isp/t234_hwpm_ip_isp.c index cf6e0b5..9878506 100644 --- a/hal/t234/ip/isp/t234_hwpm_ip_isp.c +++ b/hal/t234/ip/isp/t234_hwpm_ip_isp.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_isp_perfmon_static_array[ - T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST * - T234_HWPM_IP_ISP_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_isp_inst0_perfmon_element_static_array[ + T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_isp0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_isp0_base_r(), .end_abs_pa = addr_map_rpg_pm_isp0_limit_r(), .start_pa = 0, @@ -41,19 +36,14 @@ hwpm_ip_perfmon t234_isp_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_isp_perfmux_static_array[ - T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_ISP_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_isp_inst0_perfmux_element_static_array[ + T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_isp_thi_base_r(), .end_abs_pa = addr_map_isp_thi_limit_r(), .start_pa = 0, @@ -65,28 +55,113 @@ hwpm_ip_perfmux t234_isp_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_isp_inst_static_array[ + T234_HWPM_IP_ISP_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_isp_inst0_perfmux_element_static_array, + .range_start = addr_map_isp_thi_base_r(), + .range_end = addr_map_isp_thi_limit_r(), + .element_stride = addr_map_isp_thi_limit_r() - + addr_map_isp_thi_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_ISP_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST, + .element_static_array = + t234_isp_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_isp0_base_r(), + .range_end = addr_map_rpg_pm_isp0_limit_r(), + .element_stride = addr_map_rpg_pm_isp0_limit_r() - + addr_map_rpg_pm_isp0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + struct hwpm_ip t234_hwpm_ip_isp = { .num_instances = T234_HWPM_IP_ISP_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_isp_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_isp0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_isp0_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_isp0_limit_r() - - addr_map_rpg_pm_isp0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_isp_thi_base_r(), - .perfmux_range_end = addr_map_isp_thi_limit_r(), - .inst_perfmux_stride = addr_map_isp_thi_limit_r() - - addr_map_isp_thi_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_isp_thi_base_r(), + .range_end = addr_map_isp_thi_limit_r(), + .inst_stride = addr_map_isp_thi_limit_r() - + addr_map_isp_thi_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_isp0_base_r(), + .range_end = addr_map_rpg_pm_isp0_limit_r(), + .inst_stride = addr_map_rpg_pm_isp0_limit_r() - + addr_map_rpg_pm_isp0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_isp_perfmon_static_array, - .perfmux_static_array = t234_isp_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/isp/t234_hwpm_ip_isp.h b/hal/t234/ip/isp/t234_hwpm_ip_isp.h index 1c4d498..75a2116 100644 --- a/hal/t234/ip/isp/t234_hwpm_ip_isp.h +++ b/hal/t234/ip/isp/t234_hwpm_ip_isp.h @@ -21,6 +21,7 @@ #define T234_HWPM_IP_ISP_NUM_INSTANCES 1U #define T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST 1U #define T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_ISP_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_isp; diff --git a/hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.c b/hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.c index ebf167d..4979a02 100644 --- a/hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.c +++ b/hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_mgbe_perfmon_static_array[ - T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST * - T234_HWPM_IP_MGBE_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mgbe_inst0_perfmon_element_static_array[ + T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_mgbe0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mgbe0_base_r(), .end_abs_pa = addr_map_rpg_pm_mgbe0_limit_r(), .start_pa = 0, @@ -39,16 +34,16 @@ hwpm_ip_perfmon t234_mgbe_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_mgbe_inst1_perfmon_element_static_array[ + T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(1), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_mgbe1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mgbe1_base_r(), .end_abs_pa = addr_map_rpg_pm_mgbe1_limit_r(), .start_pa = 0, @@ -58,16 +53,16 @@ hwpm_ip_perfmon t234_mgbe_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_mgbe_inst2_perfmon_element_static_array[ + T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(2), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_mgbe2", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mgbe2_base_r(), .end_abs_pa = addr_map_rpg_pm_mgbe2_limit_r(), .start_pa = 0, @@ -77,16 +72,16 @@ hwpm_ip_perfmon t234_mgbe_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_mgbe_inst3_perfmon_element_static_array[ + T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(3), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_mgbe3", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mgbe3_base_r(), .end_abs_pa = addr_map_rpg_pm_mgbe3_limit_r(), .start_pa = 0, @@ -98,19 +93,14 @@ hwpm_ip_perfmon t234_mgbe_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_mgbe_perfmux_static_array[ - T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_MGBE_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mgbe_inst0_perfmux_element_static_array[ + T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mgbe0_mac_rm_base_r(), .end_abs_pa = addr_map_mgbe0_mac_rm_limit_r(), .start_pa = 0, @@ -120,16 +110,16 @@ hwpm_ip_perfmux t234_mgbe_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_mgbe_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_mgbe_inst1_perfmux_element_static_array[ + T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(1), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mgbe1_mac_rm_base_r(), .end_abs_pa = addr_map_mgbe1_mac_rm_limit_r(), .start_pa = 0, @@ -139,16 +129,16 @@ hwpm_ip_perfmux t234_mgbe_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_mgbe_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_mgbe_inst2_perfmux_element_static_array[ + T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(2), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mgbe2_mac_rm_base_r(), .end_abs_pa = addr_map_mgbe2_mac_rm_limit_r(), .start_pa = 0, @@ -158,16 +148,16 @@ hwpm_ip_perfmux t234_mgbe_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_mgbe_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_mgbe_inst3_perfmux_element_static_array[ + T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(3), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mgbe3_mac_rm_base_r(), .end_abs_pa = addr_map_mgbe3_mac_rm_limit_r(), .start_pa = 0, @@ -179,28 +169,291 @@ hwpm_ip_perfmux t234_mgbe_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_mgbe_inst_static_array[ + T234_HWPM_IP_MGBE_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_mgbe_inst0_perfmux_element_static_array, + .range_start = addr_map_mgbe0_mac_rm_base_r(), + .range_end = addr_map_mgbe0_mac_rm_limit_r(), + .element_stride = addr_map_mgbe0_mac_rm_limit_r() - + addr_map_mgbe0_mac_rm_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_mgbe_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mgbe0_base_r(), + .range_end = addr_map_rpg_pm_mgbe0_limit_r(), + .element_stride = addr_map_rpg_pm_mgbe0_limit_r() - + addr_map_rpg_pm_mgbe0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(1), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_mgbe_inst1_perfmux_element_static_array, + .range_start = addr_map_mgbe1_mac_rm_base_r(), + .range_end = addr_map_mgbe1_mac_rm_limit_r(), + .element_stride = addr_map_mgbe1_mac_rm_limit_r() - + addr_map_mgbe1_mac_rm_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_mgbe_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mgbe1_base_r(), + .range_end = addr_map_rpg_pm_mgbe1_limit_r(), + .element_stride = addr_map_rpg_pm_mgbe1_limit_r() - + addr_map_rpg_pm_mgbe1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(2), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_mgbe_inst2_perfmux_element_static_array, + .range_start = addr_map_mgbe2_mac_rm_base_r(), + .range_end = addr_map_mgbe2_mac_rm_limit_r(), + .element_stride = addr_map_mgbe2_mac_rm_limit_r() - + addr_map_mgbe2_mac_rm_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_mgbe_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mgbe2_base_r(), + .range_end = addr_map_rpg_pm_mgbe2_limit_r(), + .element_stride = addr_map_rpg_pm_mgbe2_limit_r() - + addr_map_rpg_pm_mgbe2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(3), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_mgbe_inst3_perfmux_element_static_array, + .range_start = addr_map_mgbe3_mac_rm_base_r(), + .range_end = addr_map_mgbe3_mac_rm_limit_r(), + .element_stride = addr_map_mgbe3_mac_rm_limit_r() - + addr_map_mgbe3_mac_rm_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_mgbe_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mgbe3_base_r(), + .range_end = addr_map_rpg_pm_mgbe3_limit_r(), + .element_stride = addr_map_rpg_pm_mgbe3_limit_r() - + addr_map_rpg_pm_mgbe3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_mgbe = { .num_instances = T234_HWPM_IP_MGBE_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_mgbe_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_mgbe0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_mgbe3_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_mgbe0_limit_r() - - addr_map_rpg_pm_mgbe0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_mgbe0_mac_rm_base_r(), - .perfmux_range_end = addr_map_mgbe3_mac_rm_limit_r(), - .inst_perfmux_stride = addr_map_mgbe0_mac_rm_limit_r() - - addr_map_mgbe0_mac_rm_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_mgbe0_mac_rm_base_r(), + .range_end = addr_map_mgbe3_mac_rm_limit_r(), + .inst_stride = addr_map_mgbe0_mac_rm_limit_r() - + addr_map_mgbe0_mac_rm_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_mgbe0_base_r(), + .range_end = addr_map_rpg_pm_mgbe3_limit_r(), + .inst_stride = addr_map_rpg_pm_mgbe0_limit_r() - + addr_map_rpg_pm_mgbe0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_mgbe_perfmon_static_array, - .perfmux_static_array = t234_mgbe_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.h b/hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.h index de86c3c..57e7710 100644 --- a/hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.h +++ b/hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.h @@ -18,9 +18,10 @@ #define T234_HWPM_ACTIVE_IP_MGBE T234_HWPM_IP_MGBE /* This data should ideally be available in HW headers */ -#define T234_HWPM_IP_MGBE_NUM_INSTANCES 4U -#define T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST 1U -#define T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_MGBE_NUM_INSTANCES 4U +#define T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST 1U +#define T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_MGBE_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_mgbe; diff --git a/hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.c b/hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.c index 30be9e9..d8fcacb 100644 --- a/hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.c +++ b/hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ - T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST * - T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_array[ + T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parta0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss0_base_r(), .end_abs_pa = addr_map_rpg_pm_mss0_limit_r(), .start_pa = 0, @@ -40,15 +35,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .dt_index = 2U, .dt_mmio = NULL, .name = "perfmon_msschannel_parta1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss1_base_r(), .end_abs_pa = addr_map_rpg_pm_mss1_limit_r(), .start_pa = 0, @@ -59,15 +50,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(2), + .dt_index = 3U, .dt_mmio = NULL, .name = "perfmon_msschannel_parta2", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss2_base_r(), .end_abs_pa = addr_map_rpg_pm_mss2_limit_r(), .start_pa = 0, @@ -78,15 +65,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(3), + .dt_index = 4U, .dt_mmio = NULL, .name = "perfmon_msschannel_parta3", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss3_base_r(), .end_abs_pa = addr_map_rpg_pm_mss3_limit_r(), .start_pa = 0, @@ -97,15 +80,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(1), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(4), + .dt_index = 5U, .dt_mmio = NULL, .name = "perfmon_msschannel_partb0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss4_base_r(), .end_abs_pa = addr_map_rpg_pm_mss4_limit_r(), .start_pa = 0, @@ -116,15 +95,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(1), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(5), + .dt_index = 6U, .dt_mmio = NULL, .name = "perfmon_msschannel_partb1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss5_base_r(), .end_abs_pa = addr_map_rpg_pm_mss5_limit_r(), .start_pa = 0, @@ -135,15 +110,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(1), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(6), + .dt_index = 7U, .dt_mmio = NULL, .name = "perfmon_msschannel_partb2", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss6_base_r(), .end_abs_pa = addr_map_rpg_pm_mss6_limit_r(), .start_pa = 0, @@ -154,15 +125,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(1), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(7), + .dt_index = 8U, .dt_mmio = NULL, .name = "perfmon_msschannel_partb3", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss7_base_r(), .end_abs_pa = addr_map_rpg_pm_mss7_limit_r(), .start_pa = 0, @@ -173,15 +140,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(1), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(8), + .dt_index = 9U, .dt_mmio = NULL, .name = "perfmon_msschannel_partc0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss8_base_r(), .end_abs_pa = addr_map_rpg_pm_mss8_limit_r(), .start_pa = 0, @@ -192,15 +155,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(2), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(9), + .dt_index = 10U, .dt_mmio = NULL, .name = "perfmon_msschannel_partc1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss9_base_r(), .end_abs_pa = addr_map_rpg_pm_mss9_limit_r(), .start_pa = 0, @@ -211,15 +170,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(2), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(10), + .dt_index = 11U, .dt_mmio = NULL, .name = "perfmon_msschannel_partc2", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss10_base_r(), .end_abs_pa = addr_map_rpg_pm_mss10_limit_r(), .start_pa = 0, @@ -230,15 +185,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(2), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(11), + .dt_index = 12U, .dt_mmio = NULL, .name = "perfmon_msschannel_partc3", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss11_base_r(), .end_abs_pa = addr_map_rpg_pm_mss11_limit_r(), .start_pa = 0, @@ -249,15 +200,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(3), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(12), + .dt_index = 13U, .dt_mmio = NULL, .name = "perfmon_msschannel_partd0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss12_base_r(), .end_abs_pa = addr_map_rpg_pm_mss12_limit_r(), .start_pa = 0, @@ -268,15 +215,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(3), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(13), + .dt_index = 14U, .dt_mmio = NULL, .name = "perfmon_msschannel_partd1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss13_base_r(), .end_abs_pa = addr_map_rpg_pm_mss13_limit_r(), .start_pa = 0, @@ -287,15 +230,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(3), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(14), + .dt_index = 15U, .dt_mmio = NULL, .name = "perfmon_msschannel_partd2", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss14_base_r(), .end_abs_pa = addr_map_rpg_pm_mss14_limit_r(), .start_pa = 0, @@ -306,15 +245,11 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(3), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(15), + .dt_index = 16U, .dt_mmio = NULL, .name = "perfmon_msschannel_partd3", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mss15_base_r(), .end_abs_pa = addr_map_rpg_pm_mss15_limit_r(), .start_pa = 0, @@ -326,246 +261,14 @@ hwpm_ip_perfmon t234_mss_channel_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_mss_channel_perfmux_static_array[ - T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_array[ + T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(2), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 1U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc8_base_r(), - .end_abs_pa = addr_map_mc8_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(2), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc9_base_r(), - .end_abs_pa = addr_map_mc9_limit_r(), - .fake_registers = NULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(2), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc10_base_r(), - .end_abs_pa = addr_map_mc10_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(2), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc11_base_r(), - .end_abs_pa = addr_map_mc11_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(3), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc12_base_r(), - .end_abs_pa = addr_map_mc12_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(3), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc13_base_r(), - .end_abs_pa = addr_map_mc13_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(3), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc14_base_r(), - .end_abs_pa = addr_map_mc14_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(3), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc15_base_r(), - .end_abs_pa = addr_map_mc15_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(1), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc4_base_r(), - .end_abs_pa = addr_map_mc4_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(1), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc5_base_r(), - .end_abs_pa = addr_map_mc5_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(1), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc6_base_r(), - .end_abs_pa = addr_map_mc6_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(1), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc7_base_r(), - .end_abs_pa = addr_map_mc7_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc0_base_r(), .end_abs_pa = addr_map_mc0_limit_r(), .start_pa = 0ULL, @@ -576,15 +279,11 @@ hwpm_ip_perfmux t234_mss_channel_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(1), + .dt_index = 2U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc1_base_r(), .end_abs_pa = addr_map_mc1_limit_r(), .start_pa = 0ULL, @@ -595,34 +294,26 @@ hwpm_ip_perfmux t234_mss_channel_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(2), + .dt_index = 3U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc2_base_r(), .end_abs_pa = addr_map_mc2_limit_r(), .start_pa = 0ULL, .end_pa = 0ULL, .base_pa = 0ULL, .alist = t234_mss_channel_alist, - .alist_size = ARRAY_SIZE(t234_mss_channel_alist),\ + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(3), + .dt_index = 4U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc3_base_r(), .end_abs_pa = addr_map_mc3_limit_r(), .start_pa = 0ULL, @@ -632,30 +323,317 @@ hwpm_ip_perfmux t234_mss_channel_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_mss_channel_alist), .fake_registers = NULL, }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(4), + .dt_index = 5U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc4_base_r(), + .end_abs_pa = addr_map_mc4_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(5), + .dt_index = 6U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc5_base_r(), + .end_abs_pa = addr_map_mc5_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(6), + .dt_index = 7U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc6_base_r(), + .end_abs_pa = addr_map_mc6_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(7), + .dt_index = 8U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc7_base_r(), + .end_abs_pa = addr_map_mc7_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(8), + .dt_index = 9U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc8_base_r(), + .end_abs_pa = addr_map_mc8_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(9), + .dt_index = 10U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc9_base_r(), + .end_abs_pa = addr_map_mc9_limit_r(), + .fake_registers = NULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(10), + .dt_index = 11U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc10_base_r(), + .end_abs_pa = addr_map_mc10_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(11), + .dt_index = 12U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc11_base_r(), + .end_abs_pa = addr_map_mc11_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(12), + .dt_index = 13U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc12_base_r(), + .end_abs_pa = addr_map_mc12_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(13), + .dt_index = 14U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc13_base_r(), + .end_abs_pa = addr_map_mc13_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(14), + .dt_index = 15U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc14_base_r(), + .end_abs_pa = addr_map_mc14_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(15), + .dt_index = 16U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc15_base_r(), + .end_abs_pa = addr_map_mc15_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, }; +struct hwpm_ip_aperture t234_mss_channel_inst0_broadcast_element_static_array[ + T234_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +struct hwpm_ip_inst t234_mss_channel_inst_static_array[ + T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_mss_channel_inst0_perfmux_element_static_array, + .range_start = addr_map_mc8_base_r(), + .range_end = addr_map_mc3_limit_r(), + .element_stride = addr_map_mc0_limit_r() - + addr_map_mc0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + t234_mss_channel_inst0_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + t234_mss_channel_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mss0_base_r(), + .range_end = addr_map_rpg_pm_mss15_limit_r(), + .element_stride = addr_map_rpg_pm_mss0_limit_r() - + addr_map_rpg_pm_mss0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_mss_channel = { .num_instances = T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_mss_channel_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_mss0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_mss15_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_mss0_limit_r() - - addr_map_rpg_pm_mss0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_mc8_base_r(), - .perfmux_range_end = addr_map_mc3_limit_r(), - .inst_perfmux_stride = addr_map_mc0_limit_r() - - addr_map_mc0_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_mc8_base_r(), + .range_end = addr_map_mc3_limit_r(), + .inst_stride = addr_map_mc3_limit_r() - + addr_map_mc8_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .inst_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_mss0_base_r(), + .range_end = addr_map_rpg_pm_mss15_limit_r(), + .inst_stride = addr_map_rpg_pm_mss15_limit_r() - + addr_map_rpg_pm_mss0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_mss_channel_perfmon_static_array, - .perfmux_static_array = t234_mss_channel_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.h b/hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.h index ae03955..28b04d2 100644 --- a/hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.h +++ b/hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.h @@ -18,9 +18,10 @@ #define T234_HWPM_ACTIVE_IP_MSS_CHANNEL T234_HWPM_IP_MSS_CHANNEL /* This data should ideally be available in HW headers */ -#define T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES 4U -#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST 4U -#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST 4U +#define T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES 1U +#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST 16U +#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST 16U +#define T234_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST 1U extern struct hwpm_ip t234_hwpm_ip_mss_channel; diff --git a/hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.c b/hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.c index afed5dc..f591815 100644 --- a/hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.c +++ b/hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_mss_gpu_hub_perfmon_static_array[ - T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST * - T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmon_element_static_array[ + T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_mssnvlhsh0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mssnvl_base_r(), .end_abs_pa = addr_map_rpg_pm_mssnvl_limit_r(), .start_pa = 0, @@ -41,38 +36,14 @@ hwpm_ip_perfmon t234_mss_gpu_hub_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_mss_gpu_hub_perfmux_static_array[ - T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_array[ + T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 1U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mss_nvlink_8_base_r(), - .end_abs_pa = addr_map_mss_nvlink_8_limit_r(), - .start_pa = 0, - .end_pa = 0, - .base_pa = 0ULL, - .alist = t234_mss_nvlink_alist, - .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mss_nvlink_1_base_r(), .end_abs_pa = addr_map_mss_nvlink_1_limit_r(), .start_pa = 0, @@ -83,15 +54,11 @@ hwpm_ip_perfmux t234_mss_gpu_hub_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(1), + .dt_index = 2U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mss_nvlink_2_base_r(), .end_abs_pa = addr_map_mss_nvlink_2_limit_r(), .start_pa = 0, @@ -102,15 +69,11 @@ hwpm_ip_perfmux t234_mss_gpu_hub_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(2), + .dt_index = 3U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mss_nvlink_3_base_r(), .end_abs_pa = addr_map_mss_nvlink_3_limit_r(), .start_pa = 0, @@ -121,15 +84,11 @@ hwpm_ip_perfmux t234_mss_gpu_hub_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(3), + .dt_index = 4U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mss_nvlink_4_base_r(), .end_abs_pa = addr_map_mss_nvlink_4_limit_r(), .start_pa = 0, @@ -140,15 +99,11 @@ hwpm_ip_perfmux t234_mss_gpu_hub_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(4), + .dt_index = 5U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mss_nvlink_5_base_r(), .end_abs_pa = addr_map_mss_nvlink_5_limit_r(), .start_pa = 0, @@ -159,15 +114,11 @@ hwpm_ip_perfmux t234_mss_gpu_hub_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(5), + .dt_index = 6U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mss_nvlink_6_base_r(), .end_abs_pa = addr_map_mss_nvlink_6_limit_r(), .start_pa = 0, @@ -178,15 +129,11 @@ hwpm_ip_perfmux t234_mss_gpu_hub_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(6), + .dt_index = 7U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mss_nvlink_7_base_r(), .end_abs_pa = addr_map_mss_nvlink_7_limit_r(), .start_pa = 0, @@ -196,30 +143,131 @@ hwpm_ip_perfmux t234_mss_gpu_hub_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), .fake_registers = NULL, }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(7), + .dt_index = 8U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mss_nvlink_8_base_r(), + .end_abs_pa = addr_map_mss_nvlink_8_limit_r(), + .start_pa = 0, + .end_pa = 0, + .base_pa = 0ULL, + .alist = t234_mss_nvlink_alist, + .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), + .fake_registers = NULL, + }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_mss_gpu_hub_inst_static_array[ + T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_mss_gpu_hub_inst0_perfmux_element_static_array, + .range_start = addr_map_mss_nvlink_8_base_r(), + .range_end = addr_map_mss_nvlink_7_limit_r(), + .element_stride = addr_map_mss_nvlink_8_limit_r() - + addr_map_mss_nvlink_8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_GPU_HUB_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST, + .element_static_array = + t234_mss_gpu_hub_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mssnvl_base_r(), + .range_end = addr_map_rpg_pm_mssnvl_limit_r(), + .element_stride = addr_map_rpg_pm_mssnvl_limit_r() - + addr_map_rpg_pm_mssnvl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_mss_gpu_hub = { .num_instances = T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_mss_gpu_hub_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_mssnvl_base_r(), - .perfmon_range_end = addr_map_rpg_pm_mssnvl_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_mssnvl_limit_r() - - addr_map_rpg_pm_mssnvl_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_mss_nvlink_8_base_r(), - .perfmux_range_end = addr_map_mss_nvlink_7_limit_r(), - .inst_perfmux_stride = addr_map_mss_nvlink_8_limit_r() - - addr_map_mss_nvlink_8_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_mss_nvlink_8_base_r(), + .range_end = addr_map_mss_nvlink_7_limit_r(), + .inst_stride = addr_map_mss_nvlink_7_limit_r() - + addr_map_mss_nvlink_8_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_mssnvl_base_r(), + .range_end = addr_map_rpg_pm_mssnvl_limit_r(), + .inst_stride = addr_map_rpg_pm_mssnvl_limit_r() - + addr_map_rpg_pm_mssnvl_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_mss_gpu_hub_perfmon_static_array, - .perfmux_static_array = t234_mss_gpu_hub_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.h b/hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.h index d6a909c..29c5d69 100644 --- a/hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.h +++ b/hal/t234/ip/mss_gpu_hub/t234_hwpm_ip_mss_gpu_hub.h @@ -21,6 +21,7 @@ #define T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES 1U #define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST 1U #define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST 8U +#define T234_HWPM_IP_MSS_GPU_HUB_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_mss_gpu_hub; diff --git a/hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.c b/hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.c index 6c81084..a7ea955 100644 --- a/hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.c +++ b/hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_mss_iso_niso_hubs_perfmon_static_array[ - T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST * - T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmon_element_static_array[ + T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_msshub0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_msshub0_base_r(), .end_abs_pa = addr_map_rpg_pm_msshub0_limit_r(), .start_pa = 0, @@ -40,15 +35,11 @@ hwpm_ip_perfmon t234_mss_iso_niso_hubs_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 1U, .dt_mmio = NULL, .name = "perfmon_msshub1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_msshub1_base_r(), .end_abs_pa = addr_map_rpg_pm_msshub1_limit_r(), .start_pa = 0, @@ -60,118 +51,14 @@ hwpm_ip_perfmon t234_mss_iso_niso_hubs_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_mss_iso_niso_hubs_perfmux_static_array[ - T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_static_array[ + T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 1U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc8_base_r(), - .end_abs_pa = addr_map_mc8_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mc8_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(t234_mc8_res_mss_iso_niso_hub_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc4_base_r(), - .end_abs_pa = addr_map_mc4_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = - ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc5_base_r(), - .end_abs_pa = addr_map_mc5_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = - ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc6_base_r(), - .end_abs_pa = addr_map_mc6_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = - ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc7_base_r(), - .end_abs_pa = addr_map_mc7_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = - ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc0_base_r(), .end_abs_pa = addr_map_mc0_limit_r(), .start_pa = 0ULL, @@ -183,15 +70,11 @@ hwpm_ip_perfmux t234_mss_iso_niso_hubs_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(1), + .dt_index = 2U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc1_base_r(), .end_abs_pa = addr_map_mc1_limit_r(), .start_pa = 0ULL, @@ -203,15 +86,11 @@ hwpm_ip_perfmux t234_mss_iso_niso_hubs_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(2), + .dt_index = 3U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc2_base_r(), .end_abs_pa = addr_map_mc2_limit_r(), .start_pa = 0ULL, @@ -223,15 +102,11 @@ hwpm_ip_perfmux t234_mss_iso_niso_hubs_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(3), + .dt_index = 4U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc3_base_r(), .end_abs_pa = addr_map_mc3_limit_r(), .start_pa = 0ULL, @@ -242,33 +117,218 @@ hwpm_ip_perfmux t234_mss_iso_niso_hubs_perfmux_static_array[ ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), .fake_registers = NULL, }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(4), + .dt_index = 5U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc4_base_r(), + .end_abs_pa = addr_map_mc4_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = + ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(5), + .dt_index = 6U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc5_base_r(), + .end_abs_pa = addr_map_mc5_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = + ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(6), + .dt_index = 7U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc6_base_r(), + .end_abs_pa = addr_map_mc6_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = + ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(7), + .dt_index = 8U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc7_base_r(), + .end_abs_pa = addr_map_mc7_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = + ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(8), + .dt_index = 9U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc8_base_r(), + .end_abs_pa = addr_map_mc8_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mc8_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc8_res_mss_iso_niso_hub_alist), + .fake_registers = NULL, + }, }; +struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_broadcast_element_static_array[ + T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mcb_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mcb_res_mss_iso_niso_hub_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +struct hwpm_ip_inst t234_mss_iso_niso_hub_inst_static_array[ + T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_mss_iso_niso_hub_inst0_perfmux_element_static_array, + .range_start = addr_map_mc8_base_r(), + .range_end = addr_map_mc3_limit_r(), + .element_stride = addr_map_mc8_limit_r() - + addr_map_mc8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_BROADCAST_PER_INST, + .element_static_array = + t234_mss_iso_niso_hub_inst0_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST, + .element_static_array = + t234_mss_iso_niso_hub_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msshub0_base_r(), + .range_end = addr_map_rpg_pm_msshub1_limit_r(), + .element_stride = addr_map_rpg_pm_msshub0_limit_r() - + addr_map_rpg_pm_msshub0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_mss_iso_niso_hubs = { .num_instances = T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES, - .num_perfmon_per_inst = - T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = - T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_mss_iso_niso_hub_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_msshub0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_msshub1_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_msshub0_limit_r() - - addr_map_rpg_pm_msshub0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_mc8_base_r(), - .perfmux_range_end = addr_map_mc3_limit_r(), - .inst_perfmux_stride = addr_map_mc8_limit_r() - - addr_map_mc8_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_mc8_base_r(), + .range_end = addr_map_mc3_limit_r(), + .inst_stride = addr_map_mc3_limit_r() - + addr_map_mc8_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .inst_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_msshub0_base_r(), + .range_end = addr_map_rpg_pm_msshub1_limit_r(), + .inst_stride = addr_map_rpg_pm_msshub1_limit_r() - + addr_map_rpg_pm_msshub0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_mss_iso_niso_hubs_perfmon_static_array, - .perfmux_static_array = t234_mss_iso_niso_hubs_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.h b/hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.h index 1f0fc3f..20a3bdf 100644 --- a/hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.h +++ b/hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.h @@ -21,6 +21,7 @@ #define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES 1U #define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST 2U #define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST 9U +#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_BROADCAST_PER_INST 1U extern struct hwpm_ip t234_hwpm_ip_mss_iso_niso_hubs; diff --git a/hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.c b/hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.c index 28bbf83..ad30363 100644 --- a/hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.c +++ b/hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_mss_mcf_perfmon_static_array[ - T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST * - T234_HWPM_IP_MSS_MCF_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[ + T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_mssmcfclient0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mcf0_base_r(), .end_abs_pa = addr_map_rpg_pm_mcf0_limit_r(), .start_pa = 0, @@ -40,15 +35,11 @@ hwpm_ip_perfmon t234_mss_mcf_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 1U, .dt_mmio = NULL, .name = "perfmon_mssmcfmem0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mcf1_base_r(), .end_abs_pa = addr_map_rpg_pm_mcf1_limit_r(), .start_pa = 0, @@ -59,15 +50,11 @@ hwpm_ip_perfmon t234_mss_mcf_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 2U, .dt_mmio = NULL, .name = "perfmon_mssmcfmem1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_mcf2_base_r(), .end_abs_pa = addr_map_rpg_pm_mcf2_limit_r(), .start_pa = 0, @@ -79,114 +66,14 @@ hwpm_ip_perfmon t234_mss_mcf_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_mss_mcf_perfmux_static_array[ - T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_MSS_MCF_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[ + T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 1U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc4_base_r(), - .end_abs_pa = addr_map_mc4_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc5_base_r(), - .end_abs_pa = addr_map_mc5_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc6_base_r(), - .end_abs_pa = addr_map_mc6_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mc7_base_r(), - .end_abs_pa = addr_map_mc7_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_mcb_base_r(), - .end_abs_pa = addr_map_mcb_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_mcb_mss_mcf_alist, - .alist_size = ARRAY_SIZE(t234_mcb_mss_mcf_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc0_base_r(), .end_abs_pa = addr_map_mc0_limit_r(), .start_pa = 0ULL, @@ -197,15 +84,11 @@ hwpm_ip_perfmux t234_mss_mcf_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(1), + .dt_index = 2U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc1_base_r(), .end_abs_pa = addr_map_mc1_limit_r(), .start_pa = 0ULL, @@ -216,15 +99,11 @@ hwpm_ip_perfmux t234_mss_mcf_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(2), + .dt_index = 3U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc2_base_r(), .end_abs_pa = addr_map_mc2_limit_r(), .start_pa = 0ULL, @@ -235,15 +114,11 @@ hwpm_ip_perfmux t234_mss_mcf_perfmux_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(3), + .dt_index = 4U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_mc3_base_r(), .end_abs_pa = addr_map_mc3_limit_r(), .start_pa = 0ULL, @@ -253,29 +128,198 @@ hwpm_ip_perfmux t234_mss_mcf_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), .fake_registers = NULL, }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(4), + .dt_index = 5U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc4_base_r(), + .end_abs_pa = addr_map_mc4_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(5), + .dt_index = 6U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc5_base_r(), + .end_abs_pa = addr_map_mc5_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(6), + .dt_index = 7U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc6_base_r(), + .end_abs_pa = addr_map_mc6_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(7), + .dt_index = 8U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc7_base_r(), + .end_abs_pa = addr_map_mc7_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .fake_registers = NULL, + }, }; +struct hwpm_ip_aperture t234_mss_mcf_inst0_broadcast_element_static_array[ + T234_HWPM_IP_MSS_MCF_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_mcb_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mcb_mss_mcf_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +struct hwpm_ip_inst t234_mss_mcf_inst_static_array[ + T234_HWPM_IP_MSS_MCF_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_mss_mcf_inst0_perfmux_element_static_array, + .range_start = addr_map_mc4_base_r(), + .range_end = addr_map_mc3_limit_r(), + .element_stride = addr_map_mc4_limit_r() - + addr_map_mc4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_MCF_NUM_BROADCAST_PER_INST, + .element_static_array = + t234_mss_mcf_inst0_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST, + .element_static_array = + t234_mss_mcf_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mcf0_base_r(), + .range_end = addr_map_rpg_pm_mcf2_limit_r(), + .element_stride = addr_map_rpg_pm_mcf0_limit_r() - + addr_map_rpg_pm_mcf0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_mss_mcf = { .num_instances = T234_HWPM_IP_MSS_MCF_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_mss_mcf_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_mcf0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_mcf2_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_mcf0_limit_r() - - addr_map_rpg_pm_mcf0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_mc4_base_r(), - .perfmux_range_end = addr_map_mc3_limit_r(), - .inst_perfmux_stride = addr_map_mc4_limit_r() - - addr_map_mc4_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_mc4_base_r(), + .range_end = addr_map_mc3_limit_r(), + .inst_stride = addr_map_mc4_limit_r() - + addr_map_mc4_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .inst_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_mcf0_base_r(), + .range_end = addr_map_rpg_pm_mcf2_limit_r(), + .inst_stride = addr_map_rpg_pm_mcf0_limit_r() - + addr_map_rpg_pm_mcf0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_mss_mcf_perfmon_static_array, - .perfmux_static_array = t234_mss_mcf_perfmux_static_array, + .inst_fs_mask = 0U, + .reserved = false, }; diff --git a/hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.h b/hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.h index a45bee7..cca7ca5 100644 --- a/hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.h +++ b/hal/t234/ip/mss_mcf/t234_hwpm_ip_mss_mcf.h @@ -20,7 +20,8 @@ /* This data should ideally be available in HW headers */ #define T234_HWPM_IP_MSS_MCF_NUM_INSTANCES 1U #define T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST 3U -#define T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST 9U +#define T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST 8U +#define T234_HWPM_IP_MSS_MCF_NUM_BROADCAST_PER_INST 1U extern struct hwpm_ip t234_hwpm_ip_mss_mcf; diff --git a/hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.c b/hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.c index 686f336..4c8d6f6 100644 --- a/hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.c +++ b/hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_nvdec_perfmon_static_array[ - T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST * - T234_HWPM_IP_NVDEC_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_nvdec_inst0_perfmon_element_static_array[ + T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_nvdeca0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_nvdec0_base_r(), .end_abs_pa = addr_map_rpg_pm_nvdec0_limit_r(), .start_pa = 0, @@ -41,19 +36,14 @@ hwpm_ip_perfmon t234_nvdec_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_nvdec_perfmux_static_array[ - T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_NVDEC_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_nvdec_inst0_perfmux_element_static_array[ + T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_nvdec_base_r(), .end_abs_pa = addr_map_nvdec_limit_r(), .start_pa = 0, @@ -65,28 +55,114 @@ hwpm_ip_perfmux t234_nvdec_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_nvdec_inst_static_array[ + T234_HWPM_IP_NVDEC_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_nvdec_inst0_perfmux_element_static_array, + .range_start = addr_map_nvdec_base_r(), + .range_end = addr_map_nvdec_limit_r(), + .element_stride = addr_map_nvdec_limit_r() - + addr_map_nvdec_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVDEC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST, + .element_static_array = + t234_nvdec_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_nvdec0_base_r(), + .range_end = addr_map_rpg_pm_nvdec0_limit_r(), + .element_stride = addr_map_rpg_pm_nvdec0_limit_r() - + addr_map_rpg_pm_nvdec0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_nvdec = { .num_instances = T234_HWPM_IP_NVDEC_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_nvdec_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_nvdec0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_nvdec0_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_nvdec0_limit_r() - - addr_map_rpg_pm_nvdec0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_nvdec_base_r(), - .perfmux_range_end = addr_map_nvdec_limit_r(), - .inst_perfmux_stride = addr_map_nvdec_limit_r() - - addr_map_nvdec_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_nvdec_base_r(), + .range_end = addr_map_nvdec_limit_r(), + .inst_stride = addr_map_nvdec_limit_r() - + addr_map_nvdec_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_nvdec0_base_r(), + .range_end = addr_map_rpg_pm_nvdec0_limit_r(), + .inst_stride = addr_map_rpg_pm_nvdec0_limit_r() - + addr_map_rpg_pm_nvdec0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_nvdec_perfmon_static_array, - .perfmux_static_array = t234_nvdec_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.h b/hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.h index 59cd393..ebe4c33 100644 --- a/hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.h +++ b/hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.h @@ -18,9 +18,10 @@ #define T234_HWPM_ACTIVE_IP_NVDEC T234_HWPM_IP_NVDEC /* This data should ideally be available in HW headers */ -#define T234_HWPM_IP_NVDEC_NUM_INSTANCES 1U -#define T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST 1U -#define T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_NVDEC_NUM_INSTANCES 1U +#define T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST 1U +#define T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_NVDEC_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_nvdec; diff --git a/hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.c b/hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.c index dd3a920..5ceb3d1 100644 --- a/hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.c +++ b/hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_nvdla_perfmon_static_array[ - T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST * - T234_HWPM_IP_NVDLA_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_nvdla_inst0_perfmon_element_static_array[ + T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_nvdlab0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_nvdla0_base_r(), .end_abs_pa = addr_map_rpg_pm_nvdla0_limit_r(), .start_pa = 0, @@ -39,16 +34,16 @@ hwpm_ip_perfmon t234_nvdla_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_nvdla_inst1_perfmon_element_static_array[ + T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(1), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_nvdlab1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_nvdla1_base_r(), .end_abs_pa = addr_map_rpg_pm_nvdla1_limit_r(), .start_pa = 0, @@ -60,19 +55,14 @@ hwpm_ip_perfmon t234_nvdla_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_nvdla_perfmux_static_array[ - T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_NVDLA_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_nvdla_inst0_perfmux_element_static_array[ + T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_nvdla0_base_r(), .end_abs_pa = addr_map_nvdla0_limit_r(), .start_pa = 0, @@ -82,16 +72,16 @@ hwpm_ip_perfmux t234_nvdla_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_nvdla_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_nvdla_inst1_perfmux_element_static_array[ + T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(1), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_nvdla1_base_r(), .end_abs_pa = addr_map_nvdla1_limit_r(), .start_pa = 0, @@ -103,28 +93,173 @@ hwpm_ip_perfmux t234_nvdla_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_nvdla_inst_static_array[ + T234_HWPM_IP_NVDLA_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_nvdla_inst0_perfmux_element_static_array, + .range_start = addr_map_nvdla0_base_r(), + .range_end = addr_map_nvdla0_limit_r(), + .element_stride = addr_map_nvdla0_limit_r() - + addr_map_nvdla0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVDLA_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST, + .element_static_array = + t234_nvdla_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_nvdla0_base_r(), + .range_end = addr_map_rpg_pm_nvdla0_limit_r(), + .element_stride = addr_map_rpg_pm_nvdla0_limit_r() - + addr_map_rpg_pm_nvdla0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(1), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_nvdla_inst1_perfmux_element_static_array, + .range_start = addr_map_nvdla1_base_r(), + .range_end = addr_map_nvdla1_limit_r(), + .element_stride = addr_map_nvdla1_limit_r() - + addr_map_nvdla1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVDLA_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST, + .element_static_array = + t234_nvdla_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_nvdla1_base_r(), + .range_end = addr_map_rpg_pm_nvdla1_limit_r(), + .element_stride = addr_map_rpg_pm_nvdla1_limit_r() - + addr_map_rpg_pm_nvdla1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_nvdla = { .num_instances = T234_HWPM_IP_NVDLA_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_nvdla_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_nvdla0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_nvdla1_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_nvdla0_limit_r() - - addr_map_rpg_pm_nvdla0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_nvdla0_base_r(), - .perfmux_range_end = addr_map_nvdla1_limit_r(), - .inst_perfmux_stride = addr_map_nvdla0_limit_r() - - addr_map_nvdla0_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_nvdla0_base_r(), + .range_end = addr_map_nvdla1_limit_r(), + .inst_stride = addr_map_nvdla0_limit_r() - + addr_map_nvdla0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_nvdla0_base_r(), + .range_end = addr_map_rpg_pm_nvdla1_limit_r(), + .inst_stride = addr_map_rpg_pm_nvdla0_limit_r() - + addr_map_rpg_pm_nvdla0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_nvdla_perfmon_static_array, - .perfmux_static_array = t234_nvdla_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.h b/hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.h index b10fc22..0157ee8 100644 --- a/hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.h +++ b/hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.h @@ -15,12 +15,13 @@ #define T234_HWPM_IP_NVDLA_H #if defined(CONFIG_SOC_HWPM_IP_NVDLA) -#define T234_HWPM_ACTIVE_IP_NVDLA T234_HWPM_IP_NVDLA +#define T234_HWPM_ACTIVE_IP_NVDLA T234_HWPM_IP_NVDLA /* This data should ideally be available in HW headers */ -#define T234_HWPM_IP_NVDLA_NUM_INSTANCES 2U -#define T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST 1U -#define T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_NVDLA_NUM_INSTANCES 2U +#define T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST 1U +#define T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_NVDLA_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_nvdla; diff --git a/hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.c b/hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.c index c7e173f..87b9038 100644 --- a/hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.c +++ b/hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_nvenc_perfmon_static_array[ - T234_HWPM_IP_NVENC_NUM_PERFMON_PER_INST * - T234_HWPM_IP_NVENC_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_nvenc_inst0_perfmon_element_static_array[ + T234_HWPM_IP_NVENC_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_nvenca0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_nvenc0_base_r(), .end_abs_pa = addr_map_rpg_pm_nvenc0_limit_r(), .start_pa = 0ULL, @@ -41,19 +36,14 @@ hwpm_ip_perfmon t234_nvenc_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_nvenc_perfmux_static_array[ - T234_HWPM_IP_NVENC_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_NVENC_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_nvenc_inst0_perfmux_element_static_array[ + T234_HWPM_IP_NVENC_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_nvenc_base_r(), .end_abs_pa = addr_map_nvenc_limit_r(), .start_pa = 0ULL, @@ -65,28 +55,114 @@ hwpm_ip_perfmux t234_nvenc_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_nvenc_inst_static_array[ + T234_HWPM_IP_NVENC_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVENC_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_nvenc_inst0_perfmux_element_static_array, + .range_start = addr_map_nvenc_base_r(), + .range_end = addr_map_nvenc_limit_r(), + .element_stride = addr_map_nvenc_limit_r() - + addr_map_nvenc_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVENC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_NVENC_NUM_PERFMON_PER_INST, + .element_static_array = + t234_nvenc_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_nvenc0_base_r(), + .range_end = addr_map_rpg_pm_nvenc0_limit_r(), + .element_stride = addr_map_rpg_pm_nvenc0_limit_r() - + addr_map_rpg_pm_nvenc0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_nvenc = { .num_instances = T234_HWPM_IP_NVENC_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_NVENC_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_NVENC_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_nvenc_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_nvenc0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_nvenc0_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_nvenc0_limit_r() - - addr_map_rpg_pm_nvenc0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_nvenc_base_r(), - .perfmux_range_end = addr_map_nvenc_limit_r(), - .inst_perfmux_stride = addr_map_nvenc_limit_r() - - addr_map_nvenc_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_nvenc_base_r(), + .range_end = addr_map_nvenc_limit_r(), + .inst_stride = addr_map_nvenc_limit_r() - + addr_map_nvenc_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_nvenc0_base_r(), + .range_end = addr_map_rpg_pm_nvenc0_limit_r(), + .inst_stride = addr_map_rpg_pm_nvenc0_limit_r() - + addr_map_rpg_pm_nvenc0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_nvenc_perfmon_static_array, - .perfmux_static_array = t234_nvenc_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.h b/hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.h index 56bbd43..b00a14a 100644 --- a/hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.h +++ b/hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.h @@ -15,12 +15,13 @@ #define T234_HWPM_IP_NVENC_H #if defined(CONFIG_SOC_HWPM_IP_NVENC) -#define T234_HWPM_ACTIVE_IP_NVENC T234_HWPM_IP_NVENC +#define T234_HWPM_ACTIVE_IP_NVENC T234_HWPM_IP_NVENC /* This data should ideally be available in HW headers */ -#define T234_HWPM_IP_NVENC_NUM_INSTANCES 1U -#define T234_HWPM_IP_NVENC_NUM_PERFMON_PER_INST 1U -#define T234_HWPM_IP_NVENC_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_NVENC_NUM_INSTANCES 1U +#define T234_HWPM_IP_NVENC_NUM_PERFMON_PER_INST 1U +#define T234_HWPM_IP_NVENC_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_NVENC_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_nvenc; diff --git a/hal/t234/ip/ofa/t234_hwpm_ip_ofa.c b/hal/t234/ip/ofa/t234_hwpm_ip_ofa.c index 2c4b93c..6de2d6b 100644 --- a/hal/t234/ip/ofa/t234_hwpm_ip_ofa.c +++ b/hal/t234/ip/ofa/t234_hwpm_ip_ofa.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_ofa_perfmon_static_array[ - T234_HWPM_IP_OFA_NUM_PERFMON_PER_INST * - T234_HWPM_IP_OFA_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_ofa_inst0_perfmon_element_static_array[ + T234_HWPM_IP_OFA_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_ofaa0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_ofa_base_r(), .end_abs_pa = addr_map_rpg_pm_ofa_limit_r(), .start_pa = 0ULL, @@ -41,19 +36,14 @@ hwpm_ip_perfmon t234_ofa_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_ofa_perfmux_static_array[ - T234_HWPM_IP_OFA_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_OFA_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_ofa_inst0_perfmux_element_static_array[ + T234_HWPM_IP_OFA_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_ofa_base_r(), .end_abs_pa = addr_map_ofa_limit_r(), .start_pa = 0ULL, @@ -65,28 +55,114 @@ hwpm_ip_perfmux t234_ofa_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_ofa_inst_static_array[ + T234_HWPM_IP_OFA_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_OFA_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_ofa_inst0_perfmux_element_static_array, + .range_start = addr_map_ofa_base_r(), + .range_end = addr_map_ofa_limit_r(), + .element_stride = addr_map_ofa_limit_r() - + addr_map_ofa_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_OFA_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_OFA_NUM_PERFMON_PER_INST, + .element_static_array = + t234_ofa_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_ofa_base_r(), + .range_end = addr_map_rpg_pm_ofa_limit_r(), + .element_stride = addr_map_rpg_pm_ofa_limit_r() - + addr_map_rpg_pm_ofa_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_ofa = { .num_instances = T234_HWPM_IP_OFA_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_OFA_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_OFA_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_ofa_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_ofa_base_r(), - .perfmon_range_end = addr_map_rpg_pm_ofa_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_ofa_limit_r() - - addr_map_rpg_pm_ofa_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_ofa_base_r(), - .perfmux_range_end = addr_map_ofa_limit_r(), - .inst_perfmux_stride = addr_map_ofa_limit_r() - - addr_map_ofa_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_ofa_base_r(), + .range_end = addr_map_ofa_limit_r(), + .inst_stride = addr_map_ofa_limit_r() - + addr_map_ofa_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_ofa_base_r(), + .range_end = addr_map_rpg_pm_ofa_limit_r(), + .inst_stride = addr_map_rpg_pm_ofa_limit_r() - + addr_map_rpg_pm_ofa_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_ofa_perfmon_static_array, - .perfmux_static_array = t234_ofa_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/ofa/t234_hwpm_ip_ofa.h b/hal/t234/ip/ofa/t234_hwpm_ip_ofa.h index 321611e..6f7d34c 100644 --- a/hal/t234/ip/ofa/t234_hwpm_ip_ofa.h +++ b/hal/t234/ip/ofa/t234_hwpm_ip_ofa.h @@ -21,6 +21,7 @@ #define T234_HWPM_IP_OFA_NUM_INSTANCES 1U #define T234_HWPM_IP_OFA_NUM_PERFMON_PER_INST 1U #define T234_HWPM_IP_OFA_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_OFA_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_ofa; diff --git a/hal/t234/ip/pcie/t234_hwpm_ip_pcie.c b/hal/t234/ip/pcie/t234_hwpm_ip_pcie.c index df8c97c..dd981af 100644 --- a/hal/t234/ip/pcie/t234_hwpm_ip_pcie.c +++ b/hal/t234/ip/pcie/t234_hwpm_ip_pcie.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_pcie_perfmon_static_array[ - T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST * - T234_HWPM_IP_PCIE_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_pcie_inst0_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c0_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c0_limit_r(), .start_pa = 0ULL, @@ -39,16 +34,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst1_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(1), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c1_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c1_limit_r(), .start_pa = 0ULL, @@ -58,16 +53,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst2_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(2), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie2", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c2_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c2_limit_r(), .start_pa = 0ULL, @@ -77,16 +72,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst3_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(3), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie3", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c3_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c3_limit_r(), .start_pa = 0ULL, @@ -96,16 +91,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst4_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(4), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie4", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c4_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c4_limit_r(), .start_pa = 0ULL, @@ -115,16 +110,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst5_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(5), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie5", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c5_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c5_limit_r(), .start_pa = 0ULL, @@ -134,16 +129,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst6_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(6), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie6", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c6_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c6_limit_r(), .start_pa = 0ULL, @@ -153,16 +148,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst7_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(7), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie7", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c7_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c7_limit_r(), .start_pa = 0ULL, @@ -172,16 +167,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst8_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(8), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie8", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c8_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c8_limit_r(), .start_pa = 0ULL, @@ -191,16 +186,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst9_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(9), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie9", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c9_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c9_limit_r(), .start_pa = 0ULL, @@ -210,16 +205,16 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst10_perfmon_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(10), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(10), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pcie10", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pcie_c10_base_r(), .end_abs_pa = addr_map_rpg_pm_pcie_c10_limit_r(), .start_pa = 0ULL, @@ -231,152 +226,14 @@ hwpm_ip_perfmon t234_pcie_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_pcie_perfmux_static_array[ - T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_PCIE_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_pcie_inst0_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(8), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_pcie_c8_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c8_ctl_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_pcie_ctl_alist, - .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(9), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_pcie_c9_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c9_ctl_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_pcie_ctl_alist, - .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(10), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_pcie_c10_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c10_ctl_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_pcie_ctl_alist, - .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(1), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_pcie_c1_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c1_ctl_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_pcie_ctl_alist, - .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(2), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_pcie_c2_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c2_ctl_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_pcie_ctl_alist, - .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(3), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_pcie_c3_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c3_ctl_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_pcie_ctl_alist, - .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(4), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_pcie_c4_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c4_ctl_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_pcie_ctl_alist, - .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_pcie_c0_ctl_base_r(), .end_abs_pa = addr_map_pcie_c0_ctl_limit_r(), .start_pa = 0ULL, @@ -386,16 +243,92 @@ hwpm_ip_perfmux t234_pcie_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst1_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(5), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c1_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c1_ctl_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .fake_registers = NULL, + }, +}; + +struct hwpm_ip_aperture t234_pcie_inst2_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(10), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c2_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c2_ctl_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .fake_registers = NULL, + }, +}; + +struct hwpm_ip_aperture t234_pcie_inst3_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c3_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c3_ctl_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .fake_registers = NULL, + }, +}; + +struct hwpm_ip_aperture t234_pcie_inst4_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c4_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c4_ctl_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .fake_registers = NULL, + }, +}; + +struct hwpm_ip_aperture t234_pcie_inst5_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_pcie_c5_ctl_base_r(), .end_abs_pa = addr_map_pcie_c5_ctl_limit_r(), .start_pa = 0ULL, @@ -405,16 +338,16 @@ hwpm_ip_perfmux t234_pcie_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst6_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(6), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_pcie_c6_ctl_base_r(), .end_abs_pa = addr_map_pcie_c6_ctl_limit_r(), .start_pa = 0ULL, @@ -424,16 +357,16 @@ hwpm_ip_perfmux t234_pcie_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_pcie_inst7_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(7), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_pcie_c7_ctl_base_r(), .end_abs_pa = addr_map_pcie_c7_ctl_limit_r(), .start_pa = 0ULL, @@ -445,28 +378,761 @@ hwpm_ip_perfmux t234_pcie_perfmux_static_array[ }, }; +struct hwpm_ip_aperture t234_pcie_inst8_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c8_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c8_ctl_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .fake_registers = NULL, + }, +}; + +struct hwpm_ip_aperture t234_pcie_inst9_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c9_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c9_ctl_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .fake_registers = NULL, + }, +}; + +struct hwpm_ip_aperture t234_pcie_inst10_perfmux_element_static_array[ + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_pcie_c10_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c10_ctl_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +struct hwpm_ip_inst t234_pcie_inst_static_array[ + T234_HWPM_IP_PCIE_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst0_perfmux_element_static_array, + .range_start = addr_map_pcie_c0_ctl_base_r(), + .range_end = addr_map_pcie_c0_ctl_limit_r(), + .element_stride = addr_map_pcie_c0_ctl_limit_r() - + addr_map_pcie_c0_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c0_base_r(), + .range_end = addr_map_rpg_pm_pcie_c0_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c0_limit_r() - + addr_map_rpg_pm_pcie_c0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(1), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst1_perfmux_element_static_array, + .range_start = addr_map_pcie_c1_ctl_base_r(), + .range_end = addr_map_pcie_c1_ctl_limit_r(), + .element_stride = addr_map_pcie_c1_ctl_limit_r() - + addr_map_pcie_c1_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c1_base_r(), + .range_end = addr_map_rpg_pm_pcie_c1_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c1_limit_r() - + addr_map_rpg_pm_pcie_c1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(2), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst2_perfmux_element_static_array, + .range_start = addr_map_pcie_c2_ctl_base_r(), + .range_end = addr_map_pcie_c2_ctl_limit_r(), + .element_stride = addr_map_pcie_c2_ctl_limit_r() - + addr_map_pcie_c2_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c2_base_r(), + .range_end = addr_map_rpg_pm_pcie_c2_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c2_limit_r() - + addr_map_rpg_pm_pcie_c2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(3), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst3_perfmux_element_static_array, + .range_start = addr_map_pcie_c3_ctl_base_r(), + .range_end = addr_map_pcie_c3_ctl_limit_r(), + .element_stride = addr_map_pcie_c3_ctl_limit_r() - + addr_map_pcie_c3_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c3_base_r(), + .range_end = addr_map_rpg_pm_pcie_c3_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c3_limit_r() - + addr_map_rpg_pm_pcie_c3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(4), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst4_perfmux_element_static_array, + .range_start = addr_map_pcie_c4_ctl_base_r(), + .range_end = addr_map_pcie_c4_ctl_limit_r(), + .element_stride = addr_map_pcie_c4_ctl_limit_r() - + addr_map_pcie_c4_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst4_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c4_base_r(), + .range_end = addr_map_rpg_pm_pcie_c4_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c4_limit_r() - + addr_map_rpg_pm_pcie_c4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(5), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst5_perfmux_element_static_array, + .range_start = addr_map_pcie_c5_ctl_base_r(), + .range_end = addr_map_pcie_c5_ctl_limit_r(), + .element_stride = addr_map_pcie_c5_ctl_limit_r() - + addr_map_pcie_c5_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst5_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c5_base_r(), + .range_end = addr_map_rpg_pm_pcie_c5_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c5_limit_r() - + addr_map_rpg_pm_pcie_c5_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(6), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst6_perfmux_element_static_array, + .range_start = addr_map_pcie_c6_ctl_base_r(), + .range_end = addr_map_pcie_c6_ctl_limit_r(), + .element_stride = addr_map_pcie_c6_ctl_limit_r() - + addr_map_pcie_c6_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst6_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c6_base_r(), + .range_end = addr_map_rpg_pm_pcie_c6_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c6_limit_r() - + addr_map_rpg_pm_pcie_c6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(7), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst7_perfmux_element_static_array, + .range_start = addr_map_pcie_c7_ctl_base_r(), + .range_end = addr_map_pcie_c7_ctl_limit_r(), + .element_stride = addr_map_pcie_c7_ctl_limit_r() - + addr_map_pcie_c7_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst7_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c7_base_r(), + .range_end = addr_map_rpg_pm_pcie_c7_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c7_limit_r() - + addr_map_rpg_pm_pcie_c7_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(8), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst8_perfmux_element_static_array, + .range_start = addr_map_pcie_c8_ctl_base_r(), + .range_end = addr_map_pcie_c8_ctl_limit_r(), + .element_stride = addr_map_pcie_c8_ctl_limit_r() - + addr_map_pcie_c8_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst8_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c8_base_r(), + .range_end = addr_map_rpg_pm_pcie_c8_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c8_limit_r() - + addr_map_rpg_pm_pcie_c8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(9), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst9_perfmux_element_static_array, + .range_start = addr_map_pcie_c9_ctl_base_r(), + .range_end = addr_map_pcie_c9_ctl_limit_r(), + .element_stride = addr_map_pcie_c9_ctl_limit_r() - + addr_map_pcie_c9_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst9_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c9_base_r(), + .range_end = addr_map_rpg_pm_pcie_c9_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c9_limit_r() - + addr_map_rpg_pm_pcie_c9_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(10), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pcie_inst10_perfmux_element_static_array, + .range_start = addr_map_pcie_c10_ctl_base_r(), + .range_end = addr_map_pcie_c10_ctl_limit_r(), + .element_stride = addr_map_pcie_c10_ctl_limit_r() - + addr_map_pcie_c10_ctl_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pcie_inst10_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pcie_c10_base_r(), + .range_end = addr_map_rpg_pm_pcie_c10_limit_r(), + .element_stride = addr_map_rpg_pm_pcie_c10_limit_r() - + addr_map_rpg_pm_pcie_c10_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_pcie = { .num_instances = T234_HWPM_IP_PCIE_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_pcie_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_pcie_c0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_pcie_c10_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_pcie_c0_limit_r() - - addr_map_rpg_pm_pcie_c0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_pcie_c8_ctl_base_r(), - .perfmux_range_end = addr_map_pcie_c7_ctl_limit_r(), - .inst_perfmux_stride = addr_map_pcie_c8_ctl_limit_r() - - addr_map_pcie_c8_ctl_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_pcie_c8_ctl_base_r(), + .range_end = addr_map_pcie_c7_ctl_limit_r(), + .inst_stride = addr_map_pcie_c8_ctl_limit_r() - + addr_map_pcie_c8_ctl_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_pcie_c0_base_r(), + .range_end = addr_map_rpg_pm_pcie_c10_limit_r(), + .inst_stride = addr_map_rpg_pm_pcie_c0_limit_r() - + addr_map_rpg_pm_pcie_c0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_pcie_perfmon_static_array, - .perfmux_static_array = t234_pcie_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/pcie/t234_hwpm_ip_pcie.h b/hal/t234/ip/pcie/t234_hwpm_ip_pcie.h index f9c28f7..9ccbacf 100644 --- a/hal/t234/ip/pcie/t234_hwpm_ip_pcie.h +++ b/hal/t234/ip/pcie/t234_hwpm_ip_pcie.h @@ -18,9 +18,10 @@ #define T234_HWPM_ACTIVE_IP_PCIE T234_HWPM_IP_PCIE /* This data should ideally be available in HW headers */ -#define T234_HWPM_IP_PCIE_NUM_INSTANCES 11U -#define T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST 1U -#define T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_PCIE_NUM_INSTANCES 11U +#define T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST 1U +#define T234_HWPM_IP_PCIE_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_PCIE_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_pcie; diff --git a/hal/t234/ip/pma/t234_hwpm_ip_pma.c b/hal/t234/ip/pma/t234_hwpm_ip_pma.c index f99d5a2..facd278 100644 --- a/hal/t234/ip/pma/t234_hwpm_ip_pma.c +++ b/hal/t234/ip/pma/t234_hwpm_ip_pma.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_pma_perfmon_static_array[ - T234_HWPM_IP_PMA_NUM_PERFMON_PER_INST * - T234_HWPM_IP_PMA_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_pma_inst0_perfmon_element_static_array[ + T234_HWPM_IP_PMA_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_sys0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pma_base_r(), .end_abs_pa = addr_map_rpg_pm_pma_limit_r(), .start_pa = 0ULL, @@ -41,19 +36,14 @@ hwpm_ip_perfmon t234_pma_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_pma_perfmux_static_array[ - T234_HWPM_IP_PMA_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_PMA_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_pma_inst0_perfmux_element_static_array[ + T234_HWPM_IP_PMA_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "pma", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_pma_base_r(), .end_abs_pa = addr_map_pma_limit_r(), .start_pa = 0ULL, @@ -65,28 +55,114 @@ hwpm_ip_perfmux t234_pma_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_pma_inst_static_array[ + T234_HWPM_IP_PMA_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PMA_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pma_inst0_perfmux_element_static_array, + .range_start = addr_map_pma_base_r(), + .range_end = addr_map_pma_limit_r(), + .element_stride = addr_map_pma_limit_r() - + addr_map_pma_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PMA_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PMA_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pma_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pma_base_r(), + .range_end = addr_map_rpg_pm_pma_limit_r(), + .element_stride = addr_map_rpg_pm_pma_limit_r() - + addr_map_rpg_pm_pma_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0x1U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_pma = { .num_instances = T234_HWPM_IP_PMA_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_PMA_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_PMA_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_pma_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_pma_base_r(), - .perfmon_range_end = addr_map_rpg_pm_pma_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_pma_limit_r() - - addr_map_rpg_pm_pma_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_pma_base_r(), - .perfmux_range_end = addr_map_pma_limit_r(), - .inst_perfmux_stride = addr_map_pma_limit_r() - - addr_map_pma_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_pma_base_r(), + .range_end = addr_map_pma_limit_r(), + .inst_stride = addr_map_pma_limit_r() - + addr_map_pma_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_pma_base_r(), + .range_end = addr_map_rpg_pm_pma_limit_r(), + .inst_stride = addr_map_rpg_pm_pma_limit_r() - + addr_map_rpg_pm_pma_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0x1U, - .perfmon_static_array = t234_pma_perfmon_static_array, - .perfmux_static_array = t234_pma_perfmux_static_array, + .inst_fs_mask = 0x1U, .reserved = false, }; diff --git a/hal/t234/ip/pma/t234_hwpm_ip_pma.h b/hal/t234/ip/pma/t234_hwpm_ip_pma.h index ec2ce9c..adb4964 100644 --- a/hal/t234/ip/pma/t234_hwpm_ip_pma.h +++ b/hal/t234/ip/pma/t234_hwpm_ip_pma.h @@ -20,6 +20,7 @@ #define T234_HWPM_IP_PMA_NUM_INSTANCES 1U #define T234_HWPM_IP_PMA_NUM_PERFMON_PER_INST 1U #define T234_HWPM_IP_PMA_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_PMA_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_pma; diff --git a/hal/t234/ip/pva/t234_hwpm_ip_pva.c b/hal/t234/ip/pva/t234_hwpm_ip_pva.c index 3f1961e..8daf74b 100644 --- a/hal/t234/ip/pva/t234_hwpm_ip_pva.c +++ b/hal/t234/ip/pva/t234_hwpm_ip_pva.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_pva_perfmon_static_array[ - T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST * - T234_HWPM_IP_PVA_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[ + T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_pvav0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pva0_0_base_r(), .end_abs_pa = addr_map_rpg_pm_pva0_0_limit_r(), .start_pa = 0ULL, @@ -40,15 +35,11 @@ hwpm_ip_perfmon t234_pva_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 1U, .dt_mmio = NULL, .name = "perfmon_pvav1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pva0_1_base_r(), .end_abs_pa = addr_map_rpg_pm_pva0_1_limit_r(), .start_pa = 0ULL, @@ -59,15 +50,11 @@ hwpm_ip_perfmon t234_pva_perfmon_static_array[ .fake_registers = NULL, }, { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 2U, .dt_mmio = NULL, .name = "perfmon_pvac0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_pva0_2_base_r(), .end_abs_pa = addr_map_rpg_pm_pva0_2_limit_r(), .start_pa = 0ULL, @@ -79,19 +66,14 @@ hwpm_ip_perfmon t234_pva_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_pva_perfmux_static_array[ - T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_PVA_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_pva_inst0_perfmux_element_static_array[ + T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_pva0_pm_base_r(), .end_abs_pa = addr_map_pva0_pm_limit_r(), .start_pa = 0ULL, @@ -103,28 +85,114 @@ hwpm_ip_perfmux t234_pva_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_pva_inst_static_array[ + T234_HWPM_IP_PVA_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_pva_inst0_perfmux_element_static_array, + .range_start = addr_map_pva0_pm_base_r(), + .range_end = addr_map_pva0_pm_limit_r(), + .element_stride = addr_map_pva0_pm_limit_r() - + addr_map_pva0_pm_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_PVA_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST, + .element_static_array = + t234_pva_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_pva0_0_base_r(), + .range_end = addr_map_rpg_pm_pva0_2_limit_r(), + .element_stride = addr_map_rpg_pm_pva0_0_limit_r() - + addr_map_rpg_pm_pva0_0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_pva = { .num_instances = T234_HWPM_IP_PVA_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_pva_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_pva0_0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_pva0_2_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_pva0_0_limit_r() - - addr_map_rpg_pm_pva0_0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_pva0_pm_base_r(), - .perfmux_range_end = addr_map_pva0_pm_limit_r(), - .inst_perfmux_stride = addr_map_pva0_pm_limit_r() - - addr_map_pva0_pm_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_pva0_pm_base_r(), + .range_end = addr_map_pva0_pm_limit_r(), + .inst_stride = addr_map_pva0_pm_limit_r() - + addr_map_pva0_pm_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_pva0_0_base_r(), + .range_end = addr_map_rpg_pm_pva0_2_limit_r(), + .inst_stride = addr_map_rpg_pm_pva0_2_limit_r() - + addr_map_rpg_pm_pva0_0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_pva_perfmon_static_array, - .perfmux_static_array = t234_pva_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/pva/t234_hwpm_ip_pva.h b/hal/t234/ip/pva/t234_hwpm_ip_pva.h index 8b499c8..0de8997 100644 --- a/hal/t234/ip/pva/t234_hwpm_ip_pva.h +++ b/hal/t234/ip/pva/t234_hwpm_ip_pva.h @@ -21,6 +21,7 @@ #define T234_HWPM_IP_PVA_NUM_INSTANCES 1U #define T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST 3U #define T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_PVA_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_pva; diff --git a/hal/t234/ip/rtr/t234_hwpm_ip_rtr.c b/hal/t234/ip/rtr/t234_hwpm_ip_rtr.c index fd56220..321cdfd 100644 --- a/hal/t234/ip/rtr/t234_hwpm_ip_rtr.c +++ b/hal/t234/ip/rtr/t234_hwpm_ip_rtr.c @@ -17,25 +17,15 @@ #include #include -hwpm_ip_perfmon t234_rtr_perfmon_static_array[ - T234_HWPM_IP_RTR_NUM_PERFMON_PER_INST * - T234_HWPM_IP_RTR_NUM_INSTANCES] = { - -}; - -hwpm_ip_perfmux t234_rtr_perfmux_static_array[ - T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_RTR_NUM_INSTANCES] = { +/* RTR aperture should be placed in instance T234_HWPM_IP_RTR_STATIC_RTR_INST */ +struct hwpm_ip_aperture t234_rtr_inst0_perfmux_element_static_array[ + T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "rtr", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rtr_base_r(), .end_abs_pa = addr_map_rtr_limit_r(), .start_pa = 0ULL, @@ -45,17 +35,18 @@ hwpm_ip_perfmux t234_rtr_perfmux_static_array[ .alist_size = ARRAY_SIZE(t234_rtr_alist), .fake_registers = NULL, }, - /* PMA from RTR perspective */ +}; + +/* PMA from RTR perspective */ +/* PMA aperture should be placed in instance T234_HWPM_IP_RTR_STATIC_PMA_INST */ +struct hwpm_ip_aperture t234_rtr_inst1_perfmux_element_static_array[ + T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "pma", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_pma_base_r(), .end_abs_pa = addr_map_pma_limit_r(), .start_pa = 0ULL, @@ -67,28 +58,172 @@ hwpm_ip_perfmux t234_rtr_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_rtr_inst_static_array[ + T234_HWPM_IP_RTR_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_rtr_inst0_perfmux_element_static_array, + .range_start = addr_map_rtr_base_r(), + .range_end = addr_map_rtr_limit_r(), + .element_stride = addr_map_rtr_limit_r() - + addr_map_rtr_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_RTR_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_RTR_NUM_PERFMON_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0x1U, + }, + { + .hw_inst_mask = BIT(1), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_rtr_inst1_perfmux_element_static_array, + .range_start = addr_map_pma_base_r(), + .range_end = addr_map_pma_limit_r(), + .element_stride = addr_map_pma_limit_r() - + addr_map_pma_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_RTR_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_RTR_NUM_PERFMON_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0x1U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_rtr = { .num_instances = T234_HWPM_IP_RTR_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_RTR_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_rtr_inst_static_array, - .perfmon_range_start = 0ULL, - .perfmon_range_end = 0ULL, - .inst_perfmon_stride = 0ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_pma_base_r(), - .perfmux_range_end = addr_map_rtr_limit_r(), - /* Use PMA stride which is larger block than RTR */ - .inst_perfmux_stride = addr_map_pma_limit_r() - - addr_map_pma_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_pma_base_r(), + .range_end = addr_map_rtr_limit_r(), + /* Use PMA stride as it is larger block than RTR */ + .inst_stride = addr_map_pma_limit_r() - + addr_map_pma_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_rtr_perfmon_static_array, - .perfmux_static_array = t234_rtr_perfmux_static_array, + /* RTR is defined as 2 instance IP corresponding to router and pma */ + /* Set this mask to indicate that instances are available */ + .inst_fs_mask = 0x3U, .reserved = false, }; diff --git a/hal/t234/ip/rtr/t234_hwpm_ip_rtr.h b/hal/t234/ip/rtr/t234_hwpm_ip_rtr.h index 47e1ea1..cd35f8d 100644 --- a/hal/t234/ip/rtr/t234_hwpm_ip_rtr.h +++ b/hal/t234/ip/rtr/t234_hwpm_ip_rtr.h @@ -20,12 +20,11 @@ #define T234_HWPM_IP_RTR_NUM_INSTANCES 2U #define T234_HWPM_IP_RTR_NUM_PERFMON_PER_INST 0U #define T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_RTR_NUM_BROADCAST_PER_INST 0U -#define T234_HWPM_IP_RTR_STATIC_INDEX_RTR \ - ((1U * T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST) - 1U) - -#define T234_HWPM_IP_RTR_STATIC_INDEX_PMA \ - ((2U * T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST) - 1U) +#define T234_HWPM_IP_RTR_STATIC_RTR_INST 0U +#define T234_HWPM_IP_RTR_STATIC_PMA_INST 1U +#define T234_HWPM_IP_RTR_PERMUX_INDEX 0U extern struct hwpm_ip t234_hwpm_ip_rtr; diff --git a/hal/t234/ip/scf/t234_hwpm_ip_scf.c b/hal/t234/ip/scf/t234_hwpm_ip_scf.c index 5b5001a..4874626 100644 --- a/hal/t234/ip/scf/t234_hwpm_ip_scf.c +++ b/hal/t234/ip/scf/t234_hwpm_ip_scf.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_scf_perfmon_static_array[ - T234_HWPM_IP_SCF_NUM_PERFMON_PER_INST * - T234_HWPM_IP_SCF_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_scf_inst0_perfmon_element_static_array[ + T234_HWPM_IP_SCF_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_scf", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_scf_base_r(), .end_abs_pa = addr_map_rpg_pm_scf_limit_r(), .start_pa = 0ULL, @@ -41,33 +36,111 @@ hwpm_ip_perfmon t234_scf_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_scf_perfmux_static_array[ - T234_HWPM_IP_SCF_NUM_PERFMUX_PER_INST * +/* IP instance array */ +struct hwpm_ip_inst t234_scf_inst_static_array[ T234_HWPM_IP_SCF_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_SCF_NUM_PERFMUX_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_SCF_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_SCF_NUM_PERFMON_PER_INST, + .element_static_array = + t234_scf_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_scf_base_r(), + .range_end = addr_map_rpg_pm_scf_limit_r(), + .element_stride = addr_map_rpg_pm_scf_limit_r() - + addr_map_rpg_pm_scf_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0x1U, + }, }; +/* IP structure */ struct hwpm_ip t234_hwpm_ip_scf = { .num_instances = T234_HWPM_IP_SCF_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_SCF_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_SCF_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_scf_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_scf_base_r(), - .perfmon_range_end = addr_map_rpg_pm_scf_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_scf_limit_r() - - addr_map_rpg_pm_scf_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = 0ULL, - .perfmux_range_end = 0ULL, - .inst_perfmux_stride = 0U, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_scf_base_r(), + .range_end = addr_map_rpg_pm_scf_limit_r(), + .inst_stride = addr_map_rpg_pm_scf_limit_r() - + addr_map_rpg_pm_scf_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0x1U, - .perfmon_static_array = t234_scf_perfmon_static_array, - .perfmux_static_array = t234_scf_perfmux_static_array, + .inst_fs_mask = 0x1U, .reserved = false, }; diff --git a/hal/t234/ip/scf/t234_hwpm_ip_scf.h b/hal/t234/ip/scf/t234_hwpm_ip_scf.h index 800c790..9d1c6d9 100644 --- a/hal/t234/ip/scf/t234_hwpm_ip_scf.h +++ b/hal/t234/ip/scf/t234_hwpm_ip_scf.h @@ -21,6 +21,7 @@ #define T234_HWPM_IP_SCF_NUM_INSTANCES 1U #define T234_HWPM_IP_SCF_NUM_PERFMON_PER_INST 1U #define T234_HWPM_IP_SCF_NUM_PERFMUX_PER_INST 0U +#define T234_HWPM_IP_SCF_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_scf; diff --git a/hal/t234/ip/vi/t234_hwpm_ip_vi.c b/hal/t234/ip/vi/t234_hwpm_ip_vi.c index 2cc0668..1fb5ef8 100644 --- a/hal/t234/ip/vi/t234_hwpm_ip_vi.c +++ b/hal/t234/ip/vi/t234_hwpm_ip_vi.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_vi_perfmon_static_array[ - T234_HWPM_IP_VI_NUM_PERFMON_PER_INST * - T234_HWPM_IP_VI_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_vi_inst0_perfmon_element_static_array[ + T234_HWPM_IP_VI_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_vi0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_vi0_base_r(), .end_abs_pa = addr_map_rpg_pm_vi0_limit_r(), .start_pa = 0ULL, @@ -39,16 +34,16 @@ hwpm_ip_perfmon t234_vi_perfmon_static_array[ .alist_size = ARRAY_SIZE(t234_perfmon_alist), .fake_registers = NULL, }, +}; + +struct hwpm_ip_aperture t234_vi_inst1_perfmon_element_static_array[ + T234_HWPM_IP_VI_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(1), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_vi1", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_vi1_base_r(), .end_abs_pa = addr_map_rpg_pm_vi1_limit_r(), .start_pa = 0ULL, @@ -60,38 +55,14 @@ hwpm_ip_perfmon t234_vi_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_vi_perfmux_static_array[ - T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_VI_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_vi_inst0_perfmux_element_static_array[ + T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(1), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, - .start_abs_pa = addr_map_vi2_thi_base_r(), - .end_abs_pa = addr_map_vi2_thi_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = t234_vi_thi_alist, - .alist_size = ARRAY_SIZE(t234_vi_thi_alist), - .fake_registers = NULL, - }, - { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), - .dt_mmio = NULL, - .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_vi_thi_base_r(), .end_abs_pa = addr_map_vi_thi_limit_r(), .start_pa = 0ULL, @@ -103,28 +74,192 @@ hwpm_ip_perfmux t234_vi_perfmux_static_array[ }, }; +struct hwpm_ip_aperture t234_vi_inst1_perfmux_element_static_array[ + T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_vi2_thi_base_r(), + .end_abs_pa = addr_map_vi2_thi_limit_r(), + .start_pa = 0ULL, + .end_pa = 0ULL, + .base_pa = 0ULL, + .alist = t234_vi_thi_alist, + .alist_size = ARRAY_SIZE(t234_vi_thi_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +struct hwpm_ip_inst t234_vi_inst_static_array[ + T234_HWPM_IP_VI_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_vi_inst0_perfmux_element_static_array, + .range_start = addr_map_vi_thi_base_r(), + .range_end = addr_map_vi_thi_limit_r(), + .element_stride = addr_map_vi_thi_limit_r() - + addr_map_vi_thi_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_VI_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_VI_NUM_PERFMON_PER_INST, + .element_static_array = + t234_vi_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_vi0_base_r(), + .range_end = addr_map_rpg_pm_vi0_limit_r(), + .element_stride = addr_map_rpg_pm_vi0_limit_r() - + addr_map_rpg_pm_vi0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, + { + .hw_inst_mask = BIT(1), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_vi_inst1_perfmux_element_static_array, + .range_start = addr_map_vi2_thi_base_r(), + .range_end = addr_map_vi2_thi_limit_r(), + .element_stride = addr_map_vi2_thi_limit_r() - + addr_map_vi2_thi_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_VI_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_VI_NUM_PERFMON_PER_INST, + .element_static_array = + t234_vi_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_vi1_base_r(), + .range_end = addr_map_rpg_pm_vi1_limit_r(), + .element_stride = addr_map_rpg_pm_vi1_limit_r() - + addr_map_rpg_pm_vi1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_vi = { .num_instances = T234_HWPM_IP_VI_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_VI_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_vi_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_vi0_base_r(), - .perfmon_range_end = addr_map_rpg_pm_vi1_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_vi0_limit_r() - - addr_map_rpg_pm_vi0_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_vi2_thi_base_r(), - .perfmux_range_end = addr_map_vi_thi_limit_r(), - .inst_perfmux_stride = addr_map_vi2_thi_limit_r() - - addr_map_vi2_thi_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_vi2_thi_base_r(), + .range_end = addr_map_vi_thi_limit_r(), + .inst_stride = addr_map_vi2_thi_limit_r() - + addr_map_vi2_thi_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_vi0_base_r(), + .range_end = addr_map_rpg_pm_vi1_limit_r(), + .inst_stride = addr_map_rpg_pm_vi0_limit_r() - + addr_map_rpg_pm_vi0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_vi_perfmon_static_array, - .perfmux_static_array = t234_vi_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/vi/t234_hwpm_ip_vi.h b/hal/t234/ip/vi/t234_hwpm_ip_vi.h index 0dad8a2..b630d7c 100644 --- a/hal/t234/ip/vi/t234_hwpm_ip_vi.h +++ b/hal/t234/ip/vi/t234_hwpm_ip_vi.h @@ -21,6 +21,7 @@ #define T234_HWPM_IP_VI_NUM_INSTANCES 2U #define T234_HWPM_IP_VI_NUM_PERFMON_PER_INST 1U #define T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_VI_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_vi; diff --git a/hal/t234/ip/vic/t234_hwpm_ip_vic.c b/hal/t234/ip/vic/t234_hwpm_ip_vic.c index 41c3f9e..f29a7f4 100644 --- a/hal/t234/ip/vic/t234_hwpm_ip_vic.c +++ b/hal/t234/ip/vic/t234_hwpm_ip_vic.c @@ -17,19 +17,14 @@ #include #include -hwpm_ip_perfmon t234_vic_perfmon_static_array[ - T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST * - T234_HWPM_IP_VIC_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_vic_inst0_perfmon_element_static_array[ + T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST] = { { - .is_hwpm_element = true, - .hw_inst_mask = BIT(0), + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = "perfmon_vica0", - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_rpg_pm_vic_base_r(), .end_abs_pa = addr_map_rpg_pm_vic_limit_r(), .start_pa = 0ULL, @@ -41,19 +36,14 @@ hwpm_ip_perfmon t234_vic_perfmon_static_array[ }, }; -hwpm_ip_perfmux t234_vic_perfmux_static_array[ - T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST * - T234_HWPM_IP_VIC_NUM_INSTANCES] = { +struct hwpm_ip_aperture t234_vic_inst0_perfmux_element_static_array[ + T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST] = { { - .is_hwpm_element = false, - .hw_inst_mask = BIT(0), + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .dt_index = 0U, .dt_mmio = NULL, .name = {'\0'}, - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - }, .start_abs_pa = addr_map_vic_base_r(), .end_abs_pa = addr_map_vic_limit_r(), .start_pa = 0ULL, @@ -65,28 +55,114 @@ hwpm_ip_perfmux t234_vic_perfmux_static_array[ }, }; +/* IP instance array */ +struct hwpm_ip_inst t234_vic_inst_static_array[ + T234_HWPM_IP_VIC_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST, + .element_static_array = + t234_vic_inst0_perfmux_element_static_array, + .range_start = addr_map_vic_base_r(), + .range_end = addr_map_vic_limit_r(), + .element_stride = addr_map_vic_limit_r() - + addr_map_vic_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + T234_HWPM_IP_VIC_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST, + .element_static_array = + t234_vic_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_vic_base_r(), + .range_end = addr_map_rpg_pm_vic_limit_r(), + .element_stride = addr_map_rpg_pm_vic_limit_r() - + addr_map_rpg_pm_vic_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + }, + + .element_fs_mask = 0U, + }, +}; + +/* IP structure */ struct hwpm_ip t234_hwpm_ip_vic = { .num_instances = T234_HWPM_IP_VIC_NUM_INSTANCES, - .num_perfmon_per_inst = T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST, - .num_perfmux_per_inst = T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST, + .ip_inst_static_array = t234_vic_inst_static_array, - .perfmon_range_start = addr_map_rpg_pm_vic_base_r(), - .perfmon_range_end = addr_map_rpg_pm_vic_limit_r(), - .inst_perfmon_stride = addr_map_rpg_pm_vic_limit_r() - - addr_map_rpg_pm_vic_base_r() + 1ULL, - .num_perfmon_slots = 0U, - .ip_perfmon = NULL, - - .perfmux_range_start = addr_map_vic_base_r(), - .perfmux_range_end = addr_map_vic_limit_r(), - .inst_perfmux_stride = addr_map_vic_limit_r() - - addr_map_vic_base_r() + 1ULL, - .num_perfmux_slots = 0U, - .ip_perfmux = NULL, + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .range_start = addr_map_vic_base_r(), + .range_end = addr_map_vic_limit_r(), + .inst_stride = addr_map_vic_limit_r() - + addr_map_vic_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_vic_base_r(), + .range_end = addr_map_rpg_pm_vic_limit_r(), + .inst_stride = addr_map_rpg_pm_vic_limit_r() - + addr_map_rpg_pm_vic_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, .override_enable = false, - .fs_mask = 0U, - .perfmon_static_array = t234_vic_perfmon_static_array, - .perfmux_static_array = t234_vic_perfmux_static_array, + .inst_fs_mask = 0U, .reserved = false, }; diff --git a/hal/t234/ip/vic/t234_hwpm_ip_vic.h b/hal/t234/ip/vic/t234_hwpm_ip_vic.h index 7e65476..5f0c728 100644 --- a/hal/t234/ip/vic/t234_hwpm_ip_vic.h +++ b/hal/t234/ip/vic/t234_hwpm_ip_vic.h @@ -21,6 +21,7 @@ #define T234_HWPM_IP_VIC_NUM_INSTANCES 1U #define T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST 1U #define T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST 1U +#define T234_HWPM_IP_VIC_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip t234_hwpm_ip_vic; diff --git a/hal/t234/t234_hwpm_alist_utils.c b/hal/t234/t234_hwpm_alist_utils.c index deec615..83de2c4 100644 --- a/hal/t234/t234_hwpm_alist_utils.c +++ b/hal/t234/t234_hwpm_alist_utils.c @@ -27,7 +27,7 @@ size_t t234_hwpm_get_alist_buf_size(struct tegra_soc_hwpm *hwpm) } int t234_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm, - struct hwpm_ip_aperture *aperture) + struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture) { u32 alist_idx = 0U; @@ -35,10 +35,10 @@ int t234_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm, for (alist_idx = 0; alist_idx < aperture->alist_size; alist_idx++) { if (aperture->alist[alist_idx].zero_at_init) { - tegra_hwpm_regops_writel(hwpm, aperture, + tegra_hwpm_regops_writel(hwpm, tegra_hwpm_safe_add_u64(aperture->start_abs_pa, aperture->alist[alist_idx].reg_offset), - 0U); + 0U, ip_inst, aperture); } } return 0; diff --git a/hal/t234/t234_hwpm_aperture_utils.c b/hal/t234/t234_hwpm_aperture_utils.c index 7592495..22d376b 100644 --- a/hal/t234/t234_hwpm_aperture_utils.c +++ b/hal/t234/t234_hwpm_aperture_utils.c @@ -32,18 +32,21 @@ int t234_hwpm_disable_triggers(struct tegra_soc_hwpm *hwpm) u32 field_mask = 0U; u32 field_val = 0U; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - hwpm_ip_perfmux *pma_perfmux = NULL; - hwpm_ip_perfmux *rtr_perfmux = NULL; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_RTR_INST]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); - rtr_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_RTR]; - pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; - /* Disable PMA triggers */ reg_val = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_trigger_config_user_r(0)); @@ -97,10 +100,13 @@ int t234_hwpm_init_prod_values(struct tegra_soc_hwpm *hwpm) { u32 reg_val = 0U; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - /* Currently, PMA has only one perfmux */ - hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); @@ -127,27 +133,18 @@ int t234_hwpm_disable_slcg(struct tegra_soc_hwpm *hwpm) u32 field_val = 0U; u32 reg_val = 0U; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *rtr_ip = NULL; - hwpm_ip_perfmux *pma_perfmux = NULL; - hwpm_ip_perfmux *rtr_perfmux = NULL; - - tegra_hwpm_fn(hwpm, " "); - - if (active_chip == NULL) { - return -ENODEV; - } - - rtr_ip = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)]; - - if ((rtr_ip == NULL) || !(rtr_ip->reserved)) { - tegra_hwpm_err(hwpm, "RTR uninitialized"); - return -ENODEV; - } - - pma_perfmux = &rtr_ip->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; - rtr_perfmux = &rtr_ip->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_RTR]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_RTR_INST]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; reg_val = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r()); reg_val = set_field(reg_val, pmasys_cg2_slcg_m(), @@ -175,27 +172,18 @@ int t234_hwpm_enable_slcg(struct tegra_soc_hwpm *hwpm) u32 field_mask = 0U; u32 field_val = 0U; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *rtr_ip = NULL; - hwpm_ip_perfmux *pma_perfmux = NULL; - hwpm_ip_perfmux *rtr_perfmux = NULL; - - tegra_hwpm_fn(hwpm, " "); - - if (active_chip == NULL) { - return -ENODEV; - } - - rtr_ip = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)]; - - if ((rtr_ip == NULL) || !(rtr_ip->reserved)) { - tegra_hwpm_err(hwpm, "RTR uninitialized"); - return -ENODEV; - } - - pma_perfmux = &rtr_ip->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; - rtr_perfmux = &rtr_ip->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_RTR]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_RTR_INST]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; reg_val = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r()); reg_val = set_field(reg_val, pmasys_cg2_slcg_m(), diff --git a/hal/t234/t234_hwpm_interface_utils.c b/hal/t234/t234_hwpm_interface_utils.c index 230e5de..00aedff 100644 --- a/hal/t234/t234_hwpm_interface_utils.c +++ b/hal/t234/t234_hwpm_interface_utils.c @@ -31,8 +31,6 @@ struct tegra_soc_hwpm_chip t234_chip_info = { .get_rtr_int_idx = t234_get_rtr_int_idx, .get_ip_max_idx = t234_get_ip_max_idx, - .init_chip_ip_structures = tegra_hwpm_init_chip_ip_structures, - .extract_ip_ops = t234_hwpm_extract_ip_ops, .force_enable_ips = t234_hwpm_force_enable_ips, .get_fs_info = t234_hwpm_get_fs_info, @@ -63,8 +61,6 @@ struct tegra_soc_hwpm_chip t234_chip_info = { .copy_alist = t234_hwpm_copy_alist, .check_alist = t234_hwpm_check_alist, - .exec_reg_ops = t234_hwpm_exec_reg_ops, - .release_sw_setup = tegra_hwpm_release_sw_setup, }; @@ -90,11 +86,6 @@ static bool t234_hwpm_validate_hals(struct tegra_soc_hwpm *hwpm) return false; } - if (hwpm->active_chip->init_chip_ip_structures == NULL) { - tegra_hwpm_err(hwpm, "init_chip_ip_structures uninitialized"); - return false; - } - if (hwpm->active_chip->extract_ip_ops == NULL) { tegra_hwpm_err(hwpm, "extract_ip_ops uninitialized"); return false; @@ -215,11 +206,6 @@ static bool t234_hwpm_validate_hals(struct tegra_soc_hwpm *hwpm) return false; } - if (hwpm->active_chip->exec_reg_ops == NULL) { - tegra_hwpm_err(hwpm, "exec_reg_ops uninitialized"); - return false; - } - if (hwpm->active_chip->release_sw_setup == NULL) { tegra_hwpm_err(hwpm, "release_sw_setup uninitialized"); return false; diff --git a/hal/t234/t234_hwpm_internal.h b/hal/t234/t234_hwpm_internal.h index 112f4c6..4b21715 100644 --- a/hal/t234/t234_hwpm_internal.h +++ b/hal/t234/t234_hwpm_internal.h @@ -88,11 +88,11 @@ int t234_hwpm_enable_slcg(struct tegra_soc_hwpm *hwpm); int t234_hwpm_disable_triggers(struct tegra_soc_hwpm *hwpm); int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon); + struct hwpm_ip_aperture *perfmon); int t234_hwpm_perfmux_disable(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmux *perfmux); + struct hwpm_ip_aperture *perfmux); int t234_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon); + struct hwpm_ip_aperture *perfmon); int t234_hwpm_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm); int t234_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm, @@ -107,14 +107,11 @@ bool t234_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm); size_t t234_hwpm_get_alist_buf_size(struct tegra_soc_hwpm *hwpm); int t234_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm, - struct hwpm_ip_aperture *aperture); + struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture); int t234_hwpm_copy_alist(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *aperture, u64 *full_alist, u64 *full_alist_idx); bool t234_hwpm_check_alist(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *aperture, u64 phys_addr); -int t234_hwpm_exec_reg_ops(struct tegra_soc_hwpm *hwpm, - struct tegra_soc_hwpm_reg_op *reg_op); - #endif /* T234_HWPM_INTERNAL_H */ diff --git a/hal/t234/t234_hwpm_ip_utils.c b/hal/t234/t234_hwpm_ip_utils.c index bbc52ff..90d9bb7 100644 --- a/hal/t234/t234_hwpm_ip_utils.c +++ b/hal/t234/t234_hwpm_ip_utils.c @@ -263,25 +263,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) /* MSS CHANNEL */ ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc0_base_r(), - T234_HWPM_IP_MSS_CHANNEL, true); - if (ret != 0) { - goto fail; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc4_base_r(), - T234_HWPM_IP_MSS_CHANNEL, true); - if (ret != 0) { - goto fail; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc8_base_r(), - T234_HWPM_IP_MSS_CHANNEL, true); - if (ret != 0) { - goto fail; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc12_base_r(), + addr_map_mcb_base_r(), T234_HWPM_IP_MSS_CHANNEL, true); if (ret != 0) { goto fail; @@ -289,7 +271,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) /* MSS ISO NISO HUBS */ ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc0_base_r(), + addr_map_mcb_base_r(), T234_HWPM_IP_MSS_ISO_NISO_HUBS, true); if (ret != 0) { goto fail; @@ -297,7 +279,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) /* MSS MCF */ ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc0_base_r(), + addr_map_mcb_base_r(), T234_HWPM_IP_MSS_MCF, true); if (ret != 0) { goto fail; @@ -316,7 +298,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) for (i = 0U; i < active_chip->get_ip_max_idx(hwpm); i++) { chip_ip = active_chip->chip_ips[i]; tegra_hwpm_dbg(hwpm, hwpm_verbose, "IP:%d fs_mask:0x%x", - i, chip_ip->fs_mask); + i, chip_ip->inst_fs_mask); } fail: @@ -327,10 +309,9 @@ int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm, u32 ip_index, u64 *fs_mask, u8 *ip_status) { u32 ip_idx = 0U; - u32 i = 0U; - u32 mcc_fs_mask = 0U; struct tegra_soc_hwpm_chip *active_chip = NULL; struct hwpm_ip *chip_ip = NULL; + struct hwpm_ip_inst *ip_inst = NULL; tegra_hwpm_fn(hwpm, " "); @@ -348,22 +329,20 @@ int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm, ip_index); *ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID; } - } else { - active_chip = hwpm->active_chip; - chip_ip = active_chip->chip_ips[ip_idx]; - /* TODO: Update after fS IOCTL discussion */ - if (ip_idx == T234_HWPM_IP_MSS_CHANNEL) { - for (i = 0U; i < 4U; i++) { - if (((0x1U << i) & chip_ip->fs_mask) != 0U) { - mcc_fs_mask |= (0xFU << (i*4U)); - } - } - *fs_mask = mcc_fs_mask; - } else { - *fs_mask = chip_ip->fs_mask; - } - *ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID; + return 0; } + active_chip = hwpm->active_chip; + chip_ip = active_chip->chip_ips[ip_idx]; + ip_inst = &chip_ip->ip_inst_static_array[0U]; + /* TODO: Update after fS IOCTL discussion */ + if (ip_idx == T234_HWPM_IP_MSS_CHANNEL) { + *fs_mask = ip_inst->element_fs_mask; + } else { + *fs_mask = chip_ip->inst_fs_mask; + } + *ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID; + + return 0; } diff --git a/hal/t234/t234_hwpm_mem_buf_utils.c b/hal/t234/t234_hwpm_mem_buf_utils.c index 9b6b215..1a8e235 100644 --- a/hal/t234/t234_hwpm_mem_buf_utils.c +++ b/hal/t234/t234_hwpm_mem_buf_utils.c @@ -26,9 +26,13 @@ int t234_hwpm_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm) { struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); @@ -50,9 +54,13 @@ int t234_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm, u32 outsize = 0; u32 mem_bytes_addr = 0; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); @@ -91,9 +99,13 @@ int t234_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm, int t234_hwpm_invalidate_mem_config(struct tegra_soc_hwpm *hwpm) { struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); @@ -109,9 +121,13 @@ int t234_hwpm_stream_mem_bytes(struct tegra_soc_hwpm *hwpm) u32 reg_val = 0U; u32 *mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_bytes_kernel); struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); @@ -132,9 +148,13 @@ int t234_hwpm_disable_pma_streaming(struct tegra_soc_hwpm *hwpm) { u32 reg_val = 0U; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); @@ -162,9 +182,13 @@ int t234_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm, u64 mem_bump) { struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); @@ -182,9 +206,13 @@ int t234_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm, u64 t234_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm) { struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); @@ -196,9 +224,13 @@ bool t234_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm) { u32 reg_val, field_val; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[ - T234_HWPM_IP_RTR_STATIC_INDEX_PMA]; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx(hwpm)]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_PERMUX_INDEX]; tegra_hwpm_fn(hwpm, " "); diff --git a/hal/t234/t234_hwpm_regops_allowlist.c b/hal/t234/t234_hwpm_regops_allowlist.c index 49a9456..005b53d 100644 --- a/hal/t234/t234_hwpm_regops_allowlist.c +++ b/hal/t234/t234_hwpm_regops_allowlist.c @@ -341,6 +341,12 @@ struct allowlist t234_mc8_res_mss_iso_niso_hub_alist[1] = { {0x00000828, true}, }; +struct allowlist t234_mcb_res_mss_iso_niso_hub_alist[3] = { + {0x00000818, true}, + {0x0000081c, true}, + {0x00000828, true}, +}; + struct allowlist t234_mcb_mss_mcf_alist[4] = { {0x00000800, true}, {0x00000820, true}, diff --git a/hal/t234/t234_hwpm_regops_allowlist.h b/hal/t234/t234_hwpm_regops_allowlist.h index 3c9a301..50cfe17 100644 --- a/hal/t234/t234_hwpm_regops_allowlist.h +++ b/hal/t234/t234_hwpm_regops_allowlist.h @@ -20,11 +20,7 @@ #define T234_HWPM_REGOPS_ALLOWLIST_H #include - -struct allowlist { - u64 reg_offset; - bool zero_at_init; -}; +#include extern struct allowlist t234_perfmon_alist[67]; extern struct allowlist t234_pma_res_cmd_slice_rtr_alist[86]; @@ -45,6 +41,7 @@ extern struct allowlist t234_mss_channel_alist[2]; extern struct allowlist t234_mss_nvlink_alist[1]; extern struct allowlist t234_mc0to7_res_mss_iso_niso_hub_alist[2]; extern struct allowlist t234_mc8_res_mss_iso_niso_hub_alist[1]; +extern struct allowlist t234_mcb_res_mss_iso_niso_hub_alist[3]; extern struct allowlist t234_mcb_mss_mcf_alist[4]; extern struct allowlist t234_mc0to1_mss_mcf_alist[3]; extern struct allowlist t234_mc2to7_mss_mcf_alist[1]; diff --git a/hal/t234/t234_hwpm_regops_utils.c b/hal/t234/t234_hwpm_regops_utils.c deleted file mode 100644 index b664a72..0000000 --- a/hal/t234/t234_hwpm_regops_utils.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include - -#include -#include -#include -#include -#include - -static bool t234_hwpm_is_addr_in_ip_perfmon(struct tegra_soc_hwpm *hwpm, - u64 phys_addr, u32 ip_idx, struct hwpm_ip_aperture **aperture) -{ - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_idx]; - hwpm_ip_perfmon *perfmon = NULL; - u64 address_offset = 0ULL; - u32 perfmon_idx = 0U; - - tegra_hwpm_fn(hwpm, " "); - - /* Check if phys addr doesn't belong to IP perfmon range */ - if ((phys_addr < chip_ip->perfmon_range_start) || - (phys_addr > chip_ip->perfmon_range_end)) { - return false; - } - - /* Find perfmon idx corresponding phys addr */ - address_offset = tegra_hwpm_safe_sub_u64( - phys_addr, chip_ip->perfmon_range_start); - perfmon_idx = tegra_hwpm_safe_cast_u64_to_u32( - address_offset / chip_ip->inst_perfmon_stride); - - perfmon = chip_ip->ip_perfmon[perfmon_idx]; - - /* Check if perfmon is populated */ - if (perfmon == NULL) { - /* - * NOTE: MSS channel and ISO NISO hub IPs have same perfmon - * range but differ in populated perfmons. In this case, - * NULL perfmon may not be a failure indication. - * Log this result for debug and return false. - */ - tegra_hwpm_dbg(hwpm, hwpm_info, - "Accessing IP %d unpopulated perfmon_idx %d", - ip_idx, perfmon_idx); - return false; - } - - /* Make sure that perfmon belongs to available IP instances */ - if ((perfmon->hw_inst_mask & chip_ip->fs_mask) == 0U) { - /* - * NOTE: User accessing this address indicates that - * case 1: perfmon (corresponding IP HW instance) is available - * case 2: computed allowlist is incorrect - * For case 1, - * Perfmon information is added statically. - * It is possible that perfmon (or IP) HW instance is not - * available in a configuration. - * This is a valid case, return false to indicate. - */ - tegra_hwpm_err(hwpm, - "accessed IP %d perfmon %d marked unavailable", - ip_idx, perfmon_idx); - return false; - } - - /* Make sure phys addr belongs to the perfmon */ - if ((phys_addr >= perfmon->start_abs_pa) && - (phys_addr <= perfmon->end_abs_pa)) { - if (t234_hwpm_check_alist(hwpm, perfmon, phys_addr)) { - *aperture = perfmon; - return true; - } - tegra_hwpm_dbg(hwpm, hwpm_verbose, - "phys_addr 0x%llx not in IP %d perfmon_idx %d alist", - phys_addr, ip_idx, perfmon_idx); - return false; - } - - tegra_hwpm_err(hwpm, "Execution shouldn't reach here"); - return false; -} - -static bool t234_hwpm_is_addr_in_ip_perfmux(struct tegra_soc_hwpm *hwpm, - u64 phys_addr, u32 ip_idx, struct hwpm_ip_aperture **aperture) -{ - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_idx]; - hwpm_ip_perfmux *perfmux = NULL; - u64 address_offset = 0ULL; - u32 perfmux_idx = 0U; - - tegra_hwpm_fn(hwpm, " "); - - /* Check if phys addr doesn't belong to IP perfmux range */ - if ((phys_addr < chip_ip->perfmux_range_start) || - (phys_addr > chip_ip->perfmux_range_end)) { - return false; - } - - /* Find perfmux idx corresponding phys addr */ - address_offset = tegra_hwpm_safe_sub_u64( - phys_addr, chip_ip->perfmux_range_start); - perfmux_idx = tegra_hwpm_safe_cast_u64_to_u32( - address_offset / chip_ip->inst_perfmux_stride); - - perfmux = chip_ip->ip_perfmux[perfmux_idx]; - - /* Check if perfmux is populated */ - if (perfmux == NULL) { - /* - * NOTE: MSS channel and ISO NISO hub IPs have same perfmux - * range but differ in populated perfmuxes. In this case, - * NULL perfmux may not be a failure indication. - * Log this result for debug and return false. - */ - tegra_hwpm_dbg(hwpm, hwpm_info, - "Accessing IP %d unpopulated perfmux_idx %d", - ip_idx, perfmux_idx); - return false; - } - - /* Make sure that perfmux belongs to available IP instances */ - if ((perfmux->hw_inst_mask & chip_ip->fs_mask) == 0U) { - /* - * NOTE: User accessing this address indicates that - * case 1: perfmux (corresponding IP HW instance) is available - * case 2: computed allowlist is incorrect - * For case 1, - * Perfmux information is added statically. - * It is possible that perfmux (or IP) HW instance is not - * available in a configuration. - * This is a valid case, return false to indicate. - */ - tegra_hwpm_err(hwpm, - "accessed IP %d perfmux %d marked unavailable", - ip_idx, perfmux_idx); - return false; - } - - /* Make sure phys addr belongs to the perfmux */ - if ((phys_addr >= perfmux->start_abs_pa) && - (phys_addr <= perfmux->end_abs_pa)) { - if (t234_hwpm_check_alist(hwpm, perfmux, phys_addr)) { - *aperture = perfmux; - return true; - } - tegra_hwpm_dbg(hwpm, hwpm_verbose, - "phys_addr 0x%llx not in IP %d perfmux_idx %d alist", - phys_addr, ip_idx, perfmux_idx); - return false; - } - - tegra_hwpm_err(hwpm, "Execution shouldn't reach here"); - return false; -} - -/* - * Find aperture corresponding to phys addr - */ -static int t234_hwpm_find_aperture(struct tegra_soc_hwpm *hwpm, - u64 phys_addr, struct hwpm_ip_aperture **aperture) -{ - struct tegra_soc_hwpm_chip *active_chip = NULL; - struct hwpm_ip *chip_ip = NULL; - u32 ip_idx; - - tegra_hwpm_fn(hwpm, " "); - - if (hwpm->active_chip == NULL) { - tegra_hwpm_err(hwpm, "chip struct not populated"); - return -ENODEV; - } - - active_chip = hwpm->active_chip; - - /* Find IP index */ - for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(hwpm); - ip_idx++) { - chip_ip = active_chip->chip_ips[ip_idx]; - if (chip_ip == NULL) { - tegra_hwpm_err(hwpm, "IP %d not populated as expected", - ip_idx); - return -ENODEV; - } - - if (!chip_ip->reserved) { - continue; - } - - if (t234_hwpm_is_addr_in_ip_perfmux( - hwpm, phys_addr, ip_idx, aperture)) { - return 0; - } - - if (t234_hwpm_is_addr_in_ip_perfmon( - hwpm, phys_addr, ip_idx, aperture)) { - return 0; - } - } - tegra_hwpm_err(hwpm, "addr 0x%llx not found in any IP", phys_addr); - return -EINVAL; -} - -int t234_hwpm_exec_reg_ops(struct tegra_soc_hwpm *hwpm, - struct tegra_soc_hwpm_reg_op *reg_op) -{ - int ret = 0; - u32 reg_val = 0U; - u32 ip_idx = TEGRA_SOC_HWPM_IP_INACTIVE; /* ip_idx is unknown */ - u64 addr_hi = 0ULL; - struct hwpm_ip_aperture *aperture = NULL; - - tegra_hwpm_fn(hwpm, " "); - - /* Find IP aperture containing phys_addr in allowlist */ - ret = t234_hwpm_find_aperture(hwpm, reg_op->phys_addr, &aperture); - if (ret < 0) { - if (ret == -ENODEV) { - tegra_hwpm_err(hwpm, "HWPM structures not populated"); - reg_op->status = - TEGRA_SOC_HWPM_REG_OP_STATUS_INSUFFICIENT_PERMISSIONS; - } else { - /* Phys addr not available in IP allowlist */ - tegra_hwpm_err(hwpm, - "Phys addr 0x%llx not available in IP %d", - reg_op->phys_addr, ip_idx); - reg_op->status = - TEGRA_SOC_HWPM_REG_OP_STATUS_INVALID_ADDR; - } - goto fail; - } - - tegra_hwpm_dbg(hwpm, hwpm_verbose, - "Found phys addr (0x%llx): aperture (0x%llx-0x%llx)", - reg_op->phys_addr, - aperture->start_abs_pa, aperture->end_abs_pa); - - switch (reg_op->cmd) { - case TEGRA_SOC_HWPM_REG_OP_CMD_RD32: - reg_op->reg_val_lo = tegra_hwpm_regops_readl(hwpm, - aperture, reg_op->phys_addr); - reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS; - break; - - case TEGRA_SOC_HWPM_REG_OP_CMD_RD64: - addr_hi = tegra_hwpm_safe_add_u64(reg_op->phys_addr, 4ULL); - reg_op->reg_val_lo = tegra_hwpm_regops_readl(hwpm, - aperture, reg_op->phys_addr); - reg_op->reg_val_hi = tegra_hwpm_regops_readl(hwpm, - aperture, addr_hi); - reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS; - break; - - /* Read Modify Write operation */ - case TEGRA_SOC_HWPM_REG_OP_CMD_WR32: - reg_val = tegra_hwpm_regops_readl(hwpm, - aperture, reg_op->phys_addr); - reg_val = set_field(reg_val, reg_op->mask_lo, - reg_op->reg_val_lo); - tegra_hwpm_regops_writel(hwpm, - aperture, reg_op->phys_addr, reg_val); - reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS; - break; - - /* Read Modify Write operation */ - case TEGRA_SOC_HWPM_REG_OP_CMD_WR64: - addr_hi = tegra_hwpm_safe_add_u64(reg_op->phys_addr, 4ULL); - - /* Lower 32 bits */ - reg_val = tegra_hwpm_regops_readl(hwpm, - aperture, reg_op->phys_addr); - reg_val = set_field(reg_val, reg_op->mask_lo, - reg_op->reg_val_lo); - tegra_hwpm_regops_writel(hwpm, - aperture, reg_op->phys_addr, reg_val); - - /* Upper 32 bits */ - reg_val = tegra_hwpm_regops_readl(hwpm, aperture, addr_hi); - reg_val = set_field(reg_val, reg_op->mask_hi, - reg_op->reg_val_hi); - tegra_hwpm_regops_writel(hwpm, - aperture, reg_op->phys_addr, reg_val); - reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS; - break; - - default: - tegra_hwpm_err(hwpm, "Invalid reg op command(%u)", reg_op->cmd); - reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_INVALID_CMD; - ret = -EINVAL; - break; - } -fail: - return ret; -} diff --git a/hal/t234/t234_hwpm_resource_utils.c b/hal/t234/t234_hwpm_resource_utils.c index bb63ae7..b2b0222 100644 --- a/hal/t234/t234_hwpm_resource_utils.c +++ b/hal/t234/t234_hwpm_resource_utils.c @@ -26,7 +26,7 @@ #include int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon) + struct hwpm_ip_aperture *perfmon) { u32 reg_val; @@ -47,39 +47,28 @@ int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm, } int t234_hwpm_perfmux_disable(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmux *perfmux) + struct hwpm_ip_aperture *perfmux) { - int err = 0; - tegra_hwpm_fn(hwpm, " "); - /* - * Indicate that HWPM monitoring is disabled/closed. - * Since perfmux is controlled by IP, indicate monitoring disabled - * by enabling IP power management. - */ - /* Make sure that ip_ops are initialized */ - if ((perfmux->ip_ops.ip_dev != NULL) && - (perfmux->ip_ops.hwpm_ip_pm != NULL)) { - err = (*perfmux->ip_ops.hwpm_ip_pm)( - perfmux->ip_ops.ip_dev, false); - if (err != 0) { - tegra_hwpm_err(hwpm, "Runtime PM enable failed"); - } - } else { - tegra_hwpm_dbg(hwpm, hwpm_verbose, "Runtime PM not configured"); - } - return 0; } int t234_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon) + struct hwpm_ip_aperture *perfmon) { u32 reg_val; tegra_hwpm_fn(hwpm, " "); + if (perfmon->element_type == HWPM_ELEMENT_PERFMUX) { + /* + * Since HWPM elements use perfmon functions, + * skip disabling HWPM PERFMUX elements + */ + return 0; + } + /* Disable */ tegra_hwpm_dbg(hwpm, hwpm_verbose, "Disabling PERFMON(0x%llx - 0x%llx)", perfmon->start_abs_pa, perfmon->end_abs_pa); diff --git a/include/tegra_hwpm.h b/include/tegra_hwpm.h index b12a49d..bced552 100644 --- a/include/tegra_hwpm.h +++ b/include/tegra_hwpm.h @@ -98,23 +98,51 @@ struct tegra_hwpm_ip_ops { __u64 reg_offset, __u32 *reg_data); }; +/* There are 3 types of HWPM components/apertures */ +#define TEGRA_HWPM_APERTURE_TYPE_PERFMUX 0U +#define TEGRA_HWPM_APERTURE_TYPE_BROADCAST 1U +#define TEGRA_HWPM_APERTURE_TYPE_PERFMON 2U +#define TEGRA_HWPM_APERTURE_TYPE_MAX 3U + +/* + * Devices handled by HWPM driver can be divided into 2 categories + * - HWPM : Components in HWPM device address space + * All perfmons, PMA and RTR perfmuxes + * - IP : Components in IP address space + * IP perfmuxes + * + * This enum defines MACROS to specify an element to be HWPM or IP + * and the specific aperture. + */ +enum tegra_hwpm_element_type { + HWPM_ELEMENT_INVALID, + HWPM_ELEMENT_PERFMON, + HWPM_ELEMENT_PERFMUX, + IP_ELEMENT_PERFMUX, + IP_ELEMENT_BROADCAST, +}; + +enum tegra_hwpm_funcs { + TEGRA_HWPM_INIT_IP_STRUCTURES, + TEGRA_HWPM_MATCH_BASE_ADDRESS, + TEGRA_HWPM_GET_ALIST_SIZE, + TEGRA_HWPM_COMBINE_ALIST, + TEGRA_HWPM_RESERVE_GIVEN_RESOURCE, + TEGRA_HWPM_BIND_RESOURCES, + TEGRA_HWPM_FIND_GIVEN_ADDRESS, + TEGRA_HWPM_RELEASE_RESOURCES, + TEGRA_HWPM_RELEASE_ROUTER, + TEGRA_HWPM_RELEASE_IP_STRUCTURES +}; + struct tegra_hwpm_func_args { u64 *alist; u64 full_alist_idx; }; -enum tegra_hwpm_funcs { - TEGRA_HWPM_GET_ALIST_SIZE, - TEGRA_HWPM_COMBINE_ALIST, - TEGRA_HWPM_RESERVE_GIVEN_RESOURCE, - TEGRA_HWPM_BIND_RESOURCES, - TEGRA_HWPM_RELEASE_RESOURCES, -}; - -enum hwpm_aperture_type { - HWPM_APERTURE_INVALID, - HWPM_APERTURE_PERFMUX, - HWPM_APERTURE_PERFMON, +struct allowlist { + u64 reg_offset; + bool zero_at_init; }; struct hwpm_ip_aperture { @@ -122,10 +150,19 @@ struct hwpm_ip_aperture { * Indicates which domain (HWPM or IP) aperture belongs to, * used for reverse mapping */ - bool is_hwpm_element; + enum tegra_hwpm_element_type element_type; - /* HW index : This is used to update IP fs_mask */ - u32 hw_inst_mask; + /* + * Element index : Index of this aperture within the instance + * This will be used to update element_fs_mask to indicate availability. + */ + u32 element_index_mask; + + /* + * Element index in device tree entry + * For perfmux entries, this index is passed to hwpm_ip_reg_op() + */ + u32 dt_index; /* MMIO device tree aperture - only populated for perfmon */ void __iomem *dt_mmio; @@ -133,9 +170,6 @@ struct hwpm_ip_aperture { /* DT tree name */ char name[64]; - /* IP ops - only populated for perfmux */ - struct tegra_hwpm_ip_ops ip_ops; - /* Allowlist */ struct allowlist *alist; u64 alist_size; @@ -155,50 +189,90 @@ struct hwpm_ip_aperture { u32 *fake_registers; }; -typedef struct hwpm_ip_aperture hwpm_ip_perfmon; -typedef struct hwpm_ip_aperture hwpm_ip_perfmux; +struct hwpm_ip_element_info { + /* Number of apertures per instance */ + u32 num_element_per_inst; + + /* + * Static elements in this instance corresponding to aperture + * Array size: num_element_per_inst + */ + struct hwpm_ip_aperture *element_static_array; + + /* Instance address range corresponding to aperture */ + u64 range_start; + u64 range_end; + + /* Element physical address stride for each element of IP instance */ + u64 element_stride; + + /* + * Elements that can fit into instance address range. + * This gives number of indices in element_arr + */ + u32 element_slots; + + /* + * Dynamic elements array corresponding to this aperture + * Array size: element_slots pointers + */ + struct hwpm_ip_aperture **element_arr; +}; + +struct hwpm_ip_inst { + /* + * HW inst index : HW instance index of this instance + * This mask builds hwpm_ip.inst_fs_mask indicating availability. + */ + u32 hw_inst_mask; + + /* Element details specific to this instance */ + struct hwpm_ip_element_info element_info[TEGRA_HWPM_APERTURE_TYPE_MAX]; + + /* + * IP ops are specific for an instance, used for perfmux and broadcast + * register accesses. + */ + struct tegra_hwpm_ip_ops ip_ops; + + /* + * An IP contains perfmux-perfmon groups that correspond to each other. + * If a perfmux is present, it indicates that the corresponding + * perfmon is present. + * This mask is usually updated based on available perfmuxes. + * (except for SCF). + */ + u32 element_fs_mask; +}; + +struct hwpm_ip_inst_per_aperture_info { + /* IP address range corresponding to aperture */ + u64 range_start; + u64 range_end; + + /* Aperture address range for each IP instance */ + u64 inst_stride; + + /* + * Aperture instances that can fit into IP aperture address range. + * This gives number of entries in inst_arr + */ + u32 inst_slots; + + /* IP inst aperture array */ + struct hwpm_ip_inst **inst_arr; +}; struct hwpm_ip { /* Number of instances */ u32 num_instances; - /* Number of perfmons per instance */ - u32 num_perfmon_per_inst; + /* Static array of IP instances */ + struct hwpm_ip_inst *ip_inst_static_array; - /* Number of perfmuxes per instance */ - u32 num_perfmux_per_inst; - - /* IP perfmon address range */ - u64 perfmon_range_start; - u64 perfmon_range_end; - - /* Perfmon physical address stride for each IP instance */ - u64 inst_perfmon_stride; - - /* - * Perfmon slots that can fit into perfmon address range. - * This gives number of indices in ip_perfmon - */ - u32 num_perfmon_slots; - - /* IP perfmon array */ - hwpm_ip_perfmon **ip_perfmon; - - /* IP perfmux address range */ - u64 perfmux_range_start; - u64 perfmux_range_end; - - /* Perfmux physical address stride for each IP instance */ - u64 inst_perfmux_stride; - - /* - * Perfmux slots that can fit into perfmux address range. - * This gives number of indices in ip_perfmux - */ - u32 num_perfmux_slots; - - /* IP perfmux array */ - hwpm_ip_perfmux **ip_perfmux; + /* Instance info corresponding to apertures in this IP */ + struct hwpm_ip_inst_per_aperture_info inst_aperture_info[ + TEGRA_HWPM_APERTURE_TYPE_MAX]; /* Override IP config based on fuse value */ bool override_enable; @@ -209,13 +283,7 @@ struct hwpm_ip { * hwpm driver clients use hw instance index to find aperture * info (start/end address) from hw manual. */ - u32 fs_mask; - - /* IP perfmon array */ - hwpm_ip_perfmon *perfmon_static_array; - - /* IP perfmux array */ - hwpm_ip_perfmux *perfmux_static_array; + u32 inst_fs_mask; bool reserved; }; @@ -235,8 +303,6 @@ struct tegra_soc_hwpm_chip { u32 (*get_rtr_int_idx)(struct tegra_soc_hwpm *hwpm); u32 (*get_ip_max_idx)(struct tegra_soc_hwpm *hwpm); - int (*init_chip_ip_structures)(struct tegra_soc_hwpm *hwpm); - int (*extract_ip_ops)(struct tegra_soc_hwpm *hwpm, struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops, bool available); int (*force_enable_ips)(struct tegra_soc_hwpm *hwpm); @@ -252,11 +318,11 @@ struct tegra_soc_hwpm_chip { int (*disable_triggers)(struct tegra_soc_hwpm *hwpm); int (*perfmon_enable)(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon); + struct hwpm_ip_aperture *perfmon); int (*perfmon_disable)(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon); + struct hwpm_ip_aperture *perfmon); int (*perfmux_disable)(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmux *perfmux); + struct hwpm_ip_aperture *perfmux); int (*disable_mem_mgmt)(struct tegra_soc_hwpm *hwpm); int (*enable_mem_mgmt)(struct tegra_soc_hwpm *hwpm, @@ -271,6 +337,7 @@ struct tegra_soc_hwpm_chip { size_t (*get_alist_buf_size)(struct tegra_soc_hwpm *hwpm); int (*zero_alist_regs)(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture); int (*copy_alist)(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *aperture, @@ -279,9 +346,6 @@ struct tegra_soc_hwpm_chip { bool (*check_alist)(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *aperture, u64 phys_addr); - int (*exec_reg_ops)(struct tegra_soc_hwpm *hwpm, - struct tegra_soc_hwpm_reg_op *reg_op); - void (*release_sw_setup)(struct tegra_soc_hwpm *hwpm); }; diff --git a/include/tegra_hwpm_common.h b/include/tegra_hwpm_common.h index c144505..8cf1ed6 100644 --- a/include/tegra_hwpm_common.h +++ b/include/tegra_hwpm_common.h @@ -16,6 +16,7 @@ enum tegra_hwpm_funcs; enum hwpm_aperture_type; +enum tegra_hwpm_element_type; struct tegra_hwpm_func_args; struct tegra_soc_hwpm; struct tegra_soc_hwpm_exec_reg_ops; @@ -24,33 +25,23 @@ struct tegra_soc_hwpm_alloc_pma_stream; struct tegra_soc_hwpm_update_get_put; struct hwpm_ip; struct tegra_soc_hwpm_ip_ops; +struct hwpm_ip_inst; struct hwpm_ip_aperture; -typedef struct hwpm_ip_aperture hwpm_ip_perfmon; -typedef struct hwpm_ip_aperture hwpm_ip_perfmux; int tegra_hwpm_init_sw_components(struct tegra_soc_hwpm *hwpm); void tegra_hwpm_release_sw_components(struct tegra_soc_hwpm *hwpm); -int tegra_hwpm_func_single_aperture(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, - u32 inst_idx, u32 aperture_idx, enum hwpm_aperture_type a_type); -int tegra_hwpm_func_all_perfmons(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, u32 inst_idx); -int tegra_hwpm_func_all_perfmuxes(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip, u32 inst_idx); -int tegra_hwpm_func_all_inst(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip); -int tegra_hwpm_func_single_ip(struct tegra_soc_hwpm *hwpm, - struct tegra_hwpm_func_args *func_args, - enum tegra_hwpm_funcs iia_func, u32 ip_idx); int tegra_hwpm_func_all_ip(struct tegra_soc_hwpm *hwpm, struct tegra_hwpm_func_args *func_args, enum tegra_hwpm_funcs iia_func); +int tegra_hwpm_func_single_ip(struct tegra_soc_hwpm *hwpm, + struct tegra_hwpm_func_args *func_args, + enum tegra_hwpm_funcs iia_func, u32 ip_idx); +bool tegra_hwpm_aperture_for_address(struct tegra_soc_hwpm *hwpm, + enum tegra_hwpm_funcs iia_func, + u64 find_addr, u32 *ip_idx, u32 *inst_idx, u32 *element_idx, + enum tegra_hwpm_element_type *element_type); int tegra_hwpm_reserve_resource(struct tegra_soc_hwpm *hwpm, u32 resource); int tegra_hwpm_release_resources(struct tegra_soc_hwpm *hwpm); @@ -59,20 +50,17 @@ int tegra_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm); int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm); int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm); -int tegra_hwpm_perfmon_reserve(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon); -int tegra_hwpm_perfmon_release(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmon *perfmon); -int tegra_hwpm_perfmux_reserve(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmux *perfmux); -int tegra_hwpm_perfmux_release(struct tegra_soc_hwpm *hwpm, - hwpm_ip_perfmux *perfmux); +int tegra_hwpm_element_reserve(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *perfmon); +int tegra_hwpm_element_release(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_aperture *perfmon); -int tegra_hwpm_init_chip_ip_structures(struct tegra_soc_hwpm *hwpm); int tegra_hwpm_set_fs_info_ip_ops(struct tegra_soc_hwpm *hwpm, struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops, u64 base_address, u32 ip_idx, bool available); int tegra_hwpm_finalize_chip_info(struct tegra_soc_hwpm *hwpm); +int tegra_hwpm_ip_handle_power_mgmt(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_inst *ip_inst, bool disable); int tegra_hwpm_get_allowlist_size(struct tegra_soc_hwpm *hwpm); int tegra_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm, diff --git a/include/tegra_hwpm_io.h b/include/tegra_hwpm_io.h index b72c1a8..6663eb5 100644 --- a/include/tegra_hwpm_io.h +++ b/include/tegra_hwpm_io.h @@ -51,6 +51,7 @@ static inline u32 get_field(u32 input_data, u32 mask) struct tegra_soc_hwpm; +struct hwpm_ip_inst; struct hwpm_ip_aperture; u32 tegra_hwpm_readl(struct tegra_soc_hwpm *hwpm, @@ -58,8 +59,10 @@ u32 tegra_hwpm_readl(struct tegra_soc_hwpm *hwpm, void tegra_hwpm_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *aperture, u64 addr, u32 val); u32 tegra_hwpm_regops_readl(struct tegra_soc_hwpm *hwpm, - struct hwpm_ip_aperture *aperture, u64 addr); + u64 addr, struct hwpm_ip_inst *ip_inst, + struct hwpm_ip_aperture *aperture); void tegra_hwpm_regops_writel(struct tegra_soc_hwpm *hwpm, - struct hwpm_ip_aperture *aperture, u64 addr, u32 val); + u64 addr, u32 val, struct hwpm_ip_inst *ip_inst, + struct hwpm_ip_aperture *aperture); #endif /* TEGRA_HWPM_IO_H */ diff --git a/os/linux/tegra_hwpm_io.c b/os/linux/tegra_hwpm_io.c index 47423f9..5d5cbd0 100644 --- a/os/linux/tegra_hwpm_io.c +++ b/os/linux/tegra_hwpm_io.c @@ -18,10 +18,10 @@ #include -#include -#include -#include #include +#include +#include +#include static u32 fake_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *aperture, u64 offset) @@ -52,7 +52,7 @@ static void fake_writel(struct tegra_soc_hwpm *hwpm, * Read IP domain registers * IP(except PMA and RTR) perfmux fall in this category */ -static u32 ip_readl(struct tegra_soc_hwpm *hwpm, +static u32 ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture, u64 offset) { tegra_hwpm_dbg(hwpm, hwpm_register, @@ -63,7 +63,7 @@ static u32 ip_readl(struct tegra_soc_hwpm *hwpm, return fake_readl(hwpm, aperture, offset); } else { u32 reg_val = 0U; - struct tegra_hwpm_ip_ops *ip_ops_ptr = &aperture->ip_ops; + struct tegra_hwpm_ip_ops *ip_ops_ptr = &ip_inst->ip_ops; if (ip_ops_ptr->hwpm_ip_reg_op != NULL) { int err = 0; @@ -107,7 +107,7 @@ static u32 ip_readl(struct tegra_soc_hwpm *hwpm, * Write to IP domain registers * IP(except PMA and RTR) perfmux fall in this category */ -static void ip_writel(struct tegra_soc_hwpm *hwpm, +static void ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture, u64 offset, u32 val) { tegra_hwpm_dbg(hwpm, hwpm_register, @@ -117,7 +117,7 @@ static void ip_writel(struct tegra_soc_hwpm *hwpm, if (hwpm->fake_registers_enabled) { fake_writel(hwpm, aperture, offset, val); } else { - struct tegra_hwpm_ip_ops *ip_ops_ptr = &aperture->ip_ops; + struct tegra_hwpm_ip_ops *ip_ops_ptr = &ip_inst->ip_ops; if (ip_ops_ptr->hwpm_ip_reg_op != NULL) { int err = 0; @@ -216,7 +216,8 @@ u32 tegra_hwpm_readl(struct tegra_soc_hwpm *hwpm, return 0; } - if (aperture->is_hwpm_element) { + if ((aperture->element_type == HWPM_ELEMENT_PERFMON) || + (aperture->element_type == HWPM_ELEMENT_PERFMUX)) { u64 reg_offset = tegra_hwpm_safe_sub_u64( addr, aperture->base_pa); /* HWPM domain registers */ @@ -240,7 +241,8 @@ void tegra_hwpm_writel(struct tegra_soc_hwpm *hwpm, return; } - if (aperture->is_hwpm_element) { + if ((aperture->element_type == HWPM_ELEMENT_PERFMON) || + (aperture->element_type == HWPM_ELEMENT_PERFMUX)) { u64 reg_offset = tegra_hwpm_safe_sub_u64( addr, aperture->base_pa); /* HWPM domain internal registers */ @@ -256,7 +258,8 @@ void tegra_hwpm_writel(struct tegra_soc_hwpm *hwpm, * check has been done before calling this function. */ u32 tegra_hwpm_regops_readl(struct tegra_soc_hwpm *hwpm, - struct hwpm_ip_aperture *aperture, u64 addr) + u64 addr, struct hwpm_ip_inst *ip_inst, + struct hwpm_ip_aperture *aperture) { u32 reg_val = 0; u64 reg_offset = 0ULL; @@ -268,11 +271,11 @@ u32 tegra_hwpm_regops_readl(struct tegra_soc_hwpm *hwpm, reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa); - if (aperture->is_hwpm_element) { - /* HWPM unit internal registers */ + if ((aperture->element_type == HWPM_ELEMENT_PERFMON) || + (aperture->element_type == HWPM_ELEMENT_PERFMUX)) { reg_val = hwpm_readl(hwpm, aperture, reg_offset); } else { - reg_val = ip_readl(hwpm, aperture, reg_offset); + reg_val = ip_readl(hwpm, ip_inst, aperture, reg_offset); } return reg_val; } @@ -282,7 +285,8 @@ u32 tegra_hwpm_regops_readl(struct tegra_soc_hwpm *hwpm, * allowlist check has been done before calling this function. */ void tegra_hwpm_regops_writel(struct tegra_soc_hwpm *hwpm, - struct hwpm_ip_aperture *aperture, u64 addr, u32 val) + u64 addr, u32 val, struct hwpm_ip_inst *ip_inst, + struct hwpm_ip_aperture *aperture) { u64 reg_offset = 0ULL; @@ -293,10 +297,10 @@ void tegra_hwpm_regops_writel(struct tegra_soc_hwpm *hwpm, reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa); - if (aperture->is_hwpm_element) { - /* HWPM unit internal registers */ + if ((aperture->element_type == HWPM_ELEMENT_PERFMON) || + (aperture->element_type == HWPM_ELEMENT_PERFMUX)) { hwpm_writel(hwpm, aperture, reg_offset, val); } else { - ip_writel(hwpm, aperture, reg_offset, val); + ip_writel(hwpm, ip_inst, aperture, reg_offset, val); } }