diff --git a/Makefile b/Makefile index 790c870..346166c 100644 --- a/Makefile +++ b/Makefile @@ -4,13 +4,16 @@ GCOV_PROFILE := y -ccflags-y += -I$(srctree.nvidia)/drivers/platform/tegra/hwpm/include/regops/t234 -ccflags-y += -I$(srctree.nvidia)/drivers/platform/tegra/hwpm/include/hw/t234 ccflags-y += -I$(srctree.nvidia)/drivers/platform/tegra/hwpm +ccflags-y += -I$(srctree.nvidia)/include obj-y += tegra-soc-hwpm.o obj-y += tegra-soc-hwpm-io.o obj-y += tegra-soc-hwpm-ioctl.o obj-y += tegra-soc-hwpm-log.o obj-y += tegra-soc-hwpm-ip.o +obj-y += hal/tegra_soc_hwpm_init.o +obj-y += hal/t234/t234_soc_hwpm_init.o +obj-y += hal/t234/t234_soc_hwpm_mem_buf_utils.o +obj-y += hal/t234/t234_soc_hwpm_resource_utils.o obj-$(CONFIG_DEBUG_FS) += tegra-soc-hwpm-debugfs.o diff --git a/include/hw/t234/hw_addr_map_soc_hwpm.h b/hal/t234/hw/t234_addr_map_soc_hwpm.h similarity index 99% rename from include/hw/t234/hw_addr_map_soc_hwpm.h rename to hal/t234/hw/t234_addr_map_soc_hwpm.h index 1e02609..ac72d46 100644 --- a/include/hw/t234/hw_addr_map_soc_hwpm.h +++ b/hal/t234/hw/t234_addr_map_soc_hwpm.h @@ -53,8 +53,8 @@ * comparison with unshifted values appropriate for use in field * of register . */ -#ifndef TEGRA_HW_ADDR_MAP_SOC_HWPM_H -#define TEGRA_HW_ADDR_MAP_SOC_HWPM_H +#ifndef T234_ADDR_MAP_SOC_HWPM_H +#define T234_ADDR_MAP_SOC_HWPM_H #define addr_map_rpg_pm_base_r() (0x0f100000U) #define addr_map_rpg_pm_limit_r() (0x0f149fffU) diff --git a/include/hw/t234/hw_pmasys_soc_hwpm.h b/hal/t234/hw/t234_pmasys_soc_hwpm.h similarity index 99% rename from include/hw/t234/hw_pmasys_soc_hwpm.h rename to hal/t234/hw/t234_pmasys_soc_hwpm.h index 8f35757..6ba519c 100644 --- a/include/hw/t234/hw_pmasys_soc_hwpm.h +++ b/hal/t234/hw/t234_pmasys_soc_hwpm.h @@ -53,8 +53,8 @@ * comparison with unshifted values appropriate for use in field * of register . */ -#ifndef TEGRA_HW_PMASYS_SOC_HWPM_H -#define TEGRA_HW_PMASYS_SOC_HWPM_H +#ifndef T234_PMASYS_SOC_HWPM_H +#define T234_PMASYS_SOC_HWPM_H #define pmasys_cg2_r() (0x0f14a044U) #define pmasys_cg2_slcg_f(v) (((v) & 0x1U) << 0U) diff --git a/include/hw/t234/hw_pmmsys_soc_hwpm.h b/hal/t234/hw/t234_pmmsys_soc_hwpm.h similarity index 98% rename from include/hw/t234/hw_pmmsys_soc_hwpm.h rename to hal/t234/hw/t234_pmmsys_soc_hwpm.h index 70903a3..c751795 100644 --- a/include/hw/t234/hw_pmmsys_soc_hwpm.h +++ b/hal/t234/hw/t234_pmmsys_soc_hwpm.h @@ -53,8 +53,8 @@ * comparison with unshifted values appropriate for use in field * of register . */ -#ifndef TEGRA_HW_PMMSYS_SOC_HWPM_H -#define TEGRA_HW_PMMSYS_SOC_HWPM_H +#ifndef T234_PMMSYS_SOC_HWPM_H +#define T234_PMMSYS_SOC_HWPM_H #define pmmsys_perdomain_offset_v() (0x00001000U) #define pmmsys_control_r(i)\ diff --git a/hal/t234/t234_soc_hwpm_init.c b/hal/t234/t234_soc_hwpm_init.c new file mode 100644 index 0000000..2110363 --- /dev/null +++ b/hal/t234/t234_soc_hwpm_init.c @@ -0,0 +1,1008 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +void __iomem *t234_dt_apertures[T234_SOC_HWPM_NUM_DT_APERTURES]; +struct tegra_soc_hwpm_ip_ops t234_ip_info[T234_SOC_HWPM_NUM_DT_APERTURES]; + +/* + * Normally there is a 1-to-1 mapping between an MMIO aperture and a + * hwpm_resource_aperture struct. But the PMA MMIO aperture is used in + * multiple hwpm_resource_aperture structs. Therefore, we have to share the fake + * register array between these hwpm_resource_aperture structs. This is why we + * have to define the fake register array globally. For all other 1-to-1 + * mapping apertures the fake register arrays are directly embedded inside the + * hwpm_resource_aperture structs. + */ +u32 *t234_pma_fake_regs; + +struct hwpm_resource t234_hwpm_resources[TERGA_SOC_HWPM_NUM_RESOURCES] = { + [TEGRA_SOC_HWPM_RESOURCE_VI] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_vi_map), + .map = t234_vi_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_ISP] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_isp_map), + .map = t234_isp_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_VIC] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_vic_map), + .map = t234_vic_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_OFA] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_ofa_map), + .map = t234_ofa_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_PVA] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_pva_map), + .map = t234_pva_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_NVDLA] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_nvdla_map), + .map = t234_nvdla_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_MGBE] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_mgbe_map), + .map = t234_mgbe_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_SCF] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_scf_map), + .map = t234_scf_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_NVDEC] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_nvdec_map), + .map = t234_nvdec_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_NVENC] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_nvenc_map), + .map = t234_nvenc_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_PCIE] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_pcie_map), + .map = t234_pcie_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_DISPLAY] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_display_map), + .map = t234_display_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_mss_channel_map), + .map = t234_mss_channel_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_MSS_GPU_HUB] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_mss_gpu_hub_map), + .map = t234_mss_gpu_hub_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_MSS_ISO_NISO_HUBS] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_mss_iso_niso_hub_map), + .map = t234_mss_iso_niso_hub_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_MSS_MCF] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_mss_mcf_map), + .map = t234_mss_mcf_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_PMA] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_pma_map), + .map = t234_pma_map, + }, + [TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR] = { + .reserved = false, + .map_size = ARRAY_SIZE(t234_cmd_slice_rtr_map), + .map = t234_cmd_slice_rtr_map, + }, +}; + +void __iomem **t234_soc_hwpm_init_dt_apertures(void) +{ + return t234_dt_apertures; +} + +struct tegra_soc_hwpm_ip_ops *t234_soc_hwpm_init_ip_ops_info(void) +{ + return t234_ip_info; +} + +bool t234_soc_hwpm_is_perfmon(u32 dt_aperture) +{ + return IS_PERFMON(dt_aperture); +} + +u64 t234_soc_hwpm_get_perfmon_base(u32 dt_aperture) +{ + if (t234_soc_hwpm_is_perfmon(dt_aperture)) { + return PERFMON_BASE(dt_aperture); + } else if (dt_aperture == T234_SOC_HWPM_PMA_DT) { + return addr_map_pma_base_r(); + } else if (dt_aperture == T234_SOC_HWPM_RTR_DT) { + return addr_map_rtr_base_r(); + } else { + return 0ULL; + } +} + +bool t234_soc_hwpm_is_dt_aperture(u32 dt_aperture) +{ + return (dt_aperture < T234_SOC_HWPM_NUM_DT_APERTURES); +} + +u32 t234_soc_hwpm_get_ip_aperture(struct tegra_soc_hwpm *hwpm, + u64 phys_address, u64 *ip_base_addr) +{ + enum t234_soc_hwpm_dt_aperture aperture = + TEGRA_SOC_HWPM_DT_APERTURE_INVALID; + + if ((phys_address >= addr_map_vi_thi_base_r()) && + (phys_address <= addr_map_vi_thi_limit_r())) { + aperture = T234_SOC_HWPM_VI0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_vi_thi_base_r(); + } + } else if ((phys_address >= addr_map_vi2_thi_base_r()) && + (phys_address <= addr_map_vi2_thi_limit_r())) { + aperture = T234_SOC_HWPM_VI1_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_vi2_thi_base_r(); + } + } else if ((phys_address >= addr_map_isp_thi_base_r()) && + (phys_address <= addr_map_isp_thi_limit_r())) { + aperture = T234_SOC_HWPM_ISP0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_isp_thi_base_r(); + } + } else if ((phys_address >= addr_map_vic_base_r()) && + (phys_address <= addr_map_vic_limit_r())) { + aperture = T234_SOC_HWPM_VICA0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_vic_base_r(); + } + } else if ((phys_address >= addr_map_ofa_base_r()) && + (phys_address <= addr_map_ofa_limit_r())) { + aperture = T234_SOC_HWPM_OFAA0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_ofa_base_r(); + } + } else if ((phys_address >= addr_map_pva0_pm_base_r()) && + (phys_address <= addr_map_pva0_pm_limit_r())) { + aperture = T234_SOC_HWPM_PVAV0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pva0_pm_base_r(); + } + } else if ((phys_address >= addr_map_nvdla0_base_r()) && + (phys_address <= addr_map_nvdla0_limit_r())) { + aperture = T234_SOC_HWPM_NVDLAB0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_nvdla0_base_r(); + } + } else if ((phys_address >= addr_map_nvdla1_base_r()) && + (phys_address <= addr_map_nvdla1_limit_r())) { + aperture = T234_SOC_HWPM_NVDLAB1_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_nvdla1_base_r(); + } + } else if ((phys_address >= addr_map_disp_base_r()) && + (phys_address <= addr_map_disp_limit_r())) { + aperture = T234_SOC_HWPM_NVDISPLAY0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_disp_base_r(); + } + } else if ((phys_address >= addr_map_mgbe0_base_r()) && + (phys_address <= addr_map_mgbe0_limit_r())) { + aperture = T234_SOC_HWPM_MGBE0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mgbe0_base_r(); + } + } else if ((phys_address >= addr_map_mgbe1_base_r()) && + (phys_address <= addr_map_mgbe1_limit_r())) { + aperture = T234_SOC_HWPM_MGBE1_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mgbe1_base_r(); + } + } else if ((phys_address >= addr_map_mgbe2_base_r()) && + (phys_address <= addr_map_mgbe2_limit_r())) { + aperture = T234_SOC_HWPM_MGBE2_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mgbe2_base_r(); + } + } else if ((phys_address >= addr_map_mgbe3_base_r()) && + (phys_address <= addr_map_mgbe3_limit_r())) { + aperture = T234_SOC_HWPM_MGBE3_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mgbe3_base_r(); + } + } else if ((phys_address >= addr_map_nvdec_base_r()) && + (phys_address <= addr_map_nvdec_limit_r())) { + aperture = T234_SOC_HWPM_NVDECA0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_nvdec_base_r(); + } + } else if ((phys_address >= addr_map_nvenc_base_r()) && + (phys_address <= addr_map_nvenc_limit_r())) { + aperture = T234_SOC_HWPM_NVENCA0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_nvenc_base_r(); + } + } else if ((phys_address >= addr_map_mss_nvlink_1_base_r()) && + (phys_address <= addr_map_mss_nvlink_1_limit_r())) { + aperture = T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mss_nvlink_1_base_r(); + } + } else if ((phys_address >= addr_map_mss_nvlink_2_base_r()) && + (phys_address <= addr_map_mss_nvlink_2_limit_r())) { + aperture = T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mss_nvlink_2_base_r(); + } + } else if ((phys_address >= addr_map_mss_nvlink_3_base_r()) && + (phys_address <= addr_map_mss_nvlink_3_limit_r())) { + aperture = T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mss_nvlink_3_base_r(); + } + } else if ((phys_address >= addr_map_mss_nvlink_4_base_r()) && + (phys_address <= addr_map_mss_nvlink_4_limit_r())) { + aperture = T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mss_nvlink_4_base_r(); + } + } else if ((phys_address >= addr_map_mss_nvlink_5_base_r()) && + (phys_address <= addr_map_mss_nvlink_5_limit_r())) { + aperture = T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mss_nvlink_5_base_r(); + } + } else if ((phys_address >= addr_map_mss_nvlink_6_base_r()) && + (phys_address <= addr_map_mss_nvlink_6_limit_r())) { + aperture = T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mss_nvlink_6_base_r(); + } + } else if ((phys_address >= addr_map_mss_nvlink_7_base_r()) && + (phys_address <= addr_map_mss_nvlink_7_limit_r())) { + aperture = T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mss_nvlink_7_base_r(); + } + } else if ((phys_address >= addr_map_mss_nvlink_8_base_r()) && + (phys_address <= addr_map_mss_nvlink_8_limit_r())) { + aperture = T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mss_nvlink_8_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c0_ctl_base_r()) && + (phys_address <= addr_map_pcie_c0_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c0_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c1_ctl_base_r()) && + (phys_address <= addr_map_pcie_c1_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE1_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c1_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c2_ctl_base_r()) && + (phys_address <= addr_map_pcie_c2_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE2_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c2_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c3_ctl_base_r()) && + (phys_address <= addr_map_pcie_c3_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE3_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c3_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c4_ctl_base_r()) && + (phys_address <= addr_map_pcie_c4_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE4_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c4_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c5_ctl_base_r()) && + (phys_address <= addr_map_pcie_c5_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE5_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c5_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c6_ctl_base_r()) && + (phys_address <= addr_map_pcie_c6_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE6_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c6_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c7_ctl_base_r()) && + (phys_address <= addr_map_pcie_c7_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE7_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c7_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c8_ctl_base_r()) && + (phys_address <= addr_map_pcie_c8_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE8_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c8_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c9_ctl_base_r()) && + (phys_address <= addr_map_pcie_c9_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE9_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c9_ctl_base_r(); + } + } else if ((phys_address >= addr_map_pcie_c10_ctl_base_r()) && + (phys_address <= addr_map_pcie_c10_ctl_limit_r())) { + aperture = T234_SOC_HWPM_PCIE10_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_pcie_c10_ctl_base_r(); + } + } else if ((phys_address >= addr_map_mc0_base_r()) && + (phys_address <= addr_map_mc0_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc0_base_r(); + } + } else if ((phys_address >= addr_map_mc1_base_r()) && + (phys_address <= addr_map_mc1_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc1_base_r(); + } + } else if ((phys_address >= addr_map_mc2_base_r()) && + (phys_address <= addr_map_mc2_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc2_base_r(); + } + } else if ((phys_address >= addr_map_mc3_base_r()) && + (phys_address <= addr_map_mc3_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc3_base_r(); + } + } else if ((phys_address >= addr_map_mc4_base_r()) && + (phys_address <= addr_map_mc4_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc4_base_r(); + } + } else if ((phys_address >= addr_map_mc5_base_r()) && + (phys_address <= addr_map_mc5_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc5_base_r(); + } + } else if ((phys_address >= addr_map_mc6_base_r()) && + (phys_address <= addr_map_mc6_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc6_base_r(); + } + } else if ((phys_address >= addr_map_mc7_base_r()) && + (phys_address <= addr_map_mc7_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc7_base_r(); + } + } else if ((phys_address >= addr_map_mc8_base_r()) && + (phys_address <= addr_map_mc8_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc8_base_r(); + } + } else if ((phys_address >= addr_map_mc9_base_r()) && + (phys_address <= addr_map_mc9_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc9_base_r(); + } + } else if ((phys_address >= addr_map_mc10_base_r()) && + (phys_address <= addr_map_mc10_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc10_base_r(); + } + } else if ((phys_address >= addr_map_mc11_base_r()) && + (phys_address <= addr_map_mc11_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc11_base_r(); + } + } else if ((phys_address >= addr_map_mc4_base_r()) && + (phys_address <= addr_map_mc12_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc12_base_r(); + } + } else if ((phys_address >= addr_map_mc13_base_r()) && + (phys_address <= addr_map_mc13_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc13_base_r(); + } + } else if ((phys_address >= addr_map_mc14_base_r()) && + (phys_address <= addr_map_mc14_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc14_base_r(); + } + } else if ((phys_address >= addr_map_mc15_base_r()) && + (phys_address <= addr_map_mc15_limit_r())) { + aperture = T234_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT; + if (ip_base_addr) { + *ip_base_addr = addr_map_mc15_base_r(); + } + } + + return (u32)aperture; +} + +int t234_soc_hwpm_fs_info_init(struct tegra_soc_hwpm *hwpm) +{ + hwpm->hwpm_resources = t234_hwpm_resources; + + if (tegra_platform_is_vsp()) { + /* Static IP instances as per VSP netlist */ + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_VIC] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_CHANNEL] = 0xF; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_GPU_HUB] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_MCF] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_NVLINK] = 0x1; + } + if (tegra_platform_is_silicon()) { + /* Static IP instances corresponding to silicon */ + // hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_VI] = 0x3; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_ISP] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_VIC] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_OFA] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_PVA] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_NVDLA] = 0x3; + // hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MGBE] = 0xF; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_SCF] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_NVDEC] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_NVENC] = 0x1; + // hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_PCIE] = 0x32; + // hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_DISPLAY] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_CHANNEL] = 0xFFFF; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_GPU_HUB] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_MCF] = 0x1; + hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_NVLINK] = 0x1; + } + return 0; +} + +int t234_soc_hwpm_pma_rtr_map(struct tegra_soc_hwpm *hwpm) +{ + struct resource *res = NULL; + u64 num_regs = 0ULL; + + hwpm->dt_apertures[T234_SOC_HWPM_PMA_DT] = + of_iomap(hwpm->np, T234_SOC_HWPM_PMA_DT); + if (!hwpm->dt_apertures[T234_SOC_HWPM_PMA_DT]) { + tegra_soc_hwpm_err("Couldn't map the PMA aperture"); + return -ENOMEM; + } + res = platform_get_resource(hwpm->pdev, + IORESOURCE_MEM, + T234_SOC_HWPM_PMA_DT); + if ((!res) || (res->start == 0) || (res->end == 0)) { + tegra_soc_hwpm_err("Invalid resource for PMA"); + return -ENOMEM; + } + t234_pma_map[1].start_pa = res->start; + t234_pma_map[1].end_pa = res->end; + t234_cmd_slice_rtr_map[0].start_pa = res->start; + t234_cmd_slice_rtr_map[0].end_pa = res->end; + if (hwpm->fake_registers_enabled) { + num_regs = (res->end + 1 - res->start) / sizeof(*t234_pma_fake_regs); + t234_pma_fake_regs = (u32 *)kzalloc(sizeof(*t234_pma_fake_regs) * num_regs, + GFP_KERNEL); + if (!t234_pma_fake_regs) { + tegra_soc_hwpm_err("Couldn't allocate memory for PMA" + " fake registers"); + return -ENOMEM; + } + t234_pma_map[1].fake_registers = t234_pma_fake_regs; + t234_cmd_slice_rtr_map[0].fake_registers = t234_pma_fake_regs; + } + + hwpm->hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_PMA].reserved = true; + + hwpm->dt_apertures[T234_SOC_HWPM_RTR_DT] = + of_iomap(hwpm->np, T234_SOC_HWPM_RTR_DT); + if (!hwpm->dt_apertures[T234_SOC_HWPM_RTR_DT]) { + tegra_soc_hwpm_err("Couldn't map the RTR aperture"); + return -ENOMEM; + } + res = platform_get_resource(hwpm->pdev, + IORESOURCE_MEM, + T234_SOC_HWPM_RTR_DT); + if ((!res) || (res->start == 0) || (res->end == 0)) { + tegra_soc_hwpm_err("Invalid resource for RTR"); + return -ENOMEM; + } + t234_cmd_slice_rtr_map[1].start_pa = res->start; + t234_cmd_slice_rtr_map[1].end_pa = res->end; + if (hwpm->fake_registers_enabled) { + num_regs = (res->end + 1 - res->start) / + sizeof(*t234_cmd_slice_rtr_map[1].fake_registers); + t234_cmd_slice_rtr_map[1].fake_registers = + (u32 *)kzalloc( + sizeof(*t234_cmd_slice_rtr_map[1].fake_registers) * + num_regs, + GFP_KERNEL); + if (!t234_cmd_slice_rtr_map[1].fake_registers) { + tegra_soc_hwpm_err("Couldn't allocate memory for RTR" + " fake registers"); + return -ENOMEM; + } + } + hwpm->hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR].reserved = true; + return 0; +} + +int t234_soc_hwpm_pma_rtr_unmap(struct tegra_soc_hwpm *hwpm) +{ + if (hwpm->dt_apertures[T234_SOC_HWPM_PMA_DT]) { + iounmap(hwpm->dt_apertures[T234_SOC_HWPM_PMA_DT]); + hwpm->dt_apertures[T234_SOC_HWPM_PMA_DT] = NULL; + } + t234_pma_map[1].start_pa = 0; + t234_pma_map[1].end_pa = 0; + t234_cmd_slice_rtr_map[0].start_pa = 0; + t234_cmd_slice_rtr_map[0].end_pa = 0; + if (t234_pma_fake_regs) { + kfree(t234_pma_fake_regs); + t234_pma_fake_regs = NULL; + t234_pma_map[1].fake_registers = NULL; + t234_cmd_slice_rtr_map[0].fake_registers = NULL; + } + hwpm->hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_PMA].reserved = false; + + if (hwpm->dt_apertures[T234_SOC_HWPM_RTR_DT]) { + iounmap(hwpm->dt_apertures[T234_SOC_HWPM_RTR_DT]); + hwpm->dt_apertures[T234_SOC_HWPM_RTR_DT] = NULL; + } + t234_cmd_slice_rtr_map[1].start_pa = 0; + t234_cmd_slice_rtr_map[1].end_pa = 0; + if (t234_cmd_slice_rtr_map[1].fake_registers) { + kfree(t234_cmd_slice_rtr_map[1].fake_registers); + t234_cmd_slice_rtr_map[1].fake_registers = NULL; + } + hwpm->hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR].reserved = false; + + return 0; +} + + +int t234_soc_hwpm_disable_pma_triggers(struct tegra_soc_hwpm *hwpm) +{ + int err = 0; + int ret = 0; + bool timeout = false; + u32 field_mask = 0; + u32 field_val = 0; + + /* Disable PMA triggers */ + err = reg_rmw(hwpm, NULL, T234_SOC_HWPM_PMA_DT, + pmasys_trigger_config_user_r(0) - addr_map_pma_base_r(), + pmasys_trigger_config_user_pma_pulse_m(), + pmasys_trigger_config_user_pma_pulse_disable_f(), + false, false); + RELEASE_FAIL("Unable to disable PMA triggers"); + + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_sys_trigger_start_mask_r() - addr_map_pma_base_r(), 0); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_sys_trigger_start_maskb_r() - addr_map_pma_base_r(), 0); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_sys_trigger_stop_mask_r() - addr_map_pma_base_r(), 0); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_sys_trigger_stop_maskb_r() - addr_map_pma_base_r(), 0); + + /* Wait for PERFMONs, ROUTER, and PMA to idle */ + timeout = HWPM_TIMEOUT(pmmsys_sys0router_perfmonstatus_merged_v( + hwpm_readl(hwpm, T234_SOC_HWPM_RTR_DT, + pmmsys_sys0router_perfmonstatus_r() - + addr_map_rtr_base_r())) == 0U, + "NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_EMPTY"); + if (timeout && ret == 0) { + ret = -EIO; + } + + timeout = HWPM_TIMEOUT(pmmsys_sys0router_enginestatus_status_v( + hwpm_readl(hwpm, T234_SOC_HWPM_RTR_DT, + pmmsys_sys0router_enginestatus_r() - + addr_map_rtr_base_r())) == + pmmsys_sys0router_enginestatus_status_empty_v(), + "NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_EMPTY"); + if (timeout && ret == 0) { + ret = -EIO; + } + + field_mask = pmasys_enginestatus_status_m() | + pmasys_enginestatus_rbufempty_m(); + field_val = pmasys_enginestatus_status_empty_f() | + pmasys_enginestatus_rbufempty_empty_f(); + timeout = HWPM_TIMEOUT((hwpm_readl(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_enginestatus_r() - + addr_map_pma_base_r()) & field_mask) == field_val, + "NV_PERF_PMASYS_ENGINESTATUS"); + if (timeout && ret == 0) { + ret = -EIO; + } + + hwpm->hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_PMA].reserved = false; + hwpm->hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR].reserved = false; + + return ret; +} + +int t234_soc_hwpm_disable_slcg(struct tegra_soc_hwpm *hwpm) +{ + int ret; + u32 field_mask = 0U; + u32 field_val = 0U; + + ret = reg_rmw(hwpm, NULL, T234_SOC_HWPM_PMA_DT, + pmasys_cg2_r() - addr_map_pma_base_r(), + pmasys_cg2_slcg_m(), pmasys_cg2_slcg_disabled_f(), + false, false); + if (ret < 0) { + tegra_soc_hwpm_err("Unable to disable PMA SLCG"); + ret = -EIO; + goto fail; + } + + field_mask = pmmsys_sys0router_cg2_slcg_perfmon_m() | + pmmsys_sys0router_cg2_slcg_router_m() | + pmmsys_sys0router_cg2_slcg_m(); + field_val = pmmsys_sys0router_cg2_slcg_perfmon_disabled_f() | + pmmsys_sys0router_cg2_slcg_router_disabled_f() | + pmmsys_sys0router_cg2_slcg_disabled_f(); + ret = reg_rmw(hwpm, NULL, T234_SOC_HWPM_RTR_DT, + pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(), + field_mask, field_val, false, false); + if (ret < 0) { + tegra_soc_hwpm_err("Unable to disable ROUTER SLCG"); + ret = -EIO; + goto fail; + } + + /* Program PROD values */ + ret = reg_rmw(hwpm, NULL, T234_SOC_HWPM_PMA_DT, + pmasys_controlb_r() - addr_map_pma_base_r(), + pmasys_controlb_coalesce_timeout_cycles_m(), + pmasys_controlb_coalesce_timeout_cycles__prod_f(), + false, false); + if (ret < 0) { + tegra_soc_hwpm_err("Unable to program PROD value"); + ret = -EIO; + goto fail; + } + + ret = reg_rmw(hwpm, NULL, T234_SOC_HWPM_PMA_DT, + pmasys_channel_config_user_r(0) - addr_map_pma_base_r(), + pmasys_channel_config_user_coalesce_timeout_cycles_m(), + pmasys_channel_config_user_coalesce_timeout_cycles__prod_f(), + false, false); + if (ret < 0) { + tegra_soc_hwpm_err("Unable to program PROD value"); + ret = -EIO; + goto fail; + } + + goto success; + +fail: + t234_soc_hwpm_pma_rtr_unmap(hwpm); +success: + return ret; +} + +int t234_soc_hwpm_enable_slcg(struct tegra_soc_hwpm *hwpm) +{ + int err, ret = 0; + u32 field_mask = 0U; + u32 field_val = 0U; + + err = reg_rmw(hwpm, NULL, T234_SOC_HWPM_PMA_DT, + pmasys_cg2_r() - addr_map_pma_base_r(), + pmasys_cg2_slcg_m(), + pmasys_cg2_slcg_enabled_f(), false, false); + RELEASE_FAIL("Unable to enable PMA SLCG"); + + field_mask = pmmsys_sys0router_cg2_slcg_perfmon_m() | + pmmsys_sys0router_cg2_slcg_router_m() | + pmmsys_sys0router_cg2_slcg_m(); + field_val = pmmsys_sys0router_cg2_slcg_perfmon__prod_f() | + pmmsys_sys0router_cg2_slcg_router__prod_f() | + pmmsys_sys0router_cg2_slcg__prod_f(); + err = reg_rmw(hwpm, NULL, T234_SOC_HWPM_RTR_DT, + pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(), + field_mask, field_val, false, false); + RELEASE_FAIL("Unable to enable ROUTER SLCG"); + + return err; +} + +static bool t234_soc_hwpm_ip_reg_check(struct hwpm_resource_aperture *aperture, + u64 phys_addr, bool use_absolute_base, + u64 *updated_pa) +{ + u64 start_pa = 0ULL; + u64 end_pa = 0ULL; + + if (!aperture) { + tegra_soc_hwpm_err("Aperture is NULL"); + return false; + } + + if (use_absolute_base) { + start_pa = aperture->start_abs_pa; + end_pa = aperture->end_abs_pa; + } else { + start_pa = aperture->start_pa; + end_pa = aperture->end_pa; + } + + if ((phys_addr >= start_pa) && (phys_addr <= end_pa)) { + tegra_soc_hwpm_dbg("Found aperture:" + " phys_addr(0x%llx), aperture(0x%llx - 0x%llx)", + phys_addr, start_pa, end_pa); + *updated_pa = phys_addr - start_pa + aperture->start_pa; + return true; + } + return false; +} + +/* + * Find an aperture in which phys_addr lies. If check_reservation is true, then + * we also have to do a allowlist check. + */ +struct hwpm_resource_aperture *t234_soc_hwpm_find_aperture( + struct tegra_soc_hwpm *hwpm, u64 phys_addr, + bool use_absolute_base, bool check_reservation, + u64 *updated_pa) +{ + struct hwpm_resource_aperture *aperture = NULL; + int res_idx = 0; + int aprt_idx = 0; + + for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { + if (check_reservation && !hwpm->hwpm_resources[res_idx].reserved) + continue; + + for (aprt_idx = 0; + aprt_idx < hwpm->hwpm_resources[res_idx].map_size; + aprt_idx++) { + aperture = &(hwpm->hwpm_resources[res_idx].map[aprt_idx]); + if (check_reservation) { + if (t234_soc_hwpm_allowlist_check(aperture, phys_addr, + use_absolute_base, updated_pa)) { + return aperture; + } + } else { + if (t234_soc_hwpm_ip_reg_check(aperture, phys_addr, + use_absolute_base, updated_pa)) { + return aperture; + } + } + } + } + + tegra_soc_hwpm_err("Unable to find aperture: phys(0x%llx)", phys_addr); + return NULL; +} + +void t234_soc_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture) +{ + u32 alist_idx = 0U; + + for (alist_idx = 0; alist_idx < aperture->alist_size; alist_idx++) { + if (aperture->alist[alist_idx].zero_at_init) { + ioctl_writel(hwpm, aperture, + aperture->start_pa + + aperture->alist[alist_idx].reg_offset, 0); + } + } +} + +int t234_soc_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm, + void *ioctl_struct) +{ + int err = 0; + int res_idx = 0; + int aprt_idx = 0; + u32 full_alist_idx = 0; + u32 aprt_alist_idx = 0; + long pinned_pages = 0; + long page_idx = 0; + u64 alist_buf_size = 0; + u64 num_pages = 0; + u64 *full_alist_u64 = NULL; + void *full_alist = NULL; + struct page **pages = NULL; + struct hwpm_resource_aperture *aperture = NULL; + struct tegra_soc_hwpm_query_allowlist *query_allowlist = + (struct tegra_soc_hwpm_query_allowlist *)ioctl_struct; + unsigned long user_va = (unsigned long)(query_allowlist->allowlist); + unsigned long offset = user_va & ~PAGE_MASK; + + if (hwpm->full_alist_size < 0) { + tegra_soc_hwpm_err("Invalid allowlist size"); + return -EINVAL; + } + alist_buf_size = hwpm->full_alist_size * sizeof(struct allowlist); + + /* Memory map user buffer into kernel address space */ + num_pages = DIV_ROUND_UP(offset + alist_buf_size, PAGE_SIZE); + pages = (struct page **)kzalloc(sizeof(*pages) * num_pages, GFP_KERNEL); + if (!pages) { + tegra_soc_hwpm_err("Couldn't allocate memory for pages array"); + err = -ENOMEM; + goto alist_unmap; + } + pinned_pages = get_user_pages(user_va & PAGE_MASK, num_pages, 0, + pages, NULL); + if (pinned_pages != num_pages) { + tegra_soc_hwpm_err("Requested %llu pages / Got %ld pages", + num_pages, pinned_pages); + err = -ENOMEM; + goto alist_unmap; + } + full_alist = vmap(pages, num_pages, VM_MAP, PAGE_KERNEL); + if (!full_alist) { + tegra_soc_hwpm_err("Couldn't map allowlist buffer into" + " kernel address space"); + err = -ENOMEM; + goto alist_unmap; + } + full_alist_u64 = (u64 *)(full_alist + offset); + + /* Fill in allowlist buffer */ + for (res_idx = 0, full_alist_idx = 0; + res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; + res_idx++) { + if (!(hwpm->hwpm_resources[res_idx].reserved)) + continue; + tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx); + + for (aprt_idx = 0; + aprt_idx < hwpm->hwpm_resources[res_idx].map_size; + aprt_idx++) { + aperture = &(hwpm->hwpm_resources[res_idx].map[aprt_idx]); + if (aperture->alist) { + for (aprt_alist_idx = 0; + aprt_alist_idx < aperture->alist_size; + aprt_alist_idx++, full_alist_idx++) { + full_alist_u64[full_alist_idx] = + aperture->start_pa + + aperture->alist[aprt_alist_idx].reg_offset; + } + } else { + tegra_soc_hwpm_err("NULL allowlist in aperture(0x%llx - 0x%llx)", + aperture->start_pa, + aperture->end_pa); + } + } + } + +alist_unmap: + if (full_alist) + vunmap(full_alist); + if (pinned_pages > 0) { + for (page_idx = 0; page_idx < pinned_pages; page_idx++) { + set_page_dirty(pages[page_idx]); + put_page(pages[page_idx]); + } + } + if (pages) { + kfree(pages); + } + + return err; +} + +bool t234_soc_hwpm_allowlist_check(struct hwpm_resource_aperture *aperture, + u64 phys_addr, bool use_absolute_base, + u64 *updated_pa) +{ + u32 idx = 0U; + u64 start_pa = 0ULL; + + if (!aperture) { + tegra_soc_hwpm_err("Aperture is NULL"); + return false; + } + if (!aperture->alist) { + tegra_soc_hwpm_err("NULL allowlist in dt_aperture(%d)", + aperture->dt_aperture); + return false; + } + + start_pa = use_absolute_base ? aperture->start_abs_pa : + aperture->start_pa; + + for (idx = 0; idx < aperture->alist_size; idx++) { + if (phys_addr == start_pa + aperture->alist[idx].reg_offset) { + *updated_pa = aperture->start_pa + + aperture->alist[idx].reg_offset; + return true; + } + } + + return false; +} + +void t234_soc_hwpm_get_full_allowlist(struct tegra_soc_hwpm *hwpm) +{ + int res_idx = 0; + int aprt_idx = 0; + struct hwpm_resource_aperture *aperture = NULL; + + for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { + if (!(hwpm->hwpm_resources[res_idx].reserved)) + continue; + tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx); + + for (aprt_idx = 0; + aprt_idx < hwpm->hwpm_resources[res_idx].map_size; + aprt_idx++) { + aperture = &(hwpm->hwpm_resources[res_idx].map[aprt_idx]); + if (aperture->alist) { + hwpm->full_alist_size += aperture->alist_size; + } else { + tegra_soc_hwpm_err( + "NULL allowlist in aperture(0x%llx - 0x%llx)", + aperture->start_pa, aperture->end_pa); + } + } + } +} diff --git a/hal/t234/t234_soc_hwpm_init.h b/hal/t234/t234_soc_hwpm_init.h new file mode 100644 index 0000000..c7581ea --- /dev/null +++ b/hal/t234/t234_soc_hwpm_init.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef T234_SOC_HWPM_INIT_H +#define T234_SOC_HWPM_INIT_H + +#include + +void __iomem **t234_soc_hwpm_init_dt_apertures(void); +struct tegra_soc_hwpm_ip_ops *t234_soc_hwpm_init_ip_ops_info(void); +bool t234_soc_hwpm_is_perfmon(u32 dt_aperture); +u64 t234_soc_hwpm_get_perfmon_base(u32 dt_aperture); +bool t234_soc_hwpm_is_dt_aperture(u32 dt_aperture); +u32 t234_soc_hwpm_get_ip_aperture(struct tegra_soc_hwpm *hwpm, + u64 phys_address, u64 *ip_base_addr); +int t234_soc_hwpm_fs_info_init(struct tegra_soc_hwpm *hwpm); +int t234_soc_hwpm_disable_pma_triggers(struct tegra_soc_hwpm *hwpm); +u32 **t234_soc_hwpm_get_mc_fake_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture); +void t234_soc_hwpm_set_mc_fake_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture, + bool set_null); +int t234_soc_hwpm_pma_rtr_map(struct tegra_soc_hwpm *hwpm); +int t234_soc_hwpm_pma_rtr_unmap(struct tegra_soc_hwpm *hwpm); +int t234_soc_hwpm_disable_slcg(struct tegra_soc_hwpm *hwpm); +int t234_soc_hwpm_enable_slcg(struct tegra_soc_hwpm *hwpm); +struct hwpm_resource_aperture *t234_soc_hwpm_find_aperture( + struct tegra_soc_hwpm *hwpm, u64 phys_addr, + bool use_absolute_base, bool check_reservation, + u64 *updated_pa); + +void t234_soc_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture); +int t234_soc_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm, + void *ioctl_struct); +bool t234_soc_hwpm_allowlist_check(struct hwpm_resource_aperture *aperture, + u64 phys_addr, bool use_absolute_base, + u64 *updated_pa); +void t234_soc_hwpm_get_full_allowlist(struct tegra_soc_hwpm *hwpm); + +int t234_soc_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm, + struct tegra_soc_hwpm_update_get_put *update_get_put); +int t234_soc_hwpm_clear_pipeline(struct tegra_soc_hwpm *hwpm); +int t234_soc_hwpm_stream_buf_map(struct tegra_soc_hwpm *hwpm, + struct tegra_soc_hwpm_alloc_pma_stream *alloc_pma_stream); + +bool t234_soc_hwpm_is_dt_aperture_reserved(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture, u32 rsrc_id); +int t234_soc_hwpm_reserve_given_resource( + struct tegra_soc_hwpm *hwpm, u32 resource); +void t234_soc_hwpm_reset_resources(struct tegra_soc_hwpm *hwpm); +void t234_soc_hwpm_disable_perfmons(struct tegra_soc_hwpm *hwpm); +int t234_soc_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm); + +#endif /* T234_SOC_HWPM_INIT_H */ diff --git a/hal/t234/t234_soc_hwpm_ip_map.h b/hal/t234/t234_soc_hwpm_ip_map.h new file mode 100644 index 0000000..9726dc1 --- /dev/null +++ b/hal/t234/t234_soc_hwpm_ip_map.h @@ -0,0 +1,1562 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#ifndef T234_SOC_HWPM_IP_MAP_H +#define T234_SOC_HWPM_IP_MAP_H + +#include +#include +#include + +/* + * Aperture Ranges (start_pa/end_pa): + * - start_pa and end_pa is 0 for PERFMON, PMA, and RTR apertures. These + * ranges will be extracted from the device tree. + * - IP apertures are not listed in the device tree because we don't map them. + * Therefore, start_pa and end_pa for IP apertures are hardcoded here. IP + * apertures are listed here because we need to track their allowlists. + */ +struct hwpm_resource_aperture t234_vi_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_VI0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_VI0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_VI0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_VI1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_VI1_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_VI1_PERFMON_DT, + .index_mask = 0x2U, + }, + { + .start_pa = addr_map_vi_thi_base_r(), + .end_pa = addr_map_vi_thi_limit_r(), + .start_abs_pa = addr_map_vi_thi_base_r(), + .end_abs_pa = addr_map_vi_thi_limit_r(), + .fake_registers = NULL, + .alist = t234_vi_thi_alist, + .alist_size = ARRAY_SIZE(t234_vi_thi_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_vi2_thi_base_r(), + .end_pa = addr_map_vi2_thi_limit_r(), + .start_abs_pa = addr_map_vi2_thi_base_r(), + .end_abs_pa = addr_map_vi2_thi_limit_r(), + .fake_registers = NULL, + .alist = t234_vi_thi_alist, + .alist_size = ARRAY_SIZE(t234_vi_thi_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x2U, + }, +}; + +struct hwpm_resource_aperture t234_isp_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_ISP0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_ISP0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_ISP0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_isp_thi_base_r(), + .end_pa = addr_map_isp_thi_limit_r(), + .start_abs_pa = addr_map_isp_thi_base_r(), + .end_abs_pa = addr_map_isp_thi_limit_r(), + .fake_registers = NULL, + .alist = t234_isp_thi_alist, + .alist_size = ARRAY_SIZE(t234_isp_thi_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_vic_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_VICA0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_VICA0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_VICA0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_vic_base_r(), + .end_pa = addr_map_vic_limit_r(), + .start_abs_pa = addr_map_vic_base_r(), + .end_abs_pa = addr_map_vic_limit_r(), + .fake_registers = NULL, + .alist = t234_vic_alist, + .alist_size = ARRAY_SIZE(t234_vic_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_ofa_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_OFAA0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_OFAA0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_OFAA0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_ofa_base_r(), + .end_pa = addr_map_ofa_limit_r(), + .start_abs_pa = addr_map_ofa_base_r(), + .end_abs_pa = addr_map_ofa_limit_r(), + .fake_registers = NULL, + .alist = t234_ofa_alist, + .alist_size = ARRAY_SIZE(t234_ofa_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_pva_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PVAV0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PVAV0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PVAV0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PVAV1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PVAV1_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PVAV1_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PVAC0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PVAC0_PERFMON_DT), + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .fake_registers = NULL, + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PVAC0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_pva0_pm_base_r(), + .end_pa = addr_map_pva0_pm_limit_r(), + .start_abs_pa = addr_map_pva0_pm_base_r(), + .end_abs_pa = addr_map_pva0_pm_limit_r(), + .fake_registers = NULL, + .alist = t234_pva0_pm_alist, + .alist_size = ARRAY_SIZE(t234_pva0_pm_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_nvdla_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_NVDLAB0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_NVDLAB0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_NVDLAB0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_NVDLAB1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_NVDLAB1_PERFMON_DT), + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .fake_registers = NULL, + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_NVDLAB1_PERFMON_DT, + .index_mask = 0x2U, + }, + { + .start_pa = addr_map_nvdla0_base_r(), + .end_pa = addr_map_nvdla0_limit_r(), + .start_abs_pa = addr_map_nvdla0_base_r(), + .end_abs_pa = addr_map_nvdla0_limit_r(), + .fake_registers = NULL, + .alist = t234_nvdla_alist, + .alist_size = ARRAY_SIZE(t234_nvdla_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_nvdla1_base_r(), + .end_pa = addr_map_nvdla1_limit_r(), + .start_abs_pa = addr_map_nvdla1_base_r(), + .end_abs_pa = addr_map_nvdla1_limit_r(), + .fake_registers = NULL, + .alist = t234_nvdla_alist, + .alist_size = ARRAY_SIZE(t234_nvdla_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x2U, + }, +}; + +struct hwpm_resource_aperture t234_mgbe_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MGBE0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MGBE0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MGBE0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MGBE1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MGBE1_PERFMON_DT), + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .fake_registers = NULL, + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MGBE1_PERFMON_DT, + .index_mask = 0x2U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MGBE2_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MGBE2_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MGBE2_PERFMON_DT, + .index_mask = 0x4U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MGBE3_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MGBE3_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MGBE3_PERFMON_DT, + .index_mask = 0x8U, + }, + { + .start_pa = addr_map_mgbe0_base_r(), + .end_pa = addr_map_mgbe0_limit_r(), + .start_abs_pa = addr_map_mgbe0_base_r(), + .end_abs_pa = addr_map_mgbe0_limit_r(), + .fake_registers = NULL, + .alist = t234_mgbe_alist, + .alist_size = ARRAY_SIZE(t234_mgbe_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mgbe1_base_r(), + .end_pa = addr_map_mgbe1_limit_r(), + .start_abs_pa = addr_map_mgbe1_base_r(), + .end_abs_pa = addr_map_mgbe1_limit_r(), + .fake_registers = NULL, + .alist = t234_mgbe_alist, + .alist_size = ARRAY_SIZE(t234_mgbe_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x2U, + }, + { + .start_pa = addr_map_mgbe2_base_r(), + .end_pa = addr_map_mgbe2_limit_r(), + .start_abs_pa = addr_map_mgbe2_base_r(), + .end_abs_pa = addr_map_mgbe2_limit_r(), + .fake_registers = NULL, + .alist = t234_mgbe_alist, + .alist_size = ARRAY_SIZE(t234_mgbe_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x4U, + }, + { + .start_pa = addr_map_mgbe3_base_r(), + .end_pa = addr_map_mgbe3_limit_r(), + .start_abs_pa = addr_map_mgbe3_base_r(), + .end_abs_pa = addr_map_mgbe3_limit_r(), + .fake_registers = NULL, + .alist = t234_mgbe_alist, + .alist_size = ARRAY_SIZE(t234_mgbe_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x8U, + }, +}; + +struct hwpm_resource_aperture t234_scf_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_SCF0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_SCF0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_SCF0_PERFMON_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_nvdec_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_NVDECA0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_NVDECA0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_NVDECA0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_nvdec_base_r(), + .end_pa = addr_map_nvdec_limit_r(), + .start_abs_pa = addr_map_nvdec_base_r(), + .end_abs_pa = addr_map_nvdec_limit_r(), + .fake_registers = NULL, + .alist = t234_nvdec_alist, + .alist_size = ARRAY_SIZE(t234_nvdec_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_nvenc_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_NVENCA0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_NVENCA0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_NVENCA0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_nvenc_base_r(), + .end_pa = addr_map_nvenc_limit_r(), + .start_abs_pa = addr_map_nvenc_base_r(), + .end_abs_pa = addr_map_nvenc_limit_r(), + .fake_registers = NULL, + .alist = t234_nvenc_alist, + .alist_size = ARRAY_SIZE(t234_nvenc_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_pcie_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE1_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE1_PERFMON_DT, + .index_mask = 0x2U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE2_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE2_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE2_PERFMON_DT, + .index_mask = 0x4U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE3_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE3_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE3_PERFMON_DT, + .index_mask = 0x8U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE4_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE4_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE4_PERFMON_DT, + .index_mask = 0x10U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE5_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE5_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE5_PERFMON_DT, + .index_mask = 0x20U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE6_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE6_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE6_PERFMON_DT, + .index_mask = 0x40U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE7_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE7_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE7_PERFMON_DT, + .index_mask = 0x80U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE8_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE8_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE8_PERFMON_DT, + .index_mask = 0x100U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE9_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE9_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE9_PERFMON_DT, + .index_mask = 0x200U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_PCIE10_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_PCIE10_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PCIE10_PERFMON_DT, + .index_mask = 0x400U, + }, + { + .start_pa = addr_map_pcie_c0_ctl_base_r(), + .end_pa = addr_map_pcie_c0_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c0_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c0_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_pcie_c1_ctl_base_r(), + .end_pa = addr_map_pcie_c1_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c1_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c1_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x2U, + }, + { + .start_pa = addr_map_pcie_c2_ctl_base_r(), + .end_pa = addr_map_pcie_c2_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c2_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c2_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x4U, + }, + { + .start_pa = addr_map_pcie_c3_ctl_base_r(), + .end_pa = addr_map_pcie_c3_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c3_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c3_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x8U, + }, + { + .start_pa = addr_map_pcie_c4_ctl_base_r(), + .end_pa = addr_map_pcie_c4_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c4_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c4_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x10U, + }, + { + .start_pa = addr_map_pcie_c5_ctl_base_r(), + .end_pa = addr_map_pcie_c5_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c5_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c5_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x20U, + }, + { + .start_pa = addr_map_pcie_c6_ctl_base_r(), + .end_pa = addr_map_pcie_c6_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c6_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c6_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x40U, + }, + { + .start_pa = addr_map_pcie_c7_ctl_base_r(), + .end_pa = addr_map_pcie_c7_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c7_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c7_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x80U, + }, + { + .start_pa = addr_map_pcie_c8_ctl_base_r(), + .end_pa = addr_map_pcie_c8_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c8_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c8_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x100U, + }, + { + .start_pa = addr_map_pcie_c9_ctl_base_r(), + .end_pa = addr_map_pcie_c9_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c9_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c9_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x200U, + }, + { + .start_pa = addr_map_pcie_c10_ctl_base_r(), + .end_pa = addr_map_pcie_c10_ctl_limit_r(), + .start_abs_pa = addr_map_pcie_c10_ctl_base_r(), + .end_abs_pa = addr_map_pcie_c10_ctl_limit_r(), + .fake_registers = NULL, + .alist = t234_pcie_ctl_alist, + .alist_size = ARRAY_SIZE(t234_pcie_ctl_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x400U, + }, +}; + +struct hwpm_resource_aperture t234_display_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_NVDISPLAY0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_NVDISPLAY0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_NVDISPLAY0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_disp_base_r(), + .end_pa = addr_map_disp_limit_r(), + .start_abs_pa = addr_map_disp_base_r(), + .end_abs_pa = addr_map_disp_limit_r(), + .fake_registers = NULL, + .alist = t234_disp_alist, + .alist_size = ARRAY_SIZE(t234_disp_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_mss_channel_map[] = { + { + .start_pa = addr_map_mc0_base_r(), + .end_pa = addr_map_mc0_limit_r(), + .start_abs_pa = addr_map_mc0_base_r(), + .end_abs_pa = addr_map_mc0_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc1_base_r(), + .end_pa = addr_map_mc1_limit_r(), + .start_abs_pa = addr_map_mc1_base_r(), + .end_abs_pa = addr_map_mc1_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x2U, + }, + { + .start_pa = addr_map_mc2_base_r(), + .end_pa = addr_map_mc2_limit_r(), + .start_abs_pa = addr_map_mc2_base_r(), + .end_abs_pa = addr_map_mc2_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x4U, + }, + { + .start_pa = addr_map_mc3_base_r(), + .end_pa = addr_map_mc3_limit_r(), + .start_abs_pa = addr_map_mc3_base_r(), + .end_abs_pa = addr_map_mc3_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x8U, + }, + { + .start_pa = addr_map_mc4_base_r(), + .end_pa = addr_map_mc4_limit_r(), + .start_abs_pa = addr_map_mc4_base_r(), + .end_abs_pa = addr_map_mc4_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x10U, + }, + { + .start_pa = addr_map_mc5_base_r(), + .end_pa = addr_map_mc5_limit_r(), + .start_abs_pa = addr_map_mc5_base_r(), + .end_abs_pa = addr_map_mc5_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x20U, + }, + { + .start_pa = addr_map_mc6_base_r(), + .end_pa = addr_map_mc6_limit_r(), + .start_abs_pa = addr_map_mc6_base_r(), + .end_abs_pa = addr_map_mc6_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x40U, + }, + { + .start_pa = addr_map_mc7_base_r(), + .end_pa = addr_map_mc7_limit_r(), + .start_abs_pa = addr_map_mc7_base_r(), + .end_abs_pa = addr_map_mc7_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x80U, + }, + { + .start_pa = addr_map_mc8_base_r(), + .end_pa = addr_map_mc8_limit_r(), + .start_abs_pa = addr_map_mc8_base_r(), + .end_abs_pa = addr_map_mc8_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x100U, + }, + { + .start_pa = addr_map_mc9_base_r(), + .end_pa = addr_map_mc9_limit_r(), + .start_abs_pa = addr_map_mc9_base_r(), + .end_abs_pa = addr_map_mc9_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x200U, + }, + { + .start_pa = addr_map_mc10_base_r(), + .end_pa = addr_map_mc10_limit_r(), + .start_abs_pa = addr_map_mc10_base_r(), + .end_abs_pa = addr_map_mc10_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x400U, + }, + { + .start_pa = addr_map_mc11_base_r(), + .end_pa = addr_map_mc11_limit_r(), + .start_abs_pa = addr_map_mc11_base_r(), + .end_abs_pa = addr_map_mc11_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x800U, + }, + { + .start_pa = addr_map_mc12_base_r(), + .end_pa = addr_map_mc12_limit_r(), + .start_abs_pa = addr_map_mc12_base_r(), + .end_abs_pa = addr_map_mc12_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1000U, + }, + { + .start_pa = addr_map_mc13_base_r(), + .end_pa = addr_map_mc13_limit_r(), + .start_abs_pa = addr_map_mc13_base_r(), + .end_abs_pa = addr_map_mc13_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x2000U, + }, + { + .start_pa = addr_map_mc14_base_r(), + .end_pa = addr_map_mc14_limit_r(), + .start_abs_pa = addr_map_mc14_base_r(), + .end_abs_pa = addr_map_mc14_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x4000U, + }, + { + .start_pa = addr_map_mc15_base_r(), + .end_pa = addr_map_mc15_limit_r(), + .start_abs_pa = addr_map_mc15_base_r(), + .end_abs_pa = addr_map_mc15_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_channel_alist, + .alist_size = ARRAY_SIZE(t234_mss_channel_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x8000U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT, + .index_mask = 0x2U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT, + .index_mask = 0x4U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT, + .index_mask = 0x8U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT, + .index_mask = 0x10U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT, + .index_mask = 0x20U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT, + .index_mask = 0x40U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT, + .index_mask = 0x80U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT, + .index_mask = 0x100U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT, + .index_mask = 0x200U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT, + .index_mask = 0x400U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT, + .index_mask = 0x800U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT, + .index_mask = 0x1000U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT, + .index_mask = 0x2000U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT, + .index_mask = 0x4000U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT, + .index_mask = 0x8000U, + }, +}; + +struct hwpm_resource_aperture t234_mss_gpu_hub_map[] = { + { + .start_pa = addr_map_mss_nvlink_1_base_r(), + .end_pa = addr_map_mss_nvlink_1_limit_r(), + .start_abs_pa = addr_map_mss_nvlink_1_base_r(), + .end_abs_pa = addr_map_mss_nvlink_1_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_nvlink_alist, + .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mss_nvlink_2_base_r(), + .end_pa = addr_map_mss_nvlink_2_limit_r(), + .start_abs_pa = addr_map_mss_nvlink_2_base_r(), + .end_abs_pa = addr_map_mss_nvlink_2_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_nvlink_alist, + .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x2U, + }, + { + .start_pa = addr_map_mss_nvlink_3_base_r(), + .end_pa = addr_map_mss_nvlink_3_limit_r(), + .start_abs_pa = addr_map_mss_nvlink_3_base_r(), + .end_abs_pa = addr_map_mss_nvlink_3_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_nvlink_alist, + .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x4U, + }, + { + .start_pa = addr_map_mss_nvlink_4_base_r(), + .end_pa = addr_map_mss_nvlink_4_limit_r(), + .start_abs_pa = addr_map_mss_nvlink_4_base_r(), + .end_abs_pa = addr_map_mss_nvlink_4_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_nvlink_alist, + .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x8U, + }, + { + .start_pa = addr_map_mss_nvlink_5_base_r(), + .end_pa = addr_map_mss_nvlink_5_limit_r(), + .start_abs_pa = addr_map_mss_nvlink_5_base_r(), + .end_abs_pa = addr_map_mss_nvlink_5_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_nvlink_alist, + .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x10U, + }, + { + .start_pa = addr_map_mss_nvlink_6_base_r(), + .end_pa = addr_map_mss_nvlink_6_limit_r(), + .start_abs_pa = addr_map_mss_nvlink_6_base_r(), + .end_abs_pa = addr_map_mss_nvlink_6_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_nvlink_alist, + .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x20U, + }, + { + .start_pa = addr_map_mss_nvlink_7_base_r(), + .end_pa = addr_map_mss_nvlink_7_limit_r(), + .start_abs_pa = addr_map_mss_nvlink_7_base_r(), + .end_abs_pa = addr_map_mss_nvlink_7_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_nvlink_alist, + .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x40U, + }, + { + .start_pa = addr_map_mss_nvlink_8_base_r(), + .end_pa = addr_map_mss_nvlink_8_limit_r(), + .start_abs_pa = addr_map_mss_nvlink_8_base_r(), + .end_abs_pa = addr_map_mss_nvlink_8_limit_r(), + .fake_registers = NULL, + .alist = t234_mss_nvlink_alist, + .alist_size = ARRAY_SIZE(t234_mss_nvlink_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x80U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT, + .index_mask = 0xFFU, + }, +}; + +struct hwpm_resource_aperture t234_mss_iso_niso_hub_map[] = { + { + .start_pa = addr_map_mc0_base_r(), + .end_pa = addr_map_mc0_limit_r(), + .start_abs_pa = addr_map_mc0_base_r(), + .end_abs_pa = addr_map_mc0_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc1_base_r(), + .end_pa = addr_map_mc1_limit_r(), + .start_abs_pa = addr_map_mc1_base_r(), + .end_abs_pa = addr_map_mc1_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc2_base_r(), + .end_pa = addr_map_mc2_limit_r(), + .start_abs_pa = addr_map_mc2_base_r(), + .end_abs_pa = addr_map_mc2_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc3_base_r(), + .end_pa = addr_map_mc3_limit_r(), + .start_abs_pa = addr_map_mc3_base_r(), + .end_abs_pa = addr_map_mc3_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc4_base_r(), + .end_pa = addr_map_mc4_limit_r(), + .start_abs_pa = addr_map_mc4_base_r(), + .end_abs_pa = addr_map_mc4_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc5_base_r(), + .end_pa = addr_map_mc5_limit_r(), + .start_abs_pa = addr_map_mc5_base_r(), + .end_abs_pa = addr_map_mc5_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + }, + { + .start_pa = addr_map_mc6_base_r(), + .end_pa = addr_map_mc6_limit_r(), + .start_abs_pa = addr_map_mc6_base_r(), + .end_abs_pa = addr_map_mc6_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc7_base_r(), + .end_pa = addr_map_mc7_limit_r(), + .start_abs_pa = addr_map_mc7_base_r(), + .end_abs_pa = addr_map_mc7_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to7_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc8_base_r(), + .end_pa = addr_map_mc8_limit_r(), + .start_abs_pa = addr_map_mc8_base_r(), + .end_abs_pa = addr_map_mc8_limit_r(), + .fake_registers = NULL, + .alist = t234_mc8_res_mss_iso_niso_hub_alist, + .alist_size = ARRAY_SIZE(t234_mc8_res_mss_iso_niso_hub_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSHUB0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSHUB0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSHUB0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSHUB1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSHUB1_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSHUB1_PERFMON_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_mss_mcf_map[] = { + { + .start_pa = addr_map_mc0_base_r(), + .end_pa = addr_map_mc0_limit_r(), + .start_abs_pa = addr_map_mc0_base_r(), + .end_abs_pa = addr_map_mc0_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to1_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc0to1_mss_mcf_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc1_base_r(), + .end_pa = addr_map_mc1_limit_r(), + .start_abs_pa = addr_map_mc1_base_r(), + .end_abs_pa = addr_map_mc1_limit_r(), + .fake_registers = NULL, + .alist = t234_mc0to1_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc0to1_mss_mcf_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc2_base_r(), + .end_pa = addr_map_mc2_limit_r(), + .start_abs_pa = addr_map_mc2_base_r(), + .end_abs_pa = addr_map_mc2_limit_r(), + .fake_registers = NULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc3_base_r(), + .end_pa = addr_map_mc3_limit_r(), + .start_abs_pa = addr_map_mc3_base_r(), + .end_abs_pa = addr_map_mc3_limit_r(), + .fake_registers = NULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc4_base_r(), + .end_pa = addr_map_mc4_limit_r(), + .start_abs_pa = addr_map_mc4_base_r(), + .end_abs_pa = addr_map_mc4_limit_r(), + .fake_registers = NULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc5_base_r(), + .end_pa = addr_map_mc5_limit_r(), + .start_abs_pa = addr_map_mc5_base_r(), + .end_abs_pa = addr_map_mc5_limit_r(), + .fake_registers = NULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc6_base_r(), + .end_pa = addr_map_mc6_limit_r(), + .start_abs_pa = addr_map_mc6_base_r(), + .end_abs_pa = addr_map_mc6_limit_r(), + .fake_registers = NULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mc7_base_r(), + .end_pa = addr_map_mc7_limit_r(), + .start_abs_pa = addr_map_mc7_base_r(), + .end_abs_pa = addr_map_mc7_limit_r(), + .fake_registers = NULL, + .alist = t234_mc2to7_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .fake_registers = NULL, + .alist = t234_mcb_mss_mcf_alist, + .alist_size = ARRAY_SIZE(t234_mcb_mss_mcf_alist), + .is_ip = true, + .dt_aperture = T234_SOC_HWPM_INVALID_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSMCFCLIENT0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSMCFCLIENT0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSMCFCLIENT0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSMCFMEM0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSMCFMEM0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSMCFMEM0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_MSSMCFMEM1_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_MSSMCFMEM1_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_MSSMCFMEM1_PERFMON_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_pma_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = PERFMON_BASE(T234_SOC_HWPM_SYS0_PERFMON_DT), + .end_abs_pa = PERFMON_LIMIT(T234_SOC_HWPM_SYS0_PERFMON_DT), + .fake_registers = NULL, + .alist = t234_perfmon_alist, + .alist_size = ARRAY_SIZE(t234_perfmon_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_SYS0_PERFMON_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = addr_map_pma_base_r(), + .end_abs_pa = addr_map_pma_limit_r(), + .fake_registers = NULL, + .alist = t234_pma_res_pma_alist, + .alist_size = ARRAY_SIZE(t234_pma_res_pma_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PMA_DT, + .index_mask = 0x1U, + }, +}; + +struct hwpm_resource_aperture t234_cmd_slice_rtr_map[] = { + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = addr_map_pma_base_r(), + .end_abs_pa = addr_map_pma_limit_r(), + .fake_registers = NULL, + .alist = t234_pma_res_cmd_slice_rtr_alist, + .alist_size = ARRAY_SIZE(t234_pma_res_cmd_slice_rtr_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_PMA_DT, + .index_mask = 0x1U, + }, + { + .start_pa = 0, + .end_pa = 0, + .start_abs_pa = addr_map_rtr_base_r(), + .end_abs_pa = addr_map_rtr_limit_r(), + .fake_registers = NULL, + .alist = t234_rtr_alist, + .alist_size = ARRAY_SIZE(t234_rtr_alist), + .is_ip = false, + .dt_aperture = T234_SOC_HWPM_RTR_DT, + .index_mask = 0x1U, + }, +}; + +#endif /* T234_SOC_HWPM_IP_MAP_H */ diff --git a/hal/t234/t234_soc_hwpm_mem_buf_utils.c b/hal/t234/t234_soc_hwpm_mem_buf_utils.c new file mode 100644 index 0000000..fb46804 --- /dev/null +++ b/hal/t234/t234_soc_hwpm_mem_buf_utils.c @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +int t234_soc_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm, + struct tegra_soc_hwpm_update_get_put *update_get_put) +{ + u32 *mem_bytes_kernel_u32 = NULL; + u32 reg_val = 0U; + u32 field_val = 0U; + int ret; + + + /* Update SW get pointer */ + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_mem_bump_r(0) - addr_map_pma_base_r(), + update_get_put->mem_bump); + + /* Stream MEM_BYTES value to MEM_BYTES buffer */ + if (update_get_put->b_stream_mem_bytes) { + mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_bytes_kernel); + *mem_bytes_kernel_u32 = TEGRA_SOC_HWPM_MEM_BYTES_INVALID; + ret = reg_rmw(hwpm, NULL, T234_SOC_HWPM_PMA_DT, + pmasys_channel_control_user_r(0) - addr_map_pma_base_r(), + pmasys_channel_control_user_update_bytes_m(), + pmasys_channel_control_user_update_bytes_doit_f(), + false, false); + if (ret < 0) { + tegra_soc_hwpm_err("Failed to stream mem_bytes to buffer"); + return -EIO; + } + } + + /* Read HW put pointer */ + if (update_get_put->b_read_mem_head) { + update_get_put->mem_head = hwpm_readl(hwpm, + T234_SOC_HWPM_PMA_DT, + pmasys_channel_mem_head_r(0) - addr_map_pma_base_r()); + tegra_soc_hwpm_dbg("MEM_HEAD = 0x%llx", + update_get_put->mem_head); + } + + /* Check overflow error status */ + if (update_get_put->b_check_overflow) { + reg_val = hwpm_readl(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_status_secure_r(0) - + addr_map_pma_base_r()); + field_val = pmasys_channel_status_secure_membuf_status_v( + reg_val); + update_get_put->b_overflowed = (field_val == + pmasys_channel_status_secure_membuf_status_overflowed_v()); + tegra_soc_hwpm_dbg("OVERFLOWED = %u", + update_get_put->b_overflowed); + } + + return 0; +} + +int t234_soc_hwpm_clear_pipeline(struct tegra_soc_hwpm *hwpm) +{ + int err = 0; + int ret = 0; + bool timeout = false; + u32 *mem_bytes_kernel_u32 = NULL; + + /* Stream MEM_BYTES to clear pipeline */ + if (hwpm->mem_bytes_kernel) { + mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_bytes_kernel); + *mem_bytes_kernel_u32 = TEGRA_SOC_HWPM_MEM_BYTES_INVALID; + err = reg_rmw(hwpm, NULL, T234_SOC_HWPM_PMA_DT, + pmasys_channel_control_user_r(0) - addr_map_pma_base_r(), + pmasys_channel_control_user_update_bytes_m(), + pmasys_channel_control_user_update_bytes_doit_f(), + false, false); + RELEASE_FAIL("Unable to stream MEM_BYTES"); + timeout = HWPM_TIMEOUT(*mem_bytes_kernel_u32 != + TEGRA_SOC_HWPM_MEM_BYTES_INVALID, + "MEM_BYTES streaming"); + if (timeout && ret == 0) + ret = -EIO; + } + + /* Disable PMA streaming */ + err = reg_rmw(hwpm, NULL, T234_SOC_HWPM_PMA_DT, + pmasys_trigger_config_user_r(0) - addr_map_pma_base_r(), + pmasys_trigger_config_user_record_stream_m(), + pmasys_trigger_config_user_record_stream_disable_f(), + false, false); + RELEASE_FAIL("Unable to disable PMA streaming"); + + err = reg_rmw(hwpm, NULL, T234_SOC_HWPM_PMA_DT, + pmasys_channel_control_user_r(0) - addr_map_pma_base_r(), + pmasys_channel_control_user_stream_m(), + pmasys_channel_control_user_stream_disable_f(), + false, false); + RELEASE_FAIL("Unable to disable PMA streaming"); + + /* Memory Management */ + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_outbase_r(0) - addr_map_pma_base_r(), 0); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_outbaseupper_r(0) - addr_map_pma_base_r(), 0); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_outsize_r(0) - addr_map_pma_base_r(), 0); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_mem_bytes_addr_r(0) - addr_map_pma_base_r(), 0); + + if (hwpm->stream_sgt && (!IS_ERR(hwpm->stream_sgt))) { + dma_buf_unmap_attachment(hwpm->stream_attach, + hwpm->stream_sgt, + DMA_FROM_DEVICE); + } + hwpm->stream_sgt = NULL; + + if (hwpm->stream_attach && (!IS_ERR(hwpm->stream_attach))) { + dma_buf_detach(hwpm->stream_dma_buf, hwpm->stream_attach); + } + hwpm->stream_attach = NULL; + + if (hwpm->stream_dma_buf && (!IS_ERR(hwpm->stream_dma_buf))) { + dma_buf_put(hwpm->stream_dma_buf); + } + hwpm->stream_dma_buf = NULL; + + if (hwpm->mem_bytes_kernel) { + dma_buf_vunmap(hwpm->mem_bytes_dma_buf, + hwpm->mem_bytes_kernel); + hwpm->mem_bytes_kernel = NULL; + } + + if (hwpm->mem_bytes_sgt && (!IS_ERR(hwpm->mem_bytes_sgt))) { + dma_buf_unmap_attachment(hwpm->mem_bytes_attach, + hwpm->mem_bytes_sgt, + DMA_FROM_DEVICE); + } + hwpm->mem_bytes_sgt = NULL; + + if (hwpm->mem_bytes_attach && (!IS_ERR(hwpm->mem_bytes_attach))) { + dma_buf_detach(hwpm->mem_bytes_dma_buf, hwpm->mem_bytes_attach); + } + hwpm->mem_bytes_attach = NULL; + + if (hwpm->mem_bytes_dma_buf && (!IS_ERR(hwpm->mem_bytes_dma_buf))) { + dma_buf_put(hwpm->mem_bytes_dma_buf); + } + hwpm->mem_bytes_dma_buf = NULL; + + return ret; +} + +int t234_soc_hwpm_stream_buf_map(struct tegra_soc_hwpm *hwpm, + struct tegra_soc_hwpm_alloc_pma_stream *alloc_pma_stream) +{ + int ret = 0; + u32 reg_val = 0; + u32 outbase_lo = 0; + u32 outbase_hi = 0; + u32 outsize = 0; + u32 mem_bytes_addr = 0; + + /* Memory map stream buffer */ + hwpm->stream_dma_buf = dma_buf_get(alloc_pma_stream->stream_buf_fd); + if (IS_ERR(hwpm->stream_dma_buf)) { + tegra_soc_hwpm_err("Unable to get stream dma_buf"); + ret = PTR_ERR(hwpm->stream_dma_buf); + goto fail; + } + hwpm->stream_attach = dma_buf_attach(hwpm->stream_dma_buf, hwpm->dev); + if (IS_ERR(hwpm->stream_attach)) { + tegra_soc_hwpm_err("Unable to attach stream dma_buf"); + ret = PTR_ERR(hwpm->stream_attach); + goto fail; + } + hwpm->stream_sgt = dma_buf_map_attachment(hwpm->stream_attach, + DMA_FROM_DEVICE); + if (IS_ERR(hwpm->stream_sgt)) { + tegra_soc_hwpm_err("Unable to map stream attachment"); + ret = PTR_ERR(hwpm->stream_sgt); + goto fail; + } + alloc_pma_stream->stream_buf_pma_va = + sg_dma_address(hwpm->stream_sgt->sgl); + if (alloc_pma_stream->stream_buf_pma_va == 0) { + tegra_soc_hwpm_err("Invalid stream buffer SMMU IOVA"); + ret = -ENXIO; + goto fail; + } + tegra_soc_hwpm_dbg("stream_buf_pma_va = 0x%llx", + alloc_pma_stream->stream_buf_pma_va); + + /* Memory map mem bytes buffer */ + hwpm->mem_bytes_dma_buf = + dma_buf_get(alloc_pma_stream->mem_bytes_buf_fd); + if (IS_ERR(hwpm->mem_bytes_dma_buf)) { + tegra_soc_hwpm_err("Unable to get mem bytes dma_buf"); + ret = PTR_ERR(hwpm->mem_bytes_dma_buf); + goto fail; + } + hwpm->mem_bytes_attach = dma_buf_attach(hwpm->mem_bytes_dma_buf, + hwpm->dev); + if (IS_ERR(hwpm->mem_bytes_attach)) { + tegra_soc_hwpm_err("Unable to attach mem bytes dma_buf"); + ret = PTR_ERR(hwpm->mem_bytes_attach); + goto fail; + } + hwpm->mem_bytes_sgt = dma_buf_map_attachment(hwpm->mem_bytes_attach, + DMA_FROM_DEVICE); + if (IS_ERR(hwpm->mem_bytes_sgt)) { + tegra_soc_hwpm_err("Unable to map mem bytes attachment"); + ret = PTR_ERR(hwpm->mem_bytes_sgt); + goto fail; + } + hwpm->mem_bytes_kernel = dma_buf_vmap(hwpm->mem_bytes_dma_buf); + if (!hwpm->mem_bytes_kernel) { + tegra_soc_hwpm_err( + "Unable to map mem_bytes buffer into kernel VA space"); + ret = -ENOMEM; + goto fail; + } + memset(hwpm->mem_bytes_kernel, 0, 32); + + outbase_lo = alloc_pma_stream->stream_buf_pma_va & + pmasys_channel_outbase_ptr_m(); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_outbase_r(0) - addr_map_pma_base_r(), + outbase_lo); + tegra_soc_hwpm_dbg("OUTBASE = 0x%x", reg_val); + + outbase_hi = (alloc_pma_stream->stream_buf_pma_va >> 32) & + pmasys_channel_outbaseupper_ptr_m(); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_outbaseupper_r(0) - addr_map_pma_base_r(), + outbase_hi); + tegra_soc_hwpm_dbg("OUTBASEUPPER = 0x%x", reg_val); + + outsize = alloc_pma_stream->stream_buf_size & + pmasys_channel_outsize_numbytes_m(); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_outsize_r(0) - addr_map_pma_base_r(), + outsize); + tegra_soc_hwpm_dbg("OUTSIZE = 0x%x", reg_val); + + mem_bytes_addr = sg_dma_address(hwpm->mem_bytes_sgt->sgl) & + pmasys_channel_mem_bytes_addr_ptr_m(); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_mem_bytes_addr_r(0) - addr_map_pma_base_r(), + mem_bytes_addr); + tegra_soc_hwpm_dbg("MEM_BYTES_ADDR = 0x%x", reg_val); + + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_mem_block_r(0) - addr_map_pma_base_r(), + pmasys_channel_mem_block_valid_f( + pmasys_channel_mem_block_valid_true_v())); + + return 0; + +fail: + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_mem_block_r(0) - addr_map_pma_base_r(), + pmasys_channel_mem_block_valid_f( + pmasys_channel_mem_block_valid_false_v())); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_outbase_r(0) - addr_map_pma_base_r(), 0); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_outbaseupper_r(0) - addr_map_pma_base_r(), 0); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_outsize_r(0) - addr_map_pma_base_r(), 0); + hwpm_writel(hwpm, T234_SOC_HWPM_PMA_DT, + pmasys_channel_mem_bytes_addr_r(0) - addr_map_pma_base_r(), 0); + + alloc_pma_stream->stream_buf_pma_va = 0; + + if (hwpm->stream_sgt && (!IS_ERR(hwpm->stream_sgt))) { + dma_buf_unmap_attachment(hwpm->stream_attach, + hwpm->stream_sgt, + DMA_FROM_DEVICE); + } + hwpm->stream_sgt = NULL; + + if (hwpm->stream_attach && (!IS_ERR(hwpm->stream_attach))) { + dma_buf_detach(hwpm->stream_dma_buf, hwpm->stream_attach); + } + hwpm->stream_attach = NULL; + + if (hwpm->stream_dma_buf && (!IS_ERR(hwpm->stream_dma_buf))) { + dma_buf_put(hwpm->stream_dma_buf); + } + hwpm->stream_dma_buf = NULL; + + if (hwpm->mem_bytes_kernel) { + dma_buf_vunmap(hwpm->mem_bytes_dma_buf, + hwpm->mem_bytes_kernel); + hwpm->mem_bytes_kernel = NULL; + } + if (hwpm->mem_bytes_sgt && (!IS_ERR(hwpm->mem_bytes_sgt))) { + dma_buf_unmap_attachment(hwpm->mem_bytes_attach, + hwpm->mem_bytes_sgt, + DMA_FROM_DEVICE); + } + hwpm->mem_bytes_sgt = NULL; + + if (hwpm->mem_bytes_attach && (!IS_ERR(hwpm->mem_bytes_attach))) { + dma_buf_detach(hwpm->mem_bytes_dma_buf, hwpm->mem_bytes_attach); + } + hwpm->mem_bytes_attach = NULL; + + if (hwpm->mem_bytes_dma_buf && (!IS_ERR(hwpm->mem_bytes_dma_buf))) { + dma_buf_put(hwpm->mem_bytes_dma_buf); + } + hwpm->mem_bytes_dma_buf = NULL; + + return ret; +} diff --git a/hal/t234/t234_soc_hwpm_perfmon_dt.h b/hal/t234/t234_soc_hwpm_perfmon_dt.h new file mode 100644 index 0000000..e727245 --- /dev/null +++ b/hal/t234/t234_soc_hwpm_perfmon_dt.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * This header contains HW aperture and register info for the Tegra SOC HWPM + * driver. + */ + +#ifndef T234_SOC_HWPM_PERFMON_DT_H +#define T234_SOC_HWPM_PERFMON_DT_H + +#include + +#include +#include +#include + +enum t234_soc_hwpm_dt_aperture { + T234_SOC_HWPM_INVALID_DT = -1, + + /* PERFMONs */ + T234_SOC_HWPM_FIRST_PERFMON_DT = 0, + T234_SOC_HWPM_VI0_PERFMON_DT = T234_SOC_HWPM_FIRST_PERFMON_DT, + T234_SOC_HWPM_VI1_PERFMON_DT = T234_SOC_HWPM_FIRST_PERFMON_DT + 1, + T234_SOC_HWPM_ISP0_PERFMON_DT, + T234_SOC_HWPM_VICA0_PERFMON_DT, + T234_SOC_HWPM_OFAA0_PERFMON_DT, + T234_SOC_HWPM_PVAV0_PERFMON_DT, + T234_SOC_HWPM_PVAV1_PERFMON_DT, + T234_SOC_HWPM_PVAC0_PERFMON_DT, + T234_SOC_HWPM_NVDLAB0_PERFMON_DT, + T234_SOC_HWPM_NVDLAB1_PERFMON_DT, + T234_SOC_HWPM_NVDISPLAY0_PERFMON_DT, + T234_SOC_HWPM_SYS0_PERFMON_DT, + T234_SOC_HWPM_MGBE0_PERFMON_DT, + T234_SOC_HWPM_MGBE1_PERFMON_DT, + T234_SOC_HWPM_MGBE2_PERFMON_DT, + T234_SOC_HWPM_MGBE3_PERFMON_DT, + T234_SOC_HWPM_SCF0_PERFMON_DT, + T234_SOC_HWPM_NVDECA0_PERFMON_DT, + T234_SOC_HWPM_NVENCA0_PERFMON_DT, + T234_SOC_HWPM_MSSNVLHSH0_PERFMON_DT, + T234_SOC_HWPM_PCIE0_PERFMON_DT, + T234_SOC_HWPM_PCIE1_PERFMON_DT, + T234_SOC_HWPM_PCIE2_PERFMON_DT, + T234_SOC_HWPM_PCIE3_PERFMON_DT, + T234_SOC_HWPM_PCIE4_PERFMON_DT, + T234_SOC_HWPM_PCIE5_PERFMON_DT, + T234_SOC_HWPM_PCIE6_PERFMON_DT, + T234_SOC_HWPM_PCIE7_PERFMON_DT, + T234_SOC_HWPM_PCIE8_PERFMON_DT, + T234_SOC_HWPM_PCIE9_PERFMON_DT, + T234_SOC_HWPM_PCIE10_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT, + T234_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT, + T234_SOC_HWPM_MSSHUB0_PERFMON_DT, + T234_SOC_HWPM_MSSHUB1_PERFMON_DT, + T234_SOC_HWPM_MSSMCFCLIENT0_PERFMON_DT, + T234_SOC_HWPM_MSSMCFMEM0_PERFMON_DT, + T234_SOC_HWPM_MSSMCFMEM1_PERFMON_DT, + T234_SOC_HWPM_LAST_PERFMON_DT = T234_SOC_HWPM_MSSMCFMEM1_PERFMON_DT, + T234_SOC_HWPM_PMA_DT = T234_SOC_HWPM_LAST_PERFMON_DT + 1, + T234_SOC_HWPM_RTR_DT, + T234_SOC_HWPM_NUM_DT_APERTURES +}; +#define IS_PERFMON(idx) (((idx) >= T234_SOC_HWPM_FIRST_PERFMON_DT) && \ + ((idx) <= T234_SOC_HWPM_LAST_PERFMON_DT)) + +/* RPG_PM Aperture */ +#define PERFMON_BASE(ip_idx) (addr_map_rpg_pm_base_r() + \ + ((u32)(ip_idx)) * pmmsys_perdomain_offset_v()) +#define PERFMON_LIMIT(ip_idx) (PERFMON_BASE((ip_idx) + 1) - 1) + +#endif /* T234_SOC_HWPM_PERFMON_DT_H */ diff --git a/include/regops/t234/reg_allowlist.h b/hal/t234/t234_soc_hwpm_regops_allowlist.h similarity index 86% rename from include/regops/t234/reg_allowlist.h rename to hal/t234/t234_soc_hwpm_regops_allowlist.h index e31256c..46376b9 100644 --- a/include/regops/t234/reg_allowlist.h +++ b/hal/t234/t234_soc_hwpm_regops_allowlist.h @@ -22,15 +22,15 @@ * This file is autogenerated. Do not edit. */ -#ifndef SOC_HWPM_REGOPS_ALLOWLIST_H -#define SOC_HWPM_REGOPS_ALLOWLIST_H +#ifndef T234_SOC_HWPM_REGOPS_ALLOWLIST_H +#define T234_SOC_HWPM_REGOPS_ALLOWLIST_H struct allowlist { u64 reg_offset; bool zero_at_init; }; -struct allowlist perfmon_alist[] = { +struct allowlist t234_perfmon_alist[] = { {0x00000000, true}, {0x00000004, true}, {0x00000008, true}, @@ -100,7 +100,7 @@ struct allowlist perfmon_alist[] = { {0x00000130, true}, }; -struct allowlist pma_res_cmd_slice_rtr_alist[] = { +struct allowlist t234_pma_res_cmd_slice_rtr_alist[] = { {0x00000000, false}, {0x00000008, false}, {0x0000000c, false}, @@ -189,11 +189,11 @@ struct allowlist pma_res_cmd_slice_rtr_alist[] = { {0x0000075c, false}, }; -struct allowlist pma_res_pma_alist[] = { +struct allowlist t234_pma_res_pma_alist[] = { {0x00000628, true}, }; -struct allowlist rtr_alist[] = { +struct allowlist t234_rtr_alist[] = { {0x00000000, false}, {0x00000008, false}, {0x0000000c, false}, @@ -204,7 +204,7 @@ struct allowlist rtr_alist[] = { {0x00000154, false}, }; -struct allowlist vi_thi_alist[] = { +struct allowlist t234_vi_thi_alist[] = { {0x0000e800, false}, {0x0000e804, false}, {0x0000e808, true}, @@ -214,7 +214,7 @@ struct allowlist vi_thi_alist[] = { {0x0000e818, true}, }; -struct allowlist isp_thi_alist[] = { +struct allowlist t234_isp_thi_alist[] = { {0x000091c0, false}, {0x000091c4, false}, {0x000091c8, true}, @@ -224,7 +224,7 @@ struct allowlist isp_thi_alist[] = { {0x000091d8, true}, }; -struct allowlist vic_alist[] = { +struct allowlist t234_vic_alist[] = { {0x00001088, false}, {0x000010a8, false}, {0x00001c00, true}, @@ -236,7 +236,7 @@ struct allowlist vic_alist[] = { {0x00001c18, false}, }; -struct allowlist ofa_alist[] = { +struct allowlist t234_ofa_alist[] = { {0x00001088, false}, {0x000010a8, false}, {0x00003308, true}, @@ -247,7 +247,7 @@ struct allowlist ofa_alist[] = { {0x0000331c, false}, }; -struct allowlist pva0_pm_alist[] = { +struct allowlist t234_pva0_pm_alist[] = { {0x00008000, false}, {0x00008004, false}, {0x00008008, false}, @@ -259,7 +259,7 @@ struct allowlist pva0_pm_alist[] = { {0x00008020, true}, }; -struct allowlist nvdla_alist[] = { +struct allowlist t234_nvdla_alist[] = { {0x00001088, false}, {0x000010a8, false}, {0x0001a000, false}, @@ -296,12 +296,12 @@ struct allowlist nvdla_alist[] = { {0x0001a07c, true}, }; -struct allowlist mgbe_alist[] = { +struct allowlist t234_mgbe_alist[] = { {0x00008020, true}, {0x00008024, false}, }; -struct allowlist nvdec_alist[] = { +struct allowlist t234_nvdec_alist[] = { {0x00001088, false}, {0x000010a8, false}, {0x00001b48, false}, @@ -312,7 +312,7 @@ struct allowlist nvdec_alist[] = { {0x00001b5c, true}, }; -struct allowlist nvenc_alist[] = { +struct allowlist t234_nvenc_alist[] = { {0x00001088, false}, {0x000010a8, false}, {0x00002134, true}, @@ -324,50 +324,50 @@ struct allowlist nvenc_alist[] = { {0x00002130, false}, }; -struct allowlist pcie_ctl_alist[] = { +struct allowlist t234_pcie_ctl_alist[] = { {0x00000174, true}, {0x00000178, false}, }; -struct allowlist disp_alist[] = { +struct allowlist t234_disp_alist[] = { {0x0001e118, true}, {0x0001e120, true}, {0x0001e124, false}, }; -struct allowlist mss_channel_alist[] = { +struct allowlist t234_mss_channel_alist[] = { {0x00000814, true}, {0x0000082c, true}, }; -struct allowlist mss_nvlink_alist[] = { +struct allowlist t234_mss_nvlink_alist[] = { {0x00000a30, true}, }; -struct allowlist mc0to7_res_mss_iso_niso_hub_alist[] = { +struct allowlist t234_mc0to7_res_mss_iso_niso_hub_alist[] = { {0x00000818, true}, {0x0000081c, true}, }; -struct allowlist mc8_res_mss_iso_niso_hub_alist[] = { +struct allowlist t234_mc8_res_mss_iso_niso_hub_alist[] = { {0x00000828, true}, }; -struct allowlist mcb_mss_mcf_alist[] = { +struct allowlist t234_mcb_mss_mcf_alist[] = { {0x00000800, true}, {0x00000820, true}, {0x0000080c, true}, {0x00000824, true}, }; -struct allowlist mc0to1_mss_mcf_alist[] = { +struct allowlist t234_mc0to1_mss_mcf_alist[] = { {0x00000808, true}, {0x00000804, true}, {0x00000810, true}, }; -struct allowlist mc2to7_mss_mcf_alist[] = { +struct allowlist t234_mc2to7_mss_mcf_alist[] = { {0x00000810, true}, }; -#endif /* SOC_HWPM_REGOPS_ALLOWLIST_H */ +#endif /* T234_SOC_HWPM_REGOPS_ALLOWLIST_H */ diff --git a/hal/t234/t234_soc_hwpm_resource_utils.c b/hal/t234/t234_soc_hwpm_resource_utils.c new file mode 100644 index 0000000..df5a692 --- /dev/null +++ b/hal/t234/t234_soc_hwpm_resource_utils.c @@ -0,0 +1,531 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +/* + * Normally there is a 1-to-1 mapping between an MMIO aperture and a + * hwpm_resource_aperture struct. But MC MMIO apertures are used in multiple + * hwpm_resource_aperture structs. Therefore, we have to share the fake register + * arrays between these hwpm_resource_aperture structs. This is why we have to + * define the fake register arrays globally. For all other 1-to-1 mapping + * apertures the fake register arrays are directly embedded inside the + * hwpm_resource_aperture structs. + */ +u32 *t234_mc_fake_regs[16] = {NULL}; + +bool t234_soc_hwpm_is_dt_aperture_reserved(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture, u32 rsrc_id) +{ + return ((aperture->dt_aperture == T234_SOC_HWPM_PMA_DT) || + (aperture->dt_aperture == T234_SOC_HWPM_RTR_DT) || + (aperture->dt_aperture == T234_SOC_HWPM_SYS0_PERFMON_DT) || + ((aperture->index_mask & hwpm->ip_fs_info[rsrc_id]) != 0)); +} + +u32 **t234_soc_hwpm_get_mc_fake_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture) +{ + if (!hwpm->fake_registers_enabled) + return NULL; + if (!aperture) { + tegra_soc_hwpm_err("aperture is NULL"); + return NULL; + } + + switch (aperture->start_pa) { + case addr_map_mc0_base_r(): + return &t234_mc_fake_regs[0]; + case addr_map_mc1_base_r(): + return &t234_mc_fake_regs[1]; + case addr_map_mc2_base_r(): + return &t234_mc_fake_regs[2]; + case addr_map_mc3_base_r(): + return &t234_mc_fake_regs[3]; + case addr_map_mc4_base_r(): + return &t234_mc_fake_regs[4]; + case addr_map_mc5_base_r(): + return &t234_mc_fake_regs[5]; + case addr_map_mc6_base_r(): + return &t234_mc_fake_regs[6]; + case addr_map_mc7_base_r(): + return &t234_mc_fake_regs[7]; + case addr_map_mc8_base_r(): + return &t234_mc_fake_regs[8]; + case addr_map_mc9_base_r(): + return &t234_mc_fake_regs[9]; + case addr_map_mc10_base_r(): + return &t234_mc_fake_regs[10]; + case addr_map_mc11_base_r(): + return &t234_mc_fake_regs[11]; + case addr_map_mc12_base_r(): + return &t234_mc_fake_regs[12]; + case addr_map_mc13_base_r(): + return &t234_mc_fake_regs[13]; + case addr_map_mc14_base_r(): + return &t234_mc_fake_regs[14]; + case addr_map_mc15_base_r(): + return &t234_mc_fake_regs[15]; + default: + return NULL; + } +} + +void t234_soc_hwpm_set_mc_fake_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture, + bool set_null) +{ + u32 *fake_regs = NULL; + + /* Get pointer to array of MSS channel apertures */ + struct hwpm_resource_aperture *l_mss_channel_map = + hwpm->hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL].map; + /* Get pointer to array of MSS ISO/NISO hub apertures */ + struct hwpm_resource_aperture *l_mss_iso_niso_map = + hwpm->hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_MSS_ISO_NISO_HUBS].map; + /* Get pointer to array of MSS MCF apertures */ + struct hwpm_resource_aperture *l_mss_mcf_map = + hwpm->hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_MSS_MCF].map; + + if (!aperture) { + tegra_soc_hwpm_err("aperture is NULL"); + return; + } + + switch (aperture->start_pa) { + case addr_map_mc0_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[0]; + l_mss_channel_map[0].fake_registers = fake_regs; + l_mss_iso_niso_map[0].fake_registers = fake_regs; + l_mss_mcf_map[0].fake_registers = fake_regs; + break; + case addr_map_mc1_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[1]; + l_mss_channel_map[1].fake_registers = fake_regs; + l_mss_iso_niso_map[1].fake_registers = fake_regs; + l_mss_mcf_map[1].fake_registers = fake_regs; + break; + case addr_map_mc2_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[2]; + l_mss_channel_map[2].fake_registers = fake_regs; + l_mss_iso_niso_map[2].fake_registers = fake_regs; + l_mss_mcf_map[2].fake_registers = fake_regs; + break; + case addr_map_mc3_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[3]; + l_mss_channel_map[3].fake_registers = fake_regs; + l_mss_iso_niso_map[3].fake_registers = fake_regs; + l_mss_mcf_map[3].fake_registers = fake_regs; + break; + case addr_map_mc4_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[4]; + l_mss_channel_map[4].fake_registers = fake_regs; + l_mss_iso_niso_map[4].fake_registers = fake_regs; + l_mss_mcf_map[4].fake_registers = fake_regs; + break; + case addr_map_mc5_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[5]; + l_mss_channel_map[5].fake_registers = fake_regs; + l_mss_iso_niso_map[5].fake_registers = fake_regs; + l_mss_mcf_map[5].fake_registers = fake_regs; + break; + case addr_map_mc6_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[6]; + l_mss_channel_map[6].fake_registers = fake_regs; + l_mss_iso_niso_map[6].fake_registers = fake_regs; + l_mss_mcf_map[6].fake_registers = fake_regs; + break; + case addr_map_mc7_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[7]; + l_mss_channel_map[7].fake_registers = fake_regs; + l_mss_iso_niso_map[7].fake_registers = fake_regs; + l_mss_mcf_map[7].fake_registers = fake_regs; + break; + case addr_map_mc8_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[8]; + l_mss_channel_map[8].fake_registers = fake_regs; + l_mss_iso_niso_map[8].fake_registers = fake_regs; + break; + case addr_map_mc9_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[9]; + l_mss_channel_map[9].fake_registers = fake_regs; + break; + case addr_map_mc10_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[10]; + l_mss_channel_map[10].fake_registers = fake_regs; + break; + case addr_map_mc11_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[11]; + l_mss_channel_map[11].fake_registers = fake_regs; + break; + case addr_map_mc12_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[12]; + l_mss_channel_map[12].fake_registers = fake_regs; + break; + case addr_map_mc13_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[13]; + l_mss_channel_map[13].fake_registers = fake_regs; + break; + case addr_map_mc14_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[14]; + l_mss_channel_map[14].fake_registers = fake_regs; + break; + case addr_map_mc15_base_r(): + fake_regs = (!hwpm->fake_registers_enabled || set_null) ? + NULL : t234_mc_fake_regs[15]; + l_mss_channel_map[15].fake_registers = fake_regs; + break; + default: + break; + } +} + +int t234_soc_hwpm_reserve_given_resource(struct tegra_soc_hwpm *hwpm, u32 resource) +{ + struct hwpm_resource_aperture *aperture = NULL; + int aprt_idx = 0; + int ret = 0, err; + struct tegra_soc_hwpm_ip_ops *ip_ops; + + /* Map reserved apertures and allocate fake register arrays if needed */ + for (aprt_idx = 0; + aprt_idx < hwpm->hwpm_resources[resource].map_size; + aprt_idx++) { + aperture = &(hwpm->hwpm_resources[resource].map[aprt_idx]); + if ((aperture->dt_aperture == T234_SOC_HWPM_PMA_DT) || + (aperture->dt_aperture == T234_SOC_HWPM_RTR_DT)) { + /* PMA and RTR apertures are handled in open(fd) */ + continue; + } else if (t234_soc_hwpm_is_dt_aperture_reserved(hwpm, + aperture, resource)) { + if (t234_soc_hwpm_is_perfmon(aperture->dt_aperture)) { + struct resource *res = NULL; + u64 num_regs = 0; + + tegra_soc_hwpm_dbg("Found PERFMON(0x%llx - 0x%llx)", + aperture->start_pa, aperture->end_pa); + ip_ops = &hwpm->ip_info[aperture->dt_aperture]; + if (ip_ops && (*ip_ops->hwpm_ip_pm)) { + err = (*ip_ops->hwpm_ip_pm) + (ip_ops->ip_dev, true); + if (err) { + tegra_soc_hwpm_err( + "Disable Runtime PM(%d) Failed", + aperture->dt_aperture); + } + } else { + tegra_soc_hwpm_dbg( + "No Runtime PM(%d) for IP", + aperture->dt_aperture); + } + hwpm->dt_apertures[aperture->dt_aperture] = + of_iomap(hwpm->np, aperture->dt_aperture); + if (!hwpm->dt_apertures[aperture->dt_aperture]) { + tegra_soc_hwpm_err("Couldn't map PERFMON(%d)", + aperture->dt_aperture); + ret = -ENOMEM; + goto fail; + } + + res = platform_get_resource(hwpm->pdev, + IORESOURCE_MEM, + aperture->dt_aperture); + if ((!res) || (res->start == 0) || (res->end == 0)) { + tegra_soc_hwpm_err("Invalid resource for PERFMON(%d)", + aperture->dt_aperture); + ret = -ENOMEM; + goto fail; + } + aperture->start_pa = res->start; + aperture->end_pa = res->end; + + if (hwpm->fake_registers_enabled) { + num_regs = (aperture->end_pa + 1 - aperture->start_pa) / + sizeof(*aperture->fake_registers); + aperture->fake_registers = + (u32 *)kzalloc(sizeof(*aperture->fake_registers) * + num_regs, + GFP_KERNEL); + if (!aperture->fake_registers) { + tegra_soc_hwpm_err("Aperture(0x%llx - 0x%llx):" + " Couldn't allocate memory for fake" + " registers", + aperture->start_pa, + aperture->end_pa); + ret = -ENOMEM; + goto fail; + } + } + } else { /* IP apertures */ + if (hwpm->fake_registers_enabled) { + u64 num_regs = 0; + u32 **fake_regs = + t234_soc_hwpm_get_mc_fake_regs(hwpm, aperture); + + if (!fake_regs) + fake_regs = &aperture->fake_registers; + + num_regs = (aperture->end_pa + 1 - aperture->start_pa) / + sizeof(*(*fake_regs)); + *fake_regs = + (u32 *)kzalloc(sizeof(*(*fake_regs)) * num_regs, + GFP_KERNEL); + if (!(*fake_regs)) { + tegra_soc_hwpm_err("Aperture(0x%llx - 0x%llx):" + " Couldn't allocate memory for fake" + " registers", + aperture->start_pa, + aperture->end_pa); + ret = -ENOMEM; + goto fail; + } + + t234_soc_hwpm_set_mc_fake_regs(hwpm, aperture, false); + } + } + } else { + tegra_soc_hwpm_dbg("resource %d index_mask %d not available", + resource, aperture->index_mask); + } + } + + hwpm->hwpm_resources[resource].reserved = true; + goto success; + +fail: + for (aprt_idx = 0; + aprt_idx < hwpm->hwpm_resources[resource].map_size; + aprt_idx++) { + aperture = &(hwpm->hwpm_resources[resource].map[aprt_idx]); + if ((aperture->dt_aperture == T234_SOC_HWPM_PMA_DT) || + (aperture->dt_aperture == T234_SOC_HWPM_RTR_DT)) { + /* PMA and RTR apertures are handled in open(fd) */ + continue; + } else if (t234_soc_hwpm_is_dt_aperture_reserved(hwpm, + aperture, resource)) { + if (t234_soc_hwpm_is_perfmon(aperture->dt_aperture)) { + if (hwpm->dt_apertures[aperture->dt_aperture]) { + iounmap(hwpm->dt_apertures[aperture->dt_aperture]); + hwpm->dt_apertures[aperture->dt_aperture] = NULL; + } + + aperture->start_pa = 0; + aperture->end_pa = 0; + + if (aperture->fake_registers) { + kfree(aperture->fake_registers); + aperture->fake_registers = NULL; + } + } else { /* IP apertures */ + if (aperture->fake_registers) { + kfree(aperture->fake_registers); + aperture->fake_registers = NULL; + t234_soc_hwpm_set_mc_fake_regs(hwpm, aperture, true); + } + } + } + } + + hwpm->hwpm_resources[resource].reserved = false; + +success: + return ret; +} + +void t234_soc_hwpm_reset_resources(struct tegra_soc_hwpm *hwpm) +{ + int res_idx = 0; + int aprt_idx = 0; + struct hwpm_resource_aperture *aperture = NULL; + + /* Reset resource and aperture state */ + for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { + if (!hwpm->hwpm_resources[res_idx].reserved) + continue; + hwpm->hwpm_resources[res_idx].reserved = false; + + for (aprt_idx = 0; + aprt_idx < hwpm->hwpm_resources[res_idx].map_size; + aprt_idx++) { + aperture = &(hwpm->hwpm_resources[res_idx].map[aprt_idx]); + if ((aperture->dt_aperture == T234_SOC_HWPM_PMA_DT) || + (aperture->dt_aperture == T234_SOC_HWPM_RTR_DT)) { + /* PMA and RTR apertures are handled separately */ + continue; + } else if (t234_soc_hwpm_is_perfmon(aperture->dt_aperture)) { + if (hwpm->dt_apertures[aperture->dt_aperture]) { + iounmap(hwpm->dt_apertures[aperture->dt_aperture]); + hwpm->dt_apertures[aperture->dt_aperture] = NULL; + } + + aperture->start_pa = 0; + aperture->end_pa = 0; + + if (aperture->fake_registers) { + kfree(aperture->fake_registers); + aperture->fake_registers = NULL; + } + } else { /* IP apertures */ + if (aperture->fake_registers) { + kfree(aperture->fake_registers); + aperture->fake_registers = NULL; + t234_soc_hwpm_set_mc_fake_regs(hwpm, aperture, true); + } + } + } + } +} + +void t234_soc_hwpm_disable_perfmons(struct tegra_soc_hwpm *hwpm) +{ + int res_idx = 0; + int aprt_idx = 0; + struct hwpm_resource_aperture *aperture = NULL; + struct tegra_soc_hwpm_ip_ops *ip_ops; + int err, ret = 0; + + for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { + if (!hwpm->hwpm_resources[res_idx].reserved) + continue; + tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx); + + for (aprt_idx = 0; + aprt_idx < hwpm->hwpm_resources[res_idx].map_size; + aprt_idx++) { + aperture = &(hwpm->hwpm_resources[res_idx].map[aprt_idx]); + if (t234_soc_hwpm_is_perfmon(aperture->dt_aperture)) { + if (t234_soc_hwpm_is_dt_aperture_reserved(hwpm, + aperture, res_idx)) { + tegra_soc_hwpm_dbg("Found PERFMON(0x%llx - 0x%llx)", + aperture->start_pa, + aperture->end_pa); + err = reg_rmw(hwpm, NULL, aperture->dt_aperture, + pmmsys_control_r(0) - addr_map_rpg_pm_base_r(), + pmmsys_control_mode_m(), + pmmsys_control_mode_disable_f(), + false, false); + RELEASE_FAIL("Unable to disable PERFMON(0x%llx - 0x%llx)", + aperture->start_pa, + aperture->end_pa); + ip_ops = &hwpm->ip_info[aperture->dt_aperture]; + if (ip_ops && (*ip_ops->hwpm_ip_pm)) { + err = (*ip_ops->hwpm_ip_pm) + (ip_ops->ip_dev, false); + if (err) { + tegra_soc_hwpm_err( + "Enable Runtime PM(%d) Failed", + aperture->dt_aperture); + } + } else { + tegra_soc_hwpm_dbg( + "No Runtime PM(%d) for IP", + aperture->dt_aperture); + } + } + } + } + } +} + +int t234_soc_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm) +{ + int ret = 0; + int res_idx = 0; + int aprt_idx = 0; + struct hwpm_resource_aperture *aperture = NULL; + + for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { + if (!hwpm->hwpm_resources[res_idx].reserved) + continue; + tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx); + + for (aprt_idx = 0; + aprt_idx < hwpm->hwpm_resources[res_idx].map_size; + aprt_idx++) { + aperture = &(hwpm->hwpm_resources[res_idx].map[aprt_idx]); + + if (t234_soc_hwpm_is_dt_aperture_reserved(hwpm, + aperture, res_idx)) { + + /* Zero out necessary registers */ + if (aperture->alist) { + t234_soc_hwpm_zero_alist_regs(hwpm, aperture); + } else { + tegra_soc_hwpm_err( + "NULL allowlist in aperture(0x%llx - 0x%llx)", + aperture->start_pa, aperture->end_pa); + } + + /* + * Enable reporting of PERFMON status to + * NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED + */ + if (t234_soc_hwpm_is_perfmon(aperture->dt_aperture)) { + tegra_soc_hwpm_dbg("Found PERFMON(0x%llx - 0x%llx)", + aperture->start_pa, + aperture->end_pa); + ret = reg_rmw(hwpm, NULL, aperture->dt_aperture, + pmmsys_sys0_enginestatus_r(0) - + addr_map_rpg_pm_base_r(), + pmmsys_sys0_enginestatus_enable_m(), + pmmsys_sys0_enginestatus_enable_out_f(), + false, false); + if (ret < 0) { + tegra_soc_hwpm_err( + "Unable to set PMM ENGINESTATUS_ENABLE" + " for PERFMON(0x%llx - 0x%llx)", + aperture->start_pa, + aperture->end_pa); + return -EIO; + } + } + } + } + } + return 0; +} diff --git a/hal/tegra-soc-hwpm-structures.h b/hal/tegra-soc-hwpm-structures.h new file mode 100644 index 0000000..00bd127 --- /dev/null +++ b/hal/tegra-soc-hwpm-structures.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef TEGRA_SOC_HWPM_STRUCTURES_H +#define TEGRA_SOC_HWPM_STRUCTURES_H + +#include +#include +#include +#include + +#include + +#define TEGRA_SOC_HWPM_DT_APERTURE_INVALID 100U + +#define RELEASE_FAIL(msg, ...) \ + do { \ + if (err < 0) { \ + tegra_soc_hwpm_err(msg, ##__VA_ARGS__); \ + if (ret == 0) \ + ret = err; \ + } \ + } while (0) + +/* FIXME: Default timeout is 1 sec. Is this sufficient for pre-si? */ +#define HWPM_TIMEOUT(timeout_check, expiry_msg) ({ \ + bool timeout_expired = false; \ + s32 timeout_msecs = 1000; \ + u32 sleep_msecs = 100; \ + while (!(timeout_check)) { \ + msleep(sleep_msecs); \ + timeout_msecs -= sleep_msecs; \ + if (timeout_msecs <= 0) { \ + tegra_soc_hwpm_err("Timeout expired for %s!", \ + expiry_msg); \ + timeout_expired = true; \ + break; \ + } \ + } \ + timeout_expired; \ +}) + +struct allowlist; +extern struct platform_device *tegra_soc_hwpm_pdev; +extern const struct file_operations tegra_soc_hwpm_ops; + +/* Driver struct */ +struct tegra_soc_hwpm { + /* Device */ + struct platform_device *pdev; + struct device *dev; + struct device_node *np; + struct class class; + dev_t dev_t; + struct cdev cdev; + + struct hwpm_resource *hwpm_resources; + + /* IP floorsweep info */ + u64 ip_fs_info[TERGA_SOC_HWPM_NUM_IPS]; + + /* MMIO apertures in device tree */ + void __iomem **dt_apertures; + + /* Clocks and resets */ + struct clk *la_clk; + struct clk *la_parent_clk; + struct reset_control *la_rst; + struct reset_control *hwpm_rst; + + struct tegra_soc_hwpm_ip_ops *ip_info; + + /* Memory Management */ + struct dma_buf *stream_dma_buf; + struct dma_buf_attachment *stream_attach; + struct sg_table *stream_sgt; + struct dma_buf *mem_bytes_dma_buf; + struct dma_buf_attachment *mem_bytes_attach; + struct sg_table *mem_bytes_sgt; + void *mem_bytes_kernel; + + /* SW State */ + bool bind_completed; + s32 full_alist_size; + + /* Debugging */ +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_root; +#endif + bool fake_registers_enabled; +}; + +struct hwpm_resource_aperture { + /* + * If false, this is a HWPM aperture (PERFRMON, PMA or RTR). Else this + * is a non-HWPM aperture (ex: VIC). + */ + bool is_ip; + + /* + * If is_ip == false, specify dt_aperture for readl/writel operations. + * If is_ip == true, dt_aperture == TEGRA_SOC_HWPM_INVALID_DT. + */ + u32 dt_aperture; + + /* Physical aperture */ + u64 start_abs_pa; + u64 end_abs_pa; + u64 start_pa; + u64 end_pa; + + /* Allowlist */ + struct allowlist *alist; + u64 alist_size; + + /* + * Currently, perfmons and perfmuxes for all instances of an IP + * are listed in a single aperture mask. It is possible that + * some instances are disable. In this case, accessing corresponding + * registers will result in kernel panic. + * Bit set in the index_mask value will indicate the instance index + * within that IP (or resource). + */ + u32 index_mask; + + /* Fake registers for VDK which doesn't have a SOC HWPM fmodel */ + u32 *fake_registers; +}; + +struct hwpm_resource { + bool reserved; + u32 map_size; + struct hwpm_resource_aperture *map; +}; + +#endif /* TEGRA_SOC_HWPM_STRUCTURES_H */ diff --git a/hal/tegra_soc_hwpm_init.c b/hal/tegra_soc_hwpm_init.c new file mode 100644 index 0000000..723fbcf --- /dev/null +++ b/hal/tegra_soc_hwpm_init.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include + +void __iomem **tegra_soc_hwpm_init_dt_apertures(void) +{ + return t234_soc_hwpm_init_dt_apertures(); +} + +struct tegra_soc_hwpm_ip_ops *tegra_soc_hwpm_init_ip_ops_info(void) +{ + return t234_soc_hwpm_init_ip_ops_info(); +} + +bool tegra_soc_hwpm_is_perfmon(u32 dt_aperture) +{ + return t234_soc_hwpm_is_perfmon(dt_aperture); +} + +u64 tegra_soc_hwpm_get_perfmon_base(u32 dt_aperture) +{ + return t234_soc_hwpm_get_perfmon_base(dt_aperture); +} + +bool tegra_soc_hwpm_is_dt_aperture(u32 dt_aperture) +{ + return t234_soc_hwpm_is_dt_aperture(dt_aperture); +} + +bool tegra_soc_hwpm_is_dt_aperture_reserved(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture, u32 rsrc_id) +{ + return t234_soc_hwpm_is_dt_aperture_reserved(hwpm, aperture, rsrc_id); +} + +u32 tegra_soc_hwpm_get_ip_aperture(struct tegra_soc_hwpm *hwpm, + u64 phys_address, u64 *ip_base_addr) +{ + return t234_soc_hwpm_get_ip_aperture(hwpm, phys_address, ip_base_addr); +} + +struct hwpm_resource_aperture *tegra_soc_hwpm_find_aperture( + struct tegra_soc_hwpm *hwpm, u64 phys_addr, + bool use_absolute_base, bool check_reservation, + u64 *updated_pa) +{ + return t234_soc_hwpm_find_aperture(hwpm, phys_addr, + use_absolute_base, check_reservation, updated_pa); +} + +int tegra_soc_hwpm_fs_info_init(struct tegra_soc_hwpm *hwpm) +{ + return t234_soc_hwpm_fs_info_init(hwpm); +} + +int tegra_soc_hwpm_disable_pma_triggers(struct tegra_soc_hwpm *hwpm) +{ + return t234_soc_hwpm_disable_pma_triggers(hwpm); +} + +u32 **tegra_soc_hwpm_get_mc_fake_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture) +{ + return t234_soc_hwpm_get_mc_fake_regs(hwpm, aperture); +} + +void tegra_soc_hwpm_set_mc_fake_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture, + bool set_null) +{ + t234_soc_hwpm_set_mc_fake_regs(hwpm, aperture, set_null); +} + +int tegra_soc_hwpm_disable_slcg(struct tegra_soc_hwpm *hwpm) +{ + return t234_soc_hwpm_disable_slcg(hwpm); +} + +int tegra_soc_hwpm_enable_slcg(struct tegra_soc_hwpm *hwpm) +{ + return t234_soc_hwpm_enable_slcg(hwpm); +} + +void tegra_soc_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture) +{ + t234_soc_hwpm_zero_alist_regs(hwpm, aperture); +} + +int tegra_soc_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm, + void *ioctl_struct) +{ + return t234_soc_hwpm_update_allowlist(hwpm, ioctl_struct); +} + +bool tegra_soc_hwpm_allowlist_check(struct hwpm_resource_aperture *aperture, + u64 phys_addr, bool use_absolute_base, + u64 *updated_pa) +{ + return t234_soc_hwpm_allowlist_check(aperture, phys_addr, + use_absolute_base, updated_pa); +} + +void tegra_soc_hwpm_get_full_allowlist(struct tegra_soc_hwpm *hwpm) +{ + t234_soc_hwpm_get_full_allowlist(hwpm); +} + +int tegra_soc_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm, + struct tegra_soc_hwpm_update_get_put *update_get_put) +{ + return t234_soc_hwpm_update_mem_bytes(hwpm, update_get_put); +} + +int tegra_soc_hwpm_clear_pipeline(struct tegra_soc_hwpm *hwpm) +{ + return t234_soc_hwpm_clear_pipeline(hwpm); +} + +int tegra_soc_hwpm_stream_buf_map(struct tegra_soc_hwpm *hwpm, + struct tegra_soc_hwpm_alloc_pma_stream *alloc_pma_stream) +{ + return t234_soc_hwpm_stream_buf_map(hwpm, alloc_pma_stream); +} + +int tegra_soc_hwpm_pma_rtr_map(struct tegra_soc_hwpm *hwpm) +{ + return t234_soc_hwpm_pma_rtr_map(hwpm); +} + +int tegra_soc_hwpm_pma_rtr_unmap(struct tegra_soc_hwpm *hwpm) +{ + return t234_soc_hwpm_pma_rtr_unmap(hwpm); +} + +int tegra_soc_hwpm_reserve_given_resource(struct tegra_soc_hwpm *hwpm, u32 resource) +{ + return t234_soc_hwpm_reserve_given_resource(hwpm, resource); +} + +void tegra_soc_hwpm_reset_resources(struct tegra_soc_hwpm *hwpm) +{ + t234_soc_hwpm_reset_resources(hwpm); +} + +void tegra_soc_hwpm_disable_perfmons(struct tegra_soc_hwpm *hwpm) +{ + t234_soc_hwpm_disable_perfmons(hwpm); +} + +int tegra_soc_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm) +{ + return t234_soc_hwpm_bind_resources(hwpm); +} diff --git a/hal/tegra_soc_hwpm_init.h b/hal/tegra_soc_hwpm_init.h new file mode 100644 index 0000000..202fe37 --- /dev/null +++ b/hal/tegra_soc_hwpm_init.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * This header contains interfaces to soc specific functions. + */ + +#ifndef TEGRA_SOC_HWPM_INIT_H +#define TEGRA_SOC_HWPM_INIT_H + +#include +#include + +void __iomem **tegra_soc_hwpm_init_dt_apertures(void); +struct tegra_soc_hwpm_ip_ops *tegra_soc_hwpm_init_ip_ops_info(void); +bool tegra_soc_hwpm_is_perfmon(u32 dt_aperture); +u64 tegra_soc_hwpm_get_perfmon_base(u32 dt_aperture); +bool tegra_soc_hwpm_is_dt_aperture(u32 dt_aperture); +bool tegra_soc_hwpm_is_dt_aperture_reserved(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture, u32 rsrc_id); +u32 tegra_soc_hwpm_get_ip_aperture(struct tegra_soc_hwpm *hwpm, + u64 phys_address, u64 *ip_base_addr); +struct hwpm_resource_aperture *tegra_soc_hwpm_find_aperture( + struct tegra_soc_hwpm *hwpm, u64 phys_addr, + bool use_absolute_base, bool check_reservation, + u64 *updated_pa); +int tegra_soc_hwpm_fs_info_init(struct tegra_soc_hwpm *hwpm); +int tegra_soc_hwpm_disable_pma_triggers(struct tegra_soc_hwpm *hwpm); +u32 **tegra_soc_hwpm_get_mc_fake_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture); +void tegra_soc_hwpm_set_mc_fake_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture, + bool set_null); +int tegra_soc_hwpm_disable_slcg(struct tegra_soc_hwpm *hwpm); +int tegra_soc_hwpm_enable_slcg(struct tegra_soc_hwpm *hwpm); +void tegra_soc_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm, + struct hwpm_resource_aperture *aperture); +int tegra_soc_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm, + void *ioctl_struct); +bool tegra_soc_hwpm_allowlist_check(struct hwpm_resource_aperture *aperture, + u64 phys_addr, bool use_absolute_base, + u64 *updated_pa); +void tegra_soc_hwpm_get_full_allowlist(struct tegra_soc_hwpm *hwpm); +int tegra_soc_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm, + struct tegra_soc_hwpm_update_get_put *update_get_put); +int tegra_soc_hwpm_clear_pipeline(struct tegra_soc_hwpm *hwpm); +int tegra_soc_hwpm_stream_buf_map(struct tegra_soc_hwpm *hwpm, + struct tegra_soc_hwpm_alloc_pma_stream *alloc_pma_stream); +int tegra_soc_hwpm_pma_rtr_map(struct tegra_soc_hwpm *hwpm); +int tegra_soc_hwpm_pma_rtr_unmap(struct tegra_soc_hwpm *hwpm); +int tegra_soc_hwpm_reserve_given_resource( + struct tegra_soc_hwpm *hwpm, u32 resource); +void tegra_soc_hwpm_reset_resources(struct tegra_soc_hwpm *hwpm); +void tegra_soc_hwpm_disable_perfmons(struct tegra_soc_hwpm *hwpm); +int tegra_soc_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm); + +#endif /* TEGRA_SOC_HWPM_INIT_H */ diff --git a/tegra-soc-hwpm-debugfs.c b/tegra-soc-hwpm-debugfs.c index fb33d93..4d9270b 100644 --- a/tegra-soc-hwpm-debugfs.c +++ b/tegra-soc-hwpm-debugfs.c @@ -17,6 +17,11 @@ * along with this program. If not, see . */ +#include +#include + +#include +#include "tegra-soc-hwpm-log.h" #include "tegra-soc-hwpm.h" /* FIXME: This is a placeholder for now. We can add debugfs nodes as needed. */ diff --git a/tegra-soc-hwpm-hw.h b/tegra-soc-hwpm-hw.h deleted file mode 100644 index 71262c3..0000000 --- a/tegra-soc-hwpm-hw.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * tegra-soc-hwpm-hw.h: - * This header contains HW aperture and register info for the Tegra SOC HWPM - * driver. - */ - -#ifndef TEGRA_SOC_HWPM_HW_H -#define TEGRA_SOC_HWPM_HW_H - -#include - -#include "include/hw/t234/hw_addr_map_soc_hwpm.h" -#include "include/hw/t234/hw_pmasys_soc_hwpm.h" -#include "include/hw/t234/hw_pmmsys_soc_hwpm.h" - -/* FIXME: Move enum to DT include file? */ -enum tegra_soc_hwpm_dt_aperture { - TEGRA_SOC_HWPM_INVALID_DT = -1, - - /* PERFMONs */ - TEGRA_SOC_HWPM_FIRST_PERFMON_DT = 0, - TEGRA_SOC_HWPM_VI0_PERFMON_DT = TEGRA_SOC_HWPM_FIRST_PERFMON_DT, - TEGRA_SOC_HWPM_VI1_PERFMON_DT = TEGRA_SOC_HWPM_FIRST_PERFMON_DT + 1, - TEGRA_SOC_HWPM_ISP0_PERFMON_DT, - TEGRA_SOC_HWPM_VICA0_PERFMON_DT, - TEGRA_SOC_HWPM_OFAA0_PERFMON_DT, - TEGRA_SOC_HWPM_PVAV0_PERFMON_DT, - TEGRA_SOC_HWPM_PVAV1_PERFMON_DT, - TEGRA_SOC_HWPM_PVAC0_PERFMON_DT, - TEGRA_SOC_HWPM_NVDLAB0_PERFMON_DT, - TEGRA_SOC_HWPM_NVDLAB1_PERFMON_DT, - TEGRA_SOC_HWPM_NVDISPLAY0_PERFMON_DT, - TEGRA_SOC_HWPM_SYS0_PERFMON_DT, - TEGRA_SOC_HWPM_MGBE0_PERFMON_DT, - TEGRA_SOC_HWPM_MGBE1_PERFMON_DT, - TEGRA_SOC_HWPM_MGBE2_PERFMON_DT, - TEGRA_SOC_HWPM_MGBE3_PERFMON_DT, - TEGRA_SOC_HWPM_SCF0_PERFMON_DT, - TEGRA_SOC_HWPM_NVDECA0_PERFMON_DT, - TEGRA_SOC_HWPM_NVENCA0_PERFMON_DT, - TEGRA_SOC_HWPM_MSSNVLHSH0_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE0_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE1_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE2_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE3_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE4_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE5_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE6_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE7_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE8_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE9_PERFMON_DT, - TEGRA_SOC_HWPM_PCIE10_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT, - TEGRA_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT, - TEGRA_SOC_HWPM_MSSHUB0_PERFMON_DT, - TEGRA_SOC_HWPM_MSSHUB1_PERFMON_DT, - TEGRA_SOC_HWPM_MSSMCFCLIENT0_PERFMON_DT, - TEGRA_SOC_HWPM_MSSMCFMEM0_PERFMON_DT, - TEGRA_SOC_HWPM_MSSMCFMEM1_PERFMON_DT, - TEGRA_SOC_HWPM_LAST_PERFMON_DT = TEGRA_SOC_HWPM_MSSMCFMEM1_PERFMON_DT, - - /* PMA */ - TEGRA_SOC_HWPM_PMA_DT = TEGRA_SOC_HWPM_LAST_PERFMON_DT + 1, - - /* RTR */ - TEGRA_SOC_HWPM_RTR_DT, - - TEGRA_SOC_HWPM_NUM_DT_APERTURES -}; -#define IS_PERFMON(idx) (((idx) >= TEGRA_SOC_HWPM_FIRST_PERFMON_DT) && \ - ((idx) <= TEGRA_SOC_HWPM_LAST_PERFMON_DT)) - -/* RPG_PM Aperture */ -#define PERFMON_BASE(ip_idx) (addr_map_rpg_pm_base_r() + \ - ((u32)(ip_idx)) * pmmsys_perdomain_offset_v()) -#define PERFMON_LIMIT(ip_idx) (PERFMON_BASE((ip_idx) + 1) - 1) - -#endif /* TEGRA_SOC_HWPM_HW_H */ diff --git a/tegra-soc-hwpm-io.c b/tegra-soc-hwpm-io.c index a239f78..1e4aa6f 100644 --- a/tegra-soc-hwpm-io.c +++ b/tegra-soc-hwpm-io.c @@ -21,1861 +21,12 @@ #include #include #include +#include #include "tegra-soc-hwpm-io.h" -#include -#include - -/* - * Aperture Ranges (start_pa/end_pa): - * - start_pa and end_pa is 0 for PERFMON, PMA, and RTR apertures. These - * ranges will be extracted from the device tree. - * - IP apertures are not listed in the device tree because we don't map them. - * Therefore, start_pa and end_pa for IP apertures are hardcoded here. IP - * apertures are listed here because we need to track their allowlists. - */ -struct hwpm_resource_aperture t234_vi_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_VI0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_VI0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_VI0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_VI1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_VI1_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_VI1_PERFMON_DT, - .index_mask = 0x2U, - }, - { - .start_pa = addr_map_vi_thi_base_r(), - .end_pa = addr_map_vi_thi_limit_r(), - .start_abs_pa = addr_map_vi_thi_base_r(), - .end_abs_pa = addr_map_vi_thi_limit_r(), - .fake_registers = NULL, - .alist = vi_thi_alist, - .alist_size = ARRAY_SIZE(vi_thi_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_vi2_thi_base_r(), - .end_pa = addr_map_vi2_thi_limit_r(), - .start_abs_pa = addr_map_vi2_thi_base_r(), - .end_abs_pa = addr_map_vi2_thi_limit_r(), - .fake_registers = NULL, - .alist = vi_thi_alist, - .alist_size = ARRAY_SIZE(vi_thi_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x2U, - }, -}; - -struct hwpm_resource_aperture t234_isp_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_ISP0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_ISP0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_ISP0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_isp_thi_base_r(), - .end_pa = addr_map_isp_thi_limit_r(), - .start_abs_pa = addr_map_isp_thi_base_r(), - .end_abs_pa = addr_map_isp_thi_limit_r(), - .fake_registers = NULL, - .alist = isp_thi_alist, - .alist_size = ARRAY_SIZE(isp_thi_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_vic_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_VICA0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_VICA0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_VICA0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_vic_base_r(), - .end_pa = addr_map_vic_limit_r(), - .start_abs_pa = addr_map_vic_base_r(), - .end_abs_pa = addr_map_vic_limit_r(), - .fake_registers = NULL, - .alist = vic_alist, - .alist_size = ARRAY_SIZE(vic_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_ofa_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_OFAA0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_OFAA0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_OFAA0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_ofa_base_r(), - .end_pa = addr_map_ofa_limit_r(), - .start_abs_pa = addr_map_ofa_base_r(), - .end_abs_pa = addr_map_ofa_limit_r(), - .fake_registers = NULL, - .alist = ofa_alist, - .alist_size = ARRAY_SIZE(ofa_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_pva_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PVAV0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PVAV0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PVAV0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PVAV1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PVAV1_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PVAV1_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PVAC0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PVAC0_PERFMON_DT), - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .fake_registers = NULL, - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PVAC0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_pva0_pm_base_r(), - .end_pa = addr_map_pva0_pm_limit_r(), - .start_abs_pa = addr_map_pva0_pm_base_r(), - .end_abs_pa = addr_map_pva0_pm_limit_r(), - .fake_registers = NULL, - .alist = pva0_pm_alist, - .alist_size = ARRAY_SIZE(pva0_pm_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_nvdla_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_NVDLAB0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_NVDLAB0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_NVDLAB0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_NVDLAB1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_NVDLAB1_PERFMON_DT), - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .fake_registers = NULL, - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_NVDLAB1_PERFMON_DT, - .index_mask = 0x2U, - }, - { - .start_pa = addr_map_nvdla0_base_r(), - .end_pa = addr_map_nvdla0_limit_r(), - .start_abs_pa = addr_map_nvdla0_base_r(), - .end_abs_pa = addr_map_nvdla0_limit_r(), - .fake_registers = NULL, - .alist = nvdla_alist, - .alist_size = ARRAY_SIZE(nvdla_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_nvdla1_base_r(), - .end_pa = addr_map_nvdla1_limit_r(), - .start_abs_pa = addr_map_nvdla1_base_r(), - .end_abs_pa = addr_map_nvdla1_limit_r(), - .fake_registers = NULL, - .alist = nvdla_alist, - .alist_size = ARRAY_SIZE(nvdla_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x2U, - }, -}; - -struct hwpm_resource_aperture t234_mgbe_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MGBE0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MGBE0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MGBE0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MGBE1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MGBE1_PERFMON_DT), - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .fake_registers = NULL, - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MGBE1_PERFMON_DT, - .index_mask = 0x2U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MGBE2_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MGBE2_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MGBE2_PERFMON_DT, - .index_mask = 0x4U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MGBE3_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MGBE3_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MGBE3_PERFMON_DT, - .index_mask = 0x8U, - }, - { - .start_pa = addr_map_mgbe0_base_r(), - .end_pa = addr_map_mgbe0_limit_r(), - .start_abs_pa = addr_map_mgbe0_base_r(), - .end_abs_pa = addr_map_mgbe0_limit_r(), - .fake_registers = NULL, - .alist = mgbe_alist, - .alist_size = ARRAY_SIZE(mgbe_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mgbe1_base_r(), - .end_pa = addr_map_mgbe1_limit_r(), - .start_abs_pa = addr_map_mgbe1_base_r(), - .end_abs_pa = addr_map_mgbe1_limit_r(), - .fake_registers = NULL, - .alist = mgbe_alist, - .alist_size = ARRAY_SIZE(mgbe_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x2U, - }, - { - .start_pa = addr_map_mgbe2_base_r(), - .end_pa = addr_map_mgbe2_limit_r(), - .start_abs_pa = addr_map_mgbe2_base_r(), - .end_abs_pa = addr_map_mgbe2_limit_r(), - .fake_registers = NULL, - .alist = mgbe_alist, - .alist_size = ARRAY_SIZE(mgbe_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x4U, - }, - { - .start_pa = addr_map_mgbe3_base_r(), - .end_pa = addr_map_mgbe3_limit_r(), - .start_abs_pa = addr_map_mgbe3_base_r(), - .end_abs_pa = addr_map_mgbe3_limit_r(), - .fake_registers = NULL, - .alist = mgbe_alist, - .alist_size = ARRAY_SIZE(mgbe_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x8U, - }, -}; - -struct hwpm_resource_aperture t234_scf_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_SCF0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_SCF0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_SCF0_PERFMON_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_nvdec_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_NVDECA0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_NVDECA0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_NVDECA0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_nvdec_base_r(), - .end_pa = addr_map_nvdec_limit_r(), - .start_abs_pa = addr_map_nvdec_base_r(), - .end_abs_pa = addr_map_nvdec_limit_r(), - .fake_registers = NULL, - .alist = nvdec_alist, - .alist_size = ARRAY_SIZE(nvdec_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_nvenc_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_NVENCA0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_NVENCA0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_NVENCA0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_nvenc_base_r(), - .end_pa = addr_map_nvenc_limit_r(), - .start_abs_pa = addr_map_nvenc_base_r(), - .end_abs_pa = addr_map_nvenc_limit_r(), - .fake_registers = NULL, - .alist = nvenc_alist, - .alist_size = ARRAY_SIZE(nvenc_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_pcie_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE1_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE1_PERFMON_DT, - .index_mask = 0x2U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE2_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE2_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE2_PERFMON_DT, - .index_mask = 0x4U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE3_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE3_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE3_PERFMON_DT, - .index_mask = 0x8U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE4_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE4_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE4_PERFMON_DT, - .index_mask = 0x10U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE5_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE5_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE5_PERFMON_DT, - .index_mask = 0x20U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE6_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE6_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE6_PERFMON_DT, - .index_mask = 0x40U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE7_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE7_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE7_PERFMON_DT, - .index_mask = 0x80U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE8_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE8_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE8_PERFMON_DT, - .index_mask = 0x100U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE9_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE9_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE9_PERFMON_DT, - .index_mask = 0x200U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_PCIE10_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_PCIE10_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PCIE10_PERFMON_DT, - .index_mask = 0x400U, - }, - { - .start_pa = addr_map_pcie_c0_ctl_base_r(), - .end_pa = addr_map_pcie_c0_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c0_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c0_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_pcie_c1_ctl_base_r(), - .end_pa = addr_map_pcie_c1_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c1_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c1_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x2U, - }, - { - .start_pa = addr_map_pcie_c2_ctl_base_r(), - .end_pa = addr_map_pcie_c2_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c2_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c2_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x4U, - }, - { - .start_pa = addr_map_pcie_c3_ctl_base_r(), - .end_pa = addr_map_pcie_c3_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c3_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c3_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x8U, - }, - { - .start_pa = addr_map_pcie_c4_ctl_base_r(), - .end_pa = addr_map_pcie_c4_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c4_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c4_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x10U, - }, - { - .start_pa = addr_map_pcie_c5_ctl_base_r(), - .end_pa = addr_map_pcie_c5_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c5_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c5_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x20U, - }, - { - .start_pa = addr_map_pcie_c6_ctl_base_r(), - .end_pa = addr_map_pcie_c6_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c6_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c6_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x40U, - }, - { - .start_pa = addr_map_pcie_c7_ctl_base_r(), - .end_pa = addr_map_pcie_c7_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c7_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c7_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x80U, - }, - { - .start_pa = addr_map_pcie_c8_ctl_base_r(), - .end_pa = addr_map_pcie_c8_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c8_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c8_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x100U, - }, - { - .start_pa = addr_map_pcie_c9_ctl_base_r(), - .end_pa = addr_map_pcie_c9_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c9_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c9_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x200U, - }, - { - .start_pa = addr_map_pcie_c10_ctl_base_r(), - .end_pa = addr_map_pcie_c10_ctl_limit_r(), - .start_abs_pa = addr_map_pcie_c10_ctl_base_r(), - .end_abs_pa = addr_map_pcie_c10_ctl_limit_r(), - .fake_registers = NULL, - .alist = pcie_ctl_alist, - .alist_size = ARRAY_SIZE(pcie_ctl_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x400U, - }, -}; - -struct hwpm_resource_aperture t234_display_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_NVDISPLAY0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_NVDISPLAY0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_NVDISPLAY0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_disp_base_r(), - .end_pa = addr_map_disp_limit_r(), - .start_abs_pa = addr_map_disp_base_r(), - .end_abs_pa = addr_map_disp_limit_r(), - .fake_registers = NULL, - .alist = disp_alist, - .alist_size = ARRAY_SIZE(disp_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, -}; - -/* - * Normally there is a 1-to-1 mapping between an MMIO aperture and a - * hwpm_resource_aperture struct. But MC MMIO apertures are used in multiple - * hwpm_resource_aperture structs. Therefore, we have to share the fake register - * arrays between these hwpm_resource_aperture structs. This is why we have to - * define the fake register arrays globally. For all other 1-to-1 mapping - * apertures the fake register arrays are directly embedded inside the - * hwpm_resource_aperture structs. - */ -u32 *mc_fake_regs[16] = {NULL}; -struct hwpm_resource_aperture t234_mss_channel_map[] = { - { - .start_pa = addr_map_mc0_base_r(), - .end_pa = addr_map_mc0_limit_r(), - .start_abs_pa = addr_map_mc0_base_r(), - .end_abs_pa = addr_map_mc0_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc1_base_r(), - .end_pa = addr_map_mc1_limit_r(), - .start_abs_pa = addr_map_mc1_base_r(), - .end_abs_pa = addr_map_mc1_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x2U, - }, - { - .start_pa = addr_map_mc2_base_r(), - .end_pa = addr_map_mc2_limit_r(), - .start_abs_pa = addr_map_mc2_base_r(), - .end_abs_pa = addr_map_mc2_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x4U, - }, - { - .start_pa = addr_map_mc3_base_r(), - .end_pa = addr_map_mc3_limit_r(), - .start_abs_pa = addr_map_mc3_base_r(), - .end_abs_pa = addr_map_mc3_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x8U, - }, - { - .start_pa = addr_map_mc4_base_r(), - .end_pa = addr_map_mc4_limit_r(), - .start_abs_pa = addr_map_mc4_base_r(), - .end_abs_pa = addr_map_mc4_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x10U, - }, - { - .start_pa = addr_map_mc5_base_r(), - .end_pa = addr_map_mc5_limit_r(), - .start_abs_pa = addr_map_mc5_base_r(), - .end_abs_pa = addr_map_mc5_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x20U, - }, - { - .start_pa = addr_map_mc6_base_r(), - .end_pa = addr_map_mc6_limit_r(), - .start_abs_pa = addr_map_mc6_base_r(), - .end_abs_pa = addr_map_mc6_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x40U, - }, - { - .start_pa = addr_map_mc7_base_r(), - .end_pa = addr_map_mc7_limit_r(), - .start_abs_pa = addr_map_mc7_base_r(), - .end_abs_pa = addr_map_mc7_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x80U, - }, - { - .start_pa = addr_map_mc8_base_r(), - .end_pa = addr_map_mc8_limit_r(), - .start_abs_pa = addr_map_mc8_base_r(), - .end_abs_pa = addr_map_mc8_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x100U, - }, - { - .start_pa = addr_map_mc9_base_r(), - .end_pa = addr_map_mc9_limit_r(), - .start_abs_pa = addr_map_mc9_base_r(), - .end_abs_pa = addr_map_mc9_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x200U, - }, - { - .start_pa = addr_map_mc10_base_r(), - .end_pa = addr_map_mc10_limit_r(), - .start_abs_pa = addr_map_mc10_base_r(), - .end_abs_pa = addr_map_mc10_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x400U, - }, - { - .start_pa = addr_map_mc11_base_r(), - .end_pa = addr_map_mc11_limit_r(), - .start_abs_pa = addr_map_mc11_base_r(), - .end_abs_pa = addr_map_mc11_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x800U, - }, - { - .start_pa = addr_map_mc12_base_r(), - .end_pa = addr_map_mc12_limit_r(), - .start_abs_pa = addr_map_mc12_base_r(), - .end_abs_pa = addr_map_mc12_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1000U, - }, - { - .start_pa = addr_map_mc13_base_r(), - .end_pa = addr_map_mc13_limit_r(), - .start_abs_pa = addr_map_mc13_base_r(), - .end_abs_pa = addr_map_mc13_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x2000U, - }, - { - .start_pa = addr_map_mc14_base_r(), - .end_pa = addr_map_mc14_limit_r(), - .start_abs_pa = addr_map_mc14_base_r(), - .end_abs_pa = addr_map_mc14_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x4000U, - }, - { - .start_pa = addr_map_mc15_base_r(), - .end_pa = addr_map_mc15_limit_r(), - .start_abs_pa = addr_map_mc15_base_r(), - .end_abs_pa = addr_map_mc15_limit_r(), - .fake_registers = NULL, - .alist = mss_channel_alist, - .alist_size = ARRAY_SIZE(mss_channel_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x8000U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT, - .index_mask = 0x2U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT, - .index_mask = 0x4U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT, - .index_mask = 0x8U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT, - .index_mask = 0x10U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT, - .index_mask = 0x20U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT, - .index_mask = 0x40U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT, - .index_mask = 0x80U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT, - .index_mask = 0x100U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT, - .index_mask = 0x200U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT, - .index_mask = 0x400U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT, - .index_mask = 0x800U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT, - .index_mask = 0x1000U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT, - .index_mask = 0x2000U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT, - .index_mask = 0x4000U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT, - .index_mask = 0x8000U, - }, -}; - -struct hwpm_resource_aperture t234_mss_gpu_hub_map[] = { - { - .start_pa = addr_map_mss_nvlink_1_base_r(), - .end_pa = addr_map_mss_nvlink_1_limit_r(), - .start_abs_pa = addr_map_mss_nvlink_1_base_r(), - .end_abs_pa = addr_map_mss_nvlink_1_limit_r(), - .fake_registers = NULL, - .alist = mss_nvlink_alist, - .alist_size = ARRAY_SIZE(mss_nvlink_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mss_nvlink_2_base_r(), - .end_pa = addr_map_mss_nvlink_2_limit_r(), - .start_abs_pa = addr_map_mss_nvlink_2_base_r(), - .end_abs_pa = addr_map_mss_nvlink_2_limit_r(), - .fake_registers = NULL, - .alist = mss_nvlink_alist, - .alist_size = ARRAY_SIZE(mss_nvlink_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x2U, - }, - { - .start_pa = addr_map_mss_nvlink_3_base_r(), - .end_pa = addr_map_mss_nvlink_3_limit_r(), - .start_abs_pa = addr_map_mss_nvlink_3_base_r(), - .end_abs_pa = addr_map_mss_nvlink_3_limit_r(), - .fake_registers = NULL, - .alist = mss_nvlink_alist, - .alist_size = ARRAY_SIZE(mss_nvlink_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x4U, - }, - { - .start_pa = addr_map_mss_nvlink_4_base_r(), - .end_pa = addr_map_mss_nvlink_4_limit_r(), - .start_abs_pa = addr_map_mss_nvlink_4_base_r(), - .end_abs_pa = addr_map_mss_nvlink_4_limit_r(), - .fake_registers = NULL, - .alist = mss_nvlink_alist, - .alist_size = ARRAY_SIZE(mss_nvlink_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x8U, - }, - { - .start_pa = addr_map_mss_nvlink_5_base_r(), - .end_pa = addr_map_mss_nvlink_5_limit_r(), - .start_abs_pa = addr_map_mss_nvlink_5_base_r(), - .end_abs_pa = addr_map_mss_nvlink_5_limit_r(), - .fake_registers = NULL, - .alist = mss_nvlink_alist, - .alist_size = ARRAY_SIZE(mss_nvlink_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x10U, - }, - { - .start_pa = addr_map_mss_nvlink_6_base_r(), - .end_pa = addr_map_mss_nvlink_6_limit_r(), - .start_abs_pa = addr_map_mss_nvlink_6_base_r(), - .end_abs_pa = addr_map_mss_nvlink_6_limit_r(), - .fake_registers = NULL, - .alist = mss_nvlink_alist, - .alist_size = ARRAY_SIZE(mss_nvlink_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x20U, - }, - { - .start_pa = addr_map_mss_nvlink_7_base_r(), - .end_pa = addr_map_mss_nvlink_7_limit_r(), - .start_abs_pa = addr_map_mss_nvlink_7_base_r(), - .end_abs_pa = addr_map_mss_nvlink_7_limit_r(), - .fake_registers = NULL, - .alist = mss_nvlink_alist, - .alist_size = ARRAY_SIZE(mss_nvlink_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x40U, - }, - { - .start_pa = addr_map_mss_nvlink_8_base_r(), - .end_pa = addr_map_mss_nvlink_8_limit_r(), - .start_abs_pa = addr_map_mss_nvlink_8_base_r(), - .end_abs_pa = addr_map_mss_nvlink_8_limit_r(), - .fake_registers = NULL, - .alist = mss_nvlink_alist, - .alist_size = ARRAY_SIZE(mss_nvlink_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x80U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSNVLHSH0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSNVLHSH0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSNVLHSH0_PERFMON_DT, - .index_mask = 0xFFU, - }, -}; - -struct hwpm_resource_aperture t234_mss_iso_niso_hub_map[] = { - { - .start_pa = addr_map_mc0_base_r(), - .end_pa = addr_map_mc0_limit_r(), - .start_abs_pa = addr_map_mc0_base_r(), - .end_abs_pa = addr_map_mc0_limit_r(), - .fake_registers = NULL, - .alist = mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc1_base_r(), - .end_pa = addr_map_mc1_limit_r(), - .start_abs_pa = addr_map_mc1_base_r(), - .end_abs_pa = addr_map_mc1_limit_r(), - .fake_registers = NULL, - .alist = mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc2_base_r(), - .end_pa = addr_map_mc2_limit_r(), - .start_abs_pa = addr_map_mc2_base_r(), - .end_abs_pa = addr_map_mc2_limit_r(), - .fake_registers = NULL, - .alist = mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc3_base_r(), - .end_pa = addr_map_mc3_limit_r(), - .start_abs_pa = addr_map_mc3_base_r(), - .end_abs_pa = addr_map_mc3_limit_r(), - .fake_registers = NULL, - .alist = mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc4_base_r(), - .end_pa = addr_map_mc4_limit_r(), - .start_abs_pa = addr_map_mc4_base_r(), - .end_abs_pa = addr_map_mc4_limit_r(), - .fake_registers = NULL, - .alist = mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc5_base_r(), - .end_pa = addr_map_mc5_limit_r(), - .start_abs_pa = addr_map_mc5_base_r(), - .end_abs_pa = addr_map_mc5_limit_r(), - .fake_registers = NULL, - .alist = mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - }, - { - .start_pa = addr_map_mc6_base_r(), - .end_pa = addr_map_mc6_limit_r(), - .start_abs_pa = addr_map_mc6_base_r(), - .end_abs_pa = addr_map_mc6_limit_r(), - .fake_registers = NULL, - .alist = mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc7_base_r(), - .end_pa = addr_map_mc7_limit_r(), - .start_abs_pa = addr_map_mc7_base_r(), - .end_abs_pa = addr_map_mc7_limit_r(), - .fake_registers = NULL, - .alist = mc0to7_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc8_base_r(), - .end_pa = addr_map_mc8_limit_r(), - .start_abs_pa = addr_map_mc8_base_r(), - .end_abs_pa = addr_map_mc8_limit_r(), - .fake_registers = NULL, - .alist = mc8_res_mss_iso_niso_hub_alist, - .alist_size = ARRAY_SIZE(mc8_res_mss_iso_niso_hub_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSHUB0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSHUB0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSHUB0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSHUB1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSHUB1_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSHUB1_PERFMON_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_mss_mcf_map[] = { - { - .start_pa = addr_map_mc0_base_r(), - .end_pa = addr_map_mc0_limit_r(), - .start_abs_pa = addr_map_mc0_base_r(), - .end_abs_pa = addr_map_mc0_limit_r(), - .fake_registers = NULL, - .alist = mc0to1_mss_mcf_alist, - .alist_size = ARRAY_SIZE(mc0to1_mss_mcf_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc1_base_r(), - .end_pa = addr_map_mc1_limit_r(), - .start_abs_pa = addr_map_mc1_base_r(), - .end_abs_pa = addr_map_mc1_limit_r(), - .fake_registers = NULL, - .alist = mc0to1_mss_mcf_alist, - .alist_size = ARRAY_SIZE(mc0to1_mss_mcf_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc2_base_r(), - .end_pa = addr_map_mc2_limit_r(), - .start_abs_pa = addr_map_mc2_base_r(), - .end_abs_pa = addr_map_mc2_limit_r(), - .fake_registers = NULL, - .alist = mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(mc2to7_mss_mcf_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc3_base_r(), - .end_pa = addr_map_mc3_limit_r(), - .start_abs_pa = addr_map_mc3_base_r(), - .end_abs_pa = addr_map_mc3_limit_r(), - .fake_registers = NULL, - .alist = mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(mc2to7_mss_mcf_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc4_base_r(), - .end_pa = addr_map_mc4_limit_r(), - .start_abs_pa = addr_map_mc4_base_r(), - .end_abs_pa = addr_map_mc4_limit_r(), - .fake_registers = NULL, - .alist = mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(mc2to7_mss_mcf_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc5_base_r(), - .end_pa = addr_map_mc5_limit_r(), - .start_abs_pa = addr_map_mc5_base_r(), - .end_abs_pa = addr_map_mc5_limit_r(), - .fake_registers = NULL, - .alist = mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(mc2to7_mss_mcf_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc6_base_r(), - .end_pa = addr_map_mc6_limit_r(), - .start_abs_pa = addr_map_mc6_base_r(), - .end_abs_pa = addr_map_mc6_limit_r(), - .fake_registers = NULL, - .alist = mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(mc2to7_mss_mcf_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mc7_base_r(), - .end_pa = addr_map_mc7_limit_r(), - .start_abs_pa = addr_map_mc7_base_r(), - .end_abs_pa = addr_map_mc7_limit_r(), - .fake_registers = NULL, - .alist = mc2to7_mss_mcf_alist, - .alist_size = ARRAY_SIZE(mc2to7_mss_mcf_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = addr_map_mcb_base_r(), - .end_pa = addr_map_mcb_limit_r(), - .start_abs_pa = addr_map_mcb_base_r(), - .end_abs_pa = addr_map_mcb_limit_r(), - .fake_registers = NULL, - .alist = mcb_mss_mcf_alist, - .alist_size = ARRAY_SIZE(mcb_mss_mcf_alist), - .is_ip = true, - .dt_aperture = TEGRA_SOC_HWPM_INVALID_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSMCFCLIENT0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSMCFCLIENT0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSMCFCLIENT0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSMCFMEM0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSMCFMEM0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSMCFMEM0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_MSSMCFMEM1_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_MSSMCFMEM1_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_MSSMCFMEM1_PERFMON_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_pma_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = PERFMON_BASE(TEGRA_SOC_HWPM_SYS0_PERFMON_DT), - .end_abs_pa = PERFMON_LIMIT(TEGRA_SOC_HWPM_SYS0_PERFMON_DT), - .fake_registers = NULL, - .alist = perfmon_alist, - .alist_size = ARRAY_SIZE(perfmon_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_SYS0_PERFMON_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = addr_map_pma_base_r(), - .end_abs_pa = addr_map_pma_limit_r(), - .fake_registers = NULL, - .alist = pma_res_pma_alist, - .alist_size = ARRAY_SIZE(pma_res_pma_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PMA_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource_aperture t234_cmd_slice_rtr_map[] = { - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = addr_map_pma_base_r(), - .end_abs_pa = addr_map_pma_limit_r(), - .fake_registers = NULL, - .alist = pma_res_cmd_slice_rtr_alist, - .alist_size = ARRAY_SIZE(pma_res_cmd_slice_rtr_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_PMA_DT, - .index_mask = 0x1U, - }, - { - .start_pa = 0, - .end_pa = 0, - .start_abs_pa = addr_map_rtr_base_r(), - .end_abs_pa = addr_map_rtr_limit_r(), - .fake_registers = NULL, - .alist = rtr_alist, - .alist_size = ARRAY_SIZE(rtr_alist), - .is_ip = false, - .dt_aperture = TEGRA_SOC_HWPM_RTR_DT, - .index_mask = 0x1U, - }, -}; - -struct hwpm_resource hwpm_resources[TERGA_SOC_HWPM_NUM_RESOURCES] = { - [TEGRA_SOC_HWPM_RESOURCE_VI] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_vi_map), - .map = t234_vi_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_ISP] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_isp_map), - .map = t234_isp_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_VIC] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_vic_map), - .map = t234_vic_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_OFA] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_ofa_map), - .map = t234_ofa_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_PVA] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_pva_map), - .map = t234_pva_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_NVDLA] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_nvdla_map), - .map = t234_nvdla_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_MGBE] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_mgbe_map), - .map = t234_mgbe_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_SCF] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_scf_map), - .map = t234_scf_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_NVDEC] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_nvdec_map), - .map = t234_nvdec_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_NVENC] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_nvenc_map), - .map = t234_nvenc_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_PCIE] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_pcie_map), - .map = t234_pcie_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_DISPLAY] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_display_map), - .map = t234_display_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_mss_channel_map), - .map = t234_mss_channel_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_MSS_GPU_HUB] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_mss_gpu_hub_map), - .map = t234_mss_gpu_hub_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_MSS_ISO_NISO_HUBS] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_mss_iso_niso_hub_map), - .map = t234_mss_iso_niso_hub_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_MSS_MCF] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_mss_mcf_map), - .map = t234_mss_mcf_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_PMA] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_pma_map), - .map = t234_pma_map, - }, - [TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR] = { - .reserved = false, - .map_size = ARRAY_SIZE(t234_cmd_slice_rtr_map), - .map = t234_cmd_slice_rtr_map, - }, -}; - -void tegra_soc_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm, - struct hwpm_resource_aperture *aperture) -{ - u32 alist_idx = 0U; - - for (alist_idx = 0; alist_idx < aperture->alist_size; alist_idx++) { - if (aperture->alist[alist_idx].zero_at_init) { - ioctl_writel(hwpm, aperture, - aperture->start_pa + - aperture->alist[alist_idx].reg_offset, 0); - } - } -} - -int tegra_soc_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm, - void *ioctl_struct) -{ - int err = 0; - int res_idx = 0; - int aprt_idx = 0; - u32 full_alist_idx = 0; - u32 aprt_alist_idx = 0; - long pinned_pages = 0; - long page_idx = 0; - u64 alist_buf_size = 0; - u64 num_pages = 0; - u64 *full_alist_u64 = NULL; - void *full_alist = NULL; - struct page **pages = NULL; - struct hwpm_resource_aperture *aperture = NULL; - struct tegra_soc_hwpm_query_allowlist *query_allowlist = - (struct tegra_soc_hwpm_query_allowlist *)ioctl_struct; - unsigned long user_va = (unsigned long)(query_allowlist->allowlist); - unsigned long offset = user_va & ~PAGE_MASK; - - if (hwpm->full_alist_size < 0) { - tegra_soc_hwpm_err("Invalid allowlist size"); - return -EINVAL; - } - alist_buf_size = hwpm->full_alist_size * sizeof(struct allowlist); - - /* Memory map user buffer into kernel address space */ - num_pages = DIV_ROUND_UP(offset + alist_buf_size, PAGE_SIZE); - pages = (struct page **)kzalloc(sizeof(*pages) * num_pages, GFP_KERNEL); - if (!pages) { - tegra_soc_hwpm_err("Couldn't allocate memory for pages array"); - err = -ENOMEM; - goto alist_unmap; - } - pinned_pages = get_user_pages(user_va & PAGE_MASK, num_pages, 0, - pages, NULL); - if (pinned_pages != num_pages) { - tegra_soc_hwpm_err("Requested %llu pages / Got %ld pages", - num_pages, pinned_pages); - err = -ENOMEM; - goto alist_unmap; - } - full_alist = vmap(pages, num_pages, VM_MAP, PAGE_KERNEL); - if (!full_alist) { - tegra_soc_hwpm_err("Couldn't map allowlist buffer into" - " kernel address space"); - err = -ENOMEM; - goto alist_unmap; - } - full_alist_u64 = (u64 *)(full_alist + offset); - - /* Fill in allowlist buffer */ - for (res_idx = 0, full_alist_idx = 0; - res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; - res_idx++) { - if (!(hwpm_resources[res_idx].reserved)) - continue; - tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx); - - for (aprt_idx = 0; - aprt_idx < hwpm_resources[res_idx].map_size; - aprt_idx++) { - aperture = &(hwpm_resources[res_idx].map[aprt_idx]); - if (aperture->alist) { - for (aprt_alist_idx = 0; - aprt_alist_idx < aperture->alist_size; - aprt_alist_idx++, full_alist_idx++) { - full_alist_u64[full_alist_idx] = - aperture->start_pa + - aperture->alist[aprt_alist_idx].reg_offset; - } - } else { - tegra_soc_hwpm_err("NULL allowlist in aperture(0x%llx - 0x%llx)", - aperture->start_pa, - aperture->end_pa); - } - } - } - -alist_unmap: - if (full_alist) - vunmap(full_alist); - if (pinned_pages > 0) { - for (page_idx = 0; page_idx < pinned_pages; page_idx++) { - set_page_dirty(pages[page_idx]); - put_page(pages[page_idx]); - } - } - if (pages) { - kfree(pages); - } - - return err; -} - -static bool allowlist_check(struct hwpm_resource_aperture *aperture, - u64 phys_addr, bool use_absolute_base, - u64 *updated_pa) -{ - u32 idx = 0U; - u64 start_pa = 0ULL; - - if (!aperture) { - tegra_soc_hwpm_err("Aperture is NULL"); - return false; - } - if (!aperture->alist) { - tegra_soc_hwpm_err("NULL allowlist in dt_aperture(%d)", - aperture->dt_aperture); - return false; - } - - start_pa = use_absolute_base ? aperture->start_abs_pa : - aperture->start_pa; - - for (idx = 0; idx < aperture->alist_size; idx++) { - if (phys_addr == start_pa + aperture->alist[idx].reg_offset) { - *updated_pa = aperture->start_pa + - aperture->alist[idx].reg_offset; - return true; - } - } - - return false; -} - -static bool ip_reg_check(struct hwpm_resource_aperture *aperture, - u64 phys_addr, bool use_absolute_base, - u64 *updated_pa) -{ - u64 start_pa = 0ULL; - u64 end_pa = 0ULL; - - if (!aperture) { - tegra_soc_hwpm_err("Aperture is NULL"); - return false; - } - - if (use_absolute_base) { - start_pa = aperture->start_abs_pa; - end_pa = aperture->end_abs_pa; - } else { - start_pa = aperture->start_pa; - end_pa = aperture->end_pa; - } - - if ((phys_addr >= start_pa) && (phys_addr <= end_pa)) { - tegra_soc_hwpm_dbg("Found aperture:" - " phys_addr(0x%llx), aperture(0x%llx - 0x%llx)", - phys_addr, start_pa, end_pa); - *updated_pa = phys_addr - start_pa + aperture->start_pa; - return true; - } - return false; -} - -/* - * Find an aperture in which phys_addr lies. If check_reservation is true, then - * we also have to do a allowlist check. - */ -struct hwpm_resource_aperture *find_hwpm_aperture(struct tegra_soc_hwpm *hwpm, - u64 phys_addr, - bool use_absolute_base, - bool check_reservation, - u64 *updated_pa) -{ - struct hwpm_resource_aperture *aperture = NULL; - int res_idx = 0; - int aprt_idx = 0; - - for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { - if (check_reservation && !hwpm_resources[res_idx].reserved) - continue; - - for (aprt_idx = 0; - aprt_idx < hwpm_resources[res_idx].map_size; - aprt_idx++) { - aperture = &(hwpm_resources[res_idx].map[aprt_idx]); - if (check_reservation) { - if (allowlist_check(aperture, phys_addr, - use_absolute_base, updated_pa)) { - return aperture; - } - } else { - if (ip_reg_check(aperture, phys_addr, - use_absolute_base, updated_pa)) { - return aperture; - } - } - } - } - - tegra_soc_hwpm_err("Unable to find aperture: phys(0x%llx)", phys_addr); - return NULL; -} +#include "tegra-soc-hwpm-log.h" +#include +#include static u32 fake_readl(struct tegra_soc_hwpm *hwpm, u64 phys_addr) { @@ -1888,7 +39,7 @@ static u32 fake_readl(struct tegra_soc_hwpm *hwpm, u64 phys_addr) return 0; } - aperture = find_hwpm_aperture(hwpm, phys_addr, false, false, &updated_pa); + aperture = tegra_soc_hwpm_find_aperture(hwpm, phys_addr, false, false, &updated_pa); if (!aperture) { tegra_soc_hwpm_err("Invalid reg op address(0x%llx)", phys_addr); return 0; @@ -1910,7 +61,7 @@ static void fake_writel(struct tegra_soc_hwpm *hwpm, return; } - aperture = find_hwpm_aperture(hwpm, phys_addr, false, false, &updated_pa); + aperture = tegra_soc_hwpm_find_aperture(hwpm, phys_addr, false, false, &updated_pa); if (!aperture) { tegra_soc_hwpm_err("Invalid reg op address(0x%llx)", phys_addr); return; @@ -1920,11 +71,9 @@ static void fake_writel(struct tegra_soc_hwpm *hwpm, } /* Read a HWPM (PERFMON, PMA, or RTR) register */ -u32 hwpm_readl(struct tegra_soc_hwpm *hwpm, - enum tegra_soc_hwpm_dt_aperture dt_aperture, u32 reg_offset) +u32 hwpm_readl(struct tegra_soc_hwpm *hwpm, u32 dt_aperture, u32 reg_offset) { - if ((dt_aperture < 0) || - (dt_aperture >= TEGRA_SOC_HWPM_NUM_DT_APERTURES)) { + if (!tegra_soc_hwpm_is_dt_aperture(dt_aperture)) { tegra_soc_hwpm_err("Invalid dt aperture(%d)", dt_aperture); return 0; } @@ -1934,14 +83,7 @@ u32 hwpm_readl(struct tegra_soc_hwpm *hwpm, dt_aperture, hwpm->dt_apertures[dt_aperture], reg_offset); if (hwpm->fake_registers_enabled) { - u64 base_pa = 0; - - if (IS_PERFMON(dt_aperture)) - base_pa = PERFMON_BASE(dt_aperture); - else if (dt_aperture == TEGRA_SOC_HWPM_PMA_DT) - base_pa = addr_map_pma_base_r(); - else - base_pa = addr_map_rtr_base_r(); + u64 base_pa = tegra_soc_hwpm_get_perfmon_base(dt_aperture); return fake_readl(hwpm, base_pa + reg_offset); } else { @@ -1950,12 +92,10 @@ u32 hwpm_readl(struct tegra_soc_hwpm *hwpm, } /* Write a HWPM (PERFMON, PMA, or RTR) register */ -void hwpm_writel(struct tegra_soc_hwpm *hwpm, - enum tegra_soc_hwpm_dt_aperture dt_aperture, +void hwpm_writel(struct tegra_soc_hwpm *hwpm, u32 dt_aperture, u32 reg_offset, u32 val) { - if ((dt_aperture < 0) || - (dt_aperture >= TEGRA_SOC_HWPM_NUM_DT_APERTURES)) { + if (!tegra_soc_hwpm_is_dt_aperture(dt_aperture)) { tegra_soc_hwpm_err("Invalid dt aperture(%d)", dt_aperture); return; } @@ -1966,14 +106,7 @@ void hwpm_writel(struct tegra_soc_hwpm *hwpm, dt_aperture, hwpm->dt_apertures[dt_aperture], reg_offset, val); if (hwpm->fake_registers_enabled) { - u64 base_pa = 0; - - if (IS_PERFMON(dt_aperture)) - base_pa = PERFMON_BASE(dt_aperture); - else if (dt_aperture == TEGRA_SOC_HWPM_PMA_DT) - base_pa = addr_map_pma_base_r(); - else - base_pa = addr_map_rtr_base_r(); + u64 base_pa = tegra_soc_hwpm_get_perfmon_base(dt_aperture); fake_writel(hwpm, base_pa + reg_offset, val); } else { @@ -2081,7 +214,7 @@ void ioctl_writel(struct tegra_soc_hwpm *hwpm, /* Read Modify Write register operation */ int reg_rmw(struct tegra_soc_hwpm *hwpm, struct hwpm_resource_aperture *aperture, - enum tegra_soc_hwpm_dt_aperture dt_aperture, + u32 dt_aperture, u64 addr, u32 field_mask, u32 field_val, @@ -2097,8 +230,7 @@ int reg_rmw(struct tegra_soc_hwpm *hwpm, } } if (!is_ip) { - if ((dt_aperture < 0) || - (dt_aperture > TEGRA_SOC_HWPM_NUM_DT_APERTURES)) { + if (!tegra_soc_hwpm_is_dt_aperture(dt_aperture)) { tegra_soc_hwpm_err("Invalid dt_aperture(%d)", dt_aperture); return -EIO; diff --git a/tegra-soc-hwpm-io.h b/tegra-soc-hwpm-io.h index 6ac65fc..8f65844 100644 --- a/tegra-soc-hwpm-io.h +++ b/tegra-soc-hwpm-io.h @@ -20,77 +20,19 @@ #ifndef TEGRA_SOC_HWPM_IO_H #define TEGRA_SOC_HWPM_IO_H -#include "tegra-soc-hwpm.h" +struct tegra_soc_hwpm; +struct hwpm_resource_aperture; -struct allowlist; - -struct hwpm_resource_aperture { - /* - * If false, this is a HWPM aperture (PERFRMON, PMA or RTR). Else this - * is a non-HWPM aperture (ex: VIC). - */ - bool is_ip; - - /* - * If is_ip == false, specify dt_aperture for readl/writel operations. - * If is_ip == true, dt_aperture == TEGRA_SOC_HWPM_INVALID_DT. - */ - enum tegra_soc_hwpm_dt_aperture dt_aperture; - - /* Physical aperture */ - u64 start_abs_pa; - u64 end_abs_pa; - u64 start_pa; - u64 end_pa; - - /* Allowlist */ - struct allowlist *alist; - u64 alist_size; - - /* - * Currently, perfmons and perfmuxes for all instances of an IP - * are listed in a single aperture mask. It is possible that - * some instances are disable. In this case, accessing corresponding - * registers will result in kernel panic. - * Bit set in the index_mask value will indicate the instance index - * within that IP (or resource). - */ - u32 index_mask; - - /* Fake registers for VDK which doesn't have a SOC HWPM fmodel */ - u32 *fake_registers; -}; - -struct hwpm_resource { - bool reserved; - u32 map_size; - struct hwpm_resource_aperture *map; -}; - -/* Externs */ -extern struct hwpm_resource hwpm_resources[TERGA_SOC_HWPM_NUM_RESOURCES]; -extern u32 *mc_fake_regs[16]; -extern struct hwpm_resource_aperture t234_mss_channel_map[]; -extern struct hwpm_resource_aperture t234_mss_gpu_hub_map[]; -extern struct hwpm_resource_aperture t234_mss_iso_niso_hub_map[]; -extern struct hwpm_resource_aperture t234_mss_mcf_map[]; -extern struct hwpm_resource_aperture t234_pma_map[]; -extern struct hwpm_resource_aperture t234_cmd_slice_rtr_map[]; - -void tegra_soc_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm, - struct hwpm_resource_aperture *aperture); -int tegra_soc_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm, - void *ioctl_struct); struct hwpm_resource_aperture *find_hwpm_aperture(struct tegra_soc_hwpm *hwpm, u64 phys_addr, bool use_absolute_base, bool check_reservation, u64 *updated_pa); u32 hwpm_readl(struct tegra_soc_hwpm *hwpm, - enum tegra_soc_hwpm_dt_aperture dt_aperture, + u32 dt_aperture, u32 reg_offset); void hwpm_writel(struct tegra_soc_hwpm *hwpm, - enum tegra_soc_hwpm_dt_aperture dt_aperture, + u32 dt_aperture, u32 reg_offset, u32 val); u32 ip_readl(struct tegra_soc_hwpm *hwpm, u64 phys_addr); void ip_writel(struct tegra_soc_hwpm *hwpm, u64 phys_addr, u32 val); @@ -103,7 +45,7 @@ void ioctl_writel(struct tegra_soc_hwpm *hwpm, u32 val); int reg_rmw(struct tegra_soc_hwpm *hwpm, struct hwpm_resource_aperture *aperture, - enum tegra_soc_hwpm_dt_aperture dt_aperture, + u32 dt_aperture, u64 addr, u32 field_mask, u32 field_val, diff --git a/tegra-soc-hwpm-ioctl.c b/tegra-soc-hwpm-ioctl.c index 8ff2e53..7a87a69 100644 --- a/tegra-soc-hwpm-ioctl.c +++ b/tegra-soc-hwpm-ioctl.c @@ -23,6 +23,10 @@ #include #include #include +#include +#include +#include +#include /* FIXME: Is this include needed for struct resource? */ #if 0 #include @@ -32,12 +36,11 @@ #include -#include "include/hw/t234/hw_pmasys_soc_hwpm.h" -#include "include/hw/t234/hw_pmmsys_soc_hwpm.h" -#include "include/hw/t234/hw_addr_map_soc_hwpm.h" - -#include "tegra-soc-hwpm.h" -#include "tegra-soc-hwpm-io.h" +#include +#include +#include "tegra-soc-hwpm-log.h" +#include +#include #define LA_CLK_RATE 625000000UL @@ -182,179 +185,14 @@ static int timer_relation_ioctl(struct tegra_soc_hwpm *hwpm, } -static u32 **get_mc_fake_regs(struct tegra_soc_hwpm *hwpm, - struct hwpm_resource_aperture *aperture) -{ - if (!hwpm->fake_registers_enabled) - return NULL; - if (!aperture) { - tegra_soc_hwpm_err("aperture is NULL"); - return NULL; - } - switch (aperture->start_pa) { - case addr_map_mc0_base_r(): - return &mc_fake_regs[0]; - case addr_map_mc1_base_r(): - return &mc_fake_regs[1]; - case addr_map_mc2_base_r(): - return &mc_fake_regs[2]; - case addr_map_mc3_base_r(): - return &mc_fake_regs[3]; - case addr_map_mc4_base_r(): - return &mc_fake_regs[4]; - case addr_map_mc5_base_r(): - return &mc_fake_regs[5]; - case addr_map_mc6_base_r(): - return &mc_fake_regs[6]; - case addr_map_mc7_base_r(): - return &mc_fake_regs[7]; - case addr_map_mc8_base_r(): - return &mc_fake_regs[8]; - case addr_map_mc9_base_r(): - return &mc_fake_regs[9]; - case addr_map_mc10_base_r(): - return &mc_fake_regs[10]; - case addr_map_mc11_base_r(): - return &mc_fake_regs[11]; - case addr_map_mc12_base_r(): - return &mc_fake_regs[12]; - case addr_map_mc13_base_r(): - return &mc_fake_regs[13]; - case addr_map_mc14_base_r(): - return &mc_fake_regs[14]; - case addr_map_mc15_base_r(): - return &mc_fake_regs[15]; - default: - return NULL; - } -} - -static void set_mc_fake_regs(struct tegra_soc_hwpm *hwpm, - struct hwpm_resource_aperture *aperture, - bool set_null) -{ - u32 *fake_regs = NULL; - - if (!aperture) { - tegra_soc_hwpm_err("aperture is NULL"); - return; - } - - switch (aperture->start_pa) { - case addr_map_mc0_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[0]; - t234_mss_channel_map[0].fake_registers = fake_regs; - t234_mss_iso_niso_hub_map[0].fake_registers = fake_regs; - t234_mss_mcf_map[0].fake_registers = fake_regs; - break; - case addr_map_mc1_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[1]; - t234_mss_channel_map[1].fake_registers = fake_regs; - t234_mss_iso_niso_hub_map[1].fake_registers = fake_regs; - t234_mss_mcf_map[1].fake_registers = fake_regs; - break; - case addr_map_mc2_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[2]; - t234_mss_channel_map[2].fake_registers = fake_regs; - t234_mss_iso_niso_hub_map[2].fake_registers = fake_regs; - t234_mss_mcf_map[2].fake_registers = fake_regs; - break; - case addr_map_mc3_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[3]; - t234_mss_channel_map[3].fake_registers = fake_regs; - t234_mss_iso_niso_hub_map[3].fake_registers = fake_regs; - t234_mss_mcf_map[3].fake_registers = fake_regs; - break; - case addr_map_mc4_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[4]; - t234_mss_channel_map[4].fake_registers = fake_regs; - t234_mss_iso_niso_hub_map[4].fake_registers = fake_regs; - t234_mss_mcf_map[4].fake_registers = fake_regs; - break; - case addr_map_mc5_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[5]; - t234_mss_channel_map[5].fake_registers = fake_regs; - t234_mss_iso_niso_hub_map[5].fake_registers = fake_regs; - t234_mss_mcf_map[5].fake_registers = fake_regs; - break; - case addr_map_mc6_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[6]; - t234_mss_channel_map[6].fake_registers = fake_regs; - t234_mss_iso_niso_hub_map[6].fake_registers = fake_regs; - t234_mss_mcf_map[6].fake_registers = fake_regs; - break; - case addr_map_mc7_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[7]; - t234_mss_channel_map[7].fake_registers = fake_regs; - t234_mss_iso_niso_hub_map[7].fake_registers = fake_regs; - t234_mss_mcf_map[7].fake_registers = fake_regs; - break; - case addr_map_mc8_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[8]; - t234_mss_channel_map[8].fake_registers = fake_regs; - t234_mss_iso_niso_hub_map[8].fake_registers = fake_regs; - break; - case addr_map_mc9_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[9]; - t234_mss_channel_map[9].fake_registers = fake_regs; - break; - case addr_map_mc10_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[10]; - t234_mss_channel_map[10].fake_registers = fake_regs; - break; - case addr_map_mc11_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[11]; - t234_mss_channel_map[11].fake_registers = fake_regs; - break; - case addr_map_mc12_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[12]; - t234_mss_channel_map[12].fake_registers = fake_regs; - break; - case addr_map_mc13_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[13]; - t234_mss_channel_map[13].fake_registers = fake_regs; - break; - case addr_map_mc14_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[14]; - t234_mss_channel_map[14].fake_registers = fake_regs; - break; - case addr_map_mc15_base_r(): - fake_regs = (!hwpm->fake_registers_enabled || set_null) ? - NULL : mc_fake_regs[15]; - t234_mss_channel_map[15].fake_registers = fake_regs; - break; - default: - break; - } -} static int reserve_resource_ioctl(struct tegra_soc_hwpm *hwpm, void *ioctl_struct) { - int ret = 0; struct tegra_soc_hwpm_reserve_resource *reserve_resource = (struct tegra_soc_hwpm_reserve_resource *)ioctl_struct; u32 resource = reserve_resource->resource; - struct hwpm_resource_aperture *aperture = NULL; - int aprt_idx = 0; - struct tegra_soc_hwpm_ip_ops *ip_ops; - int err; if (hwpm->bind_completed) { tegra_soc_hwpm_err("The RESERVE_RESOURCE IOCTL can only be" @@ -379,159 +217,12 @@ static int reserve_resource_ioctl(struct tegra_soc_hwpm *hwpm, * FIXME: Tell IPs which are being profiled to power up IP and * disable power management */ - /* Map reserved apertures and allocate fake register arrays if needed */ - for (aprt_idx = 0; - aprt_idx < hwpm_resources[resource].map_size; - aprt_idx++) { - aperture = &(hwpm_resources[resource].map[aprt_idx]); - if ((aperture->dt_aperture == TEGRA_SOC_HWPM_PMA_DT) || - (aperture->dt_aperture == TEGRA_SOC_HWPM_RTR_DT)) { - /* PMA and RTR apertures are handled in open(fd) */ - continue; - } else if ((aperture->dt_aperture == TEGRA_SOC_HWPM_SYS0_PERFMON_DT) || - ((hwpm->ip_fs_info[resource] & aperture->index_mask) != 0U)) { - if (IS_PERFMON(aperture->dt_aperture)) { - struct resource *res = NULL; - u64 num_regs = 0; - - tegra_soc_hwpm_dbg("Found PERFMON(0x%llx - 0x%llx)", - aperture->start_pa, aperture->end_pa); - ip_ops = &hwpm->ip_info[aperture->dt_aperture]; - if (ip_ops && (*ip_ops->hwpm_ip_pm)) { - err = (*ip_ops->hwpm_ip_pm) - (ip_ops->ip_dev, true); - if (err) { - tegra_soc_hwpm_err( - "Disable Runtime PM(%d) Failed", - aperture->dt_aperture); - } - } else { - tegra_soc_hwpm_dbg( - "No Runtime PM(%d) for IP", - aperture->dt_aperture); - } - hwpm->dt_apertures[aperture->dt_aperture] = - of_iomap(hwpm->np, aperture->dt_aperture); - if (!hwpm->dt_apertures[aperture->dt_aperture]) { - tegra_soc_hwpm_err("Couldn't map PERFMON(%d)", - aperture->dt_aperture); - ret = -ENOMEM; - goto fail; - } - - res = platform_get_resource(hwpm->pdev, - IORESOURCE_MEM, - aperture->dt_aperture); - if ((!res) || (res->start == 0) || (res->end == 0)) { - tegra_soc_hwpm_err("Invalid resource for PERFMON(%d)", - aperture->dt_aperture); - ret = -ENOMEM; - goto fail; - } - aperture->start_pa = res->start; - aperture->end_pa = res->end; - - if (hwpm->fake_registers_enabled) { - num_regs = (aperture->end_pa + 1 - aperture->start_pa) / - sizeof(*aperture->fake_registers); - aperture->fake_registers = - (u32 *)kzalloc(sizeof(*aperture->fake_registers) * - num_regs, - GFP_KERNEL); - if (!aperture->fake_registers) { - tegra_soc_hwpm_err("Aperture(0x%llx - 0x%llx):" - " Couldn't allocate memory for fake" - " registers", - aperture->start_pa, - aperture->end_pa); - ret = -ENOMEM; - goto fail; - } - } - } else { /* IP apertures */ - if (hwpm->fake_registers_enabled) { - u64 num_regs = 0; - u32 **fake_regs = get_mc_fake_regs(hwpm, aperture); - if (!fake_regs) - fake_regs = &aperture->fake_registers; - - num_regs = (aperture->end_pa + 1 - aperture->start_pa) / - sizeof(*(*fake_regs)); - *fake_regs = - (u32 *)kzalloc(sizeof(*(*fake_regs)) * num_regs, - GFP_KERNEL); - if (!(*fake_regs)) { - tegra_soc_hwpm_err("Aperture(0x%llx - 0x%llx):" - " Couldn't allocate memory for fake" - " registers", - aperture->start_pa, - aperture->end_pa); - ret = -ENOMEM; - goto fail; - } - - set_mc_fake_regs(hwpm, aperture, false); - } - } - } else { - tegra_soc_hwpm_dbg("resource %d index_mask %d not available", - resource, aperture->index_mask); - } - } - - hwpm_resources[resource].reserved = true; - goto success; - -fail: - for (aprt_idx = 0; - aprt_idx < hwpm_resources[resource].map_size; - aprt_idx++) { - aperture = &(hwpm_resources[resource].map[aprt_idx]); - if ((aperture->dt_aperture == TEGRA_SOC_HWPM_PMA_DT) || - (aperture->dt_aperture == TEGRA_SOC_HWPM_RTR_DT)) { - /* PMA and RTR apertures are handled in open(fd) */ - continue; - } else if ((aperture->dt_aperture == TEGRA_SOC_HWPM_SYS0_PERFMON_DT) || - ((hwpm->ip_fs_info[resource] & aperture->index_mask) != 0U)) { - if (IS_PERFMON(aperture->dt_aperture)) { - if (hwpm->dt_apertures[aperture->dt_aperture]) { - iounmap(hwpm->dt_apertures[aperture->dt_aperture]); - hwpm->dt_apertures[aperture->dt_aperture] = NULL; - } - - aperture->start_pa = 0; - aperture->end_pa = 0; - - if (aperture->fake_registers) { - kfree(aperture->fake_registers); - aperture->fake_registers = NULL; - } - } else { /* IP apertures */ - if (aperture->fake_registers) { - kfree(aperture->fake_registers); - aperture->fake_registers = NULL; - set_mc_fake_regs(hwpm, aperture, true); - } - } - } - } - - hwpm_resources[resource].reserved = false; - -success: - return ret; - + return tegra_soc_hwpm_reserve_given_resource(hwpm, resource); } static int alloc_pma_stream_ioctl(struct tegra_soc_hwpm *hwpm, void *ioctl_struct) { - int ret = 0; - u32 reg_val = 0; - u32 outbase_lo = 0; - u32 outbase_hi = 0; - u32 outsize = 0; - u32 mem_bytes_addr = 0; struct tegra_soc_hwpm_alloc_pma_stream *alloc_pma_stream = (struct tegra_soc_hwpm_alloc_pma_stream *)ioctl_struct; @@ -554,216 +245,15 @@ static int alloc_pma_stream_ioctl(struct tegra_soc_hwpm *hwpm, return -EINVAL; } - /* Memory map stream buffer */ - hwpm->stream_dma_buf = dma_buf_get(alloc_pma_stream->stream_buf_fd); - if (IS_ERR(hwpm->stream_dma_buf)) { - tegra_soc_hwpm_err("Unable to get stream dma_buf"); - ret = PTR_ERR(hwpm->stream_dma_buf); - goto fail; - } - hwpm->stream_attach = dma_buf_attach(hwpm->stream_dma_buf, hwpm->dev); - if (IS_ERR(hwpm->stream_attach)) { - tegra_soc_hwpm_err("Unable to attach stream dma_buf"); - ret = PTR_ERR(hwpm->stream_attach); - goto fail; - } - hwpm->stream_sgt = dma_buf_map_attachment(hwpm->stream_attach, - DMA_FROM_DEVICE); - if (IS_ERR(hwpm->stream_sgt)) { - tegra_soc_hwpm_err("Unable to map stream attachment"); - ret = PTR_ERR(hwpm->stream_sgt); - goto fail; - } - alloc_pma_stream->stream_buf_pma_va = - sg_dma_address(hwpm->stream_sgt->sgl); - if (alloc_pma_stream->stream_buf_pma_va == 0) { - tegra_soc_hwpm_err("Invalid stream buffer SMMU IOVA"); - ret = -ENXIO; - goto fail; - } - tegra_soc_hwpm_dbg("stream_buf_pma_va = 0x%llx", - alloc_pma_stream->stream_buf_pma_va); - - /* Memory map mem bytes buffer */ - hwpm->mem_bytes_dma_buf = - dma_buf_get(alloc_pma_stream->mem_bytes_buf_fd); - if (IS_ERR(hwpm->mem_bytes_dma_buf)) { - tegra_soc_hwpm_err("Unable to get mem bytes dma_buf"); - ret = PTR_ERR(hwpm->mem_bytes_dma_buf); - goto fail; - } - hwpm->mem_bytes_attach = dma_buf_attach(hwpm->mem_bytes_dma_buf, - hwpm->dev); - if (IS_ERR(hwpm->mem_bytes_attach)) { - tegra_soc_hwpm_err("Unable to attach mem bytes dma_buf"); - ret = PTR_ERR(hwpm->mem_bytes_attach); - goto fail; - } - hwpm->mem_bytes_sgt = dma_buf_map_attachment(hwpm->mem_bytes_attach, - DMA_FROM_DEVICE); - if (IS_ERR(hwpm->mem_bytes_sgt)) { - tegra_soc_hwpm_err("Unable to map mem bytes attachment"); - ret = PTR_ERR(hwpm->mem_bytes_sgt); - goto fail; - } - hwpm->mem_bytes_kernel = dma_buf_vmap(hwpm->mem_bytes_dma_buf); - if (!hwpm->mem_bytes_kernel) { - tegra_soc_hwpm_err( - "Unable to map mem_bytes buffer into kernel VA space"); - ret = -ENOMEM; - goto fail; - } - memset(hwpm->mem_bytes_kernel, 0, 32); - - outbase_lo = alloc_pma_stream->stream_buf_pma_va & - pmasys_channel_outbase_ptr_m(); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_outbase_r(0) - addr_map_pma_base_r(), - outbase_lo); - tegra_soc_hwpm_dbg("OUTBASE = 0x%x", reg_val); - - outbase_hi = (alloc_pma_stream->stream_buf_pma_va >> 32) & - pmasys_channel_outbaseupper_ptr_m(); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_outbaseupper_r(0) - addr_map_pma_base_r(), - outbase_hi); - tegra_soc_hwpm_dbg("OUTBASEUPPER = 0x%x", reg_val); - - outsize = alloc_pma_stream->stream_buf_size & - pmasys_channel_outsize_numbytes_m(); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_outsize_r(0) - addr_map_pma_base_r(), - outsize); - tegra_soc_hwpm_dbg("OUTSIZE = 0x%x", reg_val); - - mem_bytes_addr = sg_dma_address(hwpm->mem_bytes_sgt->sgl) & - pmasys_channel_mem_bytes_addr_ptr_m(); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_mem_bytes_addr_r(0) - addr_map_pma_base_r(), - mem_bytes_addr); - tegra_soc_hwpm_dbg("MEM_BYTES_ADDR = 0x%x", reg_val); - - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_mem_block_r(0) - addr_map_pma_base_r(), - pmasys_channel_mem_block_valid_f( - pmasys_channel_mem_block_valid_true_v())); - - return 0; - -fail: - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_mem_block_r(0) - addr_map_pma_base_r(), - pmasys_channel_mem_block_valid_f( - pmasys_channel_mem_block_valid_false_v())); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_outbase_r(0) - addr_map_pma_base_r(), 0); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_outbaseupper_r(0) - addr_map_pma_base_r(), 0); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_outsize_r(0) - addr_map_pma_base_r(), 0); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_mem_bytes_addr_r(0) - addr_map_pma_base_r(), 0); - - alloc_pma_stream->stream_buf_pma_va = 0; - - if (hwpm->stream_sgt && (!IS_ERR(hwpm->stream_sgt))) { - dma_buf_unmap_attachment(hwpm->stream_attach, - hwpm->stream_sgt, - DMA_FROM_DEVICE); - } - hwpm->stream_sgt = NULL; - - if (hwpm->stream_attach && (!IS_ERR(hwpm->stream_attach))) { - dma_buf_detach(hwpm->stream_dma_buf, hwpm->stream_attach); - } - hwpm->stream_attach = NULL; - - if (hwpm->stream_dma_buf && (!IS_ERR(hwpm->stream_dma_buf))) { - dma_buf_put(hwpm->stream_dma_buf); - } - hwpm->stream_dma_buf = NULL; - - if (hwpm->mem_bytes_kernel) { - dma_buf_vunmap(hwpm->mem_bytes_dma_buf, - hwpm->mem_bytes_kernel); - hwpm->mem_bytes_kernel = NULL; - } - if (hwpm->mem_bytes_sgt && (!IS_ERR(hwpm->mem_bytes_sgt))) { - dma_buf_unmap_attachment(hwpm->mem_bytes_attach, - hwpm->mem_bytes_sgt, - DMA_FROM_DEVICE); - } - hwpm->mem_bytes_sgt = NULL; - - if (hwpm->mem_bytes_attach && (!IS_ERR(hwpm->mem_bytes_attach))) { - dma_buf_detach(hwpm->mem_bytes_dma_buf, hwpm->mem_bytes_attach); - } - hwpm->mem_bytes_attach = NULL; - - if (hwpm->mem_bytes_dma_buf && (!IS_ERR(hwpm->mem_bytes_dma_buf))) { - dma_buf_put(hwpm->mem_bytes_dma_buf); - } - hwpm->mem_bytes_dma_buf = NULL; - - return ret; + return tegra_soc_hwpm_stream_buf_map(hwpm, alloc_pma_stream); } static int bind_ioctl(struct tegra_soc_hwpm *hwpm, void *ioctl_struct) { - int ret = 0; - int res_idx = 0; - int aprt_idx = 0; - struct hwpm_resource_aperture *aperture = NULL; - - for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { - if (!hwpm_resources[res_idx].reserved) - continue; - tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx); - - for (aprt_idx = 0; - aprt_idx < hwpm_resources[res_idx].map_size; - aprt_idx++) { - aperture = &(hwpm_resources[res_idx].map[aprt_idx]); - - if ((res_idx == TEGRA_SOC_HWPM_RESOURCE_PMA) || - (res_idx == TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR) || - (res_idx == TEGRA_SOC_HWPM_SYS0_PERFMON_DT) || - ((hwpm->ip_fs_info[res_idx] & aperture->index_mask) != 0U)) { - - /* Zero out necessary registers */ - if (aperture->alist) { - tegra_soc_hwpm_zero_alist_regs(hwpm, aperture); - } else { - tegra_soc_hwpm_err( - "NULL allowlist in aperture(0x%llx - 0x%llx)", - aperture->start_pa, aperture->end_pa); - } - - /* - * Enable reporting of PERFMON status to - * NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED - */ - if (IS_PERFMON(aperture->dt_aperture)) { - tegra_soc_hwpm_dbg("Found PERFMON(0x%llx - 0x%llx)", - aperture->start_pa, - aperture->end_pa); - ret = reg_rmw(hwpm, NULL, aperture->dt_aperture, - pmmsys_sys0_enginestatus_r(0) - - addr_map_rpg_pm_base_r(), - pmmsys_sys0_enginestatus_enable_m(), - pmmsys_sys0_enginestatus_enable_out_f(), - false, false); - if (ret < 0) { - tegra_soc_hwpm_err("Unable to set PMM ENGINESTATUS_ENABLE" - " for PERFMON(0x%llx - 0x%llx)", - aperture->start_pa, - aperture->end_pa); - return -EIO; - } - } - } - } + if (tegra_soc_hwpm_bind_resources(hwpm)) { + tegra_soc_hwpm_err("Failed to bind resources"); + return -EIO; } hwpm->bind_completed = true; @@ -774,9 +264,6 @@ static int query_allowlist_ioctl(struct tegra_soc_hwpm *hwpm, void *ioctl_struct) { int ret = 0; - int res_idx = 0; - int aprt_idx = 0; - struct hwpm_resource_aperture *aperture = NULL; struct tegra_soc_hwpm_query_allowlist *query_allowlist = (struct tegra_soc_hwpm_query_allowlist *)ioctl_struct; @@ -799,24 +286,7 @@ static int query_allowlist_ioctl(struct tegra_soc_hwpm *hwpm, } hwpm->full_alist_size = 0; - for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { - if (!(hwpm_resources[res_idx].reserved)) - continue; - tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx); - - for (aprt_idx = 0; - aprt_idx < hwpm_resources[res_idx].map_size; - aprt_idx++) { - aperture = &(hwpm_resources[res_idx].map[aprt_idx]); - if (aperture->alist) { - hwpm->full_alist_size += aperture->alist_size; - } else { - tegra_soc_hwpm_err( - "NULL allowlist in aperture(0x%llx - 0x%llx)", - aperture->start_pa, aperture->end_pa); - } - } - } + tegra_soc_hwpm_get_full_allowlist(hwpm); query_allowlist->allowlist_size = hwpm->full_alist_size; return ret; @@ -867,7 +337,7 @@ static int exec_reg_ops_ioctl(struct tegra_soc_hwpm *hwpm, op_idx, reg_op->phys_addr, reg_op->cmd); /* The allowlist check is done here */ - aperture = find_hwpm_aperture(hwpm, reg_op->phys_addr, + aperture = tegra_soc_hwpm_find_aperture(hwpm, reg_op->phys_addr, true, true, &upadted_pa); if (!aperture) { REG_OP_FAIL(INSUFFICIENT_PERMISSIONS, @@ -951,10 +421,6 @@ static int exec_reg_ops_ioctl(struct tegra_soc_hwpm *hwpm, static int update_get_put_ioctl(struct tegra_soc_hwpm *hwpm, void *ioctl_struct) { - int ret = 0; - u32 reg_val = 0; - u32 field_val = 0; - u32 *mem_bytes_kernel_u32 = NULL; struct tegra_soc_hwpm_update_get_put *update_get_put = (struct tegra_soc_hwpm_update_get_put *)ioctl_struct; @@ -968,49 +434,7 @@ static int update_get_put_ioctl(struct tegra_soc_hwpm *hwpm, return -ENXIO; } - /* Update SW get pointer */ - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_mem_bump_r(0) - addr_map_pma_base_r(), - update_get_put->mem_bump); - - /* Stream MEM_BYTES value to MEM_BYTES buffer */ - if (update_get_put->b_stream_mem_bytes) { - mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_bytes_kernel); - *mem_bytes_kernel_u32 = TEGRA_SOC_HWPM_MEM_BYTES_INVALID; - ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_control_user_r(0) - addr_map_pma_base_r(), - pmasys_channel_control_user_update_bytes_m(), - pmasys_channel_control_user_update_bytes_doit_f(), - false, false); - if (ret < 0) { - tegra_soc_hwpm_err("Failed to stream mem_bytes to buffer"); - return -EIO; - } - } - - /* Read HW put pointer */ - if (update_get_put->b_read_mem_head) { - update_get_put->mem_head = hwpm_readl(hwpm, - TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_mem_head_r(0) - addr_map_pma_base_r()); - tegra_soc_hwpm_dbg("MEM_HEAD = 0x%llx", - update_get_put->mem_head); - } - - /* Check overflow error status */ - if (update_get_put->b_check_overflow) { - reg_val = hwpm_readl(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_status_secure_r(0) - - addr_map_pma_base_r()); - field_val = pmasys_channel_status_secure_membuf_status_v( - reg_val); - update_get_put->b_overflowed = (field_val == - pmasys_channel_status_secure_membuf_status_overflowed_v()); - tegra_soc_hwpm_dbg("OVERFLOWED = %u", - update_get_put->b_overflowed); - } - - return 0; + return tegra_soc_hwpm_update_mem_bytes(hwpm, update_get_put); } static long tegra_soc_hwpm_ioctl(struct file *file, @@ -1102,27 +526,12 @@ cleanup: return ret; } -/* - * Normally there is a 1-to-1 mapping between an MMIO aperture and a - * hwpm_resource_aperture struct. But the PMA MMIO aperture is used in - * multiple hwpm_resource_aperture structs. Therefore, we have to share the fake - * register array between these hwpm_resource_aperture structs. This is why we - * have to define the fake register array globally. For all other 1-to-1 - * mapping apertures the fake register arrays are directly embedded inside the - * hwpm_resource_aperture structs. - */ -static u32 *pma_fake_regs; - static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp) { int ret = 0; unsigned int minor = iminor(inode); struct tegra_soc_hwpm *hwpm = NULL; - struct resource *res = NULL; - u32 field_mask = 0U; - u32 field_val = 0U; u32 i; - u64 num_regs = 0; if (!inode) { tegra_soc_hwpm_err("Invalid inode"); @@ -1198,151 +607,27 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp) for (i = 0U; i < TERGA_SOC_HWPM_NUM_IPS; i++) { hwpm->ip_fs_info[i] = 0ULL; } - if (tegra_platform_is_vsp()) { - /* Static IP instances as per VSP netlist */ - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_VIC] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_CHANNEL] = 0xF; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_GPU_HUB] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_MCF] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_NVLINK] = 0x1; - } - if (tegra_platform_is_silicon()) { - /* Static IP instances corresponding to silicon */ - // hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_VI] = 0x3; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_ISP] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_VIC] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_OFA] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_PVA] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_NVDLA] = 0x3; - // hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MGBE] = 0xF; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_SCF] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_NVDEC] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_NVENC] = 0x1; - // hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_PCIE] = 0x32; - // hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_DISPLAY] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_CHANNEL] = 0xFFFF; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_GPU_HUB] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_MCF] = 0x1; - hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_NVLINK] = 0x1; + + /* Map PMA and RTR apertures */ + ret = tegra_soc_hwpm_fs_info_init(hwpm); + if (ret < 0) { + tegra_soc_hwpm_err("Unable to initialize fs fs_info"); + ret = -EIO; + goto fail; } /* Map PMA and RTR apertures */ - hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT] = - of_iomap(hwpm->np, TEGRA_SOC_HWPM_PMA_DT); - if (!hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT]) { - tegra_soc_hwpm_err("Couldn't map the PMA aperture"); - ret = -ENOMEM; + ret = tegra_soc_hwpm_pma_rtr_map(hwpm); + if (ret < 0) { + tegra_soc_hwpm_err("Unable to reserve PMA RTR apertures"); + ret = -EIO; goto fail; } - res = platform_get_resource(hwpm->pdev, - IORESOURCE_MEM, - TEGRA_SOC_HWPM_PMA_DT); - if ((!res) || (res->start == 0) || (res->end == 0)) { - tegra_soc_hwpm_err("Invalid resource for PMA"); - ret = -ENOMEM; - goto fail; - } - t234_pma_map[1].start_pa = res->start; - t234_pma_map[1].end_pa = res->end; - t234_cmd_slice_rtr_map[0].start_pa = res->start; - t234_cmd_slice_rtr_map[0].end_pa = res->end; - if (hwpm->fake_registers_enabled) { - num_regs = (res->end + 1 - res->start) / sizeof(*pma_fake_regs); - pma_fake_regs = (u32 *)kzalloc(sizeof(*pma_fake_regs) * num_regs, - GFP_KERNEL); - if (!pma_fake_regs) { - tegra_soc_hwpm_err("Couldn't allocate memory for PMA" - " fake registers"); - ret = -ENOMEM; - goto fail; - } - t234_pma_map[1].fake_registers = pma_fake_regs; - t234_cmd_slice_rtr_map[0].fake_registers = pma_fake_regs; - } - - hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_PMA].reserved = true; - - hwpm->dt_apertures[TEGRA_SOC_HWPM_RTR_DT] = - of_iomap(hwpm->np, TEGRA_SOC_HWPM_RTR_DT); - if (!hwpm->dt_apertures[TEGRA_SOC_HWPM_RTR_DT]) { - tegra_soc_hwpm_err("Couldn't map the RTR aperture"); - ret = -ENOMEM; - goto fail; - } - res = platform_get_resource(hwpm->pdev, - IORESOURCE_MEM, - TEGRA_SOC_HWPM_RTR_DT); - if ((!res) || (res->start == 0) || (res->end == 0)) { - tegra_soc_hwpm_err("Invalid resource for RTR"); - ret = -ENOMEM; - goto fail; - } - t234_cmd_slice_rtr_map[1].start_pa = res->start; - t234_cmd_slice_rtr_map[1].end_pa = res->end; - if (hwpm->fake_registers_enabled) { - num_regs = (res->end + 1 - res->start) / - sizeof(*t234_cmd_slice_rtr_map[1].fake_registers); - t234_cmd_slice_rtr_map[1].fake_registers = - (u32 *)kzalloc(sizeof(*t234_cmd_slice_rtr_map[1].fake_registers) * - num_regs, - GFP_KERNEL); - if (!t234_cmd_slice_rtr_map[1].fake_registers) { - tegra_soc_hwpm_err("Couldn't allocate memory for RTR" - " fake registers"); - ret = -ENOMEM; - goto fail; - } - } - hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR].reserved = true; /* Disable SLCG */ - ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, - pmasys_cg2_r() - addr_map_pma_base_r(), - pmasys_cg2_slcg_m(), pmasys_cg2_slcg_disabled_f(), - false, false); + ret = tegra_soc_hwpm_disable_slcg(hwpm); if (ret < 0) { - tegra_soc_hwpm_err("Unable to disable PMA SLCG"); - ret = -EIO; - goto fail; - } - - field_mask = pmmsys_sys0router_cg2_slcg_perfmon_m() | - pmmsys_sys0router_cg2_slcg_router_m() | - pmmsys_sys0router_cg2_slcg_m(); - field_val = pmmsys_sys0router_cg2_slcg_perfmon_disabled_f() | - pmmsys_sys0router_cg2_slcg_router_disabled_f() | - pmmsys_sys0router_cg2_slcg_disabled_f(); - ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_RTR_DT, - pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(), - field_mask, field_val, false, false); - if (ret < 0) { - tegra_soc_hwpm_err("Unable to disable ROUTER SLCG"); - ret = -EIO; - goto fail; - } - - /* Program PROD values */ - ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, - pmasys_controlb_r() - addr_map_pma_base_r(), - pmasys_controlb_coalesce_timeout_cycles_m(), - pmasys_controlb_coalesce_timeout_cycles__prod_f(), - false, false); - if (ret < 0) { - tegra_soc_hwpm_err("Unable to program PROD value"); - ret = -EIO; - goto fail; - } - - ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_config_user_r(0) - addr_map_pma_base_r(), - pmasys_channel_config_user_coalesce_timeout_cycles_m(), - pmasys_channel_config_user_coalesce_timeout_cycles__prod_f(), - false, false); - if (ret < 0) { - tegra_soc_hwpm_err("Unable to program PROD value"); - ret = -EIO; + tegra_soc_hwpm_err("Unable to disable SLCG"); goto fail; } @@ -1353,33 +638,7 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp) return 0; fail: - if (hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT]) { - iounmap(hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT]); - hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT] = NULL; - } - t234_pma_map[1].start_pa = 0; - t234_pma_map[1].end_pa = 0; - t234_cmd_slice_rtr_map[0].start_pa = 0; - t234_cmd_slice_rtr_map[0].end_pa = 0; - if (pma_fake_regs) { - kfree(pma_fake_regs); - pma_fake_regs = NULL; - t234_pma_map[1].fake_registers = NULL; - t234_cmd_slice_rtr_map[0].fake_registers = NULL; - } - hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_PMA].reserved = false; - - if (hwpm->dt_apertures[TEGRA_SOC_HWPM_RTR_DT]) { - iounmap(hwpm->dt_apertures[TEGRA_SOC_HWPM_RTR_DT]); - hwpm->dt_apertures[TEGRA_SOC_HWPM_RTR_DT] = NULL; - } - t234_cmd_slice_rtr_map[1].start_pa = 0; - t234_cmd_slice_rtr_map[1].end_pa = 0; - if (t234_cmd_slice_rtr_map[1].fake_registers) { - kfree(t234_cmd_slice_rtr_map[1].fake_registers); - t234_cmd_slice_rtr_map[1].fake_registers = NULL; - } - hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR].reserved = false; + tegra_soc_hwpm_pma_rtr_unmap(hwpm); tegra_soc_hwpm_err("%s failed", __func__); return ret; @@ -1398,23 +657,7 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp) { int err = 0; int ret = 0; - bool timeout = false; - int res_idx = 0; - int aprt_idx = 0; - u32 field_mask = 0; - u32 field_val = 0; - u32 *mem_bytes_kernel_u32 = NULL; struct tegra_soc_hwpm *hwpm = NULL; - struct hwpm_resource_aperture *aperture = NULL; - struct tegra_soc_hwpm_ip_ops *ip_ops; -#define RELEASE_FAIL(msg, ...) \ - do { \ - if (err < 0) { \ - tegra_soc_hwpm_err(msg, ##__VA_ARGS__); \ - if (ret == 0) \ - ret = err; \ - } \ - } while (0) if (!inode) { tegra_soc_hwpm_err("Invalid inode"); @@ -1431,267 +674,37 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp) return -EINVAL; } - /* Disable PMA triggers */ - err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, - pmasys_trigger_config_user_r(0) - addr_map_pma_base_r(), - pmasys_trigger_config_user_pma_pulse_m(), - pmasys_trigger_config_user_pma_pulse_disable_f(), - false, false); - RELEASE_FAIL("Unable to disable PMA triggers"); - - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_sys_trigger_start_mask_r() - addr_map_pma_base_r(), 0); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_sys_trigger_start_maskb_r() - addr_map_pma_base_r(), 0); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_sys_trigger_stop_mask_r() - addr_map_pma_base_r(), 0); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_sys_trigger_stop_maskb_r() - addr_map_pma_base_r(), 0); - - /* Wait for PERFMONs, ROUTER, and PMA to idle */ - timeout = HWPM_TIMEOUT(pmmsys_sys0router_perfmonstatus_merged_v( - hwpm_readl(hwpm, TEGRA_SOC_HWPM_RTR_DT, - pmmsys_sys0router_perfmonstatus_r() - - addr_map_rtr_base_r())) == 0U, - "NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_EMPTY"); - if (timeout && ret == 0) { - ret = -EIO; + ret = tegra_soc_hwpm_disable_pma_triggers(hwpm); + if (ret != 0) { + return ret; } - timeout = HWPM_TIMEOUT(pmmsys_sys0router_enginestatus_status_v( - hwpm_readl(hwpm, TEGRA_SOC_HWPM_RTR_DT, - pmmsys_sys0router_enginestatus_r() - - addr_map_rtr_base_r())) == - pmmsys_sys0router_enginestatus_status_empty_v(), - "NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_EMPTY"); - if (timeout && ret == 0) { - ret = -EIO; - } - - field_mask = pmasys_enginestatus_status_m() | - pmasys_enginestatus_rbufempty_m(); - field_val = pmasys_enginestatus_status_empty_f() | - pmasys_enginestatus_rbufempty_empty_f(); - timeout = HWPM_TIMEOUT((hwpm_readl(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_enginestatus_r() - - addr_map_pma_base_r()) & field_mask) == field_val, - "NV_PERF_PMASYS_ENGINESTATUS"); - if (timeout && ret == 0) { - ret = -EIO; - } - - hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_PMA].reserved = false; - hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR].reserved = false; - /* Disable all PERFMONs */ tegra_soc_hwpm_dbg("Disabling PERFMONs"); - for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { - if (!hwpm_resources[res_idx].reserved) - continue; - tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx); + tegra_soc_hwpm_disable_perfmons(hwpm); - for (aprt_idx = 0; - aprt_idx < hwpm_resources[res_idx].map_size; - aprt_idx++) { - aperture = &(hwpm_resources[res_idx].map[aprt_idx]); - if (IS_PERFMON(aperture->dt_aperture)) { - if ((res_idx == TEGRA_SOC_HWPM_RESOURCE_PMA) || - (res_idx == TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR) || - (res_idx == TEGRA_SOC_HWPM_SYS0_PERFMON_DT) || - ((hwpm->ip_fs_info[res_idx] & aperture->index_mask) != 0U)) { - tegra_soc_hwpm_dbg("Found PERFMON(0x%llx - 0x%llx)", - aperture->start_pa, - aperture->end_pa); - err = reg_rmw(hwpm, NULL, aperture->dt_aperture, - pmmsys_control_r(0) - addr_map_rpg_pm_base_r(), - pmmsys_control_mode_m(), - pmmsys_control_mode_disable_f(), - false, false); - RELEASE_FAIL("Unable to disable PERFMON(0x%llx - 0x%llx)", - aperture->start_pa, - aperture->end_pa); - ip_ops = &hwpm->ip_info[aperture->dt_aperture]; - if (ip_ops && (*ip_ops->hwpm_ip_pm)) { - err = (*ip_ops->hwpm_ip_pm) - (ip_ops->ip_dev, false); - if (err) { - tegra_soc_hwpm_err( - "Enable Runtime PM(%d) Failed", - aperture->dt_aperture); - } - } else { - tegra_soc_hwpm_dbg( - "No Runtime PM(%d) for IP", - aperture->dt_aperture); - } - } - } - } + /* Clear MEM_BYTES pipeline */ + err = tegra_soc_hwpm_clear_pipeline(hwpm); + if (err < 0) { + tegra_soc_hwpm_err("Failed to clear MEM_BYTES pipeline"); + return err; } - /* Stream MEM_BYTES to clear pipeline */ - if (hwpm->mem_bytes_kernel) { - mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_bytes_kernel); - *mem_bytes_kernel_u32 = TEGRA_SOC_HWPM_MEM_BYTES_INVALID; - err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_control_user_r(0) - addr_map_pma_base_r(), - pmasys_channel_control_user_update_bytes_m(), - pmasys_channel_control_user_update_bytes_doit_f(), - false, false); - RELEASE_FAIL("Unable to stream MEM_BYTES"); - timeout = HWPM_TIMEOUT(*mem_bytes_kernel_u32 != - TEGRA_SOC_HWPM_MEM_BYTES_INVALID, - "MEM_BYTES streaming"); - if (timeout && ret == 0) - ret = -EIO; - } - - /* Disable PMA streaming */ - err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, - pmasys_trigger_config_user_r(0) - addr_map_pma_base_r(), - pmasys_trigger_config_user_record_stream_m(), - pmasys_trigger_config_user_record_stream_disable_f(), - false, false); - RELEASE_FAIL("Unable to disable PMA streaming"); - - err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_control_user_r(0) - addr_map_pma_base_r(), - pmasys_channel_control_user_stream_m(), - pmasys_channel_control_user_stream_disable_f(), - false, false); - RELEASE_FAIL("Unable to disable PMA streaming"); - - /* Memory Management */ - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_outbase_r(0) - addr_map_pma_base_r(), 0); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_outbaseupper_r(0) - addr_map_pma_base_r(), 0); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_outsize_r(0) - addr_map_pma_base_r(), 0); - hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT, - pmasys_channel_mem_bytes_addr_r(0) - addr_map_pma_base_r(), 0); - - if (hwpm->stream_sgt && (!IS_ERR(hwpm->stream_sgt))) { - dma_buf_unmap_attachment(hwpm->stream_attach, - hwpm->stream_sgt, - DMA_FROM_DEVICE); - } - hwpm->stream_sgt = NULL; - - if (hwpm->stream_attach && (!IS_ERR(hwpm->stream_attach))) { - dma_buf_detach(hwpm->stream_dma_buf, hwpm->stream_attach); - } - hwpm->stream_attach = NULL; - - if (hwpm->stream_dma_buf && (!IS_ERR(hwpm->stream_dma_buf))) { - dma_buf_put(hwpm->stream_dma_buf); - } - hwpm->stream_dma_buf = NULL; - - if (hwpm->mem_bytes_kernel) { - dma_buf_vunmap(hwpm->mem_bytes_dma_buf, - hwpm->mem_bytes_kernel); - hwpm->mem_bytes_kernel = NULL; - } - - if (hwpm->mem_bytes_sgt && (!IS_ERR(hwpm->mem_bytes_sgt))) { - dma_buf_unmap_attachment(hwpm->mem_bytes_attach, - hwpm->mem_bytes_sgt, - DMA_FROM_DEVICE); - } - hwpm->mem_bytes_sgt = NULL; - - if (hwpm->mem_bytes_attach && (!IS_ERR(hwpm->mem_bytes_attach))) { - dma_buf_detach(hwpm->mem_bytes_dma_buf, hwpm->mem_bytes_attach); - } - hwpm->mem_bytes_attach = NULL; - - if (hwpm->mem_bytes_dma_buf && (!IS_ERR(hwpm->mem_bytes_dma_buf))) { - dma_buf_put(hwpm->mem_bytes_dma_buf); - } - hwpm->mem_bytes_dma_buf = NULL; - /* Enable SLCG */ - err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, - pmasys_cg2_r() - addr_map_pma_base_r(), - pmasys_cg2_slcg_m(), - pmasys_cg2_slcg_enabled_f(), false, false); - RELEASE_FAIL("Unable to enable PMA SLCG"); - - field_mask = pmmsys_sys0router_cg2_slcg_perfmon_m() | - pmmsys_sys0router_cg2_slcg_router_m() | - pmmsys_sys0router_cg2_slcg_m(); - field_val = pmmsys_sys0router_cg2_slcg_perfmon__prod_f() | - pmmsys_sys0router_cg2_slcg_router__prod_f() | - pmmsys_sys0router_cg2_slcg__prod_f(); - err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_RTR_DT, - pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(), - field_mask, field_val, false, false); - RELEASE_FAIL("Unable to enable ROUTER SLCG"); + err = tegra_soc_hwpm_enable_slcg(hwpm); + if (err != 0) { + tegra_soc_hwpm_err("Unable to enable SLCG"); + return err; + } /* Unmap PMA and RTR apertures */ - tegra_soc_hwpm_dbg("Unmapping apertures"); - if (hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT]) { - iounmap(hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT]); - hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT] = NULL; - } - t234_pma_map[1].start_pa = 0; - t234_pma_map[1].end_pa = 0; - t234_cmd_slice_rtr_map[0].start_pa = 0; - t234_cmd_slice_rtr_map[0].end_pa = 0; - if (pma_fake_regs) { - kfree(pma_fake_regs); - pma_fake_regs = NULL; - t234_pma_map[1].fake_registers = NULL; - t234_cmd_slice_rtr_map[0].fake_registers = NULL; - } - if (hwpm->dt_apertures[TEGRA_SOC_HWPM_RTR_DT]) { - iounmap(hwpm->dt_apertures[TEGRA_SOC_HWPM_RTR_DT]); - hwpm->dt_apertures[TEGRA_SOC_HWPM_RTR_DT] = NULL; - } - t234_cmd_slice_rtr_map[1].start_pa = 0; - t234_cmd_slice_rtr_map[1].end_pa = 0; - if (t234_cmd_slice_rtr_map[1].fake_registers) { - kfree(t234_cmd_slice_rtr_map[1].fake_registers); - t234_cmd_slice_rtr_map[1].fake_registers = NULL; + err = tegra_soc_hwpm_pma_rtr_unmap(hwpm); + if (err != 0) { + tegra_soc_hwpm_err("Unable to unmap PMA and RTR"); + return err; } - /* Reset resource and aperture state */ - for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) { - if (!hwpm_resources[res_idx].reserved) - continue; - hwpm_resources[res_idx].reserved = false; - - for (aprt_idx = 0; - aprt_idx < hwpm_resources[res_idx].map_size; - aprt_idx++) { - aperture = &(hwpm_resources[res_idx].map[aprt_idx]); - if ((aperture->dt_aperture == TEGRA_SOC_HWPM_PMA_DT) || - (aperture->dt_aperture == TEGRA_SOC_HWPM_RTR_DT)) { - /* PMA and RTR apertures are handled separately */ - continue; - } else if (IS_PERFMON(aperture->dt_aperture)) { - if (hwpm->dt_apertures[aperture->dt_aperture]) { - iounmap(hwpm->dt_apertures[aperture->dt_aperture]); - hwpm->dt_apertures[aperture->dt_aperture] = NULL; - } - - aperture->start_pa = 0; - aperture->end_pa = 0; - - if (aperture->fake_registers) { - kfree(aperture->fake_registers); - aperture->fake_registers = NULL; - } - } else { /* IP apertures */ - if (aperture->fake_registers) { - kfree(aperture->fake_registers); - aperture->fake_registers = NULL; - set_mc_fake_regs(hwpm, aperture, true); - } - } - } - } + tegra_soc_hwpm_reset_resources(hwpm); if (tegra_platform_is_silicon()) { err = reset_control_assert(hwpm->hwpm_rst); diff --git a/tegra-soc-hwpm-ip.c b/tegra-soc-hwpm-ip.c index 9e5e10a..8507723 100644 --- a/tegra-soc-hwpm-ip.c +++ b/tegra-soc-hwpm-ip.c @@ -17,34 +17,18 @@ * This file contains functions for SOC HWPM <-> IPC communication. */ - #include +#include +#include +#include "tegra-soc-hwpm-log.h" #include "tegra-soc-hwpm.h" struct platform_device *tegra_soc_hwpm_pdev; -static enum tegra_soc_hwpm_dt_aperture tegra_soc_hwpm_get_apeture( - struct tegra_soc_hwpm *hwpm, u64 ip_base_address) -{ - enum tegra_soc_hwpm_dt_aperture aperture = - TEGRA_SOC_HWPM_NUM_DT_APERTURES; - - /* TODO chip speciifc implementation for finding aperture */ - if (ip_base_address == addr_map_vic_base_r()) { - aperture = TEGRA_SOC_HWPM_VICA0_PERFMON_DT; - } else if (ip_base_address == addr_map_nvenc_base_r()) { - aperture = TEGRA_SOC_HWPM_NVENCA0_PERFMON_DT; - } else if (ip_base_address == addr_map_ofa_base_r()) { - aperture = TEGRA_SOC_HWPM_OFAA0_PERFMON_DT; - } - - return aperture; -} - void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops) { struct tegra_soc_hwpm *hwpm = NULL; - enum tegra_soc_hwpm_dt_aperture dt_aperture; + u32 dt_aperture; tegra_soc_hwpm_dbg("HWPM Registered IP 0x%llx", hwpm_ip_ops->ip_base_address); @@ -59,9 +43,9 @@ void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops) return; } hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev); - dt_aperture = tegra_soc_hwpm_get_apeture(hwpm, - hwpm_ip_ops->ip_base_address); - if (dt_aperture != TEGRA_SOC_HWPM_NUM_DT_APERTURES) { + dt_aperture = tegra_soc_hwpm_get_ip_aperture(hwpm, + hwpm_ip_ops->ip_base_address, NULL); + if (dt_aperture != TEGRA_SOC_HWPM_DT_APERTURE_INVALID) { memcpy(&hwpm->ip_info[dt_aperture], hwpm_ip_ops, sizeof(struct tegra_soc_hwpm_ip_ops)); } else { @@ -76,7 +60,7 @@ void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops) void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops) { struct tegra_soc_hwpm *hwpm = NULL; - enum tegra_soc_hwpm_dt_aperture dt_aperture; + u32 dt_aperture; if (tegra_soc_hwpm_pdev == NULL) { tegra_soc_hwpm_dbg("IP unregister before SOC HWPM 0x%llx", @@ -87,9 +71,9 @@ void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops) return; } hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev); - dt_aperture = tegra_soc_hwpm_get_apeture(hwpm, - hwpm_ip_ops->ip_base_address); - if (dt_aperture != TEGRA_SOC_HWPM_NUM_DT_APERTURES) { + dt_aperture = tegra_soc_hwpm_get_ip_aperture(hwpm, + hwpm_ip_ops->ip_base_address, NULL); + if (dt_aperture != TEGRA_SOC_HWPM_DT_APERTURE_INVALID) { memset(&hwpm->ip_info[dt_aperture], 0, sizeof(struct tegra_soc_hwpm_ip_ops)); } diff --git a/tegra-soc-hwpm-log.c b/tegra-soc-hwpm-log.c index 0ea0ebb..e96975c 100644 --- a/tegra-soc-hwpm-log.c +++ b/tegra-soc-hwpm-log.c @@ -20,6 +20,7 @@ #include #include "tegra-soc-hwpm.h" +#include "tegra-soc-hwpm-log.h" #define LOG_BUF_SIZE 160 diff --git a/tegra-soc-hwpm.c b/tegra-soc-hwpm.c index 1772634..2887977 100644 --- a/tegra-soc-hwpm.c +++ b/tegra-soc-hwpm.c @@ -22,10 +22,17 @@ #include #include #include +#include +#include +#include +#include #include #include "tegra-soc-hwpm.h" +#include "tegra-soc-hwpm-log.h" +#include +#include static const struct of_device_id tegra_soc_hwpm_of_match[] = { { @@ -125,6 +132,8 @@ static int tegra_soc_hwpm_probe(struct platform_device *pdev) } tegra_soc_hwpm_debugfs_init(hwpm); + hwpm->dt_apertures = tegra_soc_hwpm_init_dt_apertures(); + hwpm->ip_info = tegra_soc_hwpm_init_ip_ops_info(); /* * Currently VDK doesn't have a fmodel for SOC HWPM. Therefore, we diff --git a/tegra-soc-hwpm.h b/tegra-soc-hwpm.h index 0ebd618..1be0836 100644 --- a/tegra-soc-hwpm.h +++ b/tegra-soc-hwpm.h @@ -20,84 +20,15 @@ #ifndef TEGRA_SOC_HWPM_H #define TEGRA_SOC_HWPM_H -#include -#include -#include -#include -#include -#include -#include -#include -#include +// +// +// #include +// -#include "tegra-soc-hwpm-log.h" -#include "tegra-soc-hwpm-hw.h" -#include +// #include "tegra-soc-hwpm-log.h" +// -/* FIXME: Default timeout is 1 sec. Is this sufficient for pre-si? */ -#define HWPM_TIMEOUT(timeout_check, expiry_msg) ({ \ - bool timeout_expired = false; \ - s32 timeout_msecs = 1000; \ - u32 sleep_msecs = 100; \ - while(!(timeout_check)) { \ - msleep(sleep_msecs); \ - timeout_msecs -= sleep_msecs; \ - if (timeout_msecs <= 0) { \ - tegra_soc_hwpm_err("Timeout expired for %s!", \ - expiry_msg); \ - timeout_expired = true; \ - break; \ - } \ - } \ - timeout_expired; \ -}) - -/* Driver struct */ -struct tegra_soc_hwpm { - /* Device */ - struct platform_device *pdev; - struct device *dev; - struct device_node *np; - struct class class; - dev_t dev_t; - struct cdev cdev; - - /* IP floorsweep info */ - u64 ip_fs_info[TERGA_SOC_HWPM_NUM_IPS]; - - /* MMIO apertures in device tree */ - void __iomem *dt_apertures[TEGRA_SOC_HWPM_NUM_DT_APERTURES]; - - /* Clocks and resets */ - struct clk *la_clk; - struct clk *la_parent_clk; - struct reset_control *la_rst; - struct reset_control *hwpm_rst; - - struct tegra_soc_hwpm_ip_ops ip_info[TEGRA_SOC_HWPM_NUM_DT_APERTURES]; - - /* Memory Management */ - struct dma_buf *stream_dma_buf; - struct dma_buf_attachment *stream_attach; - struct sg_table *stream_sgt; - struct dma_buf *mem_bytes_dma_buf; - struct dma_buf_attachment *mem_bytes_attach; - struct sg_table *mem_bytes_sgt; - void *mem_bytes_kernel; - - /* SW State */ - bool bind_completed; - s32 full_alist_size; - - /* Debugging */ -#ifdef CONFIG_DEBUG_FS - struct dentry *debugfs_root; -#endif - bool fake_registers_enabled; -}; - -extern struct platform_device *tegra_soc_hwpm_pdev; -extern const struct file_operations tegra_soc_hwpm_ops; +struct tegra_soc_hwpm; #ifdef CONFIG_DEBUG_FS void tegra_soc_hwpm_debugfs_init(struct tegra_soc_hwpm *hwpm);