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tegra: hwpm: add userspace test for next4

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Add unit test for next4.

JIRA MSST-831

Change-Id: If59fbff5f6d9a61fbcda8c0213f236d0acce8062
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3333470
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Yifei Wan <ywan@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Besar Wicaksono
2025-04-03 20:55:28 +00:00
committed by mobile promotions
parent 106bc61f86
commit 4d309240ac
5 changed files with 1892 additions and 85 deletions
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2
libnvsochwpm/test/Makefile
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@@ -24,6 +24,7 @@ endif
SOURCES = \ SOURCES = \
nv_soc_hwpm_test.cpp \ nv_soc_hwpm_test.cpp \
t241_test.cpp \ t241_test.cpp \
t410_test.cpp \
soc_mode_e_buffer.cpp soc_mode_e_buffer.cpp
OBJECTS=$(foreach x, $(basename $(SOURCES)), $(x).o) OBJECTS=$(foreach x, $(basename $(SOURCES)), $(x).o)
@@ -43,6 +44,7 @@ CXXFLAGS += -I$(NV_SOURCE)/3rdparty/google/googletest/googletest/include
CXXFLAGS += -I$(NV_SOURCE)/3rdparty/google/googletest/googletest/ CXXFLAGS += -I$(NV_SOURCE)/3rdparty/google/googletest/googletest/
CXXFLAGS += -I$(NV_SOURCE)/hwinc-private/th500/66838280 CXXFLAGS += -I$(NV_SOURCE)/hwinc-private/th500/66838280
CXXFLAGS += -I$(NV_SOURCE)/hwinc-private/tb500/84849639
GTEST_SOURCES += \ GTEST_SOURCES += \
$(NV_SOURCE)/3rdparty/google/googletest/googletest/src/gtest-all.cc \ $(NV_SOURCE)/3rdparty/google/googletest/googletest/src/gtest-all.cc \

120
libnvsochwpm/test/ip_names.h Normal file
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@@ -0,0 +1,120 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef IP_NAMES_H
#define IP_NAMES_H
#include "nv_soc_hwpm.h"
static const char *kIpNames[NV_SOC_HWPM_NUM_IPS] = {
"VI",
"ISP",
"VIC",
"OFA",
"PVA",
"NVDLA",
"MGBE",
"SCF",
"NVDEC",
"NVENC",
"PCIE",
"DISPLAY",
"MSS_CHANNEL",
"MSS_GPU_HUB",
"MSS_ISO_NISO_HUBS",
"MSS_MCF",
"APE",
"C2C",
"SMMU",
"CL2",
"NVLCTRL",
"NVLRX",
"NVLTX",
"MSS_HUB",
"MCF_SOC",
"MCF_C2C",
"MCF_CLINK",
"MCF_CORE",
"MCF_OCU",
"PCIE_XTLQ",
"PCIE_XTLRC",
"PCIE_XALRC",
"UCF_MSW",
"UCF_PSW",
"UCF_CSW",
"UCF_HUB",
"UCF_SCB",
"CPU",
"CPU_EXT_0",
"CPU_EXT_1",
"CPU_EXT_2",
"NVTHERM",
"CSN",
"CSN_EXT_0",
"CSNH",
};
static const char *kResourceNames[NV_SOC_HWPM_NUM_RESOURCES] = {
"VI",
"ISP",
"VIC",
"OFA",
"PVA",
"NVDLA",
"MGBE",
"SCF",
"NVDEC",
"NVENC",
"PCIE",
"DISPLAY",
"MSS_CHANNEL",
"MSS_GPU_HUB",
"MSS_ISO_NISO_HUBS",
"MSS_MCF",
"PMA",
"CMD_SLICE_RTR",
"APE",
"C2C",
"SMMU",
"CL2",
"NVLCTRL",
"NVLRX",
"NVLTX",
"MSS_HUB",
"MCF_SOC",
"MCF_C2C",
"MCF_CLINK",
"MCF_CORE",
"MCF_OCU",
"PCIE_XTLQ",
"PCIE_XTLRC",
"PCIE_XALRC",
"UCF_MSW",
"UCF_PSW",
"UCF_CSW",
"UCF_HUB",
"UCF_SCB",
"CPU",
"CPU_EXT_0",
"CPU_EXT_1",
"CPU_EXT_2",
"NVTHERM",
"CSN",
"CSN_EXT_0",
"CSNH",
};
#endif // IP_NAMES_H

86
libnvsochwpm/test/t241_test.cpp
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@@ -16,93 +16,9 @@
#include "soc_mode_e_buffer.h" #include "soc_mode_e_buffer.h"
#include "common/register_util.h" #include "common/register_util.h"
#include "th500/nv_ref_dev_perf.h" #include "th500/nv_ref_dev_perf.h"
#include "ip_names.h"
#include <unistd.h> #include <unistd.h>
static const char* kIpNames[] = {
"VI",
"ISP",
"VIC",
"OFA",
"PVA",
"NVDLA",
"MGBE",
"SCF",
"NVDEC",
"NVENC",
"PCIE",
"DISPLAY",
"MSS_CHANNEL",
"MSS_GPU_HUB",
"MSS_ISO_NISO_HUBS",
"MSS_MCF",
"APE",
"C2C",
"SMMU",
"CL2",
"NVLCTRL",
"NVLRX",
"NVLTX",
"MSS_HUB",
"MCF_SOC",
"MCF_C2C",
"MCF_CLINK",
"MCF_CORE",
"MCF_OCU",
"PCIE_XTLQ",
"PCIE_XTLRC",
"PCIE_XALRC",
"UCF_MSW",
"UCF_PSW",
"UCF_CSW",
"UCF_HUB",
"UCF_SCB",
"CPU",
};
static const char* kResourceNames[] = {
"VI",
"ISP",
"VIC",
"OFA",
"PVA",
"NVDLA",
"MGBE",
"SCF",
"NVDEC",
"NVENC",
"PCIE",
"DISPLAY",
"MSS_CHANNEL",
"MSS_GPU_HUB",
"MSS_ISO_NISO_HUBS",
"MSS_MCF",
"PMA",
"CMD_SLICE_RTR",
"APE",
"C2C",
"SMMU",
"CL2",
"NVLCTRL",
"NVLRX",
"NVLTX",
"MSS_HUB",
"MCF_SOC",
"MCF_C2C",
"MCF_CLINK",
"MCF_CORE",
"MCF_OCU",
"PCIE_XTLQ",
"PCIE_XTLRC",
"PCIE_XALRC",
"UCF_MSW",
"UCF_PSW",
"UCF_CSW",
"UCF_HUB",
"UCF_SCB",
"CPU",
};
T241Tests::T241Tests() : NvSocHwpmTests(), t241_dev_count(0) T241Tests::T241Tests() : NvSocHwpmTests(), t241_dev_count(0)
{ {
} }

1672
libnvsochwpm/test/t410_test.cpp Normal file
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97
libnvsochwpm/test/t410_test.h Normal file
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@@ -0,0 +1,97 @@
/*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto. Any use, reproduction, disclosure or
* distribution of this software and related documentation without an express
* license agreement from NVIDIA CORPORATION is strictly prohibited.
*/
#ifndef T410_TEST_H
#define T410_TEST_H
#include "nv_soc_hwpm_test.h"
#define T410_MAX_SOCKETS 2
class T410Tests : public NvSocHwpmTests
{
public:
T410Tests();
~T410Tests() override;
protected:
struct PmaConfigurationParams {
PmaConfigurationParams()
{
enable_streaming = false;
pulse_interval = 0;
enable_pma_record = false;
keep_latest = false;
}
bool enable_streaming;
uint32_t pulse_interval;
bool enable_pma_record;
bool keep_latest;
};
struct PmmConfigurationParams {
enum Mode {
MODE_B,
MODE_C,
MODE_E
};
PmmConfigurationParams()
{
mode = MODE_B;
perfmon_idx = 0;
enable_local_triggering = false;
enable_overflow_priming = false;
collect_one = false;
}
Mode mode;
uint32_t perfmon_idx;
bool enable_local_triggering;
bool enable_overflow_priming;
bool collect_one;
};
void SetUp(void) override;
void TearDown(void) override;
void GetDevices(void);
void TestRegopsRead(nv_soc_hwpm_session session,
uint64_t pma_record_buffer_pma_va,
size_t record_buffer_size);
void TestRegopsWrite(nv_soc_hwpm_session session);
void RegOpWrite32(
nv_soc_hwpm_session session, uint64_t address, uint32_t value, uint32_t mask);
void RegOpRead32(
nv_soc_hwpm_session session, uint64_t address, uint32_t *value);
void SetupPma(nv_soc_hwpm_session session, const PmaConfigurationParams &params);
void EnablePmaStreaming(nv_soc_hwpm_session session, const PmaConfigurationParams &params);
void SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationParams &params);
void SetupWatchbus(nv_soc_hwpm_session session, const PmmConfigurationParams &params);
void TeardownPma(nv_soc_hwpm_session session);
void TeardownPmm(nv_soc_hwpm_session session, const PmmConfigurationParams &params);
void TeardownPerfmux(nv_soc_hwpm_session session);
void IssuePmaTrigger(nv_soc_hwpm_session session);
void HarvestCounters(
nv_soc_hwpm_session session,
const PmmConfigurationParams &params,
const uint32_t sig_val[4]);
nv_soc_hwpm_device t410_dev[T410_MAX_SOCKETS];
uint32_t t410_dev_count;
};
#endif // T410_TEST_H