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tegra: hwpm: clean up code and add bug fixes

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- Create tegra_hwpm_element_enable() instead of directly using
perfmon_enable() HAL. This will allow us to expand
tegra_hwpm_element_enable in future.
- Update log messages in ip structure init code and floorsweep info
function.
- It is possible that IP instances and elements to have 0 start range
address. So, modify check for available elements to use range end
instead.
- Use tegra_hwpm_fake_readl() and tegra_hwpm_fake_writel() macros
instead of fake_readl() and fake_write() functions. That way we have
similar implementation of IO functions and macros can be used across
OSes.
- Check that reserve perfmon function is invoked only for HWPM
components. This check will be useful for expansion in types of
components in the future.
- Clean up and rearrange tegra_hwpm_regops_readl_impl() and
tegra_hwpm_regops_writel_impl() to have designated code corresponding to
the element type.
- Currently, device open and release functions are incorrectly using
clock enable/disable functions instead of using HALs. Correct open and
close functions to use lock HALs.
- Currently, tegra_hwpm_update_mem_bytes() doesn't validate mem_mgmt
structure allocation before accessing mem_bytes_kernel pointer. This can
lead to kernel crash. Update tegra_hwpm_update_mem_bytes() to return
error if mem_mgmt structure s not allocated.

Jira THWPM-74

Change-Id: Ia40bd51187e5ea08572dbee81e577dacf5fb66b6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
(cherry picked from commit 411f07484d68dfde0d350a5c67f2748e876b11b8)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2888553
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2023-02-27 10:56:15 -08:00
committed by mobile promotions
parent 5c6e6f4797
commit 4ecc672c3e
8 changed files with 137 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

80
drivers/tegra/hwpm/os/linux/io_utils.c
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@@ -44,7 +44,7 @@ int tegra_hwpm_read_sticky_bits_impl(struct tegra_soc_hwpm *hwpm,
return 0;
}
static int fake_readl(struct tegra_soc_hwpm *hwpm,
int tegra_hwpm_fake_readl_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_aperture *aperture, u64 offset, u32 *val)
{
if (!hwpm->fake_registers_enabled) {
@@ -56,7 +56,7 @@ static int fake_readl(struct tegra_soc_hwpm *hwpm,
return 0;
}
static int fake_writel(struct tegra_soc_hwpm *hwpm,
int tegra_hwpm_fake_writel_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_aperture *aperture, u64 offset, u32 val)
{
if (!hwpm->fake_registers_enabled) {
@@ -80,7 +80,7 @@ static int ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
aperture->start_abs_pa, aperture->end_abs_pa, offset);
if (hwpm->fake_registers_enabled) {
return fake_readl(hwpm, aperture, offset, val);
return tegra_hwpm_fake_readl(hwpm, aperture, offset, val);
} else {
struct tegra_hwpm_ip_ops *ip_ops_ptr = &ip_inst->ip_ops;
if (ip_ops_ptr->hwpm_ip_reg_op != NULL) {
@@ -128,7 +128,7 @@ static int ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
aperture->start_abs_pa, aperture->end_abs_pa, offset, val);
if (hwpm->fake_registers_enabled) {
return fake_writel(hwpm, aperture, offset, val);
return tegra_hwpm_fake_writel(hwpm, aperture, offset, val);
} else {
struct tegra_hwpm_ip_ops *ip_ops_ptr = &ip_inst->ip_ops;
if (ip_ops_ptr->hwpm_ip_reg_op != NULL) {
@@ -176,7 +176,7 @@ static int hwpm_readl(struct tegra_soc_hwpm *hwpm,
aperture->start_abs_pa, aperture->end_abs_pa, offset);
if (hwpm->fake_registers_enabled) {
return fake_readl(hwpm, aperture, offset, val);
return tegra_hwpm_fake_readl(hwpm, aperture, offset, val);
} else {
if (aperture->dt_mmio == NULL) {
tegra_hwpm_err(hwpm,
@@ -197,14 +197,12 @@ static int hwpm_readl(struct tegra_soc_hwpm *hwpm,
static int hwpm_writel(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_aperture *aperture, u64 offset, u32 val)
{
int err = 0;
tegra_hwpm_dbg(hwpm, hwpm_register,
"Aperture (0x%llx-0x%llx) offset(0x%llx) val(0x%x)",
aperture->start_abs_pa, aperture->end_abs_pa, offset, val);
if (hwpm->fake_registers_enabled) {
err = fake_writel(hwpm, aperture, offset, val);
return tegra_hwpm_fake_writel(hwpm, aperture, offset, val);
} else {
if (aperture->dt_mmio == NULL) {
tegra_hwpm_err(hwpm,
@@ -215,7 +213,7 @@ static int hwpm_writel(struct tegra_soc_hwpm *hwpm,
writel(val, aperture->dt_mmio + offset);
}
return err;
return 0;
}
/*
@@ -290,9 +288,6 @@ int tegra_hwpm_regops_readl_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture,
u64 addr, u32 *val)
{
u64 reg_offset = 0ULL;
int err = 0;
tegra_hwpm_fn(hwpm, " ");
if (!aperture) {
@@ -300,20 +295,29 @@ int tegra_hwpm_regops_readl_impl(struct tegra_soc_hwpm *hwpm,
return -ENODEV;
}
/*
* Register address passed to this function always belong to
* virtual address range of the aperture.
* Hence, subtract start_abs_pa from given addr for offset.
*/
reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa);
if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
err = hwpm_readl(hwpm, aperture, reg_offset, val);
/*
* Register address passed to this function always belong to
* virtual address range of the aperture.
* Hence, subtract start_abs_pa from given addr for offset.
*/
u64 reg_offset = tegra_hwpm_safe_sub_u64(addr,
aperture->start_abs_pa);
return hwpm_readl(hwpm, aperture, reg_offset, val);
} else {
err = ip_readl(hwpm, ip_inst, aperture, reg_offset, val);
/*
* Register address passed to this function always belong to
* virtual address range of the aperture.
* Hence, subtract start_abs_pa from given addr for offset.
*/
u64 reg_offset = tegra_hwpm_safe_sub_u64(addr,
aperture->start_abs_pa);
return ip_readl(hwpm, ip_inst, aperture, reg_offset, val);
}
return err;
return 0;
}
/*
@@ -324,9 +328,6 @@ int tegra_hwpm_regops_writel_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture,
u64 addr, u32 val)
{
u64 reg_offset = 0ULL;
int err = 0;
tegra_hwpm_fn(hwpm, " ");
if (!aperture) {
@@ -334,18 +335,27 @@ int tegra_hwpm_regops_writel_impl(struct tegra_soc_hwpm *hwpm,
return -ENODEV;
}
/*
* Register address passed to this function always belong to
* virtual address range of the aperture.
* Hence, subtract start_abs_pa from given addr for offset.
*/
reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa);
if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
err = hwpm_writel(hwpm, aperture, reg_offset, val);
/*
* Register address passed to this function always belong to
* virtual address range of the aperture.
* Hence, subtract start_abs_pa from given addr for offset.
*/
u64 reg_offset = tegra_hwpm_safe_sub_u64(addr,
aperture->start_abs_pa);
return hwpm_writel(hwpm, aperture, reg_offset, val);
} else {
err = ip_writel(hwpm, ip_inst, aperture, reg_offset, val);
/*
* Register address passed to this function always belong to
* virtual address range of the aperture.
* Hence, subtract start_abs_pa from given addr for offset.
*/
u64 reg_offset = tegra_hwpm_safe_sub_u64(addr,
aperture->start_abs_pa);
return ip_writel(hwpm, ip_inst, aperture, reg_offset, val);
}
return err;
return 0;
}