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tegra: hwpm: update element fs mask at open

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IPs supported for performance management register themselves with
required funtion pointers. The HWPM driver processes the request and
marks the given IP instance valid.
To mark elements of the registered IP instance valid, HWPM reads one of
the allowlist registers. Register read is essential to confirm
availability of the element. Register reads for floorswept elements
should return with error.

Currently, HWPM driver marks all elements of an IP instance as available
at registration time. The process to update element mask considering
floorswept elements is performed during IP reservation.
Users querying floorsweeping info before reservation ioctls would
receive incorrect fs_info masks.

To fix this issue, move updating of IP instance element fs_info at
device open. If device is already opened, update element mask during
registration.
- Implement TEGRA_HWPM_UPDATE_IP_INST_MASK case to update element fs
mask for given IP.

Bug 3685203
Bug 3584061

Change-Id: If992204e6f7debf24b36a94f2b752b5077333cda
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2734732
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vedashree Vidwans
2022-06-23 22:37:19 -07:00
committed by mobile promotions
parent 1563712b77
commit 56007741bc
4 changed files with 90 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
common/tegra_hwpm_ip_utils.c
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@@ -99,32 +99,6 @@ int tegra_hwpm_ip_handle_power_mgmt(struct tegra_soc_hwpm *hwpm,
return err;
}
static int tegra_hwpm_update_ip_inst_element_fs_mask(
struct tegra_soc_hwpm *hwpm,
u32 ip_idx, u32 a_type, u32 inst_idx, bool available)
{
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_idx];
struct hwpm_ip_inst_per_aperture_info *inst_a_info =
&chip_ip->inst_aperture_info[a_type];
struct hwpm_ip_inst *ip_inst = inst_a_info->inst_arr[inst_idx];
struct hwpm_ip_element_info *perfmux_info =
&ip_inst->element_info[TEGRA_HWPM_APERTURE_TYPE_PERFMUX];
struct hwpm_ip_aperture *perfmux = NULL;
u32 idx = 0U;
tegra_hwpm_fn(hwpm, " ");
/* Only perfmuxes are essential for element_fs_mask */
for (idx = 0U; idx < perfmux_info->num_element_per_inst; idx++) {
perfmux = &perfmux_info->element_static_array[idx];
ip_inst->element_fs_mask |= perfmux->element_index_mask;
}
return 0;
}
static int tegra_hwpm_update_ip_inst_fs_mask(struct tegra_soc_hwpm *hwpm,
u32 ip_idx, u32 a_type, u32 inst_idx, bool available)
{
@@ -133,6 +107,7 @@ static int tegra_hwpm_update_ip_inst_fs_mask(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_inst_per_aperture_info *inst_a_info =
&chip_ip->inst_aperture_info[a_type];
struct hwpm_ip_inst *ip_inst = inst_a_info->inst_arr[inst_idx];
int ret = 0;
tegra_hwpm_fn(hwpm, " ");
@@ -140,6 +115,22 @@ static int tegra_hwpm_update_ip_inst_fs_mask(struct tegra_soc_hwpm *hwpm,
if (available) {
chip_ip->inst_fs_mask |= ip_inst->hw_inst_mask;
chip_ip->resource_status = TEGRA_HWPM_RESOURCE_STATUS_VALID;
if (hwpm->device_opened) {
/*
* IP fs_info is updated during device open call
* However, if IP registers after HWPM device was open,
* this function call will update IP element mask
*/
ret = tegra_hwpm_func_single_ip(hwpm, NULL,
TEGRA_HWPM_UPDATE_IP_INST_MASK, ip_idx);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"IP %d Failed to update fs_info",
ip_idx);
return ret;
}
}
} else {
chip_ip->inst_fs_mask &= ~(ip_inst->hw_inst_mask);
if (chip_ip->inst_fs_mask == 0U) {
@@ -148,8 +139,7 @@ static int tegra_hwpm_update_ip_inst_fs_mask(struct tegra_soc_hwpm *hwpm,
}
}
return tegra_hwpm_update_ip_inst_element_fs_mask(hwpm, ip_idx,
a_type, inst_idx, available);
return 0;
}
static int tegra_hwpm_update_ip_ops_info(struct tegra_soc_hwpm *hwpm,