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tegra: hwpm: add force enable IP flag

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Implement flag to enable IP force_enable. IP force_enable expects full
chip config of the IP. Hence, this macro should be enabled only for
full chip configs.

Jira THWPM-41
Bug 3435091

Change-Id: Ic2f669fee4e58a22ae20cc435bf627cd37d46e7e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2717980
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vedashree Vidwans
2022-05-24 16:54:03 -07:00
committed by mobile promotions
parent bd8ca72dc2
commit 6d0e0ee04d
2 changed files with 47 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

58
hal/t234/t234_hwpm_ip_utils.c
View File

@@ -276,10 +276,11 @@ int t234_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm)
int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
{
int ret = 0, err = 0;
int ret = 0;
tegra_hwpm_fn(hwpm, " ");
#if defined(CONFIG_HWPM_ALLOW_FORCE_ENABLE)
if (tegra_platform_is_vsp()) {
/* Static IP instances as per VSP netlist */
/* MSS CHANNEL: vsp has single instance available */
@@ -290,7 +291,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_MSS_CHANNEL force enable failed");
err = ret;
return ret;
}
#endif
#if defined(CONFIG_SOC_HWPM_IP_MSS_GPU_HUB)
@@ -302,7 +303,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_MSS_GPU_HUB force enable failed");
err = ret;
return ret;
}
#endif
}
@@ -317,7 +318,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_VI force enable failed");
err = ret;
return ret;
}
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_vi2_thi_base_r(),
@@ -325,7 +326,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_VI force enable failed");
err = ret;
return ret;
}
#endif
*/
@@ -337,7 +338,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_ISP force enable failed");
err = ret;
return ret;
}
#endif
@@ -364,22 +365,11 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_MGBE force enable failed");
err = ret;
return ret;
}
#endif
*/
#if defined(CONFIG_SOC_HWPM_IP_SCF)
/* SCF */
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_rpg_pm_scf_base_r(),
T234_HWPM_IP_SCF, true);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_SCF force enable failed");
err = ret;
}
#endif
#if defined(CONFIG_SOC_HWPM_IP_NVDEC)
/* NVDEC */
@@ -389,7 +379,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_NVDEC force enable failed");
err = ret;
return ret;
}
#endif
@@ -402,7 +392,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_PCIE force enable failed");
err = ret;
return ret;
}
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_pcie_c4_ctl_base_r(),
@@ -410,7 +400,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_PCIE force enable failed");
err = ret;
return ret;
}
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_pcie_c5_ctl_base_r(),
@@ -418,7 +408,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_PCIE force enable failed");
err = ret;
return ret;
}
#endif
*/
@@ -432,7 +422,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_DISPLAY force enable failed");
err = ret;
return ret;
}
#endif
*/
@@ -445,12 +435,28 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_MSS_GPU_HUB force enable failed");
err = ret;
return ret;
}
#endif
}
#endif
/*
* SCF is an independent IP with a single perfmon only.
* SCF should not be part of force enable config flag.
*/
#if defined(CONFIG_SOC_HWPM_IP_SCF)
/* SCF */
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_rpg_pm_scf_base_r(),
T234_HWPM_IP_SCF, true);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_SCF force enable failed");
return ret;
}
#endif
return err;
return 0;
}
int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,

15
include/tegra_hwpm.h
View File

@@ -83,6 +83,21 @@ struct tegra_hwpm_ip_ops {
u32 *reg_data);
};
/*
* One of the HWPM components is a perfmux. Perfmux registers belong to the
* IP domain. There are 2 ways of accessing perfmux registers
* - option 1: implement HWPM <-> IP interface. IP drivers register with HWPM
* driver and share required function pointers
* - option 2: map perfmux register address in HWPM driver
* Option 1 is a preferred solution. However, IP drivers have yet to
* implement the interface. Such IPs can be force enabled from HWPM driver
* perspective. However, forcing an IP will enable all instances of the IP.
* Hence, IP force enable should only be done on full chip config.
* Note as power management API is not available, unpowergating the IP via
* command line is required.
*/
/*#define CONFIG_HWPM_ALLOW_FORCE_ENABLE*/
/* There are 3 types of HWPM components/apertures */
#define TEGRA_HWPM_APERTURE_TYPE_PERFMUX 0U
#define TEGRA_HWPM_APERTURE_TYPE_BROADCAST 1U