From 6e75fd7b504f395df71a63b274eb5bce6db749c3 Mon Sep 17 00:00:00 2001 From: Vishal Aslot Date: Fri, 29 Sep 2023 15:09:16 +0000 Subject: [PATCH] tegra: hwpm: th500: Add support for CL2 This patch adds support for CL2 (LTS) performance monitoring in the driver. Bug 4287384 Signed-off-by: Vishal Aslot Change-Id: Ieed663f0149bc52576fcf6d71de0e627b11fdc84 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2988343 Reviewed-by: Vedashree Vidwans GVS: Gerrit_Virtual_Submit --- drivers/tegra/hwpm/Makefile.th500.soc.sources | 3 + .../th500/soc/hw/th500_addr_map_soc_hwpm.h | 64 +- .../hwpm/hal/th500/soc/ip/cl2/th500_cl2.c | 1042 +++++++++++++++++ .../hwpm/hal/th500/soc/ip/cl2/th500_cl2.h | 48 + .../soc/th500_soc_perfmon_device_index.h | 32 +- .../th500/soc/th500_soc_regops_allowlist.c | 7 + .../th500/soc/th500_soc_regops_allowlist.h | 1 + drivers/tegra/hwpm/hal/th500/th500_internal.h | 2 + drivers/tegra/hwpm/include/tegra_hwpm.h | 2 + drivers/tegra/hwpm/os/linux/ip_utils.c | 6 + include/uapi/linux/tegra-soc-hwpm-uapi.h | 2 + 11 files changed, 1161 insertions(+), 48 deletions(-) create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.c create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.h diff --git a/drivers/tegra/hwpm/Makefile.th500.soc.sources b/drivers/tegra/hwpm/Makefile.th500.soc.sources index c222174..2e495e6 100644 --- a/drivers/tegra/hwpm/Makefile.th500.soc.sources +++ b/drivers/tegra/hwpm/Makefile.th500.soc.sources @@ -46,4 +46,7 @@ nvhwpm-th500-objs += hal/th500/soc/ip/c2c/th500_c2c.o ccflags-y += -DCONFIG_TH500_HWPM_IP_SMMU nvhwpm-th500-soc-objs += hal/th500/soc/ip/smmu/th500_smmu.o +ccflags-y += -DCONFIG_TH500_HWPM_IP_CL2 +nvhwpm-th500-soc-objs += hal/th500/soc/ip/cl2/th500_cl2.o + endif diff --git a/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h b/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h index ee37d6b..d64d429 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h +++ b/drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h @@ -188,38 +188,38 @@ #define addr_map_mc30_limit_r() (0x0441ffffU) #define addr_map_mc31_base_r() (0x04420000U) #define addr_map_mc31_limit_r() (0x0443ffffU) -#define addr_map_rpg_pm_lts0_base_r() (0x13e3f000U) -#define addr_map_rpg_pm_lts0_limit_r() (0x13e3ffffU) -#define addr_map_rpg_pm_lts1_base_r() (0x13e40000U) -#define addr_map_rpg_pm_lts1_limit_r() (0x13e40fffU) -#define addr_map_rpg_pm_lts2_base_r() (0x13e41000U) -#define addr_map_rpg_pm_lts2_limit_r() (0x13e41fffU) -#define addr_map_rpg_pm_lts3_base_r() (0x13e42000U) -#define addr_map_rpg_pm_lts3_limit_r() (0x13e42fffU) -#define addr_map_rpg_pm_lts4_base_r() (0x13e43000U) -#define addr_map_rpg_pm_lts4_limit_r() (0x13e43fffU) -#define addr_map_rpg_pm_lts5_base_r() (0x13e44000U) -#define addr_map_rpg_pm_lts5_limit_r() (0x13e44fffU) -#define addr_map_rpg_pm_lts6_base_r() (0x13e45000U) -#define addr_map_rpg_pm_lts6_limit_r() (0x13e45fffU) -#define addr_map_rpg_pm_lts7_base_r() (0x13e46000U) -#define addr_map_rpg_pm_lts7_limit_r() (0x13e46fffU) -#define addr_map_rpg_pm_lts8_base_r() (0x13e47000U) -#define addr_map_rpg_pm_lts8_limit_r() (0x13e47fffU) -#define addr_map_rpg_pm_lts9_base_r() (0x13e48000U) -#define addr_map_rpg_pm_lts9_limit_r() (0x13e48fffU) -#define addr_map_rpg_pm_lts10_base_r() (0x13e49000U) -#define addr_map_rpg_pm_lts10_limit_r() (0x13e49fffU) -#define addr_map_rpg_pm_lts11_base_r() (0x13e4a000U) -#define addr_map_rpg_pm_lts11_limit_r() (0x13e4afffU) -#define addr_map_rpg_pm_lts12_base_r() (0x13e4b000U) -#define addr_map_rpg_pm_lts12_limit_r() (0x13e4bfffU) -#define addr_map_rpg_pm_lts13_base_r() (0x13e4c000U) -#define addr_map_rpg_pm_lts13_limit_r() (0x13e4cfffU) -#define addr_map_rpg_pm_lts14_base_r() (0x13e4d000U) -#define addr_map_rpg_pm_lts14_limit_r() (0x13e4dfffU) -#define addr_map_rpg_pm_lts15_base_r() (0x13e4e000U) -#define addr_map_rpg_pm_lts15_limit_r() (0x13e4efffU) +#define addr_map_rpg_pm_ltc0s0_base_r() (0x13e3f000U) +#define addr_map_rpg_pm_ltc0s0_limit_r() (0x13e3ffffU) +#define addr_map_rpg_pm_ltc0s1_base_r() (0x13e40000U) +#define addr_map_rpg_pm_ltc0s1_limit_r() (0x13e40fffU) +#define addr_map_rpg_pm_ltc1s0_base_r() (0x13e41000U) +#define addr_map_rpg_pm_ltc1s0_limit_r() (0x13e41fffU) +#define addr_map_rpg_pm_ltc1s1_base_r() (0x13e42000U) +#define addr_map_rpg_pm_ltc1s1_limit_r() (0x13e42fffU) +#define addr_map_rpg_pm_ltc2s0_base_r() (0x13e43000U) +#define addr_map_rpg_pm_ltc2s0_limit_r() (0x13e43fffU) +#define addr_map_rpg_pm_ltc2s1_base_r() (0x13e44000U) +#define addr_map_rpg_pm_ltc2s1_limit_r() (0x13e44fffU) +#define addr_map_rpg_pm_ltc3s0_base_r() (0x13e45000U) +#define addr_map_rpg_pm_ltc3s0_limit_r() (0x13e45fffU) +#define addr_map_rpg_pm_ltc3s1_base_r() (0x13e46000U) +#define addr_map_rpg_pm_ltc3s1_limit_r() (0x13e46fffU) +#define addr_map_rpg_pm_ltc4s0_base_r() (0x13e47000U) +#define addr_map_rpg_pm_ltc4s0_limit_r() (0x13e47fffU) +#define addr_map_rpg_pm_ltc4s1_base_r() (0x13e48000U) +#define addr_map_rpg_pm_ltc4s1_limit_r() (0x13e48fffU) +#define addr_map_rpg_pm_ltc5s0_base_r() (0x13e49000U) +#define addr_map_rpg_pm_ltc5s0_limit_r() (0x13e49fffU) +#define addr_map_rpg_pm_ltc5s1_base_r() (0x13e4a000U) +#define addr_map_rpg_pm_ltc5s1_limit_r() (0x13e4afffU) +#define addr_map_rpg_pm_ltc6s0_base_r() (0x13e4b000U) +#define addr_map_rpg_pm_ltc6s0_limit_r() (0x13e4bfffU) +#define addr_map_rpg_pm_ltc6s1_base_r() (0x13e4c000U) +#define addr_map_rpg_pm_ltc6s1_limit_r() (0x13e4cfffU) +#define addr_map_rpg_pm_ltc7s0_base_r() (0x13e4d000U) +#define addr_map_rpg_pm_ltc7s0_limit_r() (0x13e4dfffU) +#define addr_map_rpg_pm_ltc7s1_base_r() (0x13e4e000U) +#define addr_map_rpg_pm_ltc7s1_limit_r() (0x13e4efffU) #define addr_map_ltc0_base_r() (0x04e10000U) #define addr_map_ltc0_limit_r() (0x04e1ffffU) #define addr_map_ltc1_base_r() (0x04e20000U) diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.c b/drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.c new file mode 100644 index 0000000..a703a34 --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.c @@ -0,0 +1,1042 @@ +// SPDX-License-Identifier: MIT +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#include "th500_cl2.h" + +#include +#include +#include +#include + +static struct hwpm_ip_aperture th500_cl2_inst0_perfmon_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_cl2_0", + .device_index = TH500_LTC0S0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc0s0_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc0s0_limit_r(), + .start_pa = addr_map_rpg_pm_ltc0s0_base_r(), + .end_pa = addr_map_rpg_pm_ltc0s0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_cl2_1", + .device_index = TH500_LTC0S1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc0s1_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc0s1_limit_r(), + .start_pa = addr_map_rpg_pm_ltc0s1_base_r(), + .end_pa = addr_map_rpg_pm_ltc0s1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst1_perfmon_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_cl2_2", + .device_index = TH500_LTC1S0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc1s0_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc1s0_limit_r(), + .start_pa = addr_map_rpg_pm_ltc1s0_base_r(), + .end_pa = addr_map_rpg_pm_ltc1s0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_cl2_3", + .device_index = TH500_LTC1S1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc1s1_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc1s1_limit_r(), + .start_pa = addr_map_rpg_pm_ltc1s1_base_r(), + .end_pa = addr_map_rpg_pm_ltc1s1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst2_perfmon_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_cl2_4", + .device_index = TH500_LTC2S0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc2s0_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc2s0_limit_r(), + .start_pa = addr_map_rpg_pm_ltc2s0_base_r(), + .end_pa = addr_map_rpg_pm_ltc2s0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_cl2_5", + .device_index = TH500_LTC2S1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc2s1_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc2s1_limit_r(), + .start_pa = addr_map_rpg_pm_ltc2s1_base_r(), + .end_pa = addr_map_rpg_pm_ltc2s1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst3_perfmon_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_cl2_6", + .device_index = TH500_LTC3S0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc3s0_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc3s0_limit_r(), + .start_pa = addr_map_rpg_pm_ltc3s0_base_r(), + .end_pa = addr_map_rpg_pm_ltc3s0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_cl2_7", + .device_index = TH500_LTC3S1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc3s1_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc3s1_limit_r(), + .start_pa = addr_map_rpg_pm_ltc3s1_base_r(), + .end_pa = addr_map_rpg_pm_ltc3s1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst4_perfmon_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_cl2_8", + .device_index = TH500_LTC4S0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc4s0_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc4s0_limit_r(), + .start_pa = addr_map_rpg_pm_ltc4s0_base_r(), + .end_pa = addr_map_rpg_pm_ltc4s0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_cl2_9", + .device_index = TH500_LTC4S1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc4s1_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc4s1_limit_r(), + .start_pa = addr_map_rpg_pm_ltc4s1_base_r(), + .end_pa = addr_map_rpg_pm_ltc4s1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst5_perfmon_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_cl2_10", + .device_index = TH500_LTC5S0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc5s0_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc5s0_limit_r(), + .start_pa = addr_map_rpg_pm_ltc5s0_base_r(), + .end_pa = addr_map_rpg_pm_ltc5s0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_cl2_11", + .device_index = TH500_LTC5S1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc5s1_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc5s1_limit_r(), + .start_pa = addr_map_rpg_pm_ltc5s1_base_r(), + .end_pa = addr_map_rpg_pm_ltc5s1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst6_perfmon_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_cl2_12", + .device_index = TH500_LTC6S0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc6s0_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc6s0_limit_r(), + .start_pa = addr_map_rpg_pm_ltc6s0_base_r(), + .end_pa = addr_map_rpg_pm_ltc6s0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_cl2_13", + .device_index = TH500_LTC6S1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc6s1_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc6s1_limit_r(), + .start_pa = addr_map_rpg_pm_ltc6s1_base_r(), + .end_pa = addr_map_rpg_pm_ltc6s1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst7_perfmon_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_cl2_14", + .device_index = TH500_LTC7S0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc7s0_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc7s0_limit_r(), + .start_pa = addr_map_rpg_pm_ltc7s0_base_r(), + .end_pa = addr_map_rpg_pm_ltc7s0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_cl2_15", + .device_index = TH500_LTC7S1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_ltc7s1_base_r(), + .end_abs_pa = addr_map_rpg_pm_ltc7s1_limit_r(), + .start_pa = addr_map_rpg_pm_ltc7s1_base_r(), + .end_pa = addr_map_rpg_pm_ltc7s1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst0_perfmux_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_ltc0_base_r(), + .end_abs_pa = addr_map_ltc0_limit_r(), + .start_pa = addr_map_ltc0_base_r(), + .end_pa = addr_map_ltc0_limit_r(), + .base_pa = 0ULL, + .alist = th500_cl2_alist, + .alist_size = ARRAY_SIZE(th500_cl2_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst1_perfmux_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_ltc1_base_r(), + .end_abs_pa = addr_map_ltc1_limit_r(), + .start_pa = addr_map_ltc1_base_r(), + .end_pa = addr_map_ltc1_limit_r(), + .base_pa = 0ULL, + .alist = th500_cl2_alist, + .alist_size = ARRAY_SIZE(th500_cl2_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst2_perfmux_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_ltc2_base_r(), + .end_abs_pa = addr_map_ltc2_limit_r(), + .start_pa = addr_map_ltc2_base_r(), + .end_pa = addr_map_ltc2_limit_r(), + .base_pa = 0ULL, + .alist = th500_cl2_alist, + .alist_size = ARRAY_SIZE(th500_cl2_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst3_perfmux_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_ltc3_base_r(), + .end_abs_pa = addr_map_ltc3_limit_r(), + .start_pa = addr_map_ltc3_base_r(), + .end_pa = addr_map_ltc3_limit_r(), + .base_pa = 0ULL, + .alist = th500_cl2_alist, + .alist_size = ARRAY_SIZE(th500_cl2_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst4_perfmux_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_ltc4_base_r(), + .end_abs_pa = addr_map_ltc4_limit_r(), + .start_pa = addr_map_ltc4_base_r(), + .end_pa = addr_map_ltc4_limit_r(), + .base_pa = 0ULL, + .alist = th500_cl2_alist, + .alist_size = ARRAY_SIZE(th500_cl2_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst5_perfmux_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_ltc5_base_r(), + .end_abs_pa = addr_map_ltc5_limit_r(), + .start_pa = addr_map_ltc5_base_r(), + .end_pa = addr_map_ltc5_limit_r(), + .base_pa = 0ULL, + .alist = th500_cl2_alist, + .alist_size = ARRAY_SIZE(th500_cl2_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst6_perfmux_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_ltc6_base_r(), + .end_abs_pa = addr_map_ltc6_limit_r(), + .start_pa = addr_map_ltc6_base_r(), + .end_pa = addr_map_ltc6_limit_r(), + .base_pa = 0ULL, + .alist = th500_cl2_alist, + .alist_size = ARRAY_SIZE(th500_cl2_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_cl2_inst7_perfmux_element_static_array[ + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_ltc7_base_r(), + .end_abs_pa = addr_map_ltc7_limit_r(), + .start_pa = addr_map_ltc7_base_r(), + .end_pa = addr_map_ltc7_limit_r(), + .base_pa = 0ULL, + .alist = th500_cl2_alist, + .alist_size = ARRAY_SIZE(th500_cl2_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +static struct hwpm_ip_inst th500_cl2_inst_static_array[ + TH500_HWPM_IP_CL2_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .num_core_elements_per_inst = + TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_cl2_inst0_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_ltc0_base_r(), + .range_end = addr_map_ltc0_limit_r(), + .element_stride = addr_map_ltc0_limit_r() - + addr_map_ltc0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST, + .element_static_array = + th500_cl2_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_ltc0s0_base_r(), + .range_end = addr_map_rpg_pm_ltc0s1_limit_r(), + .element_stride = addr_map_rpg_pm_ltc0s0_limit_r() - + addr_map_rpg_pm_ltc0s0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(1), + .num_core_elements_per_inst = + TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_cl2_inst1_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_ltc1_base_r(), + .range_end = addr_map_ltc1_limit_r(), + .element_stride = addr_map_ltc1_limit_r() - + addr_map_ltc1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST, + .element_static_array = + th500_cl2_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_ltc1s0_base_r(), + .range_end = addr_map_rpg_pm_ltc1s1_limit_r(), + .element_stride = addr_map_rpg_pm_ltc1s0_limit_r() - + addr_map_rpg_pm_ltc1s0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(2), + .num_core_elements_per_inst = + TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_cl2_inst2_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_ltc2_base_r(), + .range_end = addr_map_ltc2_limit_r(), + .element_stride = addr_map_ltc2_limit_r() - + addr_map_ltc2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST, + .element_static_array = + th500_cl2_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_ltc2s0_base_r(), + .range_end = addr_map_rpg_pm_ltc2s1_limit_r(), + .element_stride = addr_map_rpg_pm_ltc2s0_limit_r() - + addr_map_rpg_pm_ltc2s0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(3), + .num_core_elements_per_inst = + TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_cl2_inst3_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_ltc3_base_r(), + .range_end = addr_map_ltc3_limit_r(), + .element_stride = addr_map_ltc3_limit_r() - + addr_map_ltc3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST, + .element_static_array = + th500_cl2_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_ltc3s0_base_r(), + .range_end = addr_map_rpg_pm_ltc3s1_limit_r(), + .element_stride = addr_map_rpg_pm_ltc3s0_limit_r() - + addr_map_rpg_pm_ltc3s0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(4), + .num_core_elements_per_inst = + TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_cl2_inst4_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_ltc4_base_r(), + .range_end = addr_map_ltc4_limit_r(), + .element_stride = addr_map_ltc4_limit_r() - + addr_map_ltc4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST, + .element_static_array = + th500_cl2_inst4_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_ltc4s0_base_r(), + .range_end = addr_map_rpg_pm_ltc4s1_limit_r(), + .element_stride = addr_map_rpg_pm_ltc4s0_limit_r() - + addr_map_rpg_pm_ltc4s0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(5), + .num_core_elements_per_inst = + TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_cl2_inst5_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_ltc5_base_r(), + .range_end = addr_map_ltc5_limit_r(), + .element_stride = addr_map_ltc5_limit_r() - + addr_map_ltc5_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST, + .element_static_array = + th500_cl2_inst5_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_ltc5s0_base_r(), + .range_end = addr_map_rpg_pm_ltc5s1_limit_r(), + .element_stride = addr_map_rpg_pm_ltc5s0_limit_r() - + addr_map_rpg_pm_ltc5s0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(6), + .num_core_elements_per_inst = + TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_cl2_inst6_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_ltc6_base_r(), + .range_end = addr_map_ltc6_limit_r(), + .element_stride = addr_map_ltc6_limit_r() - + addr_map_ltc6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST, + .element_static_array = + th500_cl2_inst6_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_ltc6s0_base_r(), + .range_end = addr_map_rpg_pm_ltc6s1_limit_r(), + .element_stride = addr_map_rpg_pm_ltc6s0_limit_r() - + addr_map_rpg_pm_ltc6s0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(7), + .num_core_elements_per_inst = + TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_cl2_inst7_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_ltc7_base_r(), + .range_end = addr_map_ltc7_limit_r(), + .element_stride = addr_map_ltc7_limit_r() - + addr_map_ltc7_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST, + .element_static_array = + th500_cl2_inst7_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_ltc7s0_base_r(), + .range_end = addr_map_rpg_pm_ltc7s1_limit_r(), + .element_stride = addr_map_rpg_pm_ltc7s0_limit_r() - + addr_map_rpg_pm_ltc7s0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, +}; + +/* IP structure */ +struct hwpm_ip th500_hwpm_ip_cl2 = { + .num_instances = TH500_HWPM_IP_CL2_NUM_INSTANCES, + .ip_inst_static_array = th500_cl2_inst_static_array, + + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + /* NOTE: range should be in ascending order */ + .range_start = addr_map_ltc0_base_r(), + .range_end = addr_map_ltc7_limit_r(), + .inst_stride = addr_map_ltc0_limit_r() - + addr_map_ltc0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_ltc0s0_base_r(), + .range_end = addr_map_rpg_pm_ltc7s1_limit_r(), + .inst_stride = addr_map_rpg_pm_ltc0s0_limit_r() - + addr_map_rpg_pm_ltc0s0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, + + .dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK, + .override_enable = false, + .inst_fs_mask = 0U, + .resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID, + .reserved = false, +}; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.h b/drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.h new file mode 100644 index 0000000..2ad20f3 --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#ifndef TH500_HWPM_IP_CL2_H +#define TH500_HWPM_IP_CL2_H + +#if defined(CONFIG_TH500_HWPM_IP_CL2) +#define TH500_HWPM_ACTIVE_IP_CL2 TH500_HWPM_IP_CL2, + +/* This data should ideally be available in HW headers */ +#define TH500_HWPM_IP_CL2_NUM_INSTANCES 8U +#define TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST 1U +#define TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST 2U +#define TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST 1U +#define TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST 0U + +extern struct hwpm_ip th500_hwpm_ip_cl2; + +#else +#define TH500_HWPM_ACTIVE_IP_CL2 +#endif + +#endif /* TH500_HWPM_IP_CL2_H */ diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_perfmon_device_index.h b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_perfmon_device_index.h index f539106..52333cc 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_perfmon_device_index.h +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_perfmon_device_index.h @@ -87,22 +87,22 @@ enum th500_hwpm_soc_perfmon_device_index { TH500_MSS_CHANNEL_PARTH1_PERFMON_DEVICE_NODE_INDEX, TH500_MSS_CHANNEL_PARTH2_PERFMON_DEVICE_NODE_INDEX, TH500_MSS_CHANNEL_PARTH3_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS0_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS1_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS2_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS3_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS4_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS5_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS6_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS7_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS8_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS9_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS10_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS11_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS12_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS13_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS14_PERFMON_DEVICE_NODE_INDEX, - TH500_LTS15_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC0S0_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC0S1_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC1S0_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC1S1_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC2S0_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC2S1_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC3S0_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC3S1_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC4S0_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC4S1_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC5S0_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC5S1_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC6S0_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC6S1_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC7S0_PERFMON_DEVICE_NODE_INDEX, + TH500_LTC7S1_PERFMON_DEVICE_NODE_INDEX, TH500_MCFCORE0_PERFMON_DEVICE_NODE_INDEX, TH500_MCFCORE1_PERFMON_DEVICE_NODE_INDEX, TH500_MCFCORE2_PERFMON_DEVICE_NODE_INDEX, diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c index ebd196a..fb5d250 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c @@ -244,3 +244,10 @@ struct allowlist th500_soc_hub_alist[3] = { {0x00006f38, false}, {0x00006f3c, false}, }; + +struct allowlist th500_cl2_alist[4] = { + {0x00000550, false}, + {0x00000578, false}, + {0x00000750, false}, + {0x00000778, false}, +}; diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h index 608cad2..55ef5c5 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h @@ -35,5 +35,6 @@ extern struct allowlist th500_mcf_clink_alist[3]; extern struct allowlist th500_mcf_c2c_alist[2]; extern struct allowlist th500_mcf_soc_alist[2]; extern struct allowlist th500_soc_hub_alist[3]; +extern struct allowlist th500_cl2_alist[4]; #endif /* TH500_HWPM_REGOPS_ALLOWLIST_H */ diff --git a/drivers/tegra/hwpm/hal/th500/th500_internal.h b/drivers/tegra/hwpm/hal/th500/th500_internal.h index 6ad6d30..236d55e 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_internal.h +++ b/drivers/tegra/hwpm/hal/th500/th500_internal.h @@ -28,6 +28,7 @@ #include #include #include +#include #define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX @@ -37,6 +38,7 @@ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_CHANNEL) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_C2C) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_SMMU) \ + DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_CL2) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX) #undef DEFINE_SOC_HWPM_ACTIVE_IP diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h index 2622f4e..6025555 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm.h @@ -79,6 +79,7 @@ enum tegra_hwpm_ip_enum { TEGRA_HWPM_IP_APE, TEGRA_HWPM_IP_C2C, TEGRA_HWPM_IP_SMMU, + TEGRA_HWPM_IP_CL2, TERGA_HWPM_NUM_IPS }; @@ -109,6 +110,7 @@ enum tegra_hwpm_resource_enum { TEGRA_HWPM_RESOURCE_APE, TEGRA_HWPM_RESOURCE_C2C, TEGRA_HWPM_RESOURCE_SMMU, + TEGRA_HWPM_RESOURCE_CL2, TERGA_HWPM_NUM_RESOURCES }; diff --git a/drivers/tegra/hwpm/os/linux/ip_utils.c b/drivers/tegra/hwpm/os/linux/ip_utils.c index 31640dd..19f59ae 100644 --- a/drivers/tegra/hwpm/os/linux/ip_utils.c +++ b/drivers/tegra/hwpm/os/linux/ip_utils.c @@ -93,6 +93,9 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_IP_SMMU: ip_enum_idx = TEGRA_HWPM_IP_SMMU; break; + case TEGRA_SOC_HWPM_IP_CL2: + ip_enum_idx = TEGRA_HWPM_IP_CL2; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_ip %d is invalid", @@ -201,6 +204,9 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_RESOURCE_SMMU: res_enum_idx = TEGRA_HWPM_RESOURCE_SMMU; break; + case TEGRA_SOC_HWPM_RESOURCE_CL2: + res_enum_idx = TEGRA_HWPM_RESOURCE_CL2; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_resource %d is invalid", diff --git a/include/uapi/linux/tegra-soc-hwpm-uapi.h b/include/uapi/linux/tegra-soc-hwpm-uapi.h index d591fc3..78cdbe2 100644 --- a/include/uapi/linux/tegra-soc-hwpm-uapi.h +++ b/include/uapi/linux/tegra-soc-hwpm-uapi.h @@ -46,6 +46,7 @@ enum tegra_soc_hwpm_ip { TEGRA_SOC_HWPM_IP_APE, TEGRA_SOC_HWPM_IP_C2C, TEGRA_SOC_HWPM_IP_SMMU, + TEGRA_SOC_HWPM_IP_CL2, TERGA_SOC_HWPM_NUM_IPS }; @@ -114,6 +115,7 @@ enum tegra_soc_hwpm_resource { TEGRA_SOC_HWPM_RESOURCE_APE, TEGRA_SOC_HWPM_RESOURCE_C2C, TEGRA_SOC_HWPM_RESOURCE_SMMU, + TEGRA_SOC_HWPM_RESOURCE_CL2, TERGA_SOC_HWPM_NUM_RESOURCES };