tegra: hwpm: t234: decouple force IP, minimal cfg

- HWPM driver requires to know if an IP is available for performance
measurements. The ideal way is for IP driver registration with HWPM
driver. This way IP driver can share required power management and
register access function pointers.
- For IPs that do not have registration mechanism implemented, a
workaround to set an IP enabled is implemented in the HWPM driver.
- In the recent releases, MSS channel, PVA and DLA IPs are the only PORs
for production builds. Currently, this is acheived using the combination
of minimal build and force enable flags.
- However, this implementation limits the number of enabled IPs on TOT
to only minimal expected ones.
- This patch modifies the force enable IP logic implementation to make
force enable and minimal IP flag definition more clear.
- CONFIG_T234_HWPM_ALLOW_FORCE_ENABLE should be used to purposely enable
IPs that do not have registration mechanism implemented. This flag is
used for POR or non-POR IPs. Ideally, all IPs should implement HWPM
registration and force enable flag should not be required.
- CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE should be used to implement logic
for POR IPs. In other words, if CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE is
not defined, non-POR IPs should be included in the builds. This patch
sets MINIMAL IP config only for external non-safety builds.

- Fix include t234_perfmon_device_index.h error in t234_mss_mcf.c file.
- Add missing device index for PVA perfmon C0.

Jira THWPM-41

Change-Id: I20651eac14b6d42e5bf3cc5164d1f64ec208dc04
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2818735
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>

drivers/tegra/hwpm/Makefile.t234.sources

@@ -25,16 +25,33 @@ nvhwpm-t234-objs += hal/t234/ip/rtr/t234_rtr.o
 nvhwpm-t234-objs += hal/t234/ip/pma/t234_pma.o
 
 #
-# Define a Minimal IP config flag
-# Enable only MSS_Channel, NVDLA and PVA IPs
-# When CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE is set to y.
+# One of the HWPM components is a perfmux. Perfmux registers belong to the
+# IP domain. There are 2 ways of accessing perfmux registers
+# - option 1: implement HWPM <-> IP interface. IP drivers register with HWPM
+#             driver and share required function pointers
+# - option 2: map perfmux register address in HWPM driver
+# Option 1 is the preferred solution. However, IP drivers have yet to
+# implement the interface. Such IPs can be force enabled from HWPM driver
+# perspective (option 2). Marking an IP available forcefully requires the user
+# to unpowergate the IP before running any HWPM experiments.
 #
-CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE=y
-
-ifeq ($(CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE),y)
+# Enable CONFIG_T234_HWPM_ALLOW_FORCE_ENABLE for internal builds.
+# Note: We should work towards removing force enable flag dependency.
+#
+ifeq ($(NV_BUILD_CONFIGURATION_IS_EXTERNAL),0)
 ccflags-y += -DCONFIG_T234_HWPM_ALLOW_FORCE_ENABLE
 endif
 
+#
+# Currently, PVA, DLA and MSS channel are the IPs supported
+# for performance metrics in external builds.
+# Define CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE flag.
+#
+ifeq ($(NV_BUILD_CONFIGURATION_IS_EXTERNAL),1)
+CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE=y
+ccflags-y += -DCONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE
+endif
+
 ifeq ($(CONFIG_TEGRA_GRHOST_NVDLA),y)
 ccflags-y += -DCONFIG_T234_HWPM_IP_NVDLA
 nvhwpm-t234-objs += hal/t234/ip/nvdla/t234_nvdla.o
@@ -50,6 +67,7 @@ ccflags-y += -DCONFIG_T234_HWPM_IP_MSS_CHANNEL
 nvhwpm-t234-objs += hal/t234/ip/mss_channel/t234_mss_channel.o
 endif
 
+# Include other IPs if minimal build is not enabled.
 ifneq ($(CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE),y)
 ccflags-y += -DCONFIG_T234_HWPM_IP_DISPLAY
 nvhwpm-t234-objs += hal/t234/ip/display/t234_display.o

drivers/tegra/hwpm/hal/t234/ip/mss_mcf/t234_mss_mcf.c

@@ -15,8 +15,8 @@
 
 #include <tegra_hwpm.h>
 #include <hal/t234/t234_regops_allowlist.h>
+#include <hal/t234/t234_perfmon_device_index.h>
 #include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
-#include <t234_perfmon_device_index.h>
 
 static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
 	T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST] = {

drivers/tegra/hwpm/hal/t234/ip/pva/t234_pva.c

@@ -58,6 +58,7 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
 		.element_index = 2U,
 		.dt_mmio = NULL,
 		.name = "perfmon_pvac0",
+		.device_index = T234_PVAC0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pva0_2_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pva0_2_limit_r(),
 		.start_pa = 0ULL,

drivers/tegra/hwpm/hal/t234/t234_ip.c

@@ -293,11 +293,17 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
 	int ret = 0;
 
 	tegra_hwpm_fn(hwpm, " ");
-#if defined(CONFIG_T234_HWPM_ALLOW_FORCE_ENABLE)
 
-#if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL)
-	/* MSS CHANNEL */
 	if (tegra_hwpm_is_hypervisor_mode()) {
+		/* MSS CHANNEL */
+		/*
+		 * MSS channel driver cannot implement HWPM <-> IP
+		 * interface in AV + L config.
+		 * Since MSS channel is part of both POR and non-POR IPs,
+		 * this force enable is not limited by minimal config or
+		 * force enable flags.
+		 */
+#if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL)
 		ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
 			addr_map_mc0_base_r(),
 			T234_HWPM_IP_MSS_CHANNEL, true);
@@ -306,11 +312,13 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
 				"T234_HWPM_IP_MSS_CHANNEL force enable failed");
 			return ret;
 		}
-	}
 #endif
+	}
+
+#if defined(CONFIG_T234_HWPM_ALLOW_FORCE_ENABLE)
 
-#if defined(CONFIG_T234_HWPM_IP_MSS_GPU_HUB)
 	/* MSS GPU HUB */
+#if defined(CONFIG_T234_HWPM_IP_MSS_GPU_HUB)
 	ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
 		addr_map_mss_nvlink_1_base_r(),
 		T234_HWPM_IP_MSS_GPU_HUB, true);
@@ -344,8 +352,9 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
 		}
 #endif
 */
-#if defined(CONFIG_T234_HWPM_IP_ISP)
 		/* ISP */
+/*
+#if defined(CONFIG_T234_HWPM_IP_ISP)
 		ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
 			addr_map_isp_thi_base_r(),
 			T234_HWPM_IP_ISP, true);
@@ -355,6 +364,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
 			return ret;
 		}
 #endif
+*/
 
 		/* MGBE */
 /*
@@ -369,9 +379,9 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
 		}
 #endif
 */
-
-#if defined(CONFIG_T234_HWPM_IP_NVDEC)
 		/* NVDEC */
+/*
+#if defined(CONFIG_T234_HWPM_IP_NVDEC)
 		ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
 			addr_map_nvdec_base_r(),
 			T234_HWPM_IP_NVDEC, true);
@@ -381,6 +391,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
 			return ret;
 		}
 #endif
+*/
 
 		/* PCIE */
 /*
@@ -426,22 +437,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
 #endif
 */
 	}
-#endif
-		/*
-		 * SCF is an independent IP with a single perfmon only.
-		 * SCF should not be part of force enable config flag.
-		 */
-#if defined(CONFIG_T234_HWPM_IP_SCF)
-		/* SCF */
-		ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
-			addr_map_rpg_pm_scf_base_r(),
-			T234_HWPM_IP_SCF, true);
-		if (ret != 0) {
-			tegra_hwpm_err(hwpm,
-				"T234_HWPM_IP_SCF force enable failed");
-			return ret;
-		}
-#endif
+#endif /* CONFIG_T234_HWPM_ALLOW_FORCE_ENABLE */
 
 	return ret;
 }