mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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tegra: hwpm: move files to appropriate path
HWPM files are copied from the previous source in linux-nvidia repo withgit history. Create folders and move files to obtain expected folder structure. Bug 3787076 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
This commit is contained in:
Vedashree Vidwans
500
include/uapi/linux/tegra-soc-hwpm-uapi.h
Normal file
500
include/uapi/linux/tegra-soc-hwpm-uapi.h
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@@ -0,0 +1,500 @@
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/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* tegra-soc-hwpm-uapi.h:
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* This is the userspace API header for the Tegra SOC HWPM driver.
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*/
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#ifndef TEGRA_SOC_HWPM_UAPI_H
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#define TEGRA_SOC_HWPM_UAPI_H
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#define TEGRA_SOC_HWPM_DEV_NODE "/dev/tegra-soc-hwpm"
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/* IPs supported for HW configurations queries */
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enum tegra_soc_hwpm_ip {
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TEGRA_SOC_HWPM_IP_VI,
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TEGRA_SOC_HWPM_IP_ISP,
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TEGRA_SOC_HWPM_IP_VIC,
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TEGRA_SOC_HWPM_IP_OFA,
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TEGRA_SOC_HWPM_IP_PVA,
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TEGRA_SOC_HWPM_IP_NVDLA,
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TEGRA_SOC_HWPM_IP_MGBE,
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TEGRA_SOC_HWPM_IP_SCF,
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TEGRA_SOC_HWPM_IP_NVDEC,
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TEGRA_SOC_HWPM_IP_NVENC,
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TEGRA_SOC_HWPM_IP_PCIE,
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TEGRA_SOC_HWPM_IP_DISPLAY,
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TEGRA_SOC_HWPM_IP_MSS_CHANNEL,
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TEGRA_SOC_HWPM_IP_MSS_GPU_HUB,
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TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS,
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TEGRA_SOC_HWPM_IP_MSS_MCF,
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TEGRA_SOC_HWPM_IP_APE,
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TERGA_SOC_HWPM_NUM_IPS
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};
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/* TEGRA_CTRL_CMD_SOC_HWPM_DEVICE_INFO IOCTL */
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struct tegra_soc_hwpm_device_info {
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__u32 chip; /* chip id, eg. 0x23 (t23x) */
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__u32 chip_revision; /* chip_id revision, eg. 0x4 (t234) */
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__u32 revision; /* major-minor revision, eg. A01, A02 */
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__u32 platform; /* Eg. Pre-Si, Si */
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};
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/* TEGRA_CTRL_CMD_SOC_HWPM_IP_FLOORSWEEP_INFO IOCTL */
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struct tegra_soc_hwpm_ip_floorsweep_info_query {
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/* input */
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__u16 ip; /* enum tegra_soc_hwpm_ip */
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/* output */
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#define TEGRA_SOC_HWPM_IP_STATUS_VALID 0
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#define TEGRA_SOC_HWPM_IP_STATUS_INVALID 1
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__u8 status; /* IP status */
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__u8 reserved1;
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__u32 reserved2;
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/*
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* flattened availability mask of IP elements.
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* Each set bit corresponds to available IP element.
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*/
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__u64 ip_inst_mask;
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};
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#define TEGRA_SOC_HWPM_IP_QUERIES_MAX 32
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struct tegra_soc_hwpm_ip_floorsweep_info {
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/* Holds queries */
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struct tegra_soc_hwpm_ip_floorsweep_info_query ip_fsinfo[TEGRA_SOC_HWPM_IP_QUERIES_MAX];
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__u32 num_queries;
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};
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/* The resources which can be reserved for profiling */
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enum tegra_soc_hwpm_resource {
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TEGRA_SOC_HWPM_RESOURCE_VI,
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TEGRA_SOC_HWPM_RESOURCE_ISP,
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TEGRA_SOC_HWPM_RESOURCE_VIC,
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TEGRA_SOC_HWPM_RESOURCE_OFA,
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TEGRA_SOC_HWPM_RESOURCE_PVA,
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TEGRA_SOC_HWPM_RESOURCE_NVDLA,
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TEGRA_SOC_HWPM_RESOURCE_MGBE,
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TEGRA_SOC_HWPM_RESOURCE_SCF,
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TEGRA_SOC_HWPM_RESOURCE_NVDEC,
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TEGRA_SOC_HWPM_RESOURCE_NVENC,
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TEGRA_SOC_HWPM_RESOURCE_PCIE,
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TEGRA_SOC_HWPM_RESOURCE_DISPLAY,
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TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL,
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TEGRA_SOC_HWPM_RESOURCE_MSS_GPU_HUB,
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TEGRA_SOC_HWPM_RESOURCE_MSS_ISO_NISO_HUBS,
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TEGRA_SOC_HWPM_RESOURCE_MSS_MCF,
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/*
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* - SYS0 PERMON in RPG_PMG
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* - PERFMUX: PMA_CHANNEL_PERFMUX_CONFIG_SECURE
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*/
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TEGRA_SOC_HWPM_RESOURCE_PMA,
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/*
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* - PMA: Everything except PMA_CHANNEL_PERFMUX_CONFIG_SECURE
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* - RTR: Entire aperture
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*/
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TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR,
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TEGRA_SOC_HWPM_RESOURCE_APE,
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TERGA_SOC_HWPM_NUM_RESOURCES
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};
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/* TEGRA_CTRL_CMD_SOC_HWPM_RESOURCE_INFO IOCTL */
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struct tegra_soc_hwpm_resource_info_query {
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/* input */
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__u16 resource; /* enum tegra_soc_hwpm_resource */
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/* output */
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#define TEGRA_SOC_HWPM_RESOURCE_STATUS_INVALID 0
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#define TEGRA_SOC_HWPM_RESOURCE_STATUS_VALID 1
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__u8 status; /* Resource status */
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__u8 reserved1;
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__u32 reserved2;
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};
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#define TEGRA_SOC_HWPM_RESOURCE_QUERIES_MAX 32
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struct tegra_soc_hwpm_resource_info {
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/* Holds queries */
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struct tegra_soc_hwpm_resource_info_query resource_info[
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TEGRA_SOC_HWPM_RESOURCE_QUERIES_MAX];
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__u32 num_queries;
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};
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/* TEGRA_CTRL_CMD_SOC_HWPM_RESERVE_RESOURCE IOCTL */
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struct tegra_soc_hwpm_reserve_resource {
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/*
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* Inputs
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*/
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enum tegra_soc_hwpm_resource resource;
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};
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/* TEGRA_CTRL_CMD_SOC_HWPM_ALLOC_PMA_STREAM IOCTL */
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struct tegra_soc_hwpm_alloc_pma_stream {
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/*
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* Inputs
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*/
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__u64 stream_buf_size;
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__u64 stream_buf_fd; /* NvRmMemHandle */
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__u64 mem_bytes_buf_fd; /* NvRmMemHandle */
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/*
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* Outputs
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*/
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__u64 stream_buf_pma_va; /* SMMU mapped VA */
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};
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/*
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* TEGRA_CTRL_CMD_SOC_HWPM_QUERY_ALLOWLIST IOCTL
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*
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* This IOCTL needs to be called twice. In the first IOCTL call userspace will
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* set the allowlist pointer to NULL and the driver will return allowlist_size.
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* Userspace will then allocate a buffer to hold allowlist_size entries. In the
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* 2nd IOCTL call, userspace will provide the allowlist buffer pointer, and the
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* driver will fill in the buffer.
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*/
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struct tegra_soc_hwpm_query_allowlist {
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/*
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* Inputs and Outputs
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*/
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__u64 *allowlist;
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/*
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* Outputs
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*/
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__u64 allowlist_size; /* The number of entires in the map */
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};
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/* Register read/write op */
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struct tegra_soc_hwpm_reg_op {
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__u64 phys_addr;
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/*
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* For 32 bit reg-ops this is the value used for reading/writing.
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* For 64 bit reg-ops this is the value of the lower register (i.e. phys_addr).
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*/
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__u32 reg_val_lo;
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/*
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* For 32 bit reg-ops this value is unused.
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* For 64 bit reg-ops this is the value of the higher register (i.e. phys_addr + 4).
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*/
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__u32 reg_val_hi;
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/*
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* For 32 bit reg-ops this is the mask used for writing.
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* For 64 bit reg-ops this is the mask for the lower register (i.e. phys_addr).
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*/
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__u32 mask_lo;
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/*
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* For 32 bit reg-ops this mask is unused.
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* For 64 bit reg-ops this is the mask for the higher register (i.e. phys_addr + 4).
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*/
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__u32 mask_hi;
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/*
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* INVALID is first so the default value of 0 is not a valid value.
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* User is forced to pick a real value
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*/
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#define TEGRA_SOC_HWPM_REG_OP_CMD_INVALID 0
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#define TEGRA_SOC_HWPM_REG_OP_CMD_RD32 1
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#define TEGRA_SOC_HWPM_REG_OP_CMD_RD64 2
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#define TEGRA_SOC_HWPM_REG_OP_CMD_WR32 3
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#define TEGRA_SOC_HWPM_REG_OP_CMD_WR64 4
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__u8 cmd;
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/*
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* Return RegOps status
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*/
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#define TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS 0
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#define TEGRA_SOC_HWPM_REG_OP_STATUS_INVALID_CMD 1
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/* FIXME: What is this error code for? */
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#define TEGRA_SOC_HWPM_REG_OP_STATUS_INVALID_ADDR 2
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/* not in allowlist */
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#define TEGRA_SOC_HWPM_REG_OP_STATUS_INSUFFICIENT_PERMISSIONS 3
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#define TEGRA_SOC_HWPM_REG_OP_STATUS_WR_FAILED 4
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#define TEGRA_SOC_HWPM_REG_OP_STATUS_RD_FAILED 5
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__u8 status;
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/* Explicit padding for 8 Byte alignment */
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__u8 reserved[6];
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};
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/* TEGRA_CTRL_CMD_SOC_HWPM_EXEC_REG_OPS IOCTL */
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struct tegra_soc_hwpm_exec_reg_ops {
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/*
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* Inputs and Outputs
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*/
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#define TEGRA_SOC_HWPM_REG_OPS_SIZE 127
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struct tegra_soc_hwpm_reg_op ops[TEGRA_SOC_HWPM_REG_OPS_SIZE];
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__u32 op_count;
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/* Inputs */
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/*
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* INVALID is first so the default value of 0 is not a valid value.
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* User is forced to pick a real value
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*/
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#define TEGRA_SOC_HWPM_REG_OP_MODE_INVALID 0
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/* Fail the entire IOCTL on the first malformed REG_OP */
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#define TEGRA_SOC_HWPM_REG_OP_MODE_FAIL_ON_FIRST 1
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/*
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* If a malformed REG_OP is encountered, set the status in
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* struct tegra_soc_hwpm_reg_op.status. Then continue processing the remaining
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* REG_OPs.
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*/
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#define TEGRA_SOC_HWPM_REG_OP_MODE_CONT_ON_ERR 2
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__u8 mode;
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/* Output */
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__u8 b_all_reg_ops_passed;
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};
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/* TEGRA_CTRL_CMD_SOC_HWPM_UPDATE_GET_PUT IOCTL */
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#define TEGRA_SOC_HWPM_MEM_BYTES_INVALID 0xffffffff
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struct tegra_soc_hwpm_update_get_put {
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/*
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* Inputs
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*/
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__u64 mem_bump; /* Increase SW get pointer by mem_bump bytes */
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__u8 b_stream_mem_bytes; /* Stream MEM_BYTES value to MEM_BYTES buffer */
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/*
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* FIXME: This is not needed right now
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* __u8 b_wait_for_stream;
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*/
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__u8 b_read_mem_head;
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__u8 b_check_overflow;
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/*
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* Outputs
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*/
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__u64 mem_head; /* HW put pointer value */
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/*
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* FIXME: This is not needed right now
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* __u64 mem_bytes;
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*/
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__u8 b_overflowed;
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};
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/* IOCTL enum */
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enum tegra_soc_hwpm_ioctl_num {
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TEGRA_SOC_HWPM_IOCTL_DEVICE_INFO,
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TEGRA_SOC_HWPM_IOCTL_FLOORSWEEP_INFO,
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TEGRA_SOC_HWPM_IOCTL_RESOURCE_INFO,
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TEGRA_SOC_HWPM_IOCTL_RESERVE_RESOURCE,
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TEGRA_SOC_HWPM_IOCTL_ALLOC_PMA_STREAM,
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TEGRA_SOC_HWPM_IOCTL_BIND,
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TEGRA_SOC_HWPM_IOCTL_QUERY_ALLOWLIST,
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TEGRA_SOC_HWPM_IOCTL_EXEC_REG_OPS,
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TEGRA_SOC_HWPM_IOCTL_UPDATE_GET_PUT,
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TERGA_SOC_HWPM_NUM_IOCTLS
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};
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/* FIXME: Does this have to be unique? */
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#define TEGRA_SOC_HWPM_IOC_MAGIC 'P'
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/*
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* IOCTL for finding which physical instances of an IP are present in the chip
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*
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* FIXME: Convert to batch mode - refer to NV2080_CTRL_CMD_FB_GET_FS_INFO
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*/
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#define TEGRA_CTRL_CMD_SOC_HWPM_DEVICE_INFO \
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_IOWR(TEGRA_SOC_HWPM_IOC_MAGIC, \
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TEGRA_SOC_HWPM_IOCTL_DEVICE_INFO, \
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struct tegra_soc_hwpm_device_info)
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/*
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* IOCTL for querying IP instance info
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*/
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#define TEGRA_CTRL_CMD_SOC_HWPM_IP_FLOORSWEEP_INFO \
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_IOWR(TEGRA_SOC_HWPM_IOC_MAGIC, \
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TEGRA_SOC_HWPM_IOCTL_FLOORSWEEP_INFO, \
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struct tegra_soc_hwpm_ip_floorsweep_info)
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/*
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* IOCTL for resource status
|
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*/
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#define TEGRA_CTRL_CMD_SOC_HWPM_RESOURCE_INFO \
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_IOWR(TEGRA_SOC_HWPM_IOC_MAGIC, \
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TEGRA_SOC_HWPM_IOCTL_RESOURCE_INFO, \
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struct tegra_soc_hwpm_resource_info)
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/*
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* IOCTL for reserving a resource for profiling
|
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*
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* This IOCTL can only be called before BIND.
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*
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* FIXME: Convert to batch mode - refer to NV2080_CTRL_CMD_FB_GET_FS_INFO
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*/
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#define TEGRA_CTRL_CMD_SOC_HWPM_RESERVE_RESOURCE \
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_IOW(TEGRA_SOC_HWPM_IOC_MAGIC, \
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TEGRA_SOC_HWPM_IOCTL_RESERVE_RESOURCE, \
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struct tegra_soc_hwpm_reserve_resource)
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/*
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* IOCTL for allocating the PMA output stream
|
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*
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* This IOCTL can only be called before BIND.
|
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*/
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#define TEGRA_CTRL_CMD_SOC_HWPM_ALLOC_PMA_STREAM \
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_IOWR(TEGRA_SOC_HWPM_IOC_MAGIC, \
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TEGRA_SOC_HWPM_IOCTL_ALLOC_PMA_STREAM, \
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struct tegra_soc_hwpm_alloc_pma_stream)
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/*
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* IOCTL for finalizing the initialization
|
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*
|
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* SOC HWPM driver will program the HW to finalize the initialiation.
|
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*
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* The following IOCTLs can only be called before BIND:
|
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* - RESERVE_RESOURCE
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* - ALLOC_PMA_STREAM
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*
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* The following IOCTLs can only be called after BIND:
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* - QUERY_ALLOWLIST
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* - EXEC_REG_OPS
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* - UPDATE_GET_PUT
|
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*/
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#define TEGRA_CTRL_CMD_BIND \
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_IO(TEGRA_SOC_HWPM_IOC_MAGIC, \
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TEGRA_SOC_HWPM_IOCTL_BIND)
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/*
|
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* IOCTL for requesting the driver's allowlist map
|
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*
|
||||
* This IOCTL can only be called after the BIND IOCTL
|
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*
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||||
* FIXME: "ALLOWLIST" might have to be renamed to "ALLOWLIST"
|
||||
*/
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#define TEGRA_CTRL_CMD_SOC_HWPM_QUERY_ALLOWLIST \
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_IOWR(TEGRA_SOC_HWPM_IOC_MAGIC, \
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||||
TEGRA_SOC_HWPM_IOCTL_QUERY_ALLOWLIST, \
|
||||
struct tegra_soc_hwpm_query_allowlist)
|
||||
|
||||
/*
|
||||
* IOCTL for executing register read/write operations
|
||||
*
|
||||
* This IOCTL can only be called after the BIND IOCTL
|
||||
*/
|
||||
#define TEGRA_CTRL_CMD_SOC_HWPM_EXEC_REG_OPS \
|
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_IOWR(TEGRA_SOC_HWPM_IOC_MAGIC, \
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TEGRA_SOC_HWPM_IOCTL_EXEC_REG_OPS, \
|
||||
struct tegra_soc_hwpm_exec_reg_ops)
|
||||
|
||||
/*
|
||||
* IOCTL for updating get/put pointers for PMA streamout buffer
|
||||
*
|
||||
* This IOCTL can only be called after the BIND IOCTL
|
||||
*/
|
||||
#define TEGRA_CTRL_CMD_SOC_HWPM_UPDATE_GET_PUT \
|
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_IOWR(TEGRA_SOC_HWPM_IOC_MAGIC, \
|
||||
TEGRA_SOC_HWPM_IOCTL_UPDATE_GET_PUT, \
|
||||
struct tegra_soc_hwpm_update_get_put)
|
||||
|
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#define TEGRA_SOC_HWPM_MAX_ARG_SIZE \
|
||||
sizeof(struct tegra_soc_hwpm_exec_reg_ops)
|
||||
|
||||
|
||||
|
||||
/* Interface for IP driver communication */
|
||||
|
||||
/*
|
||||
* Enums for IP register read/write, to make things simple
|
||||
* from SOC HWPM driver, read or write of only 32 bit data
|
||||
* requested at a time.
|
||||
*/
|
||||
enum tegra_soc_hwpm_ip_reg_op {
|
||||
TEGRA_SOC_HWPM_IP_REG_OP_INVALID,
|
||||
TEGRA_SOC_HWPM_IP_REG_OP_READ,
|
||||
TEGRA_SOC_HWPM_IP_REG_OP_WRITE
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure describing hwpm ip ops. Once IP driver is ready
|
||||
* it will register with SOC HWPM driver with data and callback
|
||||
* functions listed here. On IP driver removal, un-register with
|
||||
* SOC HWPM driver.
|
||||
*/
|
||||
struct tegra_soc_hwpm_ip_ops {
|
||||
/*
|
||||
* IP instance identfier for SOC HWPM usage. This is base
|
||||
* address of IP instance included in device tree entry.
|
||||
* SOC HWPM should be able to map this to one instance in
|
||||
* supported IP aperture.
|
||||
*/
|
||||
__u64 ip_base_address;
|
||||
|
||||
/*
|
||||
* IP is a resource from HWPM perspective. Pass IP driver enum respect
|
||||
* to enum tegra_soc_hwpm_resource for HWPM usage. SOC HWPM should be
|
||||
* ableto map this identifier to one of supported resource structures.
|
||||
*/
|
||||
__u32 resource_enum;
|
||||
|
||||
/*
|
||||
* Opaque ip device handle used for callback from
|
||||
* SOC HWPM driver to IP drivers. This handle can be used
|
||||
* to access IP driver functionality with the callbacks.
|
||||
*/
|
||||
void *ip_dev;
|
||||
/*
|
||||
* hwpm_ip_pm is callback function to disable/enable
|
||||
* IP driver power management. Before SOC HWPM doing
|
||||
* perf measuremnts, this callback is called with
|
||||
* "disable = true ", so that IP driver will disable IP specific
|
||||
* power management to keep IP driver responsive. Once SOC HWPM is
|
||||
* done with perf measurement, this callaback is called
|
||||
* with "disable = true", so that IP driver can restore back
|
||||
* it's orignal power management.
|
||||
*/
|
||||
int (*hwpm_ip_pm)(void *dev, bool disable);
|
||||
/*
|
||||
* hwpm_ip_reg_op is callback function to do IP
|
||||
* register 32 bit read or write.
|
||||
* For read:
|
||||
* input : dev - IP device handle
|
||||
* input : reg_op - TEGRA_SOC_HWPM_IP_REG_OP_READ
|
||||
* input : inst_element_index - element index within IP instance
|
||||
* input : reg_offset - register offset
|
||||
* output: reg_data - u32 read value
|
||||
* For write:
|
||||
* input : dev - IP device handle
|
||||
* input : reg_op - TEGRA_SOC_HWPM_IP_REG_OP_WRITE
|
||||
* input : inst_element_index - element index within IP instance
|
||||
* input : reg_offset - register offset
|
||||
* output: reg_data - u32 write value
|
||||
* Return:
|
||||
* reg_op success / failure
|
||||
*/
|
||||
int (*hwpm_ip_reg_op)(void *dev,
|
||||
enum tegra_soc_hwpm_ip_reg_op reg_op,
|
||||
__u32 inst_element_index,
|
||||
__u64 reg_offset, __u32 *reg_data);
|
||||
|
||||
};
|
||||
|
||||
/*
|
||||
* tegra_soc_hwpm_ip_register: IP driver will call this function to register
|
||||
* with SOC HWPM driver with it's data and callbacks
|
||||
*/
|
||||
void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops);
|
||||
/*
|
||||
* tegra_soc_hwpm_ip_unregister: IP driver will call this function to unregister
|
||||
* with SOC HWPM driver.
|
||||
*/
|
||||
void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops);
|
||||
|
||||
#endif /* TEGRA_SOC_HWPM_UAPI_H */
|
||||
Reference in New Issue
Block a user