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tegra: hwpm: Update PMMSYS CG2 SLCG field values

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Update driver release function to write all SLCG fields of PMMSYS CG2
with prod values which enables SLCG for SOC HWPM HW.
Modify driver open function to correctly disable SLCG through all PMMSYS
CG2 fields.

THWPM-2

Change-Id: Id7f725c0cf3f05179295002479f9422cc99a2297
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2585982
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2021-08-26 17:42:11 -07:00
committed by mobile promotions
parent 93b933c955
commit 818008bdaf
2 changed files with 28 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
include/hw/t234/hw_pmmsys_soc_hwpm.h
View File

@@ -95,10 +95,19 @@
#define pmmsys_sys0router_perfmonstatus_merged_m() (0x7U << 0U) #define pmmsys_sys0router_perfmonstatus_merged_m() (0x7U << 0U)
#define pmmsys_sys0router_perfmonstatus_merged_v(r) (((r) >> 0U) & 0x7U) #define pmmsys_sys0router_perfmonstatus_merged_v(r) (((r) >> 0U) & 0x7U)
#define pmmsys_sys0router_cg2_r() (0x0f14d018U) #define pmmsys_sys0router_cg2_r() (0x0f14d018U)
#define pmmsys_sys0router_cg2_slcg_f(v) (((v) & 0x3U) << 0U) #define pmmsys_sys0router_cg2_slcg_perfmon_m() (0x1U << 0U)
#define pmmsys_sys0router_cg2_slcg_perfmon_disabled_v() (0x00000001U)
#define pmmsys_sys0router_cg2_slcg_perfmon_disabled_f() (0x1U)
#define pmmsys_sys0router_cg2_slcg_perfmon__prod_v() (0x00000000U)
#define pmmsys_sys0router_cg2_slcg_perfmon__prod_f() (0x0U)
#define pmmsys_sys0router_cg2_slcg_router_m() (0x1U << 1U)
#define pmmsys_sys0router_cg2_slcg_router_disabled_v() (0x00000001U)
#define pmmsys_sys0router_cg2_slcg_router_disabled_f() (0x2U)
#define pmmsys_sys0router_cg2_slcg_router__prod_v() (0x00000000U)
#define pmmsys_sys0router_cg2_slcg_router__prod_f() (0x0U)
#define pmmsys_sys0router_cg2_slcg_m() (0x3U << 0U) #define pmmsys_sys0router_cg2_slcg_m() (0x3U << 0U)
#define pmmsys_sys0router_cg2_slcg_enabled_v() (0x00000000U)
#define pmmsys_sys0router_cg2_slcg_enabled_f() (0x0U)
#define pmmsys_sys0router_cg2_slcg_disabled_v() (0x00000003U) #define pmmsys_sys0router_cg2_slcg_disabled_v() (0x00000003U)
#define pmmsys_sys0router_cg2_slcg_disabled_f() (0x3U) #define pmmsys_sys0router_cg2_slcg_disabled_f() (0x3U)
#define pmmsys_sys0router_cg2_slcg__prod_v() (0x00000000U)
#define pmmsys_sys0router_cg2_slcg__prod_f() (0x0U)
#endif #endif

23
tegra-soc-hwpm-ioctl.c
View File

@@ -1174,6 +1174,8 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp)
unsigned int minor = iminor(inode); unsigned int minor = iminor(inode);
struct tegra_soc_hwpm *hwpm = NULL; struct tegra_soc_hwpm *hwpm = NULL;
struct resource *res = NULL; struct resource *res = NULL;
u32 field_mask = 0U;
u32 field_val = 0U;
u32 i; u32 i;
u64 num_regs = 0; u64 num_regs = 0;
@@ -1314,7 +1316,6 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp)
} }
hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR].reserved = true; hwpm_resources[TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR].reserved = true;
/* FIXME: Remove after verification */
/* Disable SLCG */ /* Disable SLCG */
ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_cg2_r() - addr_map_pma_base_r(), pmasys_cg2_r() - addr_map_pma_base_r(),
@@ -1326,11 +1327,15 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp)
goto fail; goto fail;
} }
field_mask = pmmsys_sys0router_cg2_slcg_perfmon_m() |
pmmsys_sys0router_cg2_slcg_router_m() |
pmmsys_sys0router_cg2_slcg_m();
field_val = pmmsys_sys0router_cg2_slcg_perfmon_disabled_f() |
pmmsys_sys0router_cg2_slcg_router_disabled_f() |
pmmsys_sys0router_cg2_slcg_disabled_f();
ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_RTR_DT, ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_RTR_DT,
pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(), pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(),
pmmsys_sys0router_cg2_slcg_m(), field_mask, field_val, false, false);
pmmsys_sys0router_cg2_slcg_disabled_f(),
false, false);
if (ret < 0) { if (ret < 0) {
tegra_soc_hwpm_err("Unable to disable ROUTER SLCG"); tegra_soc_hwpm_err("Unable to disable ROUTER SLCG");
ret = -EIO; ret = -EIO;
@@ -1605,7 +1610,6 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp)
} }
hwpm->mem_bytes_dma_buf = NULL; hwpm->mem_bytes_dma_buf = NULL;
/* FIXME: Remove after verification */
/* Enable SLCG */ /* Enable SLCG */
err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT, err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_cg2_r() - addr_map_pma_base_r(), pmasys_cg2_r() - addr_map_pma_base_r(),
@@ -1613,10 +1617,15 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp)
pmasys_cg2_slcg_enabled_f(), false, false); pmasys_cg2_slcg_enabled_f(), false, false);
RELEASE_FAIL("Unable to enable PMA SLCG"); RELEASE_FAIL("Unable to enable PMA SLCG");
field_mask = pmmsys_sys0router_cg2_slcg_perfmon_m() |
pmmsys_sys0router_cg2_slcg_router_m() |
pmmsys_sys0router_cg2_slcg_m();
field_val = pmmsys_sys0router_cg2_slcg_perfmon__prod_f() |
pmmsys_sys0router_cg2_slcg_router__prod_f() |
pmmsys_sys0router_cg2_slcg__prod_f();
err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_RTR_DT, err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_RTR_DT,
pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(), pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(),
pmmsys_sys0router_cg2_slcg_m(), field_mask, field_val, false, false);
pmmsys_sys0router_cg2_slcg_enabled_f(), false, false);
RELEASE_FAIL("Unable to enable ROUTER SLCG"); RELEASE_FAIL("Unable to enable ROUTER SLCG");
/* Unmap PMA and RTR apertures */ /* Unmap PMA and RTR apertures */