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tegra: hwpm: Fix EMC Fuse Mask calculation.

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A recent change has led to EMC fuse mask calculation regression.
This is being corrected in this patch. The emc_fuse_disable mask is
set in such a way that, each bit corresponds to 4 MSS Channels.
For example, emc_fuse_disable mask=1100, corresponds to MSS_Channel0
to MSS_Channel7 being present, while MSS_Channel8 to MSS_Channel15
are floorswept. However, in HWPM Driver, the logic to represent
a floorswept IP element is indicated by '1'. Correct the logic to
indicate this.

Bug 4490868

Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: Ia3825db29715e04aa43822283b160252d00f0a81
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3099298
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
vasukis
2024-03-19 01:23:19 +00:00
committed by mobile promotions
parent be41a4158c
commit 89426a7e0a
1 changed files with 2 additions and 2 deletions
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4
drivers/tegra/hwpm/hal/t234/t234_ip.c
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT // SPDX-License-Identifier: MIT
/* /*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -236,7 +236,7 @@ static int t234_hwpm_validate_emc_config(struct tegra_soc_hwpm *hwpm)
* Convert floorsweep fuse value to available EMC elements. * Convert floorsweep fuse value to available EMC elements.
*/ */
do { do {
if (emc_disable_fuse_val & (0x1U << emc_disable_fuse_bit_idx)) { if (!(emc_disable_fuse_val & (0x1U << emc_disable_fuse_bit_idx))) {
emc_element_floorsweep_mask |= emc_element_floorsweep_mask |=
(0xFU << (emc_disable_fuse_bit_idx * 4U)); (0xFU << (emc_disable_fuse_bit_idx * 4U));
} }