From 98c51d644bb516f52568a0bc5ca2165ee9dc75f6 Mon Sep 17 00:00:00 2001 From: vasukis Date: Tue, 14 Jan 2025 04:08:46 +0000 Subject: [PATCH] tegra: hwpm: t264: Enable VI and ISP compilation Enable Camera (VI and ISP) IP file compilation in HWPM driver for AV+L builds only. Bug 4345706 Signed-off-by: vasukis Change-Id: If647e7e25ce7d1a853cc7c298780538e03392ec0 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3283197 Reviewed-by: Besar Wicaksono Reviewed-by: svcacv GVS: buildbot_gerritrpt Reviewed-by: Yifei Wan --- drivers/tegra/hwpm/Makefile.t264.sources | 8 ++++- drivers/tegra/hwpm/hal/t264/t264_ip.c | 32 +++++++++++++++---- .../hwpm/hal/t264/t264_regops_allowlist.c | 18 ++++++++--- .../hwpm/hal/t264/t264_regops_allowlist.h | 6 ++-- 4 files changed, 49 insertions(+), 15 deletions(-) diff --git a/drivers/tegra/hwpm/Makefile.t264.sources b/drivers/tegra/hwpm/Makefile.t264.sources index e502dfa..ac84c1b 100644 --- a/drivers/tegra/hwpm/Makefile.t264.sources +++ b/drivers/tegra/hwpm/Makefile.t264.sources @@ -1,6 +1,6 @@ # -*- mode: makefile -*- # -# Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -88,4 +88,10 @@ nvhwpm-t264-objs += hal/t264/ip/ucf_csw/t264_ucf_csw.o ccflags-y += -DCONFIG_T264_HWPM_IP_CPU nvhwpm-t264-objs += hal/t264/ip/cpu/t264_cpu.o +ccflags-y += -DCONFIG_T264_HWPM_IP_VI +nvhwpm-t264-objs += hal/t264/ip/vi/t264_vi.o + +ccflags-y += -DCONFIG_T264_HWPM_IP_ISP +nvhwpm-t264-objs += hal/t264/ip/isp/t264_isp.o + endif diff --git a/drivers/tegra/hwpm/hal/t264/t264_ip.c b/drivers/tegra/hwpm/hal/t264/t264_ip.c index 946136e..cb76eb7 100644 --- a/drivers/tegra/hwpm/hal/t264/t264_ip.c +++ b/drivers/tegra/hwpm/hal/t264/t264_ip.c @@ -80,12 +80,6 @@ int t264_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, #endif #if defined(CONFIG_T264_HWPM_IP_CPU) case T264_HWPM_IP_CPU: -#endif -#if defined(CONFIG_T264_HWPM_IP_VI) - case T264_HWPM_IP_VI: -#endif -#if defined(CONFIG_T264_HWPM_IP_ISP) - case T264_HWPM_IP_ISP: #endif ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops, base_address, ip_idx, available); @@ -97,6 +91,32 @@ int t264_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, goto fail; } break; + +#if defined(CONFIG_T264_HWPM_IP_VI) + case T264_HWPM_IP_VI: +#endif +#if defined(CONFIG_T264_HWPM_IP_ISP) + case T264_HWPM_IP_ISP: +#endif + if (tegra_hwpm_is_hypervisor_mode()) { + /* + * VI and ISP are enabled only on AV+L configuration + * as the camera driver is not supported on L4T. + */ + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops, + base_address, ip_idx, available); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "Failed to %s fs/ops for IP %d (base 0x%llx)", + available == true ? "set" : "reset", + ip_idx, (unsigned long long)base_address); + goto fail; + } + } else { + tegra_hwpm_err(hwpm, "Invalid IP %d for ip_ops", ip_idx); + } + break; + #if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL) case T264_HWPM_IP_MSS_CHANNEL: #endif diff --git a/drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.c b/drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.c index 9128e96..610d622 100644 --- a/drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.c +++ b/drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -224,10 +224,18 @@ struct allowlist t264_cpucore_alist[4] = { {0x00000018, true}, }; -struct allowlist t264_vi_alist[1] = { - {0x0000c004, true}, +struct allowlist t264_vi_alist[5] = { + {0x00030008, true}, + {0x0003000c, true}, + {0x00030010, true}, + {0x00030014, true}, + {0x00030018, true}, }; -struct allowlist t264_isp_alist[1] = { - {0x0000c004, true}, +struct allowlist t264_isp_alist[5] = { + {0x00030008, true}, + {0x0003000c, true}, + {0x00030010, true}, + {0x00030014, true}, + {0x00030018, true}, }; diff --git a/drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.h b/drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.h index 7280db8..eff4cb0 100644 --- a/drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.h +++ b/drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -43,7 +43,7 @@ extern struct allowlist t264_ucf_msw_slc_alist[1]; extern struct allowlist t264_ucf_psn_psw_alist[2]; extern struct allowlist t264_ucf_csw_alist[2]; extern struct allowlist t264_cpucore_alist[4]; -extern struct allowlist t264_vi_alist[1]; -extern struct allowlist t264_isp_alist[1]; +extern struct allowlist t264_vi_alist[5]; +extern struct allowlist t264_isp_alist[5]; #endif /* T264_HWPM_REGOPS_ALLOWLIST_H */