From aaf8e7f5e1b8d2f357e82446e600a141c8f7cd08 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Fri, 18 Feb 2022 10:00:32 -0800 Subject: [PATCH] tegra: hwpm: modify floorsweep info for MSS For MSS channel, hwpm client expects floorsweep info mask to indicate available MSS chanenel perfmuxes. HWPM driver would prefer to follow common fs_mask logic for IPs and is being discussed. Temporarily update floorsweep info logic for MSS channel, until floorsweep info IOCTL modifications are finalized. Bug 3477617 Change-Id: I75b51ccc60151e801dec50fa32b15b951db6e47e Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2672291 Tested-by: mobile promotions Reviewed-by: mobile promotions --- hal/t234/t234_hwpm_ip_utils.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hal/t234/t234_hwpm_ip_utils.c b/hal/t234/t234_hwpm_ip_utils.c index 99b4dc9..95f7213 100644 --- a/hal/t234/t234_hwpm_ip_utils.c +++ b/hal/t234/t234_hwpm_ip_utils.c @@ -635,6 +635,8 @@ int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm, u32 ip_index, u64 *fs_mask, u8 *ip_status) { u32 ip_idx = 0U; + u32 i = 0U; + u32 mcc_fs_mask = 0U; struct tegra_soc_hwpm_chip *active_chip = NULL; struct hwpm_ip *chip_ip = NULL; @@ -657,7 +659,17 @@ int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm, } else { active_chip = hwpm->active_chip; chip_ip = active_chip->chip_ips[ip_idx]; - *fs_mask = chip_ip->fs_mask; + /* TODO: Update after fS IOCTL discussion */ + if (ip_idx == T234_HWPM_IP_MSS_CHANNEL) { + for (i = 0U; i < 4U; i++) { + if (((0x1U << i) & chip_ip->fs_mask) != 0U) { + mcc_fs_mask |= (0xFU << i); + } + } + *fs_mask = mcc_fs_mask; + } else { + *fs_mask = chip_ip->fs_mask; + } *ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID; }