From ab110e5f274d17371be894119e52e150fd427e5d Mon Sep 17 00:00:00 2001 From: vasukis Date: Thu, 16 May 2024 20:16:56 +0000 Subject: [PATCH] tegra: hwpm: Add OPT_HWPM_DISABLE mask definition - Add OPT_HWPM_DISABLE fuse (offset 0xd18) mask for NEXT3 chip. Jira THWPM-73 Signed-off-by: vasukis Change-Id: Idc403276886fb2f00b18a69be2c285bc8b3da000 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3139627 Reviewed-by: Seema Khowala Reviewed-by: Vedashree Vidwans GVS: buildbot_gerritrpt --- drivers/tegra/hwpm/include/tegra_hwpm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h index 337be5c..623a2d0 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -39,6 +39,7 @@ #define TEGRA_HWPM_FUSE_PRODUCTION_MODE_MASK BIT(0) #define TEGRA_HWPM_FUSE_SECURITY_MODE_MASK BIT(1) #define TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK BIT(2) +#define TEGRA_HWPM_FUSE_OPT_HWPM_DISABLE_MASK BIT(3) /* Indicate the prescence of HWPM-IP debug interface for devctl calls */ #define TEGRA_HWPM_IP_DEBUG_FD_INVALID -1