tegra: hwpm: th500: update ip structure files

Update all IP files to include aperture_index variable in
hwpm_ip_aperture structures. This index will be used to
translate dynamic element index to static index.

Bug 4707244

Change-Id: I9999a7dc26c366381f37aea5f602a662d8707a8b
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3197913
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>

drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmon_element_static_array[
 	TH500_HWPM_IP_C2C_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -53,6 +54,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -73,6 +75,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	TH500_HWPM_IP_C2C_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -88,6 +91,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -103,6 +107,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -118,6 +123,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -133,6 +139,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -148,6 +155,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -163,6 +171,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -178,6 +187,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -193,6 +203,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -208,6 +219,7 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 9U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvlctrl.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_nvlctrl_inst0_perfmon_element_static_array[
 	TH500_HWPM_IP_NVLCTRL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -57,6 +58,7 @@ static struct hwpm_ip_aperture th500_nvlctrl_inst1_perfmon_element_static_array[
 	TH500_HWPM_IP_NVLCTRL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -77,6 +79,7 @@ static struct hwpm_ip_aperture th500_nvlctrl_inst0_perfmux_element_static_array[
 	TH500_HWPM_IP_NVLCTRL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -96,6 +99,7 @@ static struct hwpm_ip_aperture th500_nvlctrl_inst1_perfmux_element_static_array[
 	TH500_HWPM_IP_NVLCTRL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvlctrl.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvlrx.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	TH500_HWPM_IP_NVLRX_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -53,6 +54,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -69,6 +71,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -85,6 +88,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -101,6 +105,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -117,6 +122,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -133,6 +139,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -149,6 +156,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -165,6 +173,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -181,6 +190,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 9U,
 		.dt_mmio = NULL,
@@ -197,6 +207,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 10U,
 		.element_index_mask = BIT(10),
 		.element_index = 10U,
 		.dt_mmio = NULL,
@@ -213,6 +224,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 11U,
 		.element_index_mask = BIT(11),
 		.element_index = 11U,
 		.dt_mmio = NULL,
@@ -233,6 +245,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	TH500_HWPM_IP_NVLRX_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -249,6 +262,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -265,6 +279,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -281,6 +296,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -297,6 +313,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -313,6 +330,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -329,6 +347,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -345,6 +364,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -361,6 +381,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -377,6 +398,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 9U,
 		.dt_mmio = NULL,
@@ -393,6 +415,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 10U,
 		.element_index_mask = BIT(10),
 		.element_index = 10U,
 		.dt_mmio = NULL,
@@ -409,6 +432,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 11U,
 		.element_index_mask = BIT(11),
 		.element_index = 11U,
 		.dt_mmio = NULL,
@@ -429,6 +453,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	TH500_HWPM_IP_NVLRX_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -444,6 +469,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -459,6 +485,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -474,6 +501,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -489,6 +517,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -504,6 +533,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -519,6 +549,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -534,6 +565,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -549,6 +581,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -564,6 +597,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 9U,
 		.dt_mmio = NULL,
@@ -579,6 +613,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 10U,
 		.element_index_mask = BIT(10),
 		.element_index = 10U,
 		.dt_mmio = NULL,
@@ -594,6 +629,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 11U,
 		.element_index_mask = BIT(11),
 		.element_index = 11U,
 		.dt_mmio = NULL,
@@ -613,6 +649,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	TH500_HWPM_IP_NVLRX_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -628,6 +665,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -643,6 +681,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -658,6 +697,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -673,6 +713,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -688,6 +729,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -703,6 +745,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -718,6 +761,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -733,6 +777,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -748,6 +793,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 9U,
 		.dt_mmio = NULL,
@@ -763,6 +809,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 10U,
 		.element_index_mask = BIT(10),
 		.element_index = 10U,
 		.dt_mmio = NULL,
@@ -778,6 +825,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 11U,
 		.element_index_mask = BIT(11),
 		.element_index = 11U,
 		.dt_mmio = NULL,
@@ -797,6 +845,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_broadcast_element_static_array[
 	TH500_HWPM_IP_NVLRX_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -812,6 +861,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst0_broadcast_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -831,6 +881,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_broadcast_element_static_array[
 	TH500_HWPM_IP_NVLRX_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -846,6 +897,7 @@ static struct hwpm_ip_aperture th500_nvlrx_inst1_broadcast_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvlrx.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvltx.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	TH500_HWPM_IP_NVLTX_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -53,6 +54,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -69,6 +71,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -85,6 +88,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -101,6 +105,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -117,6 +122,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -133,6 +139,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -149,6 +156,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -165,6 +173,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -181,6 +190,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 9U,
 		.dt_mmio = NULL,
@@ -197,6 +207,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 10U,
 		.element_index_mask = BIT(10),
 		.element_index = 10U,
 		.dt_mmio = NULL,
@@ -213,6 +224,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 11U,
 		.element_index_mask = BIT(11),
 		.element_index = 11U,
 		.dt_mmio = NULL,
@@ -233,6 +245,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	TH500_HWPM_IP_NVLTX_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -249,6 +262,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -265,6 +279,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -281,6 +296,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -297,6 +313,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -313,6 +330,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -329,6 +347,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -345,6 +364,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -361,6 +381,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -377,6 +398,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 9U,
 		.dt_mmio = NULL,
@@ -393,6 +415,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 10U,
 		.element_index_mask = BIT(10),
 		.element_index = 10U,
 		.dt_mmio = NULL,
@@ -409,6 +432,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 11U,
 		.element_index_mask = BIT(11),
 		.element_index = 11U,
 		.dt_mmio = NULL,
@@ -429,6 +453,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	TH500_HWPM_IP_NVLTX_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -444,6 +469,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -459,6 +485,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -474,6 +501,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -489,6 +517,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -504,6 +533,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -519,6 +549,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -534,6 +565,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -549,6 +581,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -564,6 +597,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 9U,
 		.dt_mmio = NULL,
@@ -579,6 +613,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 10U,
 		.element_index_mask = BIT(10),
 		.element_index = 10U,
 		.dt_mmio = NULL,
@@ -594,6 +629,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 11U,
 		.element_index_mask = BIT(11),
 		.element_index = 11U,
 		.dt_mmio = NULL,
@@ -613,6 +649,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	TH500_HWPM_IP_NVLTX_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -628,6 +665,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -643,6 +681,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -658,6 +697,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -673,6 +713,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -688,6 +729,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -703,6 +745,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -718,6 +761,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -733,6 +777,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -748,6 +793,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 9U,
 		.dt_mmio = NULL,
@@ -763,6 +809,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 10U,
 		.element_index_mask = BIT(10),
 		.element_index = 10U,
 		.dt_mmio = NULL,
@@ -778,6 +825,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 11U,
 		.element_index_mask = BIT(11),
 		.element_index = 11U,
 		.dt_mmio = NULL,
@@ -797,6 +845,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_broadcast_element_static_array[
 	TH500_HWPM_IP_NVLTX_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -812,6 +861,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst0_broadcast_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -831,6 +881,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_broadcast_element_static_array[
 	TH500_HWPM_IP_NVLTX_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -846,6 +897,7 @@ static struct hwpm_ip_aperture th500_nvltx_inst1_broadcast_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/c_nvlink/th500_nvltx.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),

drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_cl2_inst0_perfmon_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -53,6 +54,7 @@ static struct hwpm_ip_aperture th500_cl2_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -73,6 +75,7 @@ static struct hwpm_ip_aperture th500_cl2_inst1_perfmon_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -89,6 +92,7 @@ static struct hwpm_ip_aperture th500_cl2_inst1_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -109,6 +113,7 @@ static struct hwpm_ip_aperture th500_cl2_inst2_perfmon_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -125,6 +130,7 @@ static struct hwpm_ip_aperture th500_cl2_inst2_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -145,6 +151,7 @@ static struct hwpm_ip_aperture th500_cl2_inst3_perfmon_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -161,6 +168,7 @@ static struct hwpm_ip_aperture th500_cl2_inst3_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -181,6 +189,7 @@ static struct hwpm_ip_aperture th500_cl2_inst4_perfmon_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -197,6 +206,7 @@ static struct hwpm_ip_aperture th500_cl2_inst4_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -217,6 +227,7 @@ static struct hwpm_ip_aperture th500_cl2_inst5_perfmon_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -233,6 +244,7 @@ static struct hwpm_ip_aperture th500_cl2_inst5_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -253,6 +265,7 @@ static struct hwpm_ip_aperture th500_cl2_inst6_perfmon_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -269,6 +282,7 @@ static struct hwpm_ip_aperture th500_cl2_inst6_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -289,6 +303,7 @@ static struct hwpm_ip_aperture th500_cl2_inst7_perfmon_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -305,6 +320,7 @@ static struct hwpm_ip_aperture th500_cl2_inst7_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -325,6 +341,7 @@ static struct hwpm_ip_aperture th500_cl2_inst0_perfmux_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -344,6 +361,7 @@ static struct hwpm_ip_aperture th500_cl2_inst1_perfmux_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -363,6 +381,7 @@ static struct hwpm_ip_aperture th500_cl2_inst2_perfmux_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -382,6 +401,7 @@ static struct hwpm_ip_aperture th500_cl2_inst3_perfmux_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -401,6 +421,7 @@ static struct hwpm_ip_aperture th500_cl2_inst4_perfmux_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -420,6 +441,7 @@ static struct hwpm_ip_aperture th500_cl2_inst5_perfmux_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -439,6 +461,7 @@ static struct hwpm_ip_aperture th500_cl2_inst6_perfmux_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -458,6 +481,7 @@ static struct hwpm_ip_aperture th500_cl2_inst7_perfmux_element_static_array[
 	TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),

drivers/tegra/hwpm/hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.c

@@ -37,8 +37,9 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmon_element_static_array[
 	TH500_HWPM_IP_MCF_C2C_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
-		.element_index = 0U,
+		.element_index = 1U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcfc2c0",
 		.device_index = TH500_MCFCTC0_PERFMON_DEVICE_NODE_INDEX,
@@ -53,8 +54,9 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmon_element_static_array[
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
-		.element_index = 1U,
+		.element_index = 2U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcfc2c1",
 		.device_index = TH500_MCFCTC1_PERFMON_DEVICE_NODE_INDEX,
@@ -73,6 +75,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	TH500_HWPM_IP_MCF_C2C_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -88,6 +91,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -103,6 +107,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -118,6 +123,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 3U,
 		.element_index_mask = BIT(3),
 		.element_index = 4U,
 		.dt_mmio = NULL,
@@ -133,6 +139,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 4U,
 		.element_index_mask = BIT(4),
 		.element_index = 5U,
 		.dt_mmio = NULL,
@@ -148,6 +155,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 5U,
 		.element_index_mask = BIT(5),
 		.element_index = 6U,
 		.dt_mmio = NULL,
@@ -163,6 +171,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 6U,
 		.element_index_mask = BIT(6),
 		.element_index = 7U,
 		.dt_mmio = NULL,
@@ -178,6 +187,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 7U,
 		.element_index_mask = BIT(7),
 		.element_index = 8U,
 		.dt_mmio = NULL,
@@ -193,6 +203,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 8U,
 		.element_index_mask = BIT(8),
 		.element_index = 9U,
 		.dt_mmio = NULL,
@@ -208,6 +219,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 9U,
 		.element_index_mask = BIT(9),
 		.element_index = 10U,
 		.dt_mmio = NULL,
@@ -227,6 +239,7 @@ static struct hwpm_ip_aperture th500_mcf_c2c_inst0_broadcast_element_static_arra
 	TH500_HWPM_IP_MCF_C2C_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),

drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmon_element_static_arra
 	TH500_HWPM_IP_MCF_CLINK_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -53,6 +54,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmon_element_static_arra
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -73,6 +75,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	TH500_HWPM_IP_MCF_CLINK_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -88,6 +91,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 11U,
 		.dt_mmio = NULL,
@@ -103,7 +107,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(2),
+		.aperture_index = 2U,
+		.element_index_mask = BIT(1),
 		.element_index = 12U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -118,7 +123,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(3),
+		.aperture_index = 3U,
+		.element_index_mask = BIT(2),
 		.element_index = 13U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -133,7 +139,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(4),
+		.aperture_index = 4U,
+		.element_index_mask = BIT(3),
 		.element_index = 14U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -148,7 +155,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(5),
+		.aperture_index = 5U,
+		.element_index_mask = BIT(4),
 		.element_index = 15U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -163,7 +171,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(6),
+		.aperture_index = 6U,
+		.element_index_mask = BIT(5),
 		.element_index = 16U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -178,7 +187,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(7),
+		.aperture_index = 7U,
+		.element_index_mask = BIT(6),
 		.element_index = 17U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -193,7 +203,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(8),
+		.aperture_index = 8U,
+		.element_index_mask = BIT(7),
 		.element_index = 18U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -208,7 +219,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(9),
+		.aperture_index = 9U,
+		.element_index_mask = BIT(8),
 		.element_index = 19U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -223,7 +235,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(10),
+		.aperture_index = 10U,
+		.element_index_mask = BIT(9),
 		.element_index = 20U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -238,7 +251,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(11),
+		.aperture_index = 11U,
+		.element_index_mask = BIT(10),
 		.element_index = 21U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -253,7 +267,8 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(12),
+		.aperture_index = 12U,
+		.element_index_mask = BIT(11),
 		.element_index = 22U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
@@ -272,6 +287,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_broadcast_element_static_ar
 	TH500_HWPM_IP_MCF_CLINK_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.c

@@ -37,8 +37,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
-		.element_index = 1U,
+		.element_index = 0U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core0",
 		.device_index = TH500_MCFCORE0_PERFMON_DEVICE_NODE_INDEX,
@@ -53,8 +54,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
-		.element_index = 2U,
+		.element_index = 1U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core1",
 		.device_index = TH500_MCFCORE1_PERFMON_DEVICE_NODE_INDEX,
@@ -73,8 +75,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst1_perfmon_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(2),
+		.element_index = 2U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core2",
 		.device_index = TH500_MCFCORE2_PERFMON_DEVICE_NODE_INDEX,
@@ -89,8 +92,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst1_perfmon_element_static_array
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(3),
+		.element_index = 3U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core3",
 		.device_index = TH500_MCFCORE3_PERFMON_DEVICE_NODE_INDEX,
@@ -109,8 +113,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst2_perfmon_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(4),
+		.element_index = 4U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core4",
 		.device_index = TH500_MCFCORE4_PERFMON_DEVICE_NODE_INDEX,
@@ -125,8 +130,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst2_perfmon_element_static_array
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(5),
+		.element_index = 5U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core5",
 		.device_index = TH500_MCFCORE5_PERFMON_DEVICE_NODE_INDEX,
@@ -145,8 +151,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst3_perfmon_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(6),
+		.element_index = 6U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core6",
 		.device_index = TH500_MCFCORE6_PERFMON_DEVICE_NODE_INDEX,
@@ -161,8 +168,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst3_perfmon_element_static_array
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(7),
+		.element_index = 7U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core7",
 		.device_index = TH500_MCFCORE7_PERFMON_DEVICE_NODE_INDEX,
@@ -181,8 +189,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst4_perfmon_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(8),
+		.element_index = 8U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core8",
 		.device_index = TH500_MCFCORE8_PERFMON_DEVICE_NODE_INDEX,
@@ -197,8 +206,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst4_perfmon_element_static_array
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(9),
+		.element_index = 9U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core9",
 		.device_index = TH500_MCFCORE9_PERFMON_DEVICE_NODE_INDEX,
@@ -217,8 +227,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst5_perfmon_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(10),
+		.element_index = 10U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core10",
 		.device_index = TH500_MCFCORE10_PERFMON_DEVICE_NODE_INDEX,
@@ -233,8 +244,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst5_perfmon_element_static_array
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(11),
+		.element_index = 11U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core11",
 		.device_index = TH500_MCFCORE11_PERFMON_DEVICE_NODE_INDEX,
@@ -253,8 +265,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst6_perfmon_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(12),
+		.element_index = 12U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core12",
 		.device_index = TH500_MCFCORE12_PERFMON_DEVICE_NODE_INDEX,
@@ -269,8 +282,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst6_perfmon_element_static_array
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(13),
+		.element_index = 13U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core13",
 		.device_index = TH500_MCFCORE13_PERFMON_DEVICE_NODE_INDEX,
@@ -289,8 +303,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst7_perfmon_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(14),
+		.element_index = 14U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core14",
 		.device_index = TH500_MCFCORE14_PERFMON_DEVICE_NODE_INDEX,
@@ -305,8 +320,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst7_perfmon_element_static_array
 	},
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(15),
+		.element_index = 15U,
 		.dt_mmio = NULL,
 		.name = "perfmon_mcf_core15",
 		.device_index = TH500_MCFCORE15_PERFMON_DEVICE_NODE_INDEX,
@@ -325,6 +341,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -340,6 +357,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -359,8 +377,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst1_perfmux_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(2),
+		.element_index = 3U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc2_base_r(),
@@ -374,8 +393,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst1_perfmux_element_static_array
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(3),
+		.element_index = 4U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc3_base_r(),
@@ -393,8 +413,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst2_perfmux_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(4),
+		.element_index = 5U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc4_base_r(),
@@ -408,8 +429,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst2_perfmux_element_static_array
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(5),
+		.element_index = 6U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc5_base_r(),
@@ -427,8 +449,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst3_perfmux_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(6),
+		.element_index = 7U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc6_base_r(),
@@ -442,8 +465,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst3_perfmux_element_static_array
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(7),
+		.element_index = 8U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc7_base_r(),
@@ -461,8 +485,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst4_perfmux_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(8),
+		.element_index = 9U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc8_base_r(),
@@ -476,8 +501,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst4_perfmux_element_static_array
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(9),
+		.element_index = 10U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc9_base_r(),
@@ -495,8 +521,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst5_perfmux_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(10),
+		.element_index = 11U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc10_base_r(),
@@ -510,8 +537,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst5_perfmux_element_static_array
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(11),
+		.element_index = 12U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc11_base_r(),
@@ -529,8 +557,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst6_perfmux_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(12),
+		.element_index = 13U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc12_base_r(),
@@ -544,8 +573,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst6_perfmux_element_static_array
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(13),
+		.element_index = 14U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc13_base_r(),
@@ -563,8 +593,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst7_perfmux_element_static_array
 	TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(14),
+		.element_index = 15U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc14_base_r(),
@@ -578,8 +609,9 @@ static struct hwpm_ip_aperture th500_mcf_core_inst7_perfmux_element_static_array
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(1),
+		.aperture_index = 1U,
-		.element_index = 2U,
+		.element_index_mask = BIT(15),
+		.element_index = 16U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc15_base_r(),
@@ -597,6 +629,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_broadcast_element_static_arr
 	TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -616,6 +649,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst1_broadcast_element_static_arr
 	TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -635,6 +669,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst2_broadcast_element_static_arr
 	TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -654,6 +689,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst3_broadcast_element_static_arr
 	TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -673,6 +709,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst4_broadcast_element_static_arr
 	TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -692,6 +729,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst5_broadcast_element_static_arr
 	TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -711,6 +749,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst6_broadcast_element_static_arr
 	TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -730,6 +769,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst7_broadcast_element_static_arr
 	TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/mcf_soc/th500_mcf_soc.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_mcf_soc_inst0_perfmon_element_static_array[
 	TH500_HWPM_IP_MCF_SOC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -57,6 +58,7 @@ static struct hwpm_ip_aperture th500_mcf_soc_inst0_perfmux_element_static_array[
 	TH500_HWPM_IP_MCF_SOC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -72,6 +74,7 @@ static struct hwpm_ip_aperture th500_mcf_soc_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 1U,
 		.element_index_mask = BIT(1),
 		.element_index = 2U,
 		.dt_mmio = NULL,
@@ -87,6 +90,7 @@ static struct hwpm_ip_aperture th500_mcf_soc_inst0_perfmux_element_static_array[
 	},
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 2U,
 		.element_index_mask = BIT(2),
 		.element_index = 3U,
 		.dt_mmio = NULL,
@@ -121,6 +125,7 @@ static struct hwpm_ip_aperture th500_mcf_soc_inst0_broadcast_element_static_arra
 	TH500_HWPM_IP_MCF_SOC_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -57,6 +58,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst1_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -77,6 +79,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst2_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -97,6 +100,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst3_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -117,6 +121,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst4_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -137,6 +142,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst5_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -157,6 +163,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst6_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -177,6 +184,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst7_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -197,6 +205,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst8_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -217,6 +226,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst9_perfmon_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -237,6 +247,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst10_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -257,6 +268,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst11_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -277,6 +289,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst12_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -297,6 +310,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst13_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -317,6 +331,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst14_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -337,6 +352,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst15_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -357,6 +373,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst16_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -377,6 +394,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst17_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -397,6 +415,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst18_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -417,6 +436,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst19_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -437,6 +457,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst20_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -457,6 +478,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst21_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -477,6 +499,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst22_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -497,6 +520,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst23_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -517,6 +541,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst24_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -537,6 +562,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst25_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -557,6 +583,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst26_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -597,8 +624,9 @@ static struct hwpm_ip_aperture th500_mss_channel_inst28_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
-		.element_index_mask = BIT(0),
+		.aperture_index = 0U,
-		.element_index = 1U,
+		.element_index_mask = BIT(28),
+		.element_index = 29U,
 		.dt_mmio = NULL,
 		.name = "perfmon_msschannel_parth0",
 		.device_index = TH500_MSS_CHANNEL_PARTH0_PERFMON_DEVICE_NODE_INDEX,
@@ -617,6 +645,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst29_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -637,6 +666,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst30_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -657,6 +687,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst31_perfmon_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -677,6 +708,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -696,6 +728,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst1_perfmux_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -715,6 +748,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst2_perfmux_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -753,6 +787,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst4_perfmux_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -772,8 +807,8 @@ static struct hwpm_ip_aperture th500_mss_channel_inst5_perfmux_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
-		.element_index_mask = BIT(0),
+		.element_index_mask = BIT(5),
-		.element_index = 1U,
+		.element_index = 6U,
 		.dt_mmio = NULL,
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc5_base_r(),
@@ -791,6 +826,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst6_perfmux_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -810,6 +846,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst7_perfmux_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -829,6 +866,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst8_perfmux_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -848,6 +886,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst9_perfmux_element_static_ar
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -867,6 +906,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst10_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -886,6 +926,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst11_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -905,6 +946,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst12_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -924,6 +966,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst13_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -943,6 +986,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst14_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -962,6 +1006,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst15_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -981,6 +1026,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst16_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1000,6 +1046,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst17_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1019,6 +1066,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst18_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1038,6 +1086,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst19_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1057,6 +1106,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst20_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1076,6 +1126,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst21_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1095,6 +1146,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst22_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1114,6 +1166,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst23_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1133,6 +1186,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst24_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1152,6 +1206,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst25_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1171,6 +1226,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst26_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1190,6 +1246,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst27_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1209,6 +1266,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst28_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1228,6 +1286,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst29_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1247,6 +1306,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst30_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1266,6 +1326,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst31_perfmux_element_static_a
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -1285,6 +1346,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1304,6 +1366,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst1_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1323,6 +1386,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst2_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1342,6 +1406,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst3_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1361,6 +1426,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst4_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1380,6 +1446,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst5_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1399,6 +1466,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst6_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1418,6 +1486,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst7_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1437,6 +1506,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst8_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1456,6 +1526,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst9_broadcast_element_static_
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -1475,6 +1546,7 @@ static struct hwpm_ip_aperture th500_mss_channel_inst10_broadcast_element_static
 	TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -57,6 +58,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst1_perfmon_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -77,6 +79,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst2_perfmon_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -97,6 +100,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst3_perfmon_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -117,6 +121,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst4_perfmon_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -137,6 +142,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst5_perfmon_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -157,6 +163,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst6_perfmon_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -177,6 +184,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst7_perfmon_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -197,6 +205,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmux_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -216,6 +225,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst1_perfmux_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -235,6 +245,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst2_perfmux_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -254,6 +265,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst3_perfmux_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -273,6 +285,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst4_perfmux_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -292,6 +305,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst5_perfmux_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -311,6 +325,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst6_perfmux_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -330,6 +345,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst7_perfmux_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 1U,
 		.dt_mmio = NULL,
@@ -349,6 +365,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_broadcast_element_static_arra
 	TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -364,10 +381,12 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_broadcast_element_static_arra
 	},
 };
 
+
 static struct hwpm_ip_aperture th500_mss_hub_inst1_broadcast_element_static_array[
 	TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -387,6 +406,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst2_broadcast_element_static_arra
 	TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -406,6 +426,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst3_broadcast_element_static_arra
 	TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -425,6 +446,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst4_broadcast_element_static_arra
 	TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -444,6 +466,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst5_broadcast_element_static_arra
 	TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -463,6 +486,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst6_broadcast_element_static_arra
 	TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -482,6 +506,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst7_broadcast_element_static_arra
 	TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_BROADCAST,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst0_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -57,6 +58,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst1_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -77,6 +79,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst2_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -97,6 +100,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst3_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -117,6 +121,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst4_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -137,6 +142,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst5_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -157,6 +163,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst6_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -177,6 +184,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst7_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -197,6 +205,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst8_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -217,6 +226,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst9_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -237,6 +247,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst0_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -256,6 +267,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst1_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -275,6 +287,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst2_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -294,6 +307,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst3_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -313,6 +327,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst4_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -332,6 +347,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst5_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -351,6 +367,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst6_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -370,6 +387,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst7_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -389,6 +407,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst8_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -408,6 +427,7 @@ static struct hwpm_ip_aperture th500_pcie_xalrc_inst9_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),

drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst0_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -57,6 +58,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst1_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -77,6 +79,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst2_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -97,6 +100,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst3_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -117,6 +121,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst4_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -137,6 +142,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst5_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -157,6 +163,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst6_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -177,6 +184,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst7_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -197,6 +205,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst8_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -217,6 +226,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst9_perfmon_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -237,6 +247,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst0_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -256,6 +267,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst1_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -275,6 +287,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst2_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -294,6 +307,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst3_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -313,6 +327,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst4_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -332,6 +347,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst5_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -351,6 +367,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst6_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -370,6 +387,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst7_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -389,6 +407,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst8_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -408,6 +427,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlq_inst9_perfmux_element_static_arra
 	TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),

drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst0_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -57,6 +58,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst1_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -77,6 +79,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst2_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -97,6 +100,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst3_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -117,6 +121,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst4_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -137,6 +142,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst5_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -157,6 +163,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst6_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -177,6 +184,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst7_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -197,6 +205,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst8_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -217,6 +226,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst9_perfmon_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -237,6 +247,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst0_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -256,6 +267,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst1_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -275,6 +287,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst2_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -294,6 +307,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst3_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -313,6 +327,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst4_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -332,6 +347,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst5_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -351,6 +367,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst6_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -370,6 +387,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst7_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -389,6 +407,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst8_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -408,6 +427,7 @@ static struct hwpm_ip_aperture th500_pcie_xtlrc_inst9_perfmux_element_static_arr
 	TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),

drivers/tegra/hwpm/hal/th500/soc/ip/smmu/th500_smmu.c

@@ -37,6 +37,7 @@ static struct hwpm_ip_aperture th500_smmu_inst0_perfmon_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -57,6 +58,7 @@ static struct hwpm_ip_aperture th500_smmu_inst1_perfmon_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -77,6 +79,7 @@ static struct hwpm_ip_aperture th500_smmu_inst2_perfmon_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -97,6 +100,7 @@ static struct hwpm_ip_aperture th500_smmu_inst3_perfmon_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -117,6 +121,7 @@ static struct hwpm_ip_aperture th500_smmu_inst4_perfmon_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMON_PER_INST] = {
 	{
 		.element_type = HWPM_ELEMENT_PERFMON,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -137,6 +142,7 @@ static struct hwpm_ip_aperture th500_smmu_inst0_perfmux_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -156,6 +162,7 @@ static struct hwpm_ip_aperture th500_smmu_inst1_perfmux_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -175,6 +182,7 @@ static struct hwpm_ip_aperture th500_smmu_inst2_perfmux_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -194,6 +202,7 @@ static struct hwpm_ip_aperture th500_smmu_inst3_perfmux_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,
@@ -213,6 +222,7 @@ static struct hwpm_ip_aperture th500_smmu_inst4_perfmux_element_static_array[
 	TH500_HWPM_IP_SMMU_NUM_PERFMUX_PER_INST] = {
 	{
 		.element_type = IP_ELEMENT_PERFMUX,
+		.aperture_index = 0U,
 		.element_index_mask = BIT(0),
 		.element_index = 0U,
 		.dt_mmio = NULL,

drivers/tegra/hwpm/hal/th500/soc/ip/smmu/th500_smmu.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: MIT */
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),