From b689a36372ffd6cf24f4f7921a1e910f6fcb69be Mon Sep 17 00:00:00 2001 From: Vishal Aslot Date: Wed, 27 Sep 2023 20:41:15 +0000 Subject: [PATCH] tegra: hwpm: th500: Add support for MSS HUB This patch adds support for MSS HUB performance monitoring in the driver. Bug 4287384 Signed-off-by: Vishal Aslot Change-Id: I35b8c8c9bf1eb8b43dc1baeb10a9701fbd3f2dd9 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2987019 GVS: Gerrit_Virtual_Submit Reviewed-by: Vedashree Vidwans --- drivers/tegra/hwpm/Makefile.th500.soc.sources | 3 + .../hal/th500/soc/ip/mss_hub/th500_mss_hub.c | 432 ++++++++++++++++++ .../hal/th500/soc/ip/mss_hub/th500_mss_hub.h | 48 ++ .../th500/soc/th500_soc_regops_allowlist.c | 2 +- .../th500/soc/th500_soc_regops_allowlist.h | 1 + .../tegra/hwpm/hal/th500/th500_interface.c | 27 +- drivers/tegra/hwpm/hal/th500/th500_internal.h | 2 + drivers/tegra/hwpm/hal/th500/th500_ip.c | 14 +- drivers/tegra/hwpm/include/tegra_hwpm.h | 2 + drivers/tegra/hwpm/os/linux/ip_utils.c | 6 + include/uapi/linux/tegra-soc-hwpm-uapi.h | 2 + 11 files changed, 518 insertions(+), 21 deletions(-) create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c create mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.h diff --git a/drivers/tegra/hwpm/Makefile.th500.soc.sources b/drivers/tegra/hwpm/Makefile.th500.soc.sources index 12e28fb..edc9f2a 100644 --- a/drivers/tegra/hwpm/Makefile.th500.soc.sources +++ b/drivers/tegra/hwpm/Makefile.th500.soc.sources @@ -54,4 +54,7 @@ nvhwpm-th500-soc-objs += hal/th500/soc/ip/c_nvlink/th500_nvlrx.o nvhwpm-th500-soc-objs += hal/th500/soc/ip/c_nvlink/th500_nvltx.o nvhwpm-th500-soc-objs += hal/th500/soc/ip/c_nvlink/th500_nvlctrl.o +ccflags-y += -DCONFIG_TH500_HWPM_IP_MSS_HUB +nvhwpm-th500-soc-objs += hal/th500/soc/ip/mss_hub/th500_mss_hub.o + endif diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c new file mode 100644 index 0000000..4291340 --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c @@ -0,0 +1,432 @@ +// SPDX-License-Identifier: MIT +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#include "th500_mss_hub.h" + +#include +#include +#include +#include + +static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = { + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = "perfmon_msshub0", + .device_index = TH500_MSSHUB0_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_msshub0_base_r(), + .end_abs_pa = addr_map_rpg_pm_msshub0_limit_r(), + .start_pa = addr_map_rpg_pm_msshub0_base_r(), + .end_pa = addr_map_rpg_pm_msshub0_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(1), + .element_index = 1U, + .dt_mmio = NULL, + .name = "perfmon_msshub1", + .device_index = TH500_MSSHUB1_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_msshub1_base_r(), + .end_abs_pa = addr_map_rpg_pm_msshub1_limit_r(), + .start_pa = addr_map_rpg_pm_msshub1_base_r(), + .end_pa = addr_map_rpg_pm_msshub1_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(2), + .element_index = 2U, + .dt_mmio = NULL, + .name = "perfmon_msshub2", + .device_index = TH500_MSSHUB2_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_msshub2_base_r(), + .end_abs_pa = addr_map_rpg_pm_msshub2_limit_r(), + .start_pa = addr_map_rpg_pm_msshub2_base_r(), + .end_pa = addr_map_rpg_pm_msshub2_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(3), + .element_index = 3U, + .dt_mmio = NULL, + .name = "perfmon_msshub3", + .device_index = TH500_MSSHUB3_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_msshub3_base_r(), + .end_abs_pa = addr_map_rpg_pm_msshub3_limit_r(), + .start_pa = addr_map_rpg_pm_msshub3_base_r(), + .end_pa = addr_map_rpg_pm_msshub3_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(4), + .element_index = 4U, + .dt_mmio = NULL, + .name = "perfmon_msshub4", + .device_index = TH500_MSSHUB4_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_msshub4_base_r(), + .end_abs_pa = addr_map_rpg_pm_msshub4_limit_r(), + .start_pa = addr_map_rpg_pm_msshub4_base_r(), + .end_pa = addr_map_rpg_pm_msshub4_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(5), + .element_index = 5U, + .dt_mmio = NULL, + .name = "perfmon_msshub5", + .device_index = TH500_MSSHUB5_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_msshub5_base_r(), + .end_abs_pa = addr_map_rpg_pm_msshub5_limit_r(), + .start_pa = addr_map_rpg_pm_msshub5_base_r(), + .end_pa = addr_map_rpg_pm_msshub5_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(6), + .element_index = 6U, + .dt_mmio = NULL, + .name = "perfmon_msshub6", + .device_index = TH500_MSSHUB6_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_msshub6_base_r(), + .end_abs_pa = addr_map_rpg_pm_msshub6_limit_r(), + .start_pa = addr_map_rpg_pm_msshub6_base_r(), + .end_pa = addr_map_rpg_pm_msshub6_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, + { + .element_type = HWPM_ELEMENT_PERFMON, + .element_index_mask = BIT(7), + .element_index = 7U, + .dt_mmio = NULL, + .name = "perfmon_msshub7", + .device_index = TH500_MSSHUB7_PERFMON_DEVICE_NODE_INDEX, + .start_abs_pa = addr_map_rpg_pm_msshub7_base_r(), + .end_abs_pa = addr_map_rpg_pm_msshub7_limit_r(), + .start_pa = addr_map_rpg_pm_msshub7_base_r(), + .end_pa = addr_map_rpg_pm_msshub7_limit_r(), + .base_pa = addr_map_rpg_pm_base_r(), + .alist = th500_perfmon_alist, + .alist_size = ARRAY_SIZE(th500_perfmon_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = { + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(0), + .element_index = 1U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc0_base_r(), + .end_abs_pa = addr_map_mc0_limit_r(), + .start_pa = addr_map_mc0_base_r(), + .end_pa = addr_map_mc0_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(1), + .element_index = 2U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc1_base_r(), + .end_abs_pa = addr_map_mc1_limit_r(), + .start_pa = addr_map_mc1_base_r(), + .end_pa = addr_map_mc1_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(2), + .element_index = 3U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc2_base_r(), + .end_abs_pa = addr_map_mc2_limit_r(), + .start_pa = addr_map_mc2_base_r(), + .end_pa = addr_map_mc2_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(3), + .element_index = 4U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc3_base_r(), + .end_abs_pa = addr_map_mc3_limit_r(), + .start_pa = addr_map_mc3_base_r(), + .end_pa = addr_map_mc3_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(4), + .element_index = 5U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc4_base_r(), + .end_abs_pa = addr_map_mc4_limit_r(), + .start_pa = addr_map_mc4_base_r(), + .end_pa = addr_map_mc4_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(5), + .element_index = 6U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc5_base_r(), + .end_abs_pa = addr_map_mc5_limit_r(), + .start_pa = addr_map_mc5_base_r(), + .end_pa = addr_map_mc5_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(6), + .element_index = 7U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc6_base_r(), + .end_abs_pa = addr_map_mc6_limit_r(), + .start_pa = addr_map_mc6_base_r(), + .end_pa = addr_map_mc6_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(7), + .element_index = 8U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc7_base_r(), + .end_abs_pa = addr_map_mc7_limit_r(), + .start_pa = addr_map_mc7_base_r(), + .end_pa = addr_map_mc7_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst0_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, +}; + +/* IP instance array */ +static struct hwpm_ip_inst th500_mss_hub_inst_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_INSTANCES] = { + { + .hw_inst_mask = BIT(0), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_hub_inst0_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc0_base_r(), + .range_end = addr_map_mc7_limit_r(), + .element_stride = addr_map_mc0_limit_r() - + addr_map_mc0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_hub_inst0_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_hub_inst0_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msshub0_base_r(), + .range_end = addr_map_rpg_pm_msshub7_limit_r(), + .element_stride = addr_map_rpg_pm_msshub0_limit_r() - + addr_map_rpg_pm_msshub0_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, +}; + +/* IP structure */ +struct hwpm_ip th500_hwpm_ip_mss_hub = { + .num_instances = TH500_HWPM_IP_MSS_HUB_NUM_INSTANCES, + .ip_inst_static_array = th500_mss_hub_inst_static_array, + + .inst_aperture_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc0_base_r(), + .range_end = addr_map_mc7_limit_r(), + .inst_stride = addr_map_mc7_limit_r() - + addr_map_mc0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .inst_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .range_start = addr_map_rpg_pm_msshub0_base_r(), + .range_end = addr_map_rpg_pm_msshub7_limit_r(), + .inst_stride = addr_map_rpg_pm_msshub7_limit_r() - + addr_map_rpg_pm_msshub0_base_r() + 1ULL, + .inst_slots = 0U, + .inst_arr = NULL, + }, + }, + + .dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK, + .override_enable = false, + .inst_fs_mask = 0U, + .resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID, + .reserved = false, +}; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.h b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.h new file mode 100644 index 0000000..9857add --- /dev/null +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This is a generated file. Do not edit. + * + * Steps to regenerate: + * python3 ip_files_generator.py [] + */ + +#ifndef TH500_HWPM_IP_MSS_HUB_H +#define TH500_HWPM_IP_MSS_HUB_H + +#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB) +#define TH500_HWPM_ACTIVE_IP_MSS_HUB TH500_HWPM_IP_MSS_HUB, + +/* This data should ideally be available in HW headers */ +#define TH500_HWPM_IP_MSS_HUB_NUM_INSTANCES 1U +#define TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST 8U +#define TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST 8U +#define TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST 8U +#define TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST 1U + +extern struct hwpm_ip th500_hwpm_ip_mss_hub; + +#else +#define TH500_HWPM_ACTIVE_IP_MSS_HUB +#endif + +#endif /* TH500_HWPM_IP_MSS_HUB_H */ diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c index 7da5c42..9287aa8 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c @@ -255,7 +255,7 @@ struct allowlist th500_mcf_soc_alist[2] = { {0x0000d61c, false}, }; -struct allowlist th500_soc_hub_alist[3] = { +struct allowlist th500_mss_hub_alist[3] = { {0x00006f34, false}, {0x00006f38, false}, {0x00006f3c, false}, diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h index 0cc0ab9..d391f44 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h @@ -38,5 +38,6 @@ extern struct allowlist th500_mcf_c2c_alist[2]; extern struct allowlist th500_mcf_soc_alist[2]; extern struct allowlist th500_soc_hub_alist[3]; extern struct allowlist th500_cl2_alist[4]; +extern struct allowlist th500_mss_hub_alist[3]; #endif /* TH500_HWPM_REGOPS_ALLOWLIST_H */ diff --git a/drivers/tegra/hwpm/hal/th500/th500_interface.c b/drivers/tegra/hwpm/hal/th500/th500_interface.c index 5e4689a..b140886 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_interface.c +++ b/drivers/tegra/hwpm/hal/th500/th500_interface.c @@ -123,6 +123,11 @@ bool th500_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm, config_ip = TH500_HWPM_IP_MSS_CHANNEL; break; #endif +#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB) + case TEGRA_HWPM_IP_MSS_HUB: + config_ip = TH500_HWPM_IP_MSS_HUB; + break; +#endif #if defined(CONFIG_TH500_HWPM_IP_CL2) case TEGRA_HWPM_IP_CL2: config_ip = TH500_HWPM_IP_CL2; @@ -153,11 +158,6 @@ bool th500_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm, config_ip = TH500_HWPM_IP_SMMU; break; #endif -#if defined(CONFIG_TH500_HWPM_IP_SOC_HUB) - case TEGRA_HWPM_IP_SOC_HUB: - config_ip = TH500_HWPM_IP_SOC_HUB; - break; -#endif #if defined(CONFIG_TH500_HWPM_IP_C_NVLINK) case TEGRA_HWPM_IP_NVLCTRL: config_ip = TH500_HWPM_IP_NVLCTRL; @@ -200,6 +200,11 @@ bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm, config_ip = TH500_HWPM_IP_MSS_CHANNEL; break; #endif +#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB) + case TEGRA_HWPM_RESOURCE_MSS_HUB: + config_ip = TH500_HWPM_IP_MSS_HUB; + break; +#endif #if defined(CONFIG_TH500_HWPM_IP_CL2) case TEGRA_HWPM_RESOURCE_CL2: config_ip = TH500_HWPM_IP_CL2; @@ -230,11 +235,6 @@ bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm, config_ip = TH500_HWPM_IP_SMMU; break; #endif -#if defined(CONFIG_TH500_HWPM_IP_SOC_HUB) - case TEGRA_HWPM_RESOURCE_SOC_HUB: - config_ip = TH500_HWPM_IP_SOC_HUB; - break; -#endif #if defined(CONFIG_TH500_HWPM_IP_C_NVLINK) case TEGRA_HWPM_RESOURCE_NVLCTRL: config_ip = TH500_HWPM_IP_NVLCTRL; @@ -303,6 +303,10 @@ int th500_hwpm_init_chip_info(struct tegra_soc_hwpm *hwpm) th500_active_ip_info[TH500_HWPM_IP_MSS_CHANNEL] = &th500_hwpm_ip_mss_channel; #endif +#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB) + th500_active_ip_info[TH500_HWPM_IP_MSS_HUB] = + &th500_hwpm_ip_mss_hub; +#endif #if defined(CONFIG_TH500_HWPM_IP_CL2) th500_active_ip_info[TH500_HWPM_IP_CL2] = &th500_hwpm_ip_cl2; #endif @@ -329,9 +333,6 @@ int th500_hwpm_init_chip_info(struct tegra_soc_hwpm *hwpm) th500_active_ip_info[TH500_HWPM_IP_NVLRX] = &th500_hwpm_ip_nvlrx; th500_active_ip_info[TH500_HWPM_IP_NVLTX] = &th500_hwpm_ip_nvltx; #endif -#if defined(CONFIG_TH500_HWPM_IP_SOC_HUB) - th500_active_ip_info[TH500_HWPM_IP_SOC_HUB] = &th500_hwpm_ip_soc_hub; -#endif #if defined(CONFIG_TH500_HWPM_IP_PCIE) th500_active_ip_info[TH500_HWPM_IP_PCIE] = &th500_hwpm_ip_pcie; #endif diff --git a/drivers/tegra/hwpm/hal/th500/th500_internal.h b/drivers/tegra/hwpm/hal/th500/th500_internal.h index a370467..9458ed4 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_internal.h +++ b/drivers/tegra/hwpm/hal/th500/th500_internal.h @@ -32,6 +32,7 @@ #include #include #include +#include #define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX @@ -45,6 +46,7 @@ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLCTRL) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLRX) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLTX) \ + DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_HUB) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX) #undef DEFINE_SOC_HWPM_ACTIVE_IP diff --git a/drivers/tegra/hwpm/hal/th500/th500_ip.c b/drivers/tegra/hwpm/hal/th500/th500_ip.c index 4958039..5dcd5fd 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_ip.c +++ b/drivers/tegra/hwpm/hal/th500/th500_ip.c @@ -94,6 +94,9 @@ int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, #if defined(CONFIG_TH500_HWPM_IP_MSS_CHANNEL) case TH500_HWPM_IP_MSS_CHANNEL: #endif +#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB) + case TH500_HWPM_IP_MSS_HUB: +#endif #if defined(CONFIG_TH500_HWPM_IP_MCF_CORE) case TH500_HWPM_IP_MCF_CORE: #endif @@ -105,13 +108,10 @@ int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, #endif #if defined(CONFIG_TH500_HWPM_IP_MCF_SOC) case TH500_HWPM_IP_MCF_SOC: -#endif -#if defined(CONFIG_TH500_HWPM_IP_SOC_HUB) - case TH500_HWPM_IP_SOC_HUB: #endif /* * MSS channel, MCF CORE, MCF CLINK, MCF C2C, MCF SOC, - * and SOC HUB share MC channels + * and MSS HUB share MC channels */ /* Check base address in TH500_HWPM_IP_MSS_CHANNEL */ @@ -229,9 +229,9 @@ int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, ret = 0; } #endif -#if defined(CONFIG_TH500_HWPM_IP_SOC_HUB) - /* Check base address in TH500_HWPM_IP_SOC_HUB */ - ip_idx = TH500_HWPM_IP_SOC_HUB; +#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB) + /* Check base address in TH500_HWPM_IP_MSS_HUB */ + ip_idx = TH500_HWPM_IP_MSS_HUB; ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops, base_address, ip_idx, available); if (ret != 0) { diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h index bac6b46..563ca83 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm.h @@ -83,6 +83,7 @@ enum tegra_hwpm_ip_enum { TEGRA_HWPM_IP_NVLCTRL, TEGRA_HWPM_IP_NVLRX, TEGRA_HWPM_IP_NVLTX, + TEGRA_HWPM_IP_MSS_HUB, TERGA_HWPM_NUM_IPS }; @@ -117,6 +118,7 @@ enum tegra_hwpm_resource_enum { TEGRA_HWPM_RESOURCE_NVLCTRL, TEGRA_HWPM_RESOURCE_NVLRX, TEGRA_HWPM_RESOURCE_NVLTX, + TEGRA_HWPM_RESOURCE_MSS_HUB, TERGA_HWPM_NUM_RESOURCES }; diff --git a/drivers/tegra/hwpm/os/linux/ip_utils.c b/drivers/tegra/hwpm/os/linux/ip_utils.c index 50845e8..15e4343 100644 --- a/drivers/tegra/hwpm/os/linux/ip_utils.c +++ b/drivers/tegra/hwpm/os/linux/ip_utils.c @@ -105,6 +105,9 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_IP_NVLTX: ip_enum_idx = TEGRA_HWPM_IP_NVLTX; break; + case TEGRA_SOC_HWPM_IP_MSS_HUB: + ip_enum_idx = TEGRA_HWPM_IP_MSS_HUB; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_ip %d is invalid", @@ -225,6 +228,9 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_RESOURCE_NVLTX: res_enum_idx = TEGRA_HWPM_RESOURCE_NVLTX; break; + case TEGRA_SOC_HWPM_RESOURCE_MSS_HUB: + res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_HUB; + break; default: tegra_hwpm_err(hwpm, "Queried enum tegra_soc_hwpm_resource %d is invalid", diff --git a/include/uapi/linux/tegra-soc-hwpm-uapi.h b/include/uapi/linux/tegra-soc-hwpm-uapi.h index 8324636..0b430fa 100644 --- a/include/uapi/linux/tegra-soc-hwpm-uapi.h +++ b/include/uapi/linux/tegra-soc-hwpm-uapi.h @@ -50,6 +50,7 @@ enum tegra_soc_hwpm_ip { TEGRA_SOC_HWPM_IP_NVLCTRL, TEGRA_SOC_HWPM_IP_NVLRX, TEGRA_SOC_HWPM_IP_NVLTX, + TEGRA_SOC_HWPM_IP_MSS_HUB, TERGA_SOC_HWPM_NUM_IPS }; @@ -122,6 +123,7 @@ enum tegra_soc_hwpm_resource { TEGRA_SOC_HWPM_RESOURCE_NVLCTRL, TEGRA_SOC_HWPM_RESOURCE_NVLRX, TEGRA_SOC_HWPM_RESOURCE_NVLTX, + TEGRA_SOC_HWPM_RESOURCE_MSS_HUB, TERGA_SOC_HWPM_NUM_RESOURCES };