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git://nv-tegra.nvidia.com/linux-hwpm.git
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tegra: hwpm: return error from read/write function
Currently, read/write functions validate aperture and mmio address pointers. However, the error cannot be returned to the parent resulting into undetected errors. Modify all read write functions to return error on failure. This will also allow HWPM driver to know about unavailable IP perfmuxes. Jira THWPM-41 Change-Id: I6cc4ba7a831d5058657d4f2536b1ce3ab20b30c6 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2707446 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
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Vedashree Vidwans
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@@ -23,59 +23,57 @@
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_static_analysis.h>
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static u32 fake_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset)
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static int fake_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 *val)
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{
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u32 reg_val = 0;
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if (!hwpm->fake_registers_enabled) {
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tegra_hwpm_err(hwpm, "Fake registers are disabled!");
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return 0;
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return -ENODEV;
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}
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reg_val = aperture->fake_registers[offset];
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return reg_val;
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*val = aperture->fake_registers[offset];
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return 0;
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}
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static void fake_writel(struct tegra_soc_hwpm *hwpm,
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static int fake_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 val)
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{
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if (!hwpm->fake_registers_enabled) {
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tegra_hwpm_err(hwpm, "Fake registers are disabled!");
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return;
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return -ENODEV;
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}
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aperture->fake_registers[offset] = val;
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return 0;
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}
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/*
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* Read IP domain registers
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* IP(except PMA and RTR) perfmux fall in this category
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*/
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static u32 ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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struct hwpm_ip_aperture *aperture, u64 offset)
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static int ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 *val)
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{
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tegra_hwpm_dbg(hwpm, hwpm_register,
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"Aperture (0x%llx-0x%llx) offset(0x%llx)",
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aperture->start_abs_pa, aperture->end_abs_pa, offset);
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if (hwpm->fake_registers_enabled) {
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return fake_readl(hwpm, aperture, offset);
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return fake_readl(hwpm, aperture, offset, val);
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} else {
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u32 reg_val = 0U;
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struct tegra_hwpm_ip_ops *ip_ops_ptr = &ip_inst->ip_ops;
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if (ip_ops_ptr->hwpm_ip_reg_op != NULL) {
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int err = 0;
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err = (*ip_ops_ptr->hwpm_ip_reg_op)(ip_ops_ptr->ip_dev,
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TEGRA_SOC_HWPM_IP_REG_OP_READ,
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offset, ®_val);
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offset, val);
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if (err < 0) {
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tegra_hwpm_err(hwpm, "Aperture (0x%llx-0x%llx) "
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"read offset(0x%llx) failed",
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aperture->start_abs_pa,
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aperture->end_abs_pa, offset);
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return 0U;
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return err;
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}
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} else {
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/* Fall back to un-registered IP method */
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@@ -86,7 +84,7 @@ static u32 ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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if (is_tegra_hypervisor_mode()) {
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tegra_hwpm_err(hwpm,
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"Fallback method not implemented on hypervisor config");
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return 0U;
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return -EINVAL;
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}
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ptr = ioremap(reg_addr, 0x4);
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@@ -94,20 +92,20 @@ static u32 ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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tegra_hwpm_err(hwpm,
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"Failed to map register(0x%llx)",
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reg_addr);
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return 0U;
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return -ENODEV;
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}
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reg_val = __raw_readl(ptr);
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*val = __raw_readl(ptr);
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iounmap(ptr);
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}
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return reg_val;
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}
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return 0;
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}
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/*
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* Write to IP domain registers
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* IP(except PMA and RTR) perfmux fall in this category
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*/
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static void ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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static int ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 val)
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{
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tegra_hwpm_dbg(hwpm, hwpm_register,
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@@ -115,7 +113,7 @@ static void ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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aperture->start_abs_pa, aperture->end_abs_pa, offset, val);
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if (hwpm->fake_registers_enabled) {
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fake_writel(hwpm, aperture, offset, val);
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return fake_writel(hwpm, aperture, offset, val);
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} else {
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struct tegra_hwpm_ip_ops *ip_ops_ptr = &ip_inst->ip_ops;
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if (ip_ops_ptr->hwpm_ip_reg_op != NULL) {
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@@ -129,7 +127,7 @@ static void ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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"write offset(0x%llx) val 0x%x failed",
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aperture->start_abs_pa,
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aperture->end_abs_pa, offset, val);
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return;
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return err;
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}
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} else {
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/* Fall back to un-registered IP method */
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@@ -140,7 +138,7 @@ static void ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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if (is_tegra_hypervisor_mode()) {
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tegra_hwpm_err(hwpm,
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"Fallback method not implemented on hypervisor config");
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return;
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return -EINVAL;
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}
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ptr = ioremap(reg_addr, 0x4);
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@@ -148,20 +146,21 @@ static void ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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tegra_hwpm_err(hwpm,
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"Failed to map register(0x%llx)",
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reg_addr);
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return;
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return -ENODEV;
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}
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__raw_writel(val, ptr);
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iounmap(ptr);
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}
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}
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return 0;
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}
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/*
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* Read HWPM domain registers
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* PERFMONs, PMA and RTR registers fall in this category
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*/
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static u32 hwpm_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset)
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static int hwpm_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 *val)
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{
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tegra_hwpm_dbg(hwpm, hwpm_register,
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"Aperture (0x%llx-0x%llx) offset(0x%llx)",
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@@ -169,51 +168,55 @@ static u32 hwpm_readl(struct tegra_soc_hwpm *hwpm,
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if (aperture->dt_mmio == NULL) {
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tegra_hwpm_err(hwpm, "aperture is not iomapped as expected");
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return 0U;
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return -ENODEV;
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}
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if (hwpm->fake_registers_enabled) {
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return fake_readl(hwpm, aperture, offset);
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return fake_readl(hwpm, aperture, offset, val);
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} else {
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return readl(aperture->dt_mmio + offset);
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*val = readl(aperture->dt_mmio + offset);
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}
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return 0;
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}
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/*
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* Write to HWPM domain registers
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* PERFMONs, PMA and RTR registers fall in this category
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*/
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static void hwpm_writel(struct tegra_soc_hwpm *hwpm,
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static int hwpm_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 val)
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{
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int err = 0;
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tegra_hwpm_dbg(hwpm, hwpm_register,
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"Aperture (0x%llx-0x%llx) offset(0x%llx) val(0x%x)",
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aperture->start_abs_pa, aperture->end_abs_pa, offset, val);
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if (aperture->dt_mmio == NULL) {
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tegra_hwpm_err(hwpm, "aperture is not iomapped as expected");
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return;
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return -ENODEV;
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}
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if (hwpm->fake_registers_enabled) {
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fake_writel(hwpm, aperture, offset, val);
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err = fake_writel(hwpm, aperture, offset, val);
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} else {
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writel(val, aperture->dt_mmio + offset);
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}
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return err;
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}
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/*
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* Read a HWPM domain register. It is assumed that valid aperture
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* is passed to the function.
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*/
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u32 tegra_hwpm_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 addr)
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int tegra_hwpm_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 addr, u32 *val)
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{
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u32 reg_val = 0;
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if (!aperture) {
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tegra_hwpm_err(hwpm, "aperture is NULL");
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return 0;
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return -ENODEV;
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}
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if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
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@@ -221,24 +224,24 @@ u32 tegra_hwpm_readl(struct tegra_soc_hwpm *hwpm,
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u64 reg_offset = tegra_hwpm_safe_sub_u64(
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addr, aperture->base_pa);
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/* HWPM domain registers */
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reg_val = hwpm_readl(hwpm, aperture, reg_offset);
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return hwpm_readl(hwpm, aperture, reg_offset, val);
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} else {
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tegra_hwpm_err(hwpm, "IP aperture read is not expected");
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return 0;
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return -EINVAL;
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}
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return reg_val;
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return 0;
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}
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/*
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* Write to a HWPM domain register. It is assumed that valid aperture
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* is passed to the function.
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*/
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void tegra_hwpm_writel(struct tegra_soc_hwpm *hwpm,
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int tegra_hwpm_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 addr, u32 val)
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{
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if (!aperture) {
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tegra_hwpm_err(hwpm, "aperture is NULL");
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return;
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return -ENODEV;
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}
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if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
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@@ -246,61 +249,64 @@ void tegra_hwpm_writel(struct tegra_soc_hwpm *hwpm,
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u64 reg_offset = tegra_hwpm_safe_sub_u64(
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addr, aperture->base_pa);
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/* HWPM domain internal registers */
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hwpm_writel(hwpm, aperture, reg_offset, val);
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return hwpm_writel(hwpm, aperture, reg_offset, val);
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} else {
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tegra_hwpm_err(hwpm, "IP aperture write is not expected");
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return;
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Read a register from the EXEC_REG_OPS IOCTL. It is assumed that the allowlist
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* check has been done before calling this function.
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*/
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u32 tegra_hwpm_regops_readl(struct tegra_soc_hwpm *hwpm,
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u64 addr, struct hwpm_ip_inst *ip_inst,
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struct hwpm_ip_aperture *aperture)
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int tegra_hwpm_regops_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture,
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u64 addr, u32 *val)
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{
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u32 reg_val = 0;
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u64 reg_offset = 0ULL;
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int err = 0;
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if (!aperture) {
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tegra_hwpm_err(hwpm, "aperture is NULL");
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return 0;
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return -ENODEV;
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}
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reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa);
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if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
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(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
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reg_val = hwpm_readl(hwpm, aperture, reg_offset);
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err = hwpm_readl(hwpm, aperture, reg_offset, val);
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} else {
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reg_val = ip_readl(hwpm, ip_inst, aperture, reg_offset);
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err = ip_readl(hwpm, ip_inst, aperture, reg_offset, val);
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}
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return reg_val;
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return err;
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}
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/*
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* Write a register from the EXEC_REG_OPS IOCTL. It is assumed that the
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* allowlist check has been done before calling this function.
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*/
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void tegra_hwpm_regops_writel(struct tegra_soc_hwpm *hwpm,
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u64 addr, u32 val, struct hwpm_ip_inst *ip_inst,
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struct hwpm_ip_aperture *aperture)
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int tegra_hwpm_regops_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture,
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u64 addr, u32 val)
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{
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u64 reg_offset = 0ULL;
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int err = 0;
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if (!aperture) {
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tegra_hwpm_err(hwpm, "aperture is NULL");
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return;
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return -ENODEV;
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}
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reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa);
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if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
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(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
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hwpm_writel(hwpm, aperture, reg_offset, val);
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err = hwpm_writel(hwpm, aperture, reg_offset, val);
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} else {
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ip_writel(hwpm, ip_inst, aperture, reg_offset, val);
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err = ip_writel(hwpm, ip_inst, aperture, reg_offset, val);
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}
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return err;
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}
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