From c4e5fde33684dde76cd534a9c2bcf749a6f09957 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Fri, 8 Nov 2024 00:32:46 -0800 Subject: [PATCH] tegra: hwpm: add ip_config debugfs flags Change-Id: I4160b776947570df9ec81f4f34bdef6376b44be8 Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3245391 Reviewed-by: mobile promotions Tested-by: mobile promotions Tested-by: Vasuki Shankar Reviewed-by: Seema Khowala GVS: buildbot_gerritrpt Reviewed-by: Vasuki Shankar --- drivers/tegra/hwpm/common/init.c | 7 + drivers/tegra/hwpm/common/ip.c | 7 - drivers/tegra/hwpm/hal/t264/t264_ip.c | 460 ++++++++++++------------ drivers/tegra/hwpm/include/tegra_hwpm.h | 55 +++ drivers/tegra/hwpm/os/linux/debugfs.c | 23 +- drivers/tegra/hwpm/os/linux/driver.h | 1 + 6 files changed, 318 insertions(+), 235 deletions(-) diff --git a/drivers/tegra/hwpm/common/init.c b/drivers/tegra/hwpm/common/init.c index e3f2ac0..24a0b34 100644 --- a/drivers/tegra/hwpm/common/init.c +++ b/drivers/tegra/hwpm/common/init.c @@ -154,6 +154,13 @@ int tegra_hwpm_setup_sw(struct tegra_soc_hwpm *hwpm) int ret = 0; tegra_hwpm_fn(hwpm, " "); + ret = hwpm->active_chip->force_enable_ips(hwpm); + if (ret != 0) { + tegra_hwpm_err(hwpm, "Failed to force enable IPs"); + /* Do not fail because of force enable failure */ + return 0; + } + ret = hwpm->active_chip->validate_current_config(hwpm); if (ret != 0) { tegra_hwpm_err(hwpm, "Failed to validate current conifg"); diff --git a/drivers/tegra/hwpm/common/ip.c b/drivers/tegra/hwpm/common/ip.c index 604f146..89bd9ed 100644 --- a/drivers/tegra/hwpm/common/ip.c +++ b/drivers/tegra/hwpm/common/ip.c @@ -302,13 +302,6 @@ int tegra_hwpm_finalize_chip_info(struct tegra_soc_hwpm *hwpm) return ret; } - ret = hwpm->active_chip->force_enable_ips(hwpm); - if (ret != 0) { - tegra_hwpm_err(hwpm, "Failed to force enable IPs"); - /* Do not fail because of force enable failure */ - return 0; - } - return 0; } diff --git a/drivers/tegra/hwpm/hal/t264/t264_ip.c b/drivers/tegra/hwpm/hal/t264/t264_ip.c index 37496c3..4f3dd32 100644 --- a/drivers/tegra/hwpm/hal/t264/t264_ip.c +++ b/drivers/tegra/hwpm/hal/t264/t264_ip.c @@ -387,245 +387,255 @@ int t264_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) if (tegra_hwpm_is_platform_silicon()) { /* Static IP instances corresponding to silicon */ #if defined(CONFIG_T264_HWPM_IP_OCU) - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + if (hwpm->ip_config[TEGRA_HWPM_IP_MCF_OCU]) { + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, addr_map_ocu_base_r(), T264_HWPM_IP_OCU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_OCU force enable failed"); - return ret; + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_OCU force enable failed"); + return ret; + } } #endif #if defined(CONFIG_T264_HWPM_IP_UCF_PSW) - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_ucf_psn0_psw_base_r(), - T264_HWPM_IP_UCF_PSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_PSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_ucf_psn1_psw_base_r(), - T264_HWPM_IP_UCF_PSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_PSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_ucf_psn2_psw_base_r(), - T264_HWPM_IP_UCF_PSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_PSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_ucf_psn3_psw_base_r(), - T264_HWPM_IP_UCF_PSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_PSW force enable failed"); - return ret; + if (hwpm->ip_config[TEGRA_HWPM_IP_UCF_PSW]) { + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_ucf_psn0_psw_base_r(), + T264_HWPM_IP_UCF_PSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_PSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_ucf_psn1_psw_base_r(), + T264_HWPM_IP_UCF_PSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_PSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_ucf_psn2_psw_base_r(), + T264_HWPM_IP_UCF_PSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_PSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_ucf_psn3_psw_base_r(), + T264_HWPM_IP_UCF_PSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_PSW force enable failed"); + return ret; + } } #endif /* CONFIG_T264_HWPM_IP_UCF_PSW */ #if defined(CONFIG_T264_HWPM_IP_UCF_CSW) - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_ucf_csw0_base_r(), - T264_HWPM_IP_UCF_CSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_CSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_ucf_csw1_base_r(), - T264_HWPM_IP_UCF_CSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_CSW force enable failed"); - return ret; + if (hwpm->ip_config[TEGRA_HWPM_IP_UCF_CSW]) { + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_ucf_csw0_base_r(), + T264_HWPM_IP_UCF_CSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_CSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_ucf_csw1_base_r(), + T264_HWPM_IP_UCF_CSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_CSW force enable failed"); + return ret; + } } #endif /* CONFIG_T264_HWPM_IP_UCF_CSW */ #if defined(CONFIG_T264_HWPM_IP_UCF_MSW) - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc0_base_r(), - T264_HWPM_IP_UCF_MSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_MSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc2_base_r(), - T264_HWPM_IP_UCF_MSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_MSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc4_base_r(), - T264_HWPM_IP_UCF_MSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_MSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc6_base_r(), - T264_HWPM_IP_UCF_MSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_MSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc8_base_r(), - T264_HWPM_IP_UCF_MSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_MSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc10_base_r(), - T264_HWPM_IP_UCF_MSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_MSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc12_base_r(), - T264_HWPM_IP_UCF_MSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_MSW force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_mc14_base_r(), - T264_HWPM_IP_UCF_MSW, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_UCF_MSW force enable failed"); - return ret; + if (hwpm->ip_config[TEGRA_HWPM_IP_UCF_MSW]) { + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_mc0_base_r(), + T264_HWPM_IP_UCF_MSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_MSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_mc2_base_r(), + T264_HWPM_IP_UCF_MSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_MSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_mc4_base_r(), + T264_HWPM_IP_UCF_MSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_MSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_mc6_base_r(), + T264_HWPM_IP_UCF_MSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_MSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_mc8_base_r(), + T264_HWPM_IP_UCF_MSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_MSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_mc10_base_r(), + T264_HWPM_IP_UCF_MSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_MSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_mc12_base_r(), + T264_HWPM_IP_UCF_MSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_MSW force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_mc14_base_r(), + T264_HWPM_IP_UCF_MSW, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_UCF_MSW force enable failed"); + return ret; + } } #endif /* CONFIG_T264_HWPM_IP_UCF_MSW */ #if defined(CONFIG_T264_HWPM_IP_CPU) - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore0_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore1_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore2_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore3_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore4_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore5_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore6_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore7_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore8_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore9_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore10_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore11_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore12_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; - } - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, - addr_map_cpucore13_base_r(), - T264_HWPM_IP_CPU, true); - if (ret != 0) { - tegra_hwpm_err(hwpm, - "T264_HWPM_IP_CPU force enable failed"); - return ret; + if (hwpm->ip_config[TEGRA_HWPM_IP_CPU]) { + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore0_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore1_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore2_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore3_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore4_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore5_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore6_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore7_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore8_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore9_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore10_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore11_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore12_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } + ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, + addr_map_cpucore13_base_r(), + T264_HWPM_IP_CPU, true); + if (ret != 0) { + tegra_hwpm_err(hwpm, + "T264_HWPM_IP_CPU force enable failed"); + return ret; + } } #endif /* CONFIG_T264_HWPM_IP_CPU */ } diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h index bd66ca2..ca6e7d1 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm.h @@ -107,6 +107,60 @@ enum tegra_hwpm_ip_enum { TERGA_HWPM_NUM_IPS }; +/* + * Function to translate IP index into IP name + * Developer is responsible to update this corresponding to tegra_hwpm_ip_enum + */ +static inline const char *tegra_hwpm_ip_string(enum tegra_hwpm_ip_enum ip_enum) +{ + const char *tegra_hwpm_ip_name[TERGA_HWPM_NUM_IPS + 1] = { + [TEGRA_HWPM_IP_VI] = "vi", + [TEGRA_HWPM_IP_ISP] = "isp", + [TEGRA_HWPM_IP_VIC] = "vic", + [TEGRA_HWPM_IP_OFA] = "ofa", + [TEGRA_HWPM_IP_PVA] = "pva", + [TEGRA_HWPM_IP_NVDLA] = "dla", + [TEGRA_HWPM_IP_MGBE] = "mgbe", + [TEGRA_HWPM_IP_SCF] = "scf", + [TEGRA_HWPM_IP_NVDEC] = "nvdec", + [TEGRA_HWPM_IP_NVENC] = "nvenc", + [TEGRA_HWPM_IP_PCIE] = "pcie", + [TEGRA_HWPM_IP_DISPLAY] = "display", + [TEGRA_HWPM_IP_MSS_CHANNEL] = "mss_channel", + [TEGRA_HWPM_IP_MSS_GPU_HUB] = "mss_gpu_hub", + [TEGRA_HWPM_IP_MSS_ISO_NISO_HUBS] = "mss_iso_niso_hubs", + [TEGRA_HWPM_IP_MSS_MCF] = "mss_mcf", + [TEGRA_HWPM_IP_APE] = "ape", + [TEGRA_HWPM_IP_C2C] = "c2c", + [TEGRA_HWPM_IP_SMMU] = "smmu", + [TEGRA_HWPM_IP_CL2] = "cl2", + [TEGRA_HWPM_IP_NVLCTRL] = "nvlctrl", + [TEGRA_HWPM_IP_NVLRX] = "nvlrx", + [TEGRA_HWPM_IP_NVLTX] = "nvltx", + [TEGRA_HWPM_IP_MSS_HUB] = "mss_hub", + [TEGRA_HWPM_IP_MCF_SOC] = "mcf_soc", + [TEGRA_HWPM_IP_MCF_C2C] = "mcf_c2c", + [TEGRA_HWPM_IP_MCF_CLINK] = "mcf_clink", + [TEGRA_HWPM_IP_MCF_CORE] = "mcf_core", + [TEGRA_HWPM_IP_MCF_OCU] = "mcf_ocu", + [TEGRA_HWPM_IP_PCIE_XTLQ] = "pcie_xtlq", + [TEGRA_HWPM_IP_PCIE_XTLRC] = "pcie_xltrc", + [TEGRA_HWPM_IP_PCIE_XALRC] = "pcie_xalrc", + [TEGRA_HWPM_IP_UCF_MSW] = "ucf_msw", + [TEGRA_HWPM_IP_UCF_PSW] = "ucf_psw", + [TEGRA_HWPM_IP_UCF_CSW] = "ucf_csw", + [TEGRA_HWPM_IP_UCF_HUB] = "ucf_hub", + [TEGRA_HWPM_IP_UCF_SCB] = "ucf_scb", + [TEGRA_HWPM_IP_CPU] = "cpu", + [TERGA_HWPM_NUM_IPS] = "unknown", + }; + + if (ip_enum >= TERGA_HWPM_NUM_IPS) { + return tegra_hwpm_ip_name[TERGA_HWPM_NUM_IPS]; + } + return tegra_hwpm_ip_name[ip_enum]; +} + /* * This is a copy of enum tegra_soc_hwpm_resource uapi structure. * It is not a hard requirement as tegra_soc_hwpm_resource is translated to @@ -620,6 +674,7 @@ struct tegra_soc_hwpm { /* SW State */ u32 dbg_mask; + bool ip_config[TERGA_HWPM_NUM_IPS]; bool bind_completed; bool device_opened; bool fake_registers_enabled; diff --git a/drivers/tegra/hwpm/os/linux/debugfs.c b/drivers/tegra/hwpm/os/linux/debugfs.c index 1a2e19d..6df766d 100644 --- a/drivers/tegra/hwpm/os/linux/debugfs.c +++ b/drivers/tegra/hwpm/os/linux/debugfs.c @@ -25,6 +25,7 @@ void tegra_hwpm_debugfs_init(struct tegra_hwpm_os_linux *hwpm_linux) { struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm; + u32 ip_idx = 0U; if (!hwpm_linux) { tegra_hwpm_err(hwpm, "Invalid hwpm_linux struct"); @@ -35,7 +36,7 @@ void tegra_hwpm_debugfs_init(struct tegra_hwpm_os_linux *hwpm_linux) debugfs_create_dir(TEGRA_SOC_HWPM_MODULE_NAME, NULL); if (!hwpm_linux->debugfs_root) { tegra_hwpm_err(hwpm, "Failed to create debugfs root directory"); - goto fail; + goto fail_root; } /* Debug logs */ @@ -46,9 +47,24 @@ void tegra_hwpm_debugfs_init(struct tegra_hwpm_os_linux *hwpm_linux) debugfs_create_bool("skip_allowlist", S_IRUGO|S_IWUSR, hwpm_linux->debugfs_root, &hwpm->dbg_skip_alist); - return; + /* Debug IP configs */ + hwpm_linux->debugfs_ip_config = + debugfs_create_dir("ip_config", hwpm_linux->debugfs_root); + if (!hwpm_linux->debugfs_ip_config) { + tegra_hwpm_err(hwpm, + "Failed to create debugfs ip_config directory"); + goto fail_ip_config; + } + for (ip_idx = 0U; ip_idx < TERGA_HWPM_NUM_IPS; ip_idx++) { + debugfs_create_bool(tegra_hwpm_ip_string(ip_idx), + S_IRUGO|S_IWUSR, hwpm_linux->debugfs_ip_config, + &hwpm->ip_config[ip_idx]); + } -fail: + return; +fail_ip_config: + debugfs_remove_recursive(hwpm_linux->debugfs_ip_config); +fail_root: debugfs_remove_recursive(hwpm_linux->debugfs_root); hwpm_linux->debugfs_root = NULL; } @@ -62,6 +78,7 @@ void tegra_hwpm_debugfs_deinit(struct tegra_hwpm_os_linux *hwpm_linux) return; } + debugfs_remove_recursive(hwpm_linux->debugfs_ip_config); debugfs_remove_recursive(hwpm_linux->debugfs_root); hwpm_linux->debugfs_root = NULL; } diff --git a/drivers/tegra/hwpm/os/linux/driver.h b/drivers/tegra/hwpm/os/linux/driver.h index 7b88c01..9d5b188 100644 --- a/drivers/tegra/hwpm/os/linux/driver.h +++ b/drivers/tegra/hwpm/os/linux/driver.h @@ -66,6 +66,7 @@ struct tegra_hwpm_os_linux { #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_root; + struct dentry *debugfs_ip_config; #endif };