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tegra: hwpm: add aperture device node index
Add Device_index tag to read IP perfmon register address index from ACPI or DTSI tables. Device_index will be used to retrieve resource information from acpi tables or device trees. This will replace current logic to procure resource details using device names. JIRA THWPM-71 Change-Id: I964546f2262dd77ec0acfb58f49d044c870deae6 Signed-off-by: vasukis <vasukis@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797448 GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Tested-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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@@ -16,6 +16,7 @@
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#include <tegra_hwpm.h>
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#include <tegra_hwpm.h>
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#include <hal/t234/t234_regops_allowlist.h>
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#include <hal/t234/t234_regops_allowlist.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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#include <hal/t234/t234_perfmon_device_index.h>
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static struct hwpm_ip_aperture t234_display_inst0_perfmon_element_static_array[
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static struct hwpm_ip_aperture t234_display_inst0_perfmon_element_static_array[
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T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST] = {
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T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST] = {
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@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_display_inst0_perfmon_element_static_array[
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.element_index = 0U,
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.element_index = 0U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_nvdisplay0",
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.name = "perfmon_nvdisplay0",
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.device_index = T234_NVDISPLAY0_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_disp_base_r(),
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.start_abs_pa = addr_map_rpg_pm_disp_base_r(),
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.end_abs_pa = addr_map_rpg_pm_disp_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_disp_limit_r(),
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.start_pa = 0ULL,
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.start_pa = 0ULL,
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@@ -16,6 +16,7 @@
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#include <tegra_hwpm.h>
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#include <tegra_hwpm.h>
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#include <hal/t234/t234_regops_allowlist.h>
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#include <hal/t234/t234_regops_allowlist.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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#include <hal/t234/t234_perfmon_device_index.h>
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static struct hwpm_ip_aperture t234_isp_inst0_perfmon_element_static_array[
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static struct hwpm_ip_aperture t234_isp_inst0_perfmon_element_static_array[
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T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST] = {
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T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST] = {
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@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_isp_inst0_perfmon_element_static_array[
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.element_index = 0U,
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.element_index = 0U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_isp0",
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.name = "perfmon_isp0",
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.device_index = T234_ISP0_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_isp0_base_r(),
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.start_abs_pa = addr_map_rpg_pm_isp0_base_r(),
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.end_abs_pa = addr_map_rpg_pm_isp0_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_isp0_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -16,6 +16,7 @@
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#include <tegra_hwpm.h>
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#include <tegra_hwpm.h>
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#include <hal/t234/t234_regops_allowlist.h>
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#include <hal/t234/t234_regops_allowlist.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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#include <hal/t234/t234_perfmon_device_index.h>
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static struct hwpm_ip_aperture t234_mgbe_inst0_perfmon_element_static_array[
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static struct hwpm_ip_aperture t234_mgbe_inst0_perfmon_element_static_array[
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T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = {
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T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = {
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@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst0_perfmon_element_static_array[
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.element_index = 0U,
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.element_index = 0U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_mgbe0",
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.name = "perfmon_mgbe0",
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.device_index = T234_MGBE0_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mgbe0_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mgbe0_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mgbe0_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mgbe0_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -44,6 +46,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst1_perfmon_element_static_array[
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.element_index = 0U,
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.element_index = 0U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_mgbe1",
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.name = "perfmon_mgbe1",
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.device_index = T234_MGBE1_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mgbe1_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mgbe1_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mgbe1_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mgbe1_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -63,6 +66,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst2_perfmon_element_static_array[
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.element_index = 0U,
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.element_index = 0U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_mgbe2",
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.name = "perfmon_mgbe2",
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.device_index = T234_MGBE2_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mgbe2_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mgbe2_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mgbe2_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mgbe2_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -82,6 +86,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst3_perfmon_element_static_array[
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.element_index = 0U,
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.element_index = 0U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_mgbe3",
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.name = "perfmon_mgbe3",
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.device_index = T234_MGBE3_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mgbe3_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mgbe3_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mgbe3_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mgbe3_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -16,6 +16,7 @@
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#include <tegra_hwpm.h>
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#include <tegra_hwpm.h>
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#include <hal/t234/t234_regops_allowlist.h>
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#include <hal/t234/t234_regops_allowlist.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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#include <hal/t234/t234_perfmon_device_index.h>
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static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_array[
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static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_array[
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T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
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T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
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@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 1U,
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.element_index = 1U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_parta0",
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.name = "perfmon_msschannel_parta0",
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.device_index = T234_MSS_CHANNEL_PARTA0_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss0_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss0_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss0_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss0_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -40,6 +42,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 2U,
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.element_index = 2U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_parta1",
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.name = "perfmon_msschannel_parta1",
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.device_index = T234_MSS_CHANNEL_PARTA1_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss1_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss1_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss1_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss1_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -55,6 +58,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 3U,
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.element_index = 3U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_parta2",
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.name = "perfmon_msschannel_parta2",
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.device_index = T234_MSS_CHANNEL_PARTA2_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss2_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss2_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss2_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss2_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -70,6 +74,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 4U,
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.element_index = 4U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_parta3",
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.name = "perfmon_msschannel_parta3",
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.device_index = T234_MSS_CHANNEL_PARTA3_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss3_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss3_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss3_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss3_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -85,6 +90,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 5U,
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.element_index = 5U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_partb0",
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.name = "perfmon_msschannel_partb0",
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.device_index = T234_MSS_CHANNEL_PARTB0_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss4_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss4_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss4_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss4_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -100,6 +106,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 6U,
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.element_index = 6U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_partb1",
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.name = "perfmon_msschannel_partb1",
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.device_index = T234_MSS_CHANNEL_PARTB1_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss5_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss5_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss5_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss5_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -115,6 +122,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 7U,
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.element_index = 7U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_partb2",
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.name = "perfmon_msschannel_partb2",
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.device_index = T234_MSS_CHANNEL_PARTB2_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss6_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss6_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss6_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss6_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -130,6 +138,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 8U,
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.element_index = 8U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_partb3",
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.name = "perfmon_msschannel_partb3",
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.device_index = T234_MSS_CHANNEL_PARTB3_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss7_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss7_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss7_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss7_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -145,6 +154,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 9U,
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.element_index = 9U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_partc0",
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.name = "perfmon_msschannel_partc0",
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.device_index = T234_MSS_CHANNEL_PARTC0_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss8_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss8_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss8_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss8_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -160,6 +170,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 10U,
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.element_index = 10U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_partc1",
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.name = "perfmon_msschannel_partc1",
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.device_index = T234_MSS_CHANNEL_PARTC1_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss9_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss9_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss9_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss9_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -175,6 +186,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 11U,
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.element_index = 11U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_partc2",
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.name = "perfmon_msschannel_partc2",
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.device_index = T234_MSS_CHANNEL_PARTC2_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss10_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss10_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss10_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss10_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -190,6 +202,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 12U,
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.element_index = 12U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_partc3",
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.name = "perfmon_msschannel_partc3",
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.device_index = T234_MSS_CHANNEL_PARTC3_PERFMON_DEVICE_NODE_INDEX,
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.start_abs_pa = addr_map_rpg_pm_mss11_base_r(),
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.start_abs_pa = addr_map_rpg_pm_mss11_base_r(),
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.end_abs_pa = addr_map_rpg_pm_mss11_limit_r(),
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.end_abs_pa = addr_map_rpg_pm_mss11_limit_r(),
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.start_pa = 0,
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.start_pa = 0,
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@@ -205,6 +218,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
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.element_index = 13U,
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.element_index = 13U,
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.dt_mmio = NULL,
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.dt_mmio = NULL,
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.name = "perfmon_msschannel_partd0",
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.name = "perfmon_msschannel_partd0",
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|
.device_index = T234_MSS_CHANNEL_PARTD0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_mss12_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_mss12_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_mss12_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_mss12_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
@@ -220,6 +234,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
|
|||||||
.element_index = 14U,
|
.element_index = 14U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_msschannel_partd1",
|
.name = "perfmon_msschannel_partd1",
|
||||||
|
.device_index = T234_MSS_CHANNEL_PARTD1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_mss13_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_mss13_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_mss13_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_mss13_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
@@ -235,6 +250,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
|
|||||||
.element_index = 15U,
|
.element_index = 15U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_msschannel_partd2",
|
.name = "perfmon_msschannel_partd2",
|
||||||
|
.device_index = T234_MSS_CHANNEL_PARTD2_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_mss14_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_mss14_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_mss14_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_mss14_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
@@ -250,6 +266,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
|
|||||||
.element_index = 16U,
|
.element_index = 16U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_msschannel_partd3",
|
.name = "perfmon_msschannel_partd3",
|
||||||
|
.device_index = T234_MSS_CHANNEL_PARTD3_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_mss15_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_mss15_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_mss15_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_mss15_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmon_element_static_arr
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_mssnvlhsh0",
|
.name = "perfmon_mssnvlhsh0",
|
||||||
|
.device_index = T234_MSSNVLHSH0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_mssnvl_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_mssnvl_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_mssnvl_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_mssnvl_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmon_element_stati
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_msshub0",
|
.name = "perfmon_msshub0",
|
||||||
|
.device_index = T234_MSSHUB0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_msshub0_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_msshub0_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_msshub0_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_msshub0_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
@@ -40,6 +42,7 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmon_element_stati
|
|||||||
.element_index = 1U,
|
.element_index = 1U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_msshub1",
|
.name = "perfmon_msshub1",
|
||||||
|
.device_index = T234_MSSHUB1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_msshub1_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_msshub1_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_msshub1_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_msshub1_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_mssmcfclient0",
|
.name = "perfmon_mssmcfclient0",
|
||||||
|
.device_index = T234_MSSMCFCLIENT0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_mcf0_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_mcf0_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_mcf0_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_mcf0_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
@@ -40,6 +42,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 1U,
|
.element_index = 1U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_mssmcfmem0",
|
.name = "perfmon_mssmcfmem0",
|
||||||
|
.device_index = T234_MSSMCFMEM0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_mcf1_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_mcf1_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_mcf1_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_mcf1_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
@@ -55,6 +58,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 2U,
|
.element_index = 2U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_mssmcfmem1",
|
.name = "perfmon_mssmcfmem1",
|
||||||
|
.device_index = T234_MSSMCFMEM1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_mcf2_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_mcf2_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_mcf2_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_mcf2_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_nvdec_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_nvdec_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_nvdec_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_nvdeca0",
|
.name = "perfmon_nvdeca0",
|
||||||
|
.device_index = T234_NVDECA0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_nvdec0_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_nvdec0_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_nvdec0_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_nvdec0_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_nvdla_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_nvdla_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_nvdla_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_nvdlab0",
|
.name = "perfmon_nvdlab0",
|
||||||
|
.device_index = T234_NVDLAB0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_nvdla0_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_nvdla0_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_nvdla0_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_nvdla0_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
@@ -44,6 +46,7 @@ static struct hwpm_ip_aperture t234_nvdla_inst1_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_nvdlab1",
|
.name = "perfmon_nvdlab1",
|
||||||
|
.device_index = T234_NVDLAB1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_nvdla1_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_nvdla1_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_nvdla1_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_nvdla1_limit_r(),
|
||||||
.start_pa = 0,
|
.start_pa = 0,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_nvenc_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_nvenc_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_NVENC_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_NVENC_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_nvenc_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_nvenca0",
|
.name = "perfmon_nvenca0",
|
||||||
|
.device_index = T234_NVENCA0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_nvenc0_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_nvenc0_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_nvenc0_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_nvenc0_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_ofa_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_ofa_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_OFA_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_OFA_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_ofa_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_ofaa0",
|
.name = "perfmon_ofaa0",
|
||||||
|
.device_index = T234_OFAA0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_ofa_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_ofa_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_ofa_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_ofa_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_pcie_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_pcie_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_PCIE_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_pcie_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie0",
|
.name = "perfmon_pcie0",
|
||||||
|
.device_index = T234_PCIE0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c0_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c0_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c0_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c0_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -44,6 +46,7 @@ static struct hwpm_ip_aperture t234_pcie_inst1_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie1",
|
.name = "perfmon_pcie1",
|
||||||
|
.device_index = T234_PCIE1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c1_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c1_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c1_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c1_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -63,6 +66,7 @@ static struct hwpm_ip_aperture t234_pcie_inst2_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie2",
|
.name = "perfmon_pcie2",
|
||||||
|
.device_index = T234_PCIE2_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c2_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c2_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c2_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c2_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -82,6 +86,7 @@ static struct hwpm_ip_aperture t234_pcie_inst3_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie3",
|
.name = "perfmon_pcie3",
|
||||||
|
.device_index = T234_PCIE3_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c3_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c3_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c3_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c3_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -101,6 +106,7 @@ static struct hwpm_ip_aperture t234_pcie_inst4_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie4",
|
.name = "perfmon_pcie4",
|
||||||
|
.device_index = T234_PCIE4_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c4_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c4_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c4_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c4_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -120,6 +126,7 @@ static struct hwpm_ip_aperture t234_pcie_inst5_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie5",
|
.name = "perfmon_pcie5",
|
||||||
|
.device_index = T234_PCIE5_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c5_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c5_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c5_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c5_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -139,6 +146,7 @@ static struct hwpm_ip_aperture t234_pcie_inst6_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie6",
|
.name = "perfmon_pcie6",
|
||||||
|
.device_index = T234_PCIE6_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c6_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c6_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c6_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c6_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -158,6 +166,7 @@ static struct hwpm_ip_aperture t234_pcie_inst7_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie7",
|
.name = "perfmon_pcie7",
|
||||||
|
.device_index = T234_PCIE7_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c7_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c7_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c7_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c7_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -177,6 +186,7 @@ static struct hwpm_ip_aperture t234_pcie_inst8_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie8",
|
.name = "perfmon_pcie8",
|
||||||
|
.device_index = T234_PCIE8_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c8_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c8_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c8_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c8_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -196,6 +206,7 @@ static struct hwpm_ip_aperture t234_pcie_inst9_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie9",
|
.name = "perfmon_pcie9",
|
||||||
|
.device_index = T234_PCIE9_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c9_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c9_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c9_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c9_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -215,6 +226,7 @@ static struct hwpm_ip_aperture t234_pcie_inst10_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pcie10",
|
.name = "perfmon_pcie10",
|
||||||
|
.device_index = T234_PCIE10_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pcie_c10_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pcie_c10_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pcie_c10_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pcie_c10_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_pma_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_pma_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_PMA_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_PMA_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_pma_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_sys0",
|
.name = "perfmon_sys0",
|
||||||
|
.device_index = T234_SYS0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pma_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pma_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pma_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pma_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -44,6 +46,7 @@ static struct hwpm_ip_aperture t234_pma_inst0_perfmux_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "pma",
|
.name = "pma",
|
||||||
|
.device_index = T234_PMA_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_pma_base_r(),
|
.start_abs_pa = addr_map_pma_base_r(),
|
||||||
.end_abs_pa = addr_map_pma_limit_r(),
|
.end_abs_pa = addr_map_pma_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pvav0",
|
.name = "perfmon_pvav0",
|
||||||
|
.device_index = T234_PVAV0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pva0_0_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pva0_0_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pva0_0_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pva0_0_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -40,6 +42,7 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 1U,
|
.element_index = 1U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_pvav1",
|
.name = "perfmon_pvav1",
|
||||||
|
.device_index = T234_PVAV1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_pva0_1_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_pva0_1_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_pva0_1_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_pva0_1_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
/* RTR aperture should be placed in instance T234_HWPM_IP_RTR_STATIC_RTR_INST */
|
/* RTR aperture should be placed in instance T234_HWPM_IP_RTR_STATIC_RTR_INST */
|
||||||
static struct hwpm_ip_aperture t234_rtr_inst0_perfmux_element_static_array[
|
static struct hwpm_ip_aperture t234_rtr_inst0_perfmux_element_static_array[
|
||||||
@@ -26,6 +27,7 @@ static struct hwpm_ip_aperture t234_rtr_inst0_perfmux_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "rtr",
|
.name = "rtr",
|
||||||
|
.device_index = T234_RTR_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rtr_base_r(),
|
.start_abs_pa = addr_map_rtr_base_r(),
|
||||||
.end_abs_pa = addr_map_rtr_limit_r(),
|
.end_abs_pa = addr_map_rtr_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -47,6 +49,7 @@ static struct hwpm_ip_aperture t234_rtr_inst1_perfmux_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "pma",
|
.name = "pma",
|
||||||
|
.device_index = T234_PMA_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_pma_base_r(),
|
.start_abs_pa = addr_map_pma_base_r(),
|
||||||
.end_abs_pa = addr_map_pma_limit_r(),
|
.end_abs_pa = addr_map_pma_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_scf_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_scf_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_SCF_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_SCF_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_scf_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_scf",
|
.name = "perfmon_scf",
|
||||||
|
.device_index = T234_SCF_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_scf_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_scf_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_scf_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_scf_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_vi_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_vi_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_VI_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_VI_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_vi_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_vi0",
|
.name = "perfmon_vi0",
|
||||||
|
.device_index = T234_VI0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_vi0_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_vi0_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_vi0_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_vi0_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
@@ -44,6 +46,7 @@ static struct hwpm_ip_aperture t234_vi_inst1_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_vi1",
|
.name = "perfmon_vi1",
|
||||||
|
.device_index = T234_VI1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_vi1_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_vi1_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_vi1_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_vi1_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
|
|||||||
@@ -16,6 +16,7 @@
|
|||||||
#include <tegra_hwpm.h>
|
#include <tegra_hwpm.h>
|
||||||
#include <hal/t234/t234_regops_allowlist.h>
|
#include <hal/t234/t234_regops_allowlist.h>
|
||||||
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
|
||||||
|
#include <hal/t234/t234_perfmon_device_index.h>
|
||||||
|
|
||||||
static struct hwpm_ip_aperture t234_vic_inst0_perfmon_element_static_array[
|
static struct hwpm_ip_aperture t234_vic_inst0_perfmon_element_static_array[
|
||||||
T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST] = {
|
T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST] = {
|
||||||
@@ -25,6 +26,7 @@ static struct hwpm_ip_aperture t234_vic_inst0_perfmon_element_static_array[
|
|||||||
.element_index = 0U,
|
.element_index = 0U,
|
||||||
.dt_mmio = NULL,
|
.dt_mmio = NULL,
|
||||||
.name = "perfmon_vica0",
|
.name = "perfmon_vica0",
|
||||||
|
.device_index = T234_VICA0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
.start_abs_pa = addr_map_rpg_pm_vic_base_r(),
|
.start_abs_pa = addr_map_rpg_pm_vic_base_r(),
|
||||||
.end_abs_pa = addr_map_rpg_pm_vic_limit_r(),
|
.end_abs_pa = addr_map_rpg_pm_vic_limit_r(),
|
||||||
.start_pa = 0ULL,
|
.start_pa = 0ULL,
|
||||||
|
|||||||
75
drivers/tegra/hwpm/hal/t234/t234_perfmon_device_index.h
Normal file
75
drivers/tegra/hwpm/hal/t234/t234_perfmon_device_index.h
Normal file
@@ -0,0 +1,75 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef T234_HWPM_PERFMON_DEVICE_INDEX_H
|
||||||
|
#define T234_HWPM_PERFMON_DEVICE_INDEX_H
|
||||||
|
|
||||||
|
enum t234_hwpm_perfmon_device_index {
|
||||||
|
T234_VI0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_VI1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_ISP0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_VICA0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_OFAA0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PVAV0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PVAV1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PVAC0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_NVDLAB0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_NVDLAB1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_NVDISPLAY0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_SYS0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MGBE0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MGBE1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MGBE2_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MGBE3_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_SCF_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_NVDECA0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_NVENCA0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSSNVLHSH0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE2_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE3_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE4_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE5_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE6_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE7_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE8_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE9_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PCIE10_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTA0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTA1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTA2_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTA3_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTB0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTB1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTB2_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTB3_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTC0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTC1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTC2_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTC3_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTD0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTD1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTD2_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSS_CHANNEL_PARTD3_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSSHUB0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSSHUB1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSSMCFCLIENT0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSSMCFMEM0_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_MSSMCFMEM1_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_PMA_PERFMON_DEVICE_NODE_INDEX,
|
||||||
|
T234_RTR_PERFMON_DEVICE_NODE_INDEX
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
@@ -210,6 +210,13 @@ struct hwpm_ip_aperture {
|
|||||||
/* DT tree name */
|
/* DT tree name */
|
||||||
char name[64];
|
char name[64];
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Device index corresponding to device node aperture address index
|
||||||
|
* in Device tree or ACPI table.
|
||||||
|
* This is used to map HWPM apertures only
|
||||||
|
*/
|
||||||
|
u32 device_index;
|
||||||
|
|
||||||
/* Allowlist */
|
/* Allowlist */
|
||||||
struct allowlist *alist;
|
struct allowlist *alist;
|
||||||
u64 alist_size;
|
u64 alist_size;
|
||||||
|
|||||||
@@ -37,13 +37,22 @@ int tegra_hwpm_perfmon_reserve_impl(struct tegra_soc_hwpm *hwpm,
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Reserve */
|
/* Reserve */
|
||||||
res = platform_get_resource_byname(hwpm_linux->pdev,
|
res = platform_get_resource(hwpm_linux->pdev,
|
||||||
IORESOURCE_MEM, perfmon->name);
|
IORESOURCE_MEM, perfmon->device_index);
|
||||||
if ((!res) || (res->start == 0) || (res->end == 0)) {
|
if ((!res) || (res->start == 0) || (res->end == 0)) {
|
||||||
tegra_hwpm_err(hwpm, "Failed to get perfmon %s", perfmon->name);
|
tegra_hwpm_err(hwpm, "Failed to get perfmon %s", perfmon->name);
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (res->start != perfmon->start_abs_pa) {
|
||||||
|
tegra_hwpm_err(hwpm, "Failed to get correct"
|
||||||
|
"perfmon address for %s,"
|
||||||
|
"Expected - 0x%llx, Returned - 0x%llx",
|
||||||
|
perfmon->name, perfmon->start_abs_pa,
|
||||||
|
res->start);
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
perfmon->dt_mmio = devm_ioremap(
|
perfmon->dt_mmio = devm_ioremap(
|
||||||
hwpm_linux->dev, res->start, resource_size(res));
|
hwpm_linux->dev, res->start, resource_size(res));
|
||||||
if (IS_ERR(perfmon->dt_mmio)) {
|
if (IS_ERR(perfmon->dt_mmio)) {
|
||||||
|
|||||||
Reference in New Issue
Block a user