From cdbd6e7a24e1539ceb0843fe84198d00db07a94f Mon Sep 17 00:00:00 2001 From: Vishal Aslot Date: Thu, 9 May 2024 04:56:05 -0700 Subject: [PATCH] tegra: hwpm: th500: fixes and reorg of IPs This patch fixes issues found during testing and guidance provided by devtools. The following is changed in this patch: 1. mcf_iobhx and mcf_ocu are merged into a single mcf_soc IP. 2a. c2c is changed from 2 instances to 1. 2b. Remove C2CS0/1 which are the broadcast apertures. Also remove the allowlist offset specific to broadcast aperture. 3. mss_hub is changed from 1 instance to 8. 4. mss_channel is changed from 1 instance to 32. 5. mc0 perfmux is added to mcf_clink. 6. mcf_core is changed from 1 instance to 8. 7. License headers updated where necessary. 8. c2c allowlist updated to have just the offsets common to all links. 9. Added a verbose comment explaining the design of th500_hwpm_force_enable_ips() 10. Added back validate_current_config module parameter as many systems still don't support fuses. 11. If all F's are read back for a regop in ip_readl(), return -ENODEV. There is a corresponding patch to update the python scripts that generated many of the C and header files. Bug 4287384 Change-Id: I8e14b0165dfa1abb9f5e04de577a41f0eb278246 Signed-off-by: Vishal Aslot Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3134365 Reviewed-by: Seema Khowala Reviewed-by: Eric Lu GVS: buildbot_gerritrpt --- drivers/tegra/hwpm/Makefile.th500.soc.sources | 7 +- .../hwpm/hal/th500/soc/ip/c2c/th500_c2c.c | 163 +- .../hwpm/hal/th500/soc/ip/c2c/th500_c2c.h | 8 +- .../th500/soc/ip/mcf_clink/th500_mcf_clink.c | 51 +- .../th500/soc/ip/mcf_clink/th500_mcf_clink.h | 6 +- .../th500/soc/ip/mcf_core/th500_mcf_core.c | 775 +++- .../th500/soc/ip/mcf_core/th500_mcf_core.h | 10 +- .../th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.c | 215 -- .../th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.h | 48 - .../th500_mcf_soc.c} | 81 +- .../th500_mcf_soc.h} | 26 +- .../soc/ip/mss_channel/th500_mss_channel.c | 3139 ++++++++++++++++- .../soc/ip/mss_channel/th500_mss_channel.h | 10 +- .../hal/th500/soc/ip/mss_hub/th500_mss_hub.c | 715 +++- .../hal/th500/soc/ip/mss_hub/th500_mss_hub.h | 10 +- .../th500/soc/th500_soc_regops_allowlist.c | 69 +- .../th500/soc/th500_soc_regops_allowlist.h | 7 +- .../tegra/hwpm/hal/th500/th500_interface.c | 32 +- drivers/tegra/hwpm/hal/th500/th500_internal.h | 6 +- drivers/tegra/hwpm/hal/th500/th500_ip.c | 195 +- drivers/tegra/hwpm/include/tegra_hwpm.h | 6 +- drivers/tegra/hwpm/include/tegra_hwpm_log.h | 2 +- drivers/tegra/hwpm/os/linux/debugfs.c | 3 - drivers/tegra/hwpm/os/linux/driver.c | 91 +- drivers/tegra/hwpm/os/linux/io_utils.c | 11 +- drivers/tegra/hwpm/os/linux/ip_utils.c | 21 +- include/uapi/linux/tegra-soc-hwpm-uapi.h | 13 +- 27 files changed, 4716 insertions(+), 1004 deletions(-) delete mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.c delete mode 100644 drivers/tegra/hwpm/hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.h rename drivers/tegra/hwpm/hal/th500/soc/ip/{mcf_ocu/th500_mcf_ocu.c => mcf_soc/th500_mcf_soc.c} (74%) rename drivers/tegra/hwpm/hal/th500/soc/ip/{mcf_ocu/th500_mcf_ocu.h => mcf_soc/th500_mcf_soc.h} (67%) diff --git a/drivers/tegra/hwpm/Makefile.th500.soc.sources b/drivers/tegra/hwpm/Makefile.th500.soc.sources index 35a13b8..11454b3 100644 --- a/drivers/tegra/hwpm/Makefile.th500.soc.sources +++ b/drivers/tegra/hwpm/Makefile.th500.soc.sources @@ -80,11 +80,8 @@ nvhwpm-th500-soc-objs += hal/th500/soc/ip/c_nvlink/th500_nvlctrl.o ccflags-y += -DCONFIG_TH500_HWPM_IP_MSS_HUB nvhwpm-th500-soc-objs += hal/th500/soc/ip/mss_hub/th500_mss_hub.o -ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_OCU -nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.o - -ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_IOBHX -nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.o +ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_SOC +nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_soc/th500_mcf_soc.o ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_C2C nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.o diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.c b/drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.c index 1bb5314..46f53f7 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.c +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.c @@ -51,14 +51,10 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmon_element_static_array[ .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, -}; - -static struct hwpm_ip_aperture th500_c2c_inst1_perfmon_element_static_array[ - TH500_HWPM_IP_C2C_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(0), - .element_index = 0U, + .element_index_mask = BIT(1), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_c2c1", .device_index = TH500_CTC1_PERFMON_DEVICE_NODE_INDEX, @@ -150,14 +146,10 @@ static struct hwpm_ip_aperture th500_c2c_inst0_perfmux_element_static_array[ .alist_size = ARRAY_SIZE(th500_c2c_alist), .fake_registers = NULL, }, -}; - -static struct hwpm_ip_aperture th500_c2c_inst1_perfmux_element_static_array[ - TH500_HWPM_IP_C2C_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(0), - .element_index = 0U, + .element_index_mask = BIT(5), + .element_index = 5U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_c2c5_base_r(), @@ -171,8 +163,8 @@ static struct hwpm_ip_aperture th500_c2c_inst1_perfmux_element_static_array[ }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(1), - .element_index = 1U, + .element_index_mask = BIT(6), + .element_index = 6U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_c2c6_base_r(), @@ -186,8 +178,8 @@ static struct hwpm_ip_aperture th500_c2c_inst1_perfmux_element_static_array[ }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(2), - .element_index = 2U, + .element_index_mask = BIT(7), + .element_index = 7U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_c2c7_base_r(), @@ -201,8 +193,8 @@ static struct hwpm_ip_aperture th500_c2c_inst1_perfmux_element_static_array[ }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(3), - .element_index = 3U, + .element_index_mask = BIT(8), + .element_index = 8U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_c2c8_base_r(), @@ -216,8 +208,8 @@ static struct hwpm_ip_aperture th500_c2c_inst1_perfmux_element_static_array[ }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(4), - .element_index = 4U, + .element_index_mask = BIT(9), + .element_index = 9U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_c2c9_base_r(), @@ -231,44 +223,6 @@ static struct hwpm_ip_aperture th500_c2c_inst1_perfmux_element_static_array[ }, }; -static struct hwpm_ip_aperture th500_c2c_inst0_broadcast_element_static_array[ - TH500_HWPM_IP_C2C_NUM_BROADCAST_PER_INST] = { - { - .element_type = IP_ELEMENT_BROADCAST, - .element_index_mask = BIT(0), - .element_index = 0U, - .dt_mmio = NULL, - .name = {'\0'}, - .start_abs_pa = addr_map_c2cs0_base_r(), - .end_abs_pa = addr_map_c2cs0_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = th500_c2c_alist, - .alist_size = ARRAY_SIZE(th500_c2c_alist), - .fake_registers = NULL, - }, -}; - -static struct hwpm_ip_aperture th500_c2c_inst1_broadcast_element_static_array[ - TH500_HWPM_IP_C2C_NUM_BROADCAST_PER_INST] = { - { - .element_type = IP_ELEMENT_BROADCAST, - .element_index_mask = BIT(0), - .element_index = 0U, - .dt_mmio = NULL, - .name = {'\0'}, - .start_abs_pa = addr_map_c2cs1_base_r(), - .end_abs_pa = addr_map_c2cs1_limit_r(), - .start_pa = 0ULL, - .end_pa = 0ULL, - .base_pa = 0ULL, - .alist = th500_c2c_alist, - .alist_size = ARRAY_SIZE(th500_c2c_alist), - .fake_registers = NULL, - }, -}; - /* IP instance array */ struct hwpm_ip_inst th500_c2c_inst_static_array[ TH500_HWPM_IP_C2C_NUM_INSTANCES] = { @@ -288,7 +242,7 @@ struct hwpm_ip_inst th500_c2c_inst_static_array[ th500_c2c_inst0_perfmux_element_static_array, /* NOTE: range should be in ascending order */ .range_start = addr_map_c2c0_base_r(), - .range_end = addr_map_c2c4_limit_r(), + .range_end = addr_map_c2c9_limit_r(), .element_stride = addr_map_c2c0_limit_r() - addr_map_c2c0_base_r() + 1ULL, .element_slots = 0U, @@ -298,15 +252,14 @@ struct hwpm_ip_inst th500_c2c_inst_static_array[ * Instance info corresponding to * TEGRA_HWPM_APERTURE_TYPE_BROADCAST */ + /* Disable C2C Broadcast apertures for now -- See Bug 4411532 */ { .num_element_per_inst = TH500_HWPM_IP_C2C_NUM_BROADCAST_PER_INST, - .element_static_array = - th500_c2c_inst0_broadcast_element_static_array, - .range_start = addr_map_c2cs0_base_r(), - .range_end = addr_map_c2cs0_limit_r(), - .element_stride = addr_map_c2cs0_limit_r() - - addr_map_c2cs0_base_r() + 1ULL, + .element_static_array = NULL, + .range_start = 0ULL, + .range_end = 0ULL, + .element_stride = 0ULL, .element_slots = 0U, .element_arr = NULL, }, @@ -320,7 +273,7 @@ struct hwpm_ip_inst th500_c2c_inst_static_array[ .element_static_array = th500_c2c_inst0_perfmon_element_static_array, .range_start = addr_map_rpg_pm_ctc0_base_r(), - .range_end = addr_map_rpg_pm_ctc0_limit_r(), + .range_end = addr_map_rpg_pm_ctc1_limit_r(), .element_stride = addr_map_rpg_pm_ctc0_limit_r() - addr_map_rpg_pm_ctc0_base_r() + 1ULL, .element_slots = 0U, @@ -335,72 +288,6 @@ struct hwpm_ip_inst th500_c2c_inst_static_array[ .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, }, - .element_fs_mask = 0U, - .dev_name = "", - }, - { - .hw_inst_mask = BIT(1), - .num_core_elements_per_inst = - TH500_HWPM_IP_C2C_NUM_CORE_ELEMENT_PER_INST, - .element_info = { - /* - * Instance info corresponding to - * TEGRA_HWPM_APERTURE_TYPE_PERFMUX - */ - { - .num_element_per_inst = - TH500_HWPM_IP_C2C_NUM_PERFMUX_PER_INST, - .element_static_array = - th500_c2c_inst1_perfmux_element_static_array, - /* NOTE: range should be in ascending order */ - .range_start = addr_map_c2c5_base_r(), - .range_end = addr_map_c2c9_limit_r(), - .element_stride = addr_map_c2c5_limit_r() - - addr_map_c2c5_base_r() + 1ULL, - .element_slots = 0U, - .element_arr = NULL, - }, - /* - * Instance info corresponding to - * TEGRA_HWPM_APERTURE_TYPE_BROADCAST - */ - { - .num_element_per_inst = - TH500_HWPM_IP_C2C_NUM_BROADCAST_PER_INST, - .element_static_array = - th500_c2c_inst1_broadcast_element_static_array, - .range_start = addr_map_c2cs1_base_r(), - .range_end = addr_map_c2cs1_limit_r(), - .element_stride = addr_map_c2cs1_limit_r() - - addr_map_c2cs1_base_r() + 1ULL, - .element_slots = 0U, - .element_arr = NULL, - }, - /* - * Instance info corresponding to - * TEGRA_HWPM_APERTURE_TYPE_PERFMON - */ - { - .num_element_per_inst = - TH500_HWPM_IP_C2C_NUM_PERFMON_PER_INST, - .element_static_array = - th500_c2c_inst1_perfmon_element_static_array, - .range_start = addr_map_rpg_pm_ctc1_base_r(), - .range_end = addr_map_rpg_pm_ctc1_limit_r(), - .element_stride = addr_map_rpg_pm_ctc1_limit_r() - - addr_map_rpg_pm_ctc1_base_r() + 1ULL, - .element_slots = 0U, - .element_arr = NULL, - }, - }, - - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, - }, - .element_fs_mask = 0U, .dev_name = "", }, @@ -420,7 +307,7 @@ struct hwpm_ip th500_hwpm_ip_c2c = { /* NOTE: range should be in ascending order */ .range_start = addr_map_c2c0_base_r(), .range_end = addr_map_c2c9_limit_r(), - .inst_stride = addr_map_c2c4_limit_r() - + .inst_stride = addr_map_c2c9_limit_r() - addr_map_c2c0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, @@ -429,11 +316,11 @@ struct hwpm_ip th500_hwpm_ip_c2c = { * Instance info corresponding to * TEGRA_HWPM_APERTURE_TYPE_BROADCAST */ + /* Disable C2C Broadcast apertures for now -- See Bug 4411532 */ { - .range_start = addr_map_c2cs0_base_r(), - .range_end = addr_map_c2cs1_limit_r(), - .inst_stride = addr_map_c2cs0_limit_r() - - addr_map_c2cs0_base_r() + 1ULL, + .range_start = 0ULL, + .range_end = 0ULL, + .inst_stride = 0ULL, .inst_slots = 0U, .inst_arr = NULL, }, @@ -444,7 +331,7 @@ struct hwpm_ip th500_hwpm_ip_c2c = { { .range_start = addr_map_rpg_pm_ctc0_base_r(), .range_end = addr_map_rpg_pm_ctc1_limit_r(), - .inst_stride = addr_map_rpg_pm_ctc0_limit_r() - + .inst_stride = addr_map_rpg_pm_ctc1_limit_r() - addr_map_rpg_pm_ctc0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.h b/drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.h index d9cdfb4..c26f984 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.h +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/c2c/th500_c2c.h @@ -33,11 +33,11 @@ #define TH500_HWPM_ACTIVE_IP_C2C TH500_HWPM_IP_C2C, /* This data should ideally be available in HW headers */ -#define TH500_HWPM_IP_C2C_NUM_INSTANCES 2U +#define TH500_HWPM_IP_C2C_NUM_INSTANCES 1U #define TH500_HWPM_IP_C2C_NUM_CORE_ELEMENT_PER_INST 1U -#define TH500_HWPM_IP_C2C_NUM_PERFMON_PER_INST 1U -#define TH500_HWPM_IP_C2C_NUM_PERFMUX_PER_INST 5U -#define TH500_HWPM_IP_C2C_NUM_BROADCAST_PER_INST 1U +#define TH500_HWPM_IP_C2C_NUM_PERFMON_PER_INST 2U +#define TH500_HWPM_IP_C2C_NUM_PERFMUX_PER_INST 10U +#define TH500_HWPM_IP_C2C_NUM_BROADCAST_PER_INST 0U extern struct hwpm_ip th500_hwpm_ip_c2c; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c index 5483d88..6759d1b 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.c @@ -38,7 +38,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmon_element_static_arra { .element_type = HWPM_ELEMENT_PERFMON, .element_index_mask = BIT(0), - .element_index = 0U, + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_mcfsys0", .device_index = TH500_MCFSYS0_PERFMON_DEVICE_NODE_INDEX, @@ -54,7 +54,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmon_element_static_arra { .element_type = HWPM_ELEMENT_PERFMON, .element_index_mask = BIT(1), - .element_index = 1U, + .element_index = 2U, .dt_mmio = NULL, .name = "perfmon_mcfsys1", .device_index = TH500_MCFSYS1_PERFMON_DEVICE_NODE_INDEX, @@ -74,6 +74,21 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra { .element_type = IP_ELEMENT_PERFMUX, .element_index_mask = BIT(0), + .element_index = 1U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc0_base_r(), + .end_abs_pa = addr_map_mc0_limit_r(), + .start_pa = addr_map_mc0_base_r(), + .end_pa = addr_map_mc0_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_clink_alist, + .alist_size = ARRAY_SIZE(th500_mcf_clink_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(1), .element_index = 11U, .dt_mmio = NULL, .name = {'\0'}, @@ -88,7 +103,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(1), + .element_index_mask = BIT(2), .element_index = 12U, .dt_mmio = NULL, .name = {'\0'}, @@ -103,7 +118,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(2), + .element_index_mask = BIT(3), .element_index = 13U, .dt_mmio = NULL, .name = {'\0'}, @@ -118,7 +133,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(3), + .element_index_mask = BIT(4), .element_index = 14U, .dt_mmio = NULL, .name = {'\0'}, @@ -133,7 +148,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(4), + .element_index_mask = BIT(5), .element_index = 15U, .dt_mmio = NULL, .name = {'\0'}, @@ -148,7 +163,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(5), + .element_index_mask = BIT(6), .element_index = 16U, .dt_mmio = NULL, .name = {'\0'}, @@ -163,7 +178,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(6), + .element_index_mask = BIT(7), .element_index = 17U, .dt_mmio = NULL, .name = {'\0'}, @@ -178,7 +193,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(7), + .element_index_mask = BIT(8), .element_index = 18U, .dt_mmio = NULL, .name = {'\0'}, @@ -193,7 +208,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(8), + .element_index_mask = BIT(9), .element_index = 19U, .dt_mmio = NULL, .name = {'\0'}, @@ -208,7 +223,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(9), + .element_index_mask = BIT(10), .element_index = 20U, .dt_mmio = NULL, .name = {'\0'}, @@ -223,7 +238,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(10), + .element_index_mask = BIT(11), .element_index = 21U, .dt_mmio = NULL, .name = {'\0'}, @@ -238,7 +253,7 @@ static struct hwpm_ip_aperture th500_mcf_clink_inst0_perfmux_element_static_arra }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(11), + .element_index_mask = BIT(12), .element_index = 22U, .dt_mmio = NULL, .name = {'\0'}, @@ -290,10 +305,10 @@ struct hwpm_ip_inst th500_mcf_clink_inst_static_array[ .element_static_array = th500_mcf_clink_inst0_perfmux_element_static_array, /* NOTE: range should be in ascending order */ - .range_start = addr_map_mc10_base_r(), + .range_start = addr_map_mc0_base_r(), .range_end = addr_map_mc21_limit_r(), - .element_stride = addr_map_mc10_limit_r() - - addr_map_mc10_base_r() + 1ULL, + .element_stride = addr_map_mc0_limit_r() - + addr_map_mc0_base_r() + 1ULL, .element_slots = 0U, .element_arr = NULL, }, @@ -355,10 +370,10 @@ struct hwpm_ip th500_hwpm_ip_mcf_clink = { */ { /* NOTE: range should be in ascending order */ - .range_start = addr_map_mc10_base_r(), + .range_start = addr_map_mc0_base_r(), .range_end = addr_map_mc21_limit_r(), .inst_stride = addr_map_mc21_limit_r() - - addr_map_mc10_base_r() + 1ULL, + addr_map_mc0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, }, diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h index e88d3bd..d6ea87c 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,9 +34,9 @@ /* This data should ideally be available in HW headers */ #define TH500_HWPM_IP_MCF_CLINK_NUM_INSTANCES 1U -#define TH500_HWPM_IP_MCF_CLINK_NUM_CORE_ELEMENT_PER_INST 12U +#define TH500_HWPM_IP_MCF_CLINK_NUM_CORE_ELEMENT_PER_INST 13U #define TH500_HWPM_IP_MCF_CLINK_NUM_PERFMON_PER_INST 2U -#define TH500_HWPM_IP_MCF_CLINK_NUM_PERFMUX_PER_INST 12U +#define TH500_HWPM_IP_MCF_CLINK_NUM_PERFMUX_PER_INST 13U #define TH500_HWPM_IP_MCF_CLINK_NUM_BROADCAST_PER_INST 1U extern struct hwpm_ip th500_hwpm_ip_mcf_clink; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.c b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.c index bdcd272..d47bb22 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.c +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.c @@ -38,7 +38,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array { .element_type = HWPM_ELEMENT_PERFMON, .element_index_mask = BIT(0), - .element_index = 0U, + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_mcf_core0", .device_index = TH500_MCFCORE0_PERFMON_DEVICE_NODE_INDEX, @@ -54,7 +54,7 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array { .element_type = HWPM_ELEMENT_PERFMON, .element_index_mask = BIT(1), - .element_index = 1U, + .element_index = 2U, .dt_mmio = NULL, .name = "perfmon_mcf_core1", .device_index = TH500_MCFCORE1_PERFMON_DEVICE_NODE_INDEX, @@ -67,10 +67,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst1_perfmon_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(2), - .element_index = 2U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_mcf_core2", .device_index = TH500_MCFCORE2_PERFMON_DEVICE_NODE_INDEX, @@ -85,8 +89,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array }, { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(3), - .element_index = 3U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = "perfmon_mcf_core3", .device_index = TH500_MCFCORE3_PERFMON_DEVICE_NODE_INDEX, @@ -99,10 +103,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst2_perfmon_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(4), - .element_index = 4U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_mcf_core4", .device_index = TH500_MCFCORE4_PERFMON_DEVICE_NODE_INDEX, @@ -117,8 +125,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array }, { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(5), - .element_index = 5U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = "perfmon_mcf_core5", .device_index = TH500_MCFCORE5_PERFMON_DEVICE_NODE_INDEX, @@ -131,10 +139,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst3_perfmon_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(6), - .element_index = 6U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_mcf_core6", .device_index = TH500_MCFCORE6_PERFMON_DEVICE_NODE_INDEX, @@ -149,8 +161,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array }, { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(7), - .element_index = 7U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = "perfmon_mcf_core7", .device_index = TH500_MCFCORE7_PERFMON_DEVICE_NODE_INDEX, @@ -163,10 +175,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst4_perfmon_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(8), - .element_index = 8U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_mcf_core8", .device_index = TH500_MCFCORE8_PERFMON_DEVICE_NODE_INDEX, @@ -181,8 +197,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array }, { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(9), - .element_index = 9U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = "perfmon_mcf_core9", .device_index = TH500_MCFCORE9_PERFMON_DEVICE_NODE_INDEX, @@ -195,10 +211,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst5_perfmon_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(10), - .element_index = 10U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_mcf_core10", .device_index = TH500_MCFCORE10_PERFMON_DEVICE_NODE_INDEX, @@ -213,8 +233,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array }, { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(11), - .element_index = 11U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = "perfmon_mcf_core11", .device_index = TH500_MCFCORE11_PERFMON_DEVICE_NODE_INDEX, @@ -227,10 +247,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst6_perfmon_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(12), - .element_index = 12U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_mcf_core12", .device_index = TH500_MCFCORE12_PERFMON_DEVICE_NODE_INDEX, @@ -245,8 +269,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array }, { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(13), - .element_index = 13U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = "perfmon_mcf_core13", .device_index = TH500_MCFCORE13_PERFMON_DEVICE_NODE_INDEX, @@ -259,10 +283,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst7_perfmon_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(14), - .element_index = 14U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_mcf_core14", .device_index = TH500_MCFCORE14_PERFMON_DEVICE_NODE_INDEX, @@ -277,8 +305,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmon_element_static_array }, { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(15), - .element_index = 15U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = "perfmon_mcf_core15", .device_index = TH500_MCFCORE15_PERFMON_DEVICE_NODE_INDEX, @@ -325,10 +353,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array .alist_size = ARRAY_SIZE(th500_mcf_core_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst1_perfmux_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(2), - .element_index = 3U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc2_base_r(), @@ -342,8 +374,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(3), - .element_index = 4U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc3_base_r(), @@ -355,10 +387,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array .alist_size = ARRAY_SIZE(th500_mcf_core_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst2_perfmux_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(4), - .element_index = 5U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc4_base_r(), @@ -372,8 +408,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(5), - .element_index = 6U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc5_base_r(), @@ -385,10 +421,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array .alist_size = ARRAY_SIZE(th500_mcf_core_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst3_perfmux_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(6), - .element_index = 7U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc6_base_r(), @@ -402,8 +442,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(7), - .element_index = 8U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc7_base_r(), @@ -415,10 +455,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array .alist_size = ARRAY_SIZE(th500_mcf_core_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst4_perfmux_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(8), - .element_index = 9U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc8_base_r(), @@ -432,8 +476,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(9), - .element_index = 10U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc9_base_r(), @@ -445,10 +489,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array .alist_size = ARRAY_SIZE(th500_mcf_core_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst5_perfmux_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(10), - .element_index = 11U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc10_base_r(), @@ -462,8 +510,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(11), - .element_index = 12U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc11_base_r(), @@ -475,10 +523,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array .alist_size = ARRAY_SIZE(th500_mcf_core_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst6_perfmux_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(12), - .element_index = 13U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc12_base_r(), @@ -492,8 +544,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(13), - .element_index = 14U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc13_base_r(), @@ -505,10 +557,14 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array .alist_size = ARRAY_SIZE(th500_mcf_core_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst7_perfmux_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(14), - .element_index = 15U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc14_base_r(), @@ -522,8 +578,8 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_perfmux_element_static_array }, { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(15), - .element_index = 16U, + .element_index_mask = BIT(1), + .element_index = 2U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc15_base_r(), @@ -556,6 +612,139 @@ static struct hwpm_ip_aperture th500_mcf_core_inst0_broadcast_element_static_arr }, }; +static struct hwpm_ip_aperture th500_mcf_core_inst1_broadcast_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_core_alist, + .alist_size = ARRAY_SIZE(th500_mcf_core_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst2_broadcast_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_core_alist, + .alist_size = ARRAY_SIZE(th500_mcf_core_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst3_broadcast_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_core_alist, + .alist_size = ARRAY_SIZE(th500_mcf_core_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst4_broadcast_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_core_alist, + .alist_size = ARRAY_SIZE(th500_mcf_core_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst5_broadcast_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_core_alist, + .alist_size = ARRAY_SIZE(th500_mcf_core_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst6_broadcast_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_core_alist, + .alist_size = ARRAY_SIZE(th500_mcf_core_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mcf_core_inst7_broadcast_element_static_array[ + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_core_alist, + .alist_size = ARRAY_SIZE(th500_mcf_core_alist), + .fake_registers = NULL, + }, +}; + /* IP instance array */ struct hwpm_ip_inst th500_mcf_core_inst_static_array[ TH500_HWPM_IP_MCF_CORE_NUM_INSTANCES] = { @@ -575,7 +764,7 @@ struct hwpm_ip_inst th500_mcf_core_inst_static_array[ th500_mcf_core_inst0_perfmux_element_static_array, /* NOTE: range should be in ascending order */ .range_start = addr_map_mc0_base_r(), - .range_end = addr_map_mc15_limit_r(), + .range_end = addr_map_mc1_limit_r(), .element_stride = addr_map_mc0_limit_r() - addr_map_mc0_base_r() + 1ULL, .element_slots = 0U, @@ -607,7 +796,7 @@ struct hwpm_ip_inst th500_mcf_core_inst_static_array[ .element_static_array = th500_mcf_core_inst0_perfmon_element_static_array, .range_start = addr_map_rpg_pm_mcfcore0_base_r(), - .range_end = addr_map_rpg_pm_mcfcore15_limit_r(), + .range_end = addr_map_rpg_pm_mcfcore1_limit_r(), .element_stride = addr_map_rpg_pm_mcfcore0_limit_r() - addr_map_rpg_pm_mcfcore0_base_r() + 1ULL, .element_slots = 0U, @@ -622,6 +811,468 @@ struct hwpm_ip_inst th500_mcf_core_inst_static_array[ .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, }, + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(1), + .num_core_elements_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mcf_core_inst1_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc2_base_r(), + .range_end = addr_map_mc3_limit_r(), + .element_stride = addr_map_mc2_limit_r() - + addr_map_mc2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mcf_core_inst1_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mcf_core_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mcfcore2_base_r(), + .range_end = addr_map_rpg_pm_mcfcore3_limit_r(), + .element_stride = addr_map_rpg_pm_mcfcore1_limit_r() - + addr_map_rpg_pm_mcfcore1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(2), + .num_core_elements_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mcf_core_inst2_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc4_base_r(), + .range_end = addr_map_mc5_limit_r(), + .element_stride = addr_map_mc4_limit_r() - + addr_map_mc4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mcf_core_inst2_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mcf_core_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mcfcore4_base_r(), + .range_end = addr_map_rpg_pm_mcfcore5_limit_r(), + .element_stride = addr_map_rpg_pm_mcfcore4_limit_r() - + addr_map_rpg_pm_mcfcore4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(3), + .num_core_elements_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mcf_core_inst3_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc6_base_r(), + .range_end = addr_map_mc7_limit_r(), + .element_stride = addr_map_mc6_limit_r() - + addr_map_mc6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mcf_core_inst3_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mcf_core_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mcfcore6_base_r(), + .range_end = addr_map_rpg_pm_mcfcore7_limit_r(), + .element_stride = addr_map_rpg_pm_mcfcore6_limit_r() - + addr_map_rpg_pm_mcfcore6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(4), + .num_core_elements_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mcf_core_inst4_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc8_base_r(), + .range_end = addr_map_mc9_limit_r(), + .element_stride = addr_map_mc8_limit_r() - + addr_map_mc8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mcf_core_inst4_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mcf_core_inst4_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mcfcore8_base_r(), + .range_end = addr_map_rpg_pm_mcfcore9_limit_r(), + .element_stride = addr_map_rpg_pm_mcfcore8_limit_r() - + addr_map_rpg_pm_mcfcore8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(5), + .num_core_elements_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mcf_core_inst5_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc10_base_r(), + .range_end = addr_map_mc11_limit_r(), + .element_stride = addr_map_mc10_limit_r() - + addr_map_mc10_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mcf_core_inst5_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mcf_core_inst5_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mcfcore10_base_r(), + .range_end = addr_map_rpg_pm_mcfcore11_limit_r(), + .element_stride = addr_map_rpg_pm_mcfcore10_limit_r() - + addr_map_rpg_pm_mcfcore10_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(6), + .num_core_elements_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mcf_core_inst6_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc12_base_r(), + .range_end = addr_map_mc13_limit_r(), + .element_stride = addr_map_mc12_limit_r() - + addr_map_mc12_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mcf_core_inst6_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mcf_core_inst6_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mcfcore12_base_r(), + .range_end = addr_map_rpg_pm_mcfcore13_limit_r(), + .element_stride = addr_map_rpg_pm_mcfcore12_limit_r() - + addr_map_rpg_pm_mcfcore12_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(7), + .num_core_elements_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mcf_core_inst7_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc14_base_r(), + .range_end = addr_map_mc15_limit_r(), + .element_stride = addr_map_mc14_limit_r() - + addr_map_mc14_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mcf_core_inst7_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mcf_core_inst7_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_mcfcore14_base_r(), + .range_end = addr_map_rpg_pm_mcfcore15_limit_r(), + .element_stride = addr_map_rpg_pm_mcfcore14_limit_r() - + addr_map_rpg_pm_mcfcore14_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + .element_fs_mask = 0U, .dev_name = "", }, @@ -641,7 +1292,7 @@ struct hwpm_ip th500_hwpm_ip_mcf_core = { /* NOTE: range should be in ascending order */ .range_start = addr_map_mc0_base_r(), .range_end = addr_map_mc15_limit_r(), - .inst_stride = addr_map_mc15_limit_r() - + .inst_stride = addr_map_mc1_limit_r() - addr_map_mc0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, @@ -665,7 +1316,7 @@ struct hwpm_ip th500_hwpm_ip_mcf_core = { { .range_start = addr_map_rpg_pm_mcfcore0_base_r(), .range_end = addr_map_rpg_pm_mcfcore15_limit_r(), - .inst_stride = addr_map_rpg_pm_mcfcore15_limit_r() - + .inst_stride = addr_map_rpg_pm_mcfcore1_limit_r() - addr_map_rpg_pm_mcfcore0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.h b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.h index 10c7787..de2d299 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.h +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_core/th500_mcf_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,10 +33,10 @@ #define TH500_HWPM_ACTIVE_IP_MCF_CORE TH500_HWPM_IP_MCF_CORE, /* This data should ideally be available in HW headers */ -#define TH500_HWPM_IP_MCF_CORE_NUM_INSTANCES 1U -#define TH500_HWPM_IP_MCF_CORE_NUM_CORE_ELEMENT_PER_INST 16U -#define TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST 16U -#define TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST 16U +#define TH500_HWPM_IP_MCF_CORE_NUM_INSTANCES 8U +#define TH500_HWPM_IP_MCF_CORE_NUM_CORE_ELEMENT_PER_INST 2U +#define TH500_HWPM_IP_MCF_CORE_NUM_PERFMON_PER_INST 2U +#define TH500_HWPM_IP_MCF_CORE_NUM_PERFMUX_PER_INST 2U #define TH500_HWPM_IP_MCF_CORE_NUM_BROADCAST_PER_INST 1U extern struct hwpm_ip th500_hwpm_ip_mcf_core; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.c b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.c deleted file mode 100644 index 661bba8..0000000 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.c +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: MIT -/* - * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This is a generated file. Do not edit. - * - * Steps to regenerate: - * python3 ip_files_generator.py [] - */ - -#include "th500_mcf_iobhx.h" - -#include -#include -#include -#include - -static struct hwpm_ip_aperture th500_mcf_iobhx_inst0_perfmon_element_static_array[ - TH500_HWPM_IP_MCF_IOBHX_NUM_PERFMON_PER_INST] = { - { - .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(0), - .element_index = 0U, - .dt_mmio = NULL, - .name = "permon_mcfsoc0_iobhx", - .device_index = TH500_MCFSOC0_PERFMON_DEVICE_NODE_INDEX, - .start_abs_pa = addr_map_rpg_pm_mcfsoc0_base_r(), - .end_abs_pa = addr_map_rpg_pm_mcfsoc0_limit_r(), - .start_pa = addr_map_rpg_pm_mcfsoc0_base_r(), - .end_pa = addr_map_rpg_pm_mcfsoc0_limit_r(), - .base_pa = addr_map_rpg_pm_base_r(), - .alist = th500_perfmon_alist, - .alist_size = ARRAY_SIZE(th500_perfmon_alist), - .fake_registers = NULL, - }, -}; - -static struct hwpm_ip_aperture th500_mcf_iobhx_inst0_perfmux_element_static_array[ - TH500_HWPM_IP_MCF_IOBHX_NUM_PERFMUX_PER_INST] = { - { - .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(0), - .element_index = 17U, - .dt_mmio = NULL, - .name = {'\0'}, - .start_abs_pa = addr_map_mc16_base_r(), - .end_abs_pa = addr_map_mc16_limit_r(), - .start_pa = addr_map_mc16_base_r(), - .end_pa = addr_map_mc16_limit_r(), - .base_pa = 0ULL, - .alist = th500_mcf_iobhx_alist, - .alist_size = ARRAY_SIZE(th500_mcf_iobhx_alist), - .fake_registers = NULL, - }, -}; - -static struct hwpm_ip_aperture th500_mcf_iobhx_inst0_broadcast_element_static_array[ - TH500_HWPM_IP_MCF_IOBHX_NUM_BROADCAST_PER_INST] = { - { - .element_type = IP_ELEMENT_BROADCAST, - .element_index_mask = BIT(0), - .element_index = 0U, - .dt_mmio = NULL, - .name = {'\0'}, - .start_abs_pa = addr_map_mcb_base_r(), - .end_abs_pa = addr_map_mcb_limit_r(), - .start_pa = addr_map_mcb_base_r(), - .end_pa = addr_map_mcb_limit_r(), - .base_pa = 0ULL, - .alist = th500_mcf_iobhx_alist, - .alist_size = ARRAY_SIZE(th500_mcf_iobhx_alist), - .fake_registers = NULL, - }, -}; - -/* IP instance array */ -struct hwpm_ip_inst th500_mcf_iobhx_inst_static_array[ - TH500_HWPM_IP_MCF_IOBHX_NUM_INSTANCES] = { - { - .hw_inst_mask = BIT(0), - .num_core_elements_per_inst = - TH500_HWPM_IP_MCF_IOBHX_NUM_CORE_ELEMENT_PER_INST, - .element_info = { - /* - * Instance info corresponding to - * TEGRA_HWPM_APERTURE_TYPE_PERFMUX - */ - { - .num_element_per_inst = - TH500_HWPM_IP_MCF_IOBHX_NUM_PERFMUX_PER_INST, - .element_static_array = - th500_mcf_iobhx_inst0_perfmux_element_static_array, - /* NOTE: range should be in ascending order */ - .range_start = addr_map_mc16_base_r(), - .range_end = addr_map_mc16_limit_r(), - .element_stride = addr_map_mc16_limit_r() - - addr_map_mc16_base_r() + 1ULL, - .element_slots = 0U, - .element_arr = NULL, - }, - /* - * Instance info corresponding to - * TEGRA_HWPM_APERTURE_TYPE_BROADCAST - */ - { - .num_element_per_inst = - TH500_HWPM_IP_MCF_IOBHX_NUM_BROADCAST_PER_INST, - .element_static_array = - th500_mcf_iobhx_inst0_broadcast_element_static_array, - .range_start = addr_map_mcb_base_r(), - .range_end = addr_map_mcb_limit_r(), - .element_stride = addr_map_mcb_limit_r() - - addr_map_mcb_base_r() + 1ULL, - .element_slots = 0U, - .element_arr = NULL, - }, - /* - * Instance info corresponding to - * TEGRA_HWPM_APERTURE_TYPE_PERFMON - */ - { - .num_element_per_inst = - TH500_HWPM_IP_MCF_IOBHX_NUM_PERFMON_PER_INST, - .element_static_array = - th500_mcf_iobhx_inst0_perfmon_element_static_array, - .range_start = addr_map_rpg_pm_mcfsoc0_base_r(), - .range_end = addr_map_rpg_pm_mcfsoc0_limit_r(), - .element_stride = addr_map_rpg_pm_mcfsoc0_limit_r() - - addr_map_rpg_pm_mcfsoc0_base_r() + 1ULL, - .element_slots = 0U, - .element_arr = NULL, - }, - }, - - .ip_ops = { - .ip_dev = NULL, - .hwpm_ip_pm = NULL, - .hwpm_ip_reg_op = NULL, - .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, - }, - - .element_fs_mask = 0U, - .dev_name = "", - }, -}; - -/* IP structure */ -struct hwpm_ip th500_hwpm_ip_mcf_iobhx = { - .num_instances = TH500_HWPM_IP_MCF_IOBHX_NUM_INSTANCES, - .ip_inst_static_array = th500_mcf_iobhx_inst_static_array, - - .inst_aperture_info = { - /* - * Instance info corresponding to - * TEGRA_HWPM_APERTURE_TYPE_PERFMUX - */ - { - /* NOTE: range should be in ascending order */ - .range_start = addr_map_mc16_base_r(), - .range_end = addr_map_mc16_limit_r(), - .inst_stride = addr_map_mc16_limit_r() - - addr_map_mc16_base_r() + 1ULL, - .inst_slots = 0U, - .inst_arr = NULL, - }, - /* - * Instance info corresponding to - * TEGRA_HWPM_APERTURE_TYPE_BROADCAST - */ - { - .range_start = addr_map_mcb_base_r(), - .range_end = addr_map_mcb_limit_r(), - .inst_stride = addr_map_mcb_limit_r() - - addr_map_mcb_base_r() + 1ULL, - .inst_slots = 0U, - .inst_arr = NULL, - }, - /* - * Instance info corresponding to - * TEGRA_HWPM_APERTURE_TYPE_PERFMON - */ - { - .range_start = addr_map_rpg_pm_mcfsoc0_base_r(), - .range_end = addr_map_rpg_pm_mcfsoc0_limit_r(), - .inst_stride = addr_map_rpg_pm_mcfsoc0_limit_r() - - addr_map_rpg_pm_mcfsoc0_base_r() + 1ULL, - .inst_slots = 0U, - .inst_arr = NULL, - }, - }, - - .dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK, - .override_enable = false, - .inst_fs_mask = 0U, - .resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID, - .reserved = false, -}; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.h b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.h deleted file mode 100644 index e6327b7..0000000 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This is a generated file. Do not edit. - * - * Steps to regenerate: - * python3 ip_files_generator.py [] - */ - -#ifndef TH500_HWPM_IP_MCF_IOBHX_H -#define TH500_HWPM_IP_MCF_IOBHX_H - -#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX) -#define TH500_HWPM_ACTIVE_IP_MCF_IOBHX TH500_HWPM_IP_MCF_IOBHX, - -/* This data should ideally be available in HW headers */ -#define TH500_HWPM_IP_MCF_IOBHX_NUM_INSTANCES 1U -#define TH500_HWPM_IP_MCF_IOBHX_NUM_CORE_ELEMENT_PER_INST 1U -#define TH500_HWPM_IP_MCF_IOBHX_NUM_PERFMON_PER_INST 1U -#define TH500_HWPM_IP_MCF_IOBHX_NUM_PERFMUX_PER_INST 1U -#define TH500_HWPM_IP_MCF_IOBHX_NUM_BROADCAST_PER_INST 1U - -extern struct hwpm_ip th500_hwpm_ip_mcf_iobhx; - -#else -#define TH500_HWPM_ACTIVE_IP_MCF_IOBHX -#endif - -#endif /* TH500_HWPM_IP_MCF_IOBHX_H */ diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.c b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_soc/th500_mcf_soc.c similarity index 74% rename from drivers/tegra/hwpm/hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.c rename to drivers/tegra/hwpm/hal/th500/soc/ip/mcf_soc/th500_mcf_soc.c index 2dc4523..c0b664a 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.c +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_soc/th500_mcf_soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,21 +26,21 @@ * python3 ip_files_generator.py [] */ -#include "th500_mcf_ocu.h" +#include "th500_mcf_soc.h" #include #include #include #include -static struct hwpm_ip_aperture th500_mcf_ocu_inst0_perfmon_element_static_array[ - TH500_HWPM_IP_MCF_OCU_NUM_PERFMON_PER_INST] = { +static struct hwpm_ip_aperture th500_mcf_soc_inst0_perfmon_element_static_array[ + TH500_HWPM_IP_MCF_SOC_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, .element_index_mask = BIT(0), - .element_index = 0U, + .element_index = 1U, .dt_mmio = NULL, - .name = "permon_mcfsoc0_ocu", + .name = "permon_mcfsoc0_soc", .device_index = TH500_MCFSOC0_PERFMON_DEVICE_NODE_INDEX, .start_abs_pa = addr_map_rpg_pm_mcfsoc0_base_r(), .end_abs_pa = addr_map_rpg_pm_mcfsoc0_limit_r(), @@ -53,8 +53,8 @@ static struct hwpm_ip_aperture th500_mcf_ocu_inst0_perfmon_element_static_array[ }, }; -static struct hwpm_ip_aperture th500_mcf_ocu_inst0_perfmux_element_static_array[ - TH500_HWPM_IP_MCF_OCU_NUM_PERFMUX_PER_INST] = { +static struct hwpm_ip_aperture th500_mcf_soc_inst0_perfmux_element_static_array[ + TH500_HWPM_IP_MCF_SOC_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, .element_index_mask = BIT(0), @@ -66,8 +66,8 @@ static struct hwpm_ip_aperture th500_mcf_ocu_inst0_perfmux_element_static_array[ .start_pa = addr_map_mc0_base_r(), .end_pa = addr_map_mc0_limit_r(), .base_pa = 0ULL, - .alist = th500_mcf_ocu_alist, - .alist_size = ARRAY_SIZE(th500_mcf_ocu_alist), + .alist = th500_mcf_soc_alist, + .alist_size = ARRAY_SIZE(th500_mcf_soc_alist), .fake_registers = NULL, }, { @@ -81,8 +81,8 @@ static struct hwpm_ip_aperture th500_mcf_ocu_inst0_perfmux_element_static_array[ .start_pa = addr_map_mc1_base_r(), .end_pa = addr_map_mc1_limit_r(), .base_pa = 0ULL, - .alist = th500_mcf_ocu_alist, - .alist_size = ARRAY_SIZE(th500_mcf_ocu_alist), + .alist = th500_mcf_soc_alist, + .alist_size = ARRAY_SIZE(th500_mcf_soc_alist), .fake_registers = NULL, }, { @@ -96,14 +96,29 @@ static struct hwpm_ip_aperture th500_mcf_ocu_inst0_perfmux_element_static_array[ .start_pa = addr_map_mc2_base_r(), .end_pa = addr_map_mc2_limit_r(), .base_pa = 0ULL, - .alist = th500_mcf_ocu_alist, - .alist_size = ARRAY_SIZE(th500_mcf_ocu_alist), + .alist = th500_mcf_soc_alist, + .alist_size = ARRAY_SIZE(th500_mcf_soc_alist), + .fake_registers = NULL, + }, + { + .element_type = IP_ELEMENT_PERFMUX, + .element_index_mask = BIT(3), + .element_index = 4U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mc16_base_r(), + .end_abs_pa = addr_map_mc16_limit_r(), + .start_pa = addr_map_mc16_base_r(), + .end_pa = addr_map_mc16_limit_r(), + .base_pa = 0ULL, + .alist = th500_mcf_soc_alist, + .alist_size = ARRAY_SIZE(th500_mcf_soc_alist), .fake_registers = NULL, }, }; -static struct hwpm_ip_aperture th500_mcf_ocu_inst0_broadcast_element_static_array[ - TH500_HWPM_IP_MCF_OCU_NUM_BROADCAST_PER_INST] = { +static struct hwpm_ip_aperture th500_mcf_soc_inst0_broadcast_element_static_array[ + TH500_HWPM_IP_MCF_SOC_NUM_BROADCAST_PER_INST] = { { .element_type = IP_ELEMENT_BROADCAST, .element_index_mask = BIT(0), @@ -115,19 +130,19 @@ static struct hwpm_ip_aperture th500_mcf_ocu_inst0_broadcast_element_static_arra .start_pa = addr_map_mcb_base_r(), .end_pa = addr_map_mcb_limit_r(), .base_pa = 0ULL, - .alist = th500_mcf_ocu_alist, - .alist_size = ARRAY_SIZE(th500_mcf_ocu_alist), + .alist = th500_mcf_soc_alist, + .alist_size = ARRAY_SIZE(th500_mcf_soc_alist), .fake_registers = NULL, }, }; /* IP instance array */ -struct hwpm_ip_inst th500_mcf_ocu_inst_static_array[ - TH500_HWPM_IP_MCF_OCU_NUM_INSTANCES] = { +struct hwpm_ip_inst th500_mcf_soc_inst_static_array[ + TH500_HWPM_IP_MCF_SOC_NUM_INSTANCES] = { { .hw_inst_mask = BIT(0), .num_core_elements_per_inst = - TH500_HWPM_IP_MCF_OCU_NUM_CORE_ELEMENT_PER_INST, + TH500_HWPM_IP_MCF_SOC_NUM_CORE_ELEMENT_PER_INST, .element_info = { /* * Instance info corresponding to @@ -135,12 +150,12 @@ struct hwpm_ip_inst th500_mcf_ocu_inst_static_array[ */ { .num_element_per_inst = - TH500_HWPM_IP_MCF_OCU_NUM_PERFMUX_PER_INST, + TH500_HWPM_IP_MCF_SOC_NUM_PERFMUX_PER_INST, .element_static_array = - th500_mcf_ocu_inst0_perfmux_element_static_array, + th500_mcf_soc_inst0_perfmux_element_static_array, /* NOTE: range should be in ascending order */ .range_start = addr_map_mc0_base_r(), - .range_end = addr_map_mc2_limit_r(), + .range_end = addr_map_mc16_limit_r(), .element_stride = addr_map_mc0_limit_r() - addr_map_mc0_base_r() + 1ULL, .element_slots = 0U, @@ -152,9 +167,9 @@ struct hwpm_ip_inst th500_mcf_ocu_inst_static_array[ */ { .num_element_per_inst = - TH500_HWPM_IP_MCF_OCU_NUM_BROADCAST_PER_INST, + TH500_HWPM_IP_MCF_SOC_NUM_BROADCAST_PER_INST, .element_static_array = - th500_mcf_ocu_inst0_broadcast_element_static_array, + th500_mcf_soc_inst0_broadcast_element_static_array, .range_start = addr_map_mcb_base_r(), .range_end = addr_map_mcb_limit_r(), .element_stride = addr_map_mcb_limit_r() - @@ -168,9 +183,9 @@ struct hwpm_ip_inst th500_mcf_ocu_inst_static_array[ */ { .num_element_per_inst = - TH500_HWPM_IP_MCF_OCU_NUM_PERFMON_PER_INST, + TH500_HWPM_IP_MCF_SOC_NUM_PERFMON_PER_INST, .element_static_array = - th500_mcf_ocu_inst0_perfmon_element_static_array, + th500_mcf_soc_inst0_perfmon_element_static_array, .range_start = addr_map_rpg_pm_mcfsoc0_base_r(), .range_end = addr_map_rpg_pm_mcfsoc0_limit_r(), .element_stride = addr_map_rpg_pm_mcfsoc0_limit_r() - @@ -193,9 +208,9 @@ struct hwpm_ip_inst th500_mcf_ocu_inst_static_array[ }; /* IP structure */ -struct hwpm_ip th500_hwpm_ip_mcf_ocu = { - .num_instances = TH500_HWPM_IP_MCF_OCU_NUM_INSTANCES, - .ip_inst_static_array = th500_mcf_ocu_inst_static_array, +struct hwpm_ip th500_hwpm_ip_mcf_soc = { + .num_instances = TH500_HWPM_IP_MCF_SOC_NUM_INSTANCES, + .ip_inst_static_array = th500_mcf_soc_inst_static_array, .inst_aperture_info = { /* @@ -205,8 +220,8 @@ struct hwpm_ip th500_hwpm_ip_mcf_ocu = { { /* NOTE: range should be in ascending order */ .range_start = addr_map_mc0_base_r(), - .range_end = addr_map_mc2_limit_r(), - .inst_stride = addr_map_mc2_limit_r() - + .range_end = addr_map_mc16_limit_r(), + .inst_stride = addr_map_mc16_limit_r() - addr_map_mc0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.h b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_soc/th500_mcf_soc.h similarity index 67% rename from drivers/tegra/hwpm/hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.h rename to drivers/tegra/hwpm/hal/th500/soc/ip/mcf_soc/th500_mcf_soc.h index d2f61b2..42218a5 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.h +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mcf_soc/th500_mcf_soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,23 +26,23 @@ * python3 ip_files_generator.py [] */ -#ifndef TH500_HWPM_IP_MCF_OCU_H -#define TH500_HWPM_IP_MCF_OCU_H +#ifndef TH500_HWPM_IP_MCF_SOC_H +#define TH500_HWPM_IP_MCF_SOC_H -#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU) -#define TH500_HWPM_ACTIVE_IP_MCF_OCU TH500_HWPM_IP_MCF_OCU, +#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC) +#define TH500_HWPM_ACTIVE_IP_MCF_SOC TH500_HWPM_IP_MCF_SOC, /* This data should ideally be available in HW headers */ -#define TH500_HWPM_IP_MCF_OCU_NUM_INSTANCES 1U -#define TH500_HWPM_IP_MCF_OCU_NUM_CORE_ELEMENT_PER_INST 3U -#define TH500_HWPM_IP_MCF_OCU_NUM_PERFMON_PER_INST 1U -#define TH500_HWPM_IP_MCF_OCU_NUM_PERFMUX_PER_INST 3U -#define TH500_HWPM_IP_MCF_OCU_NUM_BROADCAST_PER_INST 1U +#define TH500_HWPM_IP_MCF_SOC_NUM_INSTANCES 1U +#define TH500_HWPM_IP_MCF_SOC_NUM_CORE_ELEMENT_PER_INST 4U +#define TH500_HWPM_IP_MCF_SOC_NUM_PERFMON_PER_INST 1U +#define TH500_HWPM_IP_MCF_SOC_NUM_PERFMUX_PER_INST 4U +#define TH500_HWPM_IP_MCF_SOC_NUM_BROADCAST_PER_INST 1U -extern struct hwpm_ip th500_hwpm_ip_mcf_ocu; +extern struct hwpm_ip th500_hwpm_ip_mcf_soc; #else -#define TH500_HWPM_ACTIVE_IP_MCF_OCU +#define TH500_HWPM_ACTIVE_IP_MCF_SOC #endif -#endif /* TH500_HWPM_IP_MCF_OCU_H */ +#endif /* TH500_HWPM_IP_MCF_SOC_H */ diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.c b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.c index 11801d1..cf5424c 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.c +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.c @@ -51,10 +51,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst1_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(1), - .element_index = 2U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parta1", .device_index = TH500_MSS_CHANNEL_PARTA1_PERFMON_DEVICE_NODE_INDEX, @@ -67,10 +71,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst2_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(2), - .element_index = 3U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parta2", .device_index = TH500_MSS_CHANNEL_PARTA2_PERFMON_DEVICE_NODE_INDEX, @@ -83,10 +91,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst3_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(3), - .element_index = 4U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parta3", .device_index = TH500_MSS_CHANNEL_PARTA3_PERFMON_DEVICE_NODE_INDEX, @@ -99,10 +111,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst4_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(4), - .element_index = 5U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partb0", .device_index = TH500_MSS_CHANNEL_PARTB0_PERFMON_DEVICE_NODE_INDEX, @@ -115,10 +131,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst5_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(5), - .element_index = 6U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partb1", .device_index = TH500_MSS_CHANNEL_PARTB1_PERFMON_DEVICE_NODE_INDEX, @@ -131,10 +151,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst6_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(6), - .element_index = 7U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partb2", .device_index = TH500_MSS_CHANNEL_PARTB2_PERFMON_DEVICE_NODE_INDEX, @@ -147,10 +171,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst7_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(7), - .element_index = 8U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partb3", .device_index = TH500_MSS_CHANNEL_PARTB3_PERFMON_DEVICE_NODE_INDEX, @@ -163,10 +191,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst8_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(8), - .element_index = 9U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partc0", .device_index = TH500_MSS_CHANNEL_PARTC0_PERFMON_DEVICE_NODE_INDEX, @@ -179,10 +211,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst9_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(9), - .element_index = 10U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partc1", .device_index = TH500_MSS_CHANNEL_PARTC1_PERFMON_DEVICE_NODE_INDEX, @@ -195,10 +231,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst10_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(10), - .element_index = 11U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partc2", .device_index = TH500_MSS_CHANNEL_PARTC2_PERFMON_DEVICE_NODE_INDEX, @@ -211,10 +251,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst11_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(11), - .element_index = 12U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partc3", .device_index = TH500_MSS_CHANNEL_PARTC3_PERFMON_DEVICE_NODE_INDEX, @@ -227,10 +271,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst12_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(12), - .element_index = 13U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partd0", .device_index = TH500_MSS_CHANNEL_PARTD0_PERFMON_DEVICE_NODE_INDEX, @@ -243,10 +291,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst13_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(13), - .element_index = 14U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partd1", .device_index = TH500_MSS_CHANNEL_PARTD1_PERFMON_DEVICE_NODE_INDEX, @@ -259,10 +311,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst14_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(14), - .element_index = 15U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partd2", .device_index = TH500_MSS_CHANNEL_PARTD2_PERFMON_DEVICE_NODE_INDEX, @@ -275,10 +331,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst15_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(15), - .element_index = 16U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partd3", .device_index = TH500_MSS_CHANNEL_PARTD3_PERFMON_DEVICE_NODE_INDEX, @@ -291,10 +351,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst16_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(16), - .element_index = 17U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parte0", .device_index = TH500_MSS_CHANNEL_PARTE0_PERFMON_DEVICE_NODE_INDEX, @@ -307,10 +371,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst17_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(17), - .element_index = 18U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parte1", .device_index = TH500_MSS_CHANNEL_PARTE1_PERFMON_DEVICE_NODE_INDEX, @@ -323,10 +391,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst18_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(18), - .element_index = 19U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parte2", .device_index = TH500_MSS_CHANNEL_PARTE2_PERFMON_DEVICE_NODE_INDEX, @@ -339,10 +411,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst19_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(19), - .element_index = 20U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parte3", .device_index = TH500_MSS_CHANNEL_PARTE3_PERFMON_DEVICE_NODE_INDEX, @@ -355,10 +431,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst20_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(20), - .element_index = 21U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partf0", .device_index = TH500_MSS_CHANNEL_PARTF0_PERFMON_DEVICE_NODE_INDEX, @@ -371,10 +451,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst21_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(21), - .element_index = 22U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partf1", .device_index = TH500_MSS_CHANNEL_PARTF1_PERFMON_DEVICE_NODE_INDEX, @@ -387,10 +471,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst22_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(22), - .element_index = 23U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partf2", .device_index = TH500_MSS_CHANNEL_PARTF2_PERFMON_DEVICE_NODE_INDEX, @@ -403,10 +491,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst23_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(23), - .element_index = 24U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partf3", .device_index = TH500_MSS_CHANNEL_PARTF3_PERFMON_DEVICE_NODE_INDEX, @@ -419,10 +511,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst24_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(24), - .element_index = 25U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partg0", .device_index = TH500_MSS_CHANNEL_PARTG0_PERFMON_DEVICE_NODE_INDEX, @@ -435,10 +531,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst25_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(25), - .element_index = 26U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partg1", .device_index = TH500_MSS_CHANNEL_PARTG1_PERFMON_DEVICE_NODE_INDEX, @@ -451,10 +551,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst26_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(26), - .element_index = 27U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partg2", .device_index = TH500_MSS_CHANNEL_PARTG2_PERFMON_DEVICE_NODE_INDEX, @@ -467,10 +571,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst27_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(27), - .element_index = 28U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_partg3", .device_index = TH500_MSS_CHANNEL_PARTG3_PERFMON_DEVICE_NODE_INDEX, @@ -483,10 +591,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst28_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(28), - .element_index = 29U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parth0", .device_index = TH500_MSS_CHANNEL_PARTH0_PERFMON_DEVICE_NODE_INDEX, @@ -499,10 +611,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst29_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(29), - .element_index = 30U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parth1", .device_index = TH500_MSS_CHANNEL_PARTH1_PERFMON_DEVICE_NODE_INDEX, @@ -515,10 +631,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst30_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(30), - .element_index = 31U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parth2", .device_index = TH500_MSS_CHANNEL_PARTH2_PERFMON_DEVICE_NODE_INDEX, @@ -531,10 +651,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmon_element_static_ar .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst31_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(31), - .element_index = 32U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msschannel_parth3", .device_index = TH500_MSS_CHANNEL_PARTH3_PERFMON_DEVICE_NODE_INDEX, @@ -566,10 +690,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst1_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(1), - .element_index = 2U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc1_base_r(), @@ -581,10 +709,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst2_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(2), - .element_index = 3U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc2_base_r(), @@ -596,10 +728,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst3_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(3), - .element_index = 4U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc3_base_r(), @@ -611,10 +747,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst4_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(4), - .element_index = 5U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc4_base_r(), @@ -626,10 +766,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst5_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(5), - .element_index = 6U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc5_base_r(), @@ -641,10 +785,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst6_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(6), - .element_index = 7U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc6_base_r(), @@ -656,10 +804,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst7_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(7), - .element_index = 8U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc7_base_r(), @@ -671,10 +823,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst8_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(8), - .element_index = 9U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc8_base_r(), @@ -686,10 +842,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst9_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(9), - .element_index = 10U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc9_base_r(), @@ -701,10 +861,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst10_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(10), - .element_index = 11U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc10_base_r(), @@ -716,10 +880,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst11_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(11), - .element_index = 12U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc11_base_r(), @@ -731,10 +899,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst12_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(12), - .element_index = 13U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc12_base_r(), @@ -746,10 +918,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst13_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(13), - .element_index = 14U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc13_base_r(), @@ -761,10 +937,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst14_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(14), - .element_index = 15U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc14_base_r(), @@ -776,10 +956,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst15_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(15), - .element_index = 16U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc15_base_r(), @@ -791,10 +975,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst16_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(16), - .element_index = 17U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc16_base_r(), @@ -806,10 +994,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst17_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(17), - .element_index = 18U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc17_base_r(), @@ -821,10 +1013,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst18_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(18), - .element_index = 19U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc18_base_r(), @@ -836,10 +1032,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst19_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(19), - .element_index = 20U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc19_base_r(), @@ -851,10 +1051,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst20_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(20), - .element_index = 21U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc20_base_r(), @@ -866,10 +1070,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst21_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(21), - .element_index = 22U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc21_base_r(), @@ -881,10 +1089,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst22_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(22), - .element_index = 23U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc22_base_r(), @@ -896,10 +1108,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst23_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(23), - .element_index = 24U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc23_base_r(), @@ -911,10 +1127,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst24_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(24), - .element_index = 25U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc24_base_r(), @@ -926,10 +1146,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst25_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(25), - .element_index = 26U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc25_base_r(), @@ -941,10 +1165,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst26_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(26), - .element_index = 27U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc26_base_r(), @@ -956,10 +1184,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst27_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(27), - .element_index = 28U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc27_base_r(), @@ -971,10 +1203,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst28_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(28), - .element_index = 29U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc28_base_r(), @@ -986,10 +1222,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst29_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(29), - .element_index = 30U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc29_base_r(), @@ -1001,10 +1241,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst30_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(30), - .element_index = 31U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc30_base_r(), @@ -1016,10 +1260,14 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_perfmux_element_static_ar .alist_size = ARRAY_SIZE(th500_mss_channel_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst31_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(31), - .element_index = 32U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc31_base_r(), @@ -1052,6 +1300,595 @@ static struct hwpm_ip_aperture th500_mss_channel_inst0_broadcast_element_static_ }, }; +static struct hwpm_ip_aperture th500_mss_channel_inst1_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst2_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst3_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst4_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst5_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst6_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst7_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst8_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst9_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst10_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst11_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst12_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst13_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst14_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst15_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst16_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst17_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst18_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst19_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst20_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst21_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst22_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst23_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst24_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst25_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst26_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst27_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst28_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst29_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst30_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_channel_inst31_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_channel_alist, + .alist_size = ARRAY_SIZE(th500_mss_channel_alist), + .fake_registers = NULL, + }, +}; + /* IP instance array */ struct hwpm_ip_inst th500_mss_channel_inst_static_array[ TH500_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES] = { @@ -1071,7 +1908,7 @@ struct hwpm_ip_inst th500_mss_channel_inst_static_array[ th500_mss_channel_inst0_perfmux_element_static_array, /* NOTE: range should be in ascending order */ .range_start = addr_map_mc0_base_r(), - .range_end = addr_map_mc31_limit_r(), + .range_end = addr_map_mc0_limit_r(), .element_stride = addr_map_mc0_limit_r() - addr_map_mc0_base_r() + 1ULL, .element_slots = 0U, @@ -1103,7 +1940,7 @@ struct hwpm_ip_inst th500_mss_channel_inst_static_array[ .element_static_array = th500_mss_channel_inst0_perfmon_element_static_array, .range_start = addr_map_rpg_pm_msschannel0_base_r(), - .range_end = addr_map_rpg_pm_msschannel31_limit_r(), + .range_end = addr_map_rpg_pm_msschannel0_limit_r(), .element_stride = addr_map_rpg_pm_msschannel0_limit_r() - addr_map_rpg_pm_msschannel0_base_r() + 1ULL, .element_slots = 0U, @@ -1118,6 +1955,2052 @@ struct hwpm_ip_inst th500_mss_channel_inst_static_array[ .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, }, + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(1), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst1_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc1_base_r(), + .range_end = addr_map_mc1_limit_r(), + .element_stride = addr_map_mc1_limit_r() - + addr_map_mc1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst1_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel1_base_r(), + .range_end = addr_map_rpg_pm_msschannel1_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel1_limit_r() - + addr_map_rpg_pm_msschannel1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(2), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst2_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc2_base_r(), + .range_end = addr_map_mc2_limit_r(), + .element_stride = addr_map_mc2_limit_r() - + addr_map_mc2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst2_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel2_base_r(), + .range_end = addr_map_rpg_pm_msschannel2_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel2_limit_r() - + addr_map_rpg_pm_msschannel2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(3), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst3_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc3_base_r(), + .range_end = addr_map_mc3_limit_r(), + .element_stride = addr_map_mc3_limit_r() - + addr_map_mc3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst3_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel3_base_r(), + .range_end = addr_map_rpg_pm_msschannel3_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel3_limit_r() - + addr_map_rpg_pm_msschannel3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(4), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst4_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc4_base_r(), + .range_end = addr_map_mc4_limit_r(), + .element_stride = addr_map_mc4_limit_r() - + addr_map_mc4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst4_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst4_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel4_base_r(), + .range_end = addr_map_rpg_pm_msschannel4_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel4_limit_r() - + addr_map_rpg_pm_msschannel4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(5), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst5_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc5_base_r(), + .range_end = addr_map_mc5_limit_r(), + .element_stride = addr_map_mc5_limit_r() - + addr_map_mc5_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst5_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst5_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel5_base_r(), + .range_end = addr_map_rpg_pm_msschannel5_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel5_limit_r() - + addr_map_rpg_pm_msschannel5_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(6), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst6_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc6_base_r(), + .range_end = addr_map_mc6_limit_r(), + .element_stride = addr_map_mc6_limit_r() - + addr_map_mc6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst6_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst6_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel6_base_r(), + .range_end = addr_map_rpg_pm_msschannel6_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel6_limit_r() - + addr_map_rpg_pm_msschannel6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(7), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst7_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc7_base_r(), + .range_end = addr_map_mc7_limit_r(), + .element_stride = addr_map_mc7_limit_r() - + addr_map_mc7_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst7_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst7_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel7_base_r(), + .range_end = addr_map_rpg_pm_msschannel7_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel7_limit_r() - + addr_map_rpg_pm_msschannel7_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(8), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst8_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc8_base_r(), + .range_end = addr_map_mc8_limit_r(), + .element_stride = addr_map_mc8_limit_r() - + addr_map_mc8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst8_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst8_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel8_base_r(), + .range_end = addr_map_rpg_pm_msschannel8_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel8_limit_r() - + addr_map_rpg_pm_msschannel8_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(9), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst9_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc9_base_r(), + .range_end = addr_map_mc9_limit_r(), + .element_stride = addr_map_mc9_limit_r() - + addr_map_mc9_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst9_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst9_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel9_base_r(), + .range_end = addr_map_rpg_pm_msschannel9_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel9_limit_r() - + addr_map_rpg_pm_msschannel9_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(10), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst10_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc10_base_r(), + .range_end = addr_map_mc10_limit_r(), + .element_stride = addr_map_mc10_limit_r() - + addr_map_mc10_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst10_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst10_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel10_base_r(), + .range_end = addr_map_rpg_pm_msschannel10_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel10_limit_r() - + addr_map_rpg_pm_msschannel10_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(11), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst11_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc11_base_r(), + .range_end = addr_map_mc11_limit_r(), + .element_stride = addr_map_mc11_limit_r() - + addr_map_mc11_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst11_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst11_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel11_base_r(), + .range_end = addr_map_rpg_pm_msschannel11_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel11_limit_r() - + addr_map_rpg_pm_msschannel11_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(12), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst12_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc12_base_r(), + .range_end = addr_map_mc12_limit_r(), + .element_stride = addr_map_mc12_limit_r() - + addr_map_mc12_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst12_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst12_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel12_base_r(), + .range_end = addr_map_rpg_pm_msschannel12_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel12_limit_r() - + addr_map_rpg_pm_msschannel12_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(13), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst13_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc13_base_r(), + .range_end = addr_map_mc13_limit_r(), + .element_stride = addr_map_mc13_limit_r() - + addr_map_mc13_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst13_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst13_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel13_base_r(), + .range_end = addr_map_rpg_pm_msschannel13_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel13_limit_r() - + addr_map_rpg_pm_msschannel13_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(14), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst14_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc14_base_r(), + .range_end = addr_map_mc14_limit_r(), + .element_stride = addr_map_mc14_limit_r() - + addr_map_mc14_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst14_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst14_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel14_base_r(), + .range_end = addr_map_rpg_pm_msschannel14_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel14_limit_r() - + addr_map_rpg_pm_msschannel14_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(15), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst15_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc15_base_r(), + .range_end = addr_map_mc15_limit_r(), + .element_stride = addr_map_mc15_limit_r() - + addr_map_mc15_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst15_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst15_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel15_base_r(), + .range_end = addr_map_rpg_pm_msschannel15_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel15_limit_r() - + addr_map_rpg_pm_msschannel15_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(16), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst16_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc16_base_r(), + .range_end = addr_map_mc16_limit_r(), + .element_stride = addr_map_mc16_limit_r() - + addr_map_mc16_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst16_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst16_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel16_base_r(), + .range_end = addr_map_rpg_pm_msschannel16_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel16_limit_r() - + addr_map_rpg_pm_msschannel16_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(17), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst17_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc17_base_r(), + .range_end = addr_map_mc17_limit_r(), + .element_stride = addr_map_mc17_limit_r() - + addr_map_mc17_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst17_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst17_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel17_base_r(), + .range_end = addr_map_rpg_pm_msschannel17_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel17_limit_r() - + addr_map_rpg_pm_msschannel17_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(18), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst18_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc18_base_r(), + .range_end = addr_map_mc18_limit_r(), + .element_stride = addr_map_mc18_limit_r() - + addr_map_mc18_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst18_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst18_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel18_base_r(), + .range_end = addr_map_rpg_pm_msschannel18_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel18_limit_r() - + addr_map_rpg_pm_msschannel18_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(19), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst19_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc19_base_r(), + .range_end = addr_map_mc19_limit_r(), + .element_stride = addr_map_mc19_limit_r() - + addr_map_mc19_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst19_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst19_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel19_base_r(), + .range_end = addr_map_rpg_pm_msschannel19_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel19_limit_r() - + addr_map_rpg_pm_msschannel19_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(20), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst20_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc20_base_r(), + .range_end = addr_map_mc20_limit_r(), + .element_stride = addr_map_mc20_limit_r() - + addr_map_mc20_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst20_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst20_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel20_base_r(), + .range_end = addr_map_rpg_pm_msschannel20_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel20_limit_r() - + addr_map_rpg_pm_msschannel20_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(21), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst21_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc21_base_r(), + .range_end = addr_map_mc21_limit_r(), + .element_stride = addr_map_mc21_limit_r() - + addr_map_mc21_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst21_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst21_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel21_base_r(), + .range_end = addr_map_rpg_pm_msschannel21_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel21_limit_r() - + addr_map_rpg_pm_msschannel21_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(22), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst22_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc22_base_r(), + .range_end = addr_map_mc22_limit_r(), + .element_stride = addr_map_mc22_limit_r() - + addr_map_mc22_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst22_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst22_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel22_base_r(), + .range_end = addr_map_rpg_pm_msschannel22_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel22_limit_r() - + addr_map_rpg_pm_msschannel22_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(23), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst23_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc23_base_r(), + .range_end = addr_map_mc23_limit_r(), + .element_stride = addr_map_mc23_limit_r() - + addr_map_mc23_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst23_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst23_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel23_base_r(), + .range_end = addr_map_rpg_pm_msschannel23_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel23_limit_r() - + addr_map_rpg_pm_msschannel23_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(24), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst24_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc24_base_r(), + .range_end = addr_map_mc24_limit_r(), + .element_stride = addr_map_mc24_limit_r() - + addr_map_mc24_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst24_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst24_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel24_base_r(), + .range_end = addr_map_rpg_pm_msschannel24_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel24_limit_r() - + addr_map_rpg_pm_msschannel24_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(25), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst25_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc25_base_r(), + .range_end = addr_map_mc25_limit_r(), + .element_stride = addr_map_mc25_limit_r() - + addr_map_mc25_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst25_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst25_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel25_base_r(), + .range_end = addr_map_rpg_pm_msschannel25_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel25_limit_r() - + addr_map_rpg_pm_msschannel25_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(26), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst26_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc26_base_r(), + .range_end = addr_map_mc26_limit_r(), + .element_stride = addr_map_mc26_limit_r() - + addr_map_mc26_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst26_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst26_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel26_base_r(), + .range_end = addr_map_rpg_pm_msschannel26_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel26_limit_r() - + addr_map_rpg_pm_msschannel26_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(27), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst27_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc27_base_r(), + .range_end = addr_map_mc27_limit_r(), + .element_stride = addr_map_mc27_limit_r() - + addr_map_mc27_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst27_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst27_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel27_base_r(), + .range_end = addr_map_rpg_pm_msschannel27_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel27_limit_r() - + addr_map_rpg_pm_msschannel27_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(28), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst28_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc28_base_r(), + .range_end = addr_map_mc28_limit_r(), + .element_stride = addr_map_mc28_limit_r() - + addr_map_mc28_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst28_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst28_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel28_base_r(), + .range_end = addr_map_rpg_pm_msschannel28_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel28_limit_r() - + addr_map_rpg_pm_msschannel28_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(29), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst29_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc29_base_r(), + .range_end = addr_map_mc29_limit_r(), + .element_stride = addr_map_mc29_limit_r() - + addr_map_mc29_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst29_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst29_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel29_base_r(), + .range_end = addr_map_rpg_pm_msschannel29_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel29_limit_r() - + addr_map_rpg_pm_msschannel29_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(30), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst30_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc30_base_r(), + .range_end = addr_map_mc30_limit_r(), + .element_stride = addr_map_mc30_limit_r() - + addr_map_mc30_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst30_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst30_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel30_base_r(), + .range_end = addr_map_rpg_pm_msschannel30_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel30_limit_r() - + addr_map_rpg_pm_msschannel30_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(31), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_channel_inst31_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc31_base_r(), + .range_end = addr_map_mc31_limit_r(), + .element_stride = addr_map_mc31_limit_r() - + addr_map_mc31_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_channel_inst31_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_channel_inst31_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msschannel31_base_r(), + .range_end = addr_map_rpg_pm_msschannel31_limit_r(), + .element_stride = addr_map_rpg_pm_msschannel31_limit_r() - + addr_map_rpg_pm_msschannel31_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + .element_fs_mask = 0U, .dev_name = "", }, @@ -1137,7 +4020,7 @@ struct hwpm_ip th500_hwpm_ip_mss_channel = { /* NOTE: range should be in ascending order */ .range_start = addr_map_mc0_base_r(), .range_end = addr_map_mc31_limit_r(), - .inst_stride = addr_map_mc31_limit_r() - + .inst_stride = addr_map_mc0_limit_r() - addr_map_mc0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, @@ -1161,7 +4044,7 @@ struct hwpm_ip th500_hwpm_ip_mss_channel = { { .range_start = addr_map_rpg_pm_msschannel0_base_r(), .range_end = addr_map_rpg_pm_msschannel31_limit_r(), - .inst_stride = addr_map_rpg_pm_msschannel31_limit_r() - + .inst_stride = addr_map_rpg_pm_msschannel0_limit_r() - addr_map_rpg_pm_msschannel0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.h b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.h index e1bc5c2..7108695 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.h +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_channel/th500_mss_channel.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,10 +33,10 @@ #define TH500_HWPM_ACTIVE_IP_MSS_CHANNEL TH500_HWPM_IP_MSS_CHANNEL, /* This data should ideally be available in HW headers */ -#define TH500_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES 1U -#define TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST 32U -#define TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST 32U -#define TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST 32U +#define TH500_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES 32U +#define TH500_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST 1U +#define TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST 1U +#define TH500_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST 1U #define TH500_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST 1U extern struct hwpm_ip th500_hwpm_ip_mss_channel; diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c index 754c86b..a71ff08 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.c @@ -38,7 +38,7 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[ { .element_type = HWPM_ELEMENT_PERFMON, .element_index_mask = BIT(0), - .element_index = 0U, + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msshub0", .device_index = TH500_MSSHUB0_PERFMON_DEVICE_NODE_INDEX, @@ -51,9 +51,13 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[ .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst1_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(1), + .element_index_mask = BIT(0), .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msshub1", @@ -67,10 +71,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[ .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst2_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(2), - .element_index = 2U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msshub2", .device_index = TH500_MSSHUB2_PERFMON_DEVICE_NODE_INDEX, @@ -83,10 +91,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[ .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst3_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(3), - .element_index = 3U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msshub3", .device_index = TH500_MSSHUB3_PERFMON_DEVICE_NODE_INDEX, @@ -99,10 +111,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[ .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst4_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(4), - .element_index = 4U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msshub4", .device_index = TH500_MSSHUB4_PERFMON_DEVICE_NODE_INDEX, @@ -115,10 +131,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[ .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst5_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(5), - .element_index = 5U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msshub5", .device_index = TH500_MSSHUB5_PERFMON_DEVICE_NODE_INDEX, @@ -131,10 +151,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[ .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst6_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(6), - .element_index = 6U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msshub6", .device_index = TH500_MSSHUB6_PERFMON_DEVICE_NODE_INDEX, @@ -147,10 +171,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmon_element_static_array[ .alist_size = ARRAY_SIZE(th500_perfmon_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst7_perfmon_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST] = { { .element_type = HWPM_ELEMENT_PERFMON, - .element_index_mask = BIT(7), - .element_index = 7U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = "perfmon_msshub7", .device_index = TH500_MSSHUB7_PERFMON_DEVICE_NODE_INDEX, @@ -182,10 +210,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmux_element_static_array[ .alist_size = ARRAY_SIZE(th500_mss_hub_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst1_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(1), - .element_index = 2U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc1_base_r(), @@ -197,10 +229,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmux_element_static_array[ .alist_size = ARRAY_SIZE(th500_mss_hub_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst2_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(2), - .element_index = 3U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc2_base_r(), @@ -212,10 +248,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmux_element_static_array[ .alist_size = ARRAY_SIZE(th500_mss_hub_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst3_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(3), - .element_index = 4U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc3_base_r(), @@ -227,10 +267,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmux_element_static_array[ .alist_size = ARRAY_SIZE(th500_mss_hub_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst4_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(4), - .element_index = 5U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc4_base_r(), @@ -242,10 +286,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmux_element_static_array[ .alist_size = ARRAY_SIZE(th500_mss_hub_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst5_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(5), - .element_index = 6U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc5_base_r(), @@ -257,10 +305,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmux_element_static_array[ .alist_size = ARRAY_SIZE(th500_mss_hub_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst6_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(6), - .element_index = 7U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc6_base_r(), @@ -272,10 +324,14 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_perfmux_element_static_array[ .alist_size = ARRAY_SIZE(th500_mss_hub_alist), .fake_registers = NULL, }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst7_perfmux_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST] = { { .element_type = IP_ELEMENT_PERFMUX, - .element_index_mask = BIT(7), - .element_index = 8U, + .element_index_mask = BIT(0), + .element_index = 1U, .dt_mmio = NULL, .name = {'\0'}, .start_abs_pa = addr_map_mc7_base_r(), @@ -308,6 +364,139 @@ static struct hwpm_ip_aperture th500_mss_hub_inst0_broadcast_element_static_arra }, }; +static struct hwpm_ip_aperture th500_mss_hub_inst1_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst2_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst3_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst4_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst5_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst6_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, +}; + +static struct hwpm_ip_aperture th500_mss_hub_inst7_broadcast_element_static_array[ + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST] = { + { + .element_type = IP_ELEMENT_BROADCAST, + .element_index_mask = BIT(0), + .element_index = 0U, + .dt_mmio = NULL, + .name = {'\0'}, + .start_abs_pa = addr_map_mcb_base_r(), + .end_abs_pa = addr_map_mcb_limit_r(), + .start_pa = addr_map_mcb_base_r(), + .end_pa = addr_map_mcb_limit_r(), + .base_pa = 0ULL, + .alist = th500_mss_hub_alist, + .alist_size = ARRAY_SIZE(th500_mss_hub_alist), + .fake_registers = NULL, + }, +}; + /* IP instance array */ struct hwpm_ip_inst th500_mss_hub_inst_static_array[ TH500_HWPM_IP_MSS_HUB_NUM_INSTANCES] = { @@ -327,7 +516,7 @@ struct hwpm_ip_inst th500_mss_hub_inst_static_array[ th500_mss_hub_inst0_perfmux_element_static_array, /* NOTE: range should be in ascending order */ .range_start = addr_map_mc0_base_r(), - .range_end = addr_map_mc7_limit_r(), + .range_end = addr_map_mc0_limit_r(), .element_stride = addr_map_mc0_limit_r() - addr_map_mc0_base_r() + 1ULL, .element_slots = 0U, @@ -359,7 +548,7 @@ struct hwpm_ip_inst th500_mss_hub_inst_static_array[ .element_static_array = th500_mss_hub_inst0_perfmon_element_static_array, .range_start = addr_map_rpg_pm_msshub0_base_r(), - .range_end = addr_map_rpg_pm_msshub7_limit_r(), + .range_end = addr_map_rpg_pm_msshub0_limit_r(), .element_stride = addr_map_rpg_pm_msshub0_limit_r() - addr_map_rpg_pm_msshub0_base_r() + 1ULL, .element_slots = 0U, @@ -374,6 +563,468 @@ struct hwpm_ip_inst th500_mss_hub_inst_static_array[ .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, }, + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(1), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_hub_inst1_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc1_base_r(), + .range_end = addr_map_mc1_limit_r(), + .element_stride = addr_map_mc1_limit_r() - + addr_map_mc1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_hub_inst1_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_hub_inst1_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msshub1_base_r(), + .range_end = addr_map_rpg_pm_msshub1_limit_r(), + .element_stride = addr_map_rpg_pm_msshub1_limit_r() - + addr_map_rpg_pm_msshub1_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(2), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_hub_inst2_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc2_base_r(), + .range_end = addr_map_mc2_limit_r(), + .element_stride = addr_map_mc2_limit_r() - + addr_map_mc2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_hub_inst2_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_hub_inst2_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msshub2_base_r(), + .range_end = addr_map_rpg_pm_msshub2_limit_r(), + .element_stride = addr_map_rpg_pm_msshub2_limit_r() - + addr_map_rpg_pm_msshub2_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(3), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_hub_inst3_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc3_base_r(), + .range_end = addr_map_mc3_limit_r(), + .element_stride = addr_map_mc3_limit_r() - + addr_map_mc3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_hub_inst3_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_hub_inst3_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msshub3_base_r(), + .range_end = addr_map_rpg_pm_msshub3_limit_r(), + .element_stride = addr_map_rpg_pm_msshub3_limit_r() - + addr_map_rpg_pm_msshub3_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(4), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_hub_inst4_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc4_base_r(), + .range_end = addr_map_mc4_limit_r(), + .element_stride = addr_map_mc4_limit_r() - + addr_map_mc4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_hub_inst4_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_hub_inst4_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msshub4_base_r(), + .range_end = addr_map_rpg_pm_msshub4_limit_r(), + .element_stride = addr_map_rpg_pm_msshub4_limit_r() - + addr_map_rpg_pm_msshub4_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(5), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_hub_inst5_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc5_base_r(), + .range_end = addr_map_mc5_limit_r(), + .element_stride = addr_map_mc5_limit_r() - + addr_map_mc5_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_hub_inst5_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_hub_inst5_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msshub5_base_r(), + .range_end = addr_map_rpg_pm_msshub5_limit_r(), + .element_stride = addr_map_rpg_pm_msshub5_limit_r() - + addr_map_rpg_pm_msshub5_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(6), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_hub_inst6_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc6_base_r(), + .range_end = addr_map_mc6_limit_r(), + .element_stride = addr_map_mc6_limit_r() - + addr_map_mc6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_hub_inst6_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_hub_inst6_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msshub6_base_r(), + .range_end = addr_map_rpg_pm_msshub6_limit_r(), + .element_stride = addr_map_rpg_pm_msshub6_limit_r() - + addr_map_rpg_pm_msshub6_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + + .element_fs_mask = 0U, + .dev_name = "", + }, + { + .hw_inst_mask = BIT(7), + .num_core_elements_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST, + .element_info = { + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMUX + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST, + .element_static_array = + th500_mss_hub_inst7_perfmux_element_static_array, + /* NOTE: range should be in ascending order */ + .range_start = addr_map_mc7_base_r(), + .range_end = addr_map_mc7_limit_r(), + .element_stride = addr_map_mc7_limit_r() - + addr_map_mc7_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_BROADCAST + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST, + .element_static_array = + th500_mss_hub_inst7_broadcast_element_static_array, + .range_start = addr_map_mcb_base_r(), + .range_end = addr_map_mcb_limit_r(), + .element_stride = addr_map_mcb_limit_r() - + addr_map_mcb_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + /* + * Instance info corresponding to + * TEGRA_HWPM_APERTURE_TYPE_PERFMON + */ + { + .num_element_per_inst = + TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST, + .element_static_array = + th500_mss_hub_inst7_perfmon_element_static_array, + .range_start = addr_map_rpg_pm_msshub7_base_r(), + .range_end = addr_map_rpg_pm_msshub7_limit_r(), + .element_stride = addr_map_rpg_pm_msshub7_limit_r() - + addr_map_rpg_pm_msshub7_base_r() + 1ULL, + .element_slots = 0U, + .element_arr = NULL, + }, + }, + + .ip_ops = { + .ip_dev = NULL, + .hwpm_ip_pm = NULL, + .hwpm_ip_reg_op = NULL, + .fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID, + }, + .element_fs_mask = 0U, .dev_name = "", }, @@ -393,7 +1044,7 @@ struct hwpm_ip th500_hwpm_ip_mss_hub = { /* NOTE: range should be in ascending order */ .range_start = addr_map_mc0_base_r(), .range_end = addr_map_mc7_limit_r(), - .inst_stride = addr_map_mc7_limit_r() - + .inst_stride = addr_map_mc0_limit_r() - addr_map_mc0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, @@ -417,7 +1068,7 @@ struct hwpm_ip th500_hwpm_ip_mss_hub = { { .range_start = addr_map_rpg_pm_msshub0_base_r(), .range_end = addr_map_rpg_pm_msshub7_limit_r(), - .inst_stride = addr_map_rpg_pm_msshub7_limit_r() - + .inst_stride = addr_map_rpg_pm_msshub0_limit_r() - addr_map_rpg_pm_msshub0_base_r() + 1ULL, .inst_slots = 0U, .inst_arr = NULL, diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.h b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.h index 9857add..cf9de74 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.h +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/mss_hub/th500_mss_hub.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,10 +33,10 @@ #define TH500_HWPM_ACTIVE_IP_MSS_HUB TH500_HWPM_IP_MSS_HUB, /* This data should ideally be available in HW headers */ -#define TH500_HWPM_IP_MSS_HUB_NUM_INSTANCES 1U -#define TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST 8U -#define TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST 8U -#define TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST 8U +#define TH500_HWPM_IP_MSS_HUB_NUM_INSTANCES 8U +#define TH500_HWPM_IP_MSS_HUB_NUM_CORE_ELEMENT_PER_INST 1U +#define TH500_HWPM_IP_MSS_HUB_NUM_PERFMON_PER_INST 1U +#define TH500_HWPM_IP_MSS_HUB_NUM_PERFMUX_PER_INST 1U #define TH500_HWPM_IP_MSS_HUB_NUM_BROADCAST_PER_INST 1U extern struct hwpm_ip th500_hwpm_ip_mss_hub; diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c index ee58559..0e3d236 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c @@ -209,59 +209,14 @@ struct allowlist th500_smmu_alist[1] = { {0x00005000, false}, }; -struct allowlist th500_c2c_alist[52] = { - {0x00000028, false}, - {0x00001028, false}, - {0x000020ec, false}, - {0x000020f0, false}, - {0x000020f4, false}, - {0x000020f8, false}, - {0x000020fc, false}, - {0x000030ec, false}, - {0x000030f0, false}, - {0x000030f4, false}, - {0x000030f8, false}, - {0x000030fc, false}, - {0x000040ec, false}, - {0x000040f0, false}, - {0x000040f4, false}, - {0x000040f8, false}, - {0x000040fc, false}, - {0x000050ec, false}, - {0x000050f0, false}, - {0x000050f4, false}, - {0x000050f8, false}, - {0x000050fc, false}, - {0x000060ec, false}, - {0x000060f0, false}, - {0x000060f4, false}, - {0x000060f8, false}, - {0x000060fc, false}, - {0x000070ec, false}, - {0x000070f0, false}, - {0x000070f4, false}, - {0x000070f8, false}, - {0x000070fc, false}, - {0x000080ec, false}, - {0x000080f0, false}, - {0x000080f4, false}, - {0x000080f8, false}, - {0x000080fc, false}, - {0x000090ec, false}, - {0x000090f0, false}, - {0x000090f4, false}, - {0x000090f8, false}, - {0x000090fc, false}, - {0x0000a0ec, false}, - {0x0000a0f0, false}, - {0x0000a0f4, false}, - {0x0000a0f8, false}, - {0x0000a0fc, false}, - {0x0000b0ec, false}, - {0x0000b0f0, false}, - {0x0000b0f4, false}, - {0x0000b0f8, false}, - {0x0000b0fc, false}, +struct allowlist th500_c2c_alist[5] = { + /* Disable C2CS0 and C2CS1 -- Broadcast apertures for now. See Bug 4411532 */ + /* {0x00000028, false}, */ + {0x000000ec, false}, + {0x000000f0, false}, + {0x000000f4, false}, + {0x000000f8, false}, + {0x000000fc, false}, }; struct allowlist th500_pcie_xtlq_alist[1] = { @@ -292,16 +247,14 @@ struct allowlist th500_mcf_clink_alist[3] = { {0x0000e430, false}, }; -struct allowlist th500_mcf_c2c_alist[2] = { +struct allowlist th500_mcf_c2c_alist[3] = { {0x0000d608, false}, {0x0000d60c, false}, + {0x0000e430, false}, }; -struct allowlist th500_mcf_ocu_alist[1] = { +struct allowlist th500_mcf_soc_alist[3] = { {0x0000d620, false}, -}; - -struct allowlist th500_mcf_iobhx_alist[2] = { {0x0000d618, false}, {0x0000d61c, false}, }; diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h index e21f803..9142be5 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h @@ -34,16 +34,15 @@ extern struct allowlist th500_nvlrx_alist[5]; extern struct allowlist th500_nvltx_alist[3]; extern struct allowlist th500_nvlctrl_alist[2]; extern struct allowlist th500_smmu_alist[1]; -extern struct allowlist th500_c2c_alist[52]; +extern struct allowlist th500_c2c_alist[5]; extern struct allowlist th500_pcie_xtlq_alist[1]; extern struct allowlist th500_pcie_xtlrc_alist[1]; extern struct allowlist th500_pcie_xalrc_alist[1]; extern struct allowlist th500_mss_channel_alist[2]; extern struct allowlist th500_mcf_core_alist[2]; extern struct allowlist th500_mcf_clink_alist[3]; -extern struct allowlist th500_mcf_c2c_alist[2]; -extern struct allowlist th500_mcf_ocu_alist[1]; -extern struct allowlist th500_mcf_iobhx_alist[2]; +extern struct allowlist th500_mcf_c2c_alist[3]; +extern struct allowlist th500_mcf_soc_alist[3]; extern struct allowlist th500_mss_hub_alist[3]; extern struct allowlist th500_cl2_alist[4]; diff --git a/drivers/tegra/hwpm/hal/th500/th500_interface.c b/drivers/tegra/hwpm/hal/th500/th500_interface.c index 64f531e..9fb1fcb 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_interface.c +++ b/drivers/tegra/hwpm/hal/th500/th500_interface.c @@ -149,14 +149,9 @@ bool th500_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm, config_ip = TH500_HWPM_IP_MCF_C2C; break; #endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU) - case TEGRA_HWPM_IP_MCF_OCU: - config_ip = TH500_HWPM_IP_MCF_OCU; - break; -#endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX) - case TEGRA_HWPM_IP_MCF_IOBHX: - config_ip = TH500_HWPM_IP_MCF_IOBHX; +#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC) + case TEGRA_HWPM_IP_MCF_SOC: + config_ip = TH500_HWPM_IP_MCF_SOC; break; #endif #if defined(CONFIG_TH500_HWPM_IP_SMMU) @@ -237,14 +232,9 @@ bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm, config_ip = TH500_HWPM_IP_MCF_C2C; break; #endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU) - case TEGRA_HWPM_RESOURCE_MCF_OCU: - config_ip = TH500_HWPM_IP_MCF_OCU; - break; -#endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX) - case TEGRA_HWPM_RESOURCE_MCF_IOBHX: - config_ip = TH500_HWPM_IP_MCF_IOBHX; +#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC) + case TEGRA_HWPM_RESOURCE_MCF_SOC: + config_ip = TH500_HWPM_IP_MCF_SOC; break; #endif #if defined(CONFIG_TH500_HWPM_IP_SMMU) @@ -344,13 +334,9 @@ int th500_hwpm_init_chip_info(struct tegra_soc_hwpm *hwpm) th500_active_ip_info[TH500_HWPM_IP_MCF_C2C] = &th500_hwpm_ip_mcf_c2c; #endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU) - th500_active_ip_info[TH500_HWPM_IP_MCF_OCU] = - &th500_hwpm_ip_mcf_ocu; -#endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX) - th500_active_ip_info[TH500_HWPM_IP_MCF_IOBHX] = - &th500_hwpm_ip_mcf_iobhx; +#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC) + th500_active_ip_info[TH500_HWPM_IP_MCF_SOC] = + &th500_hwpm_ip_mcf_soc; #endif #if defined(CONFIG_TH500_HWPM_IP_SMMU) th500_active_ip_info[TH500_HWPM_IP_SMMU] = &th500_hwpm_ip_smmu; diff --git a/drivers/tegra/hwpm/hal/th500/th500_internal.h b/drivers/tegra/hwpm/hal/th500/th500_internal.h index e6859eb..ef23c98 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_internal.h +++ b/drivers/tegra/hwpm/hal/th500/th500_internal.h @@ -33,8 +33,7 @@ #include #include #include -#include -#include +#include #include #include #include @@ -56,8 +55,7 @@ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLRX) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLTX) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_HUB) \ - DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_OCU) \ - DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_IOBHX) \ + DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_SOC) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_CLINK) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_CORE) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XTLQ) \ diff --git a/drivers/tegra/hwpm/hal/th500/th500_ip.c b/drivers/tegra/hwpm/hal/th500/th500_ip.c index ee6410d..87d7395 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_ip.c +++ b/drivers/tegra/hwpm/hal/th500/th500_ip.c @@ -20,6 +20,8 @@ * DEALINGS IN THE SOFTWARE. */ +#include +#include #include #include #include @@ -31,6 +33,82 @@ #include #include +/* + * Optional module parameters + */ +#ifdef CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE +/* This is a WAR on TH500 */ +int validate_current_config = 1; +module_param(validate_current_config, int, 0660); + +/* + * IP software masks to be used for force-enablement. + * 0x0 means "do not force-enable". These are meant to be + * a stop-gap measure until either we have ability to + * decide these based on fuses or they have IP drivers. + */ +long nvlctrl_mask; +module_param(nvlctrl_mask, long, 0660); + +long nvlrx_mask; +module_param(nvlrx_mask, long, 0660); + +long nvltx_mask; +module_param(nvltx_mask, long, 0660); + +long c2c_mask; +module_param(c2c_mask, long, 0660); + +long cl2_mask; +module_param(cl2_mask, long, 0660); + +long mcf_c2c_mask; +module_param(mcf_c2c_mask, long, 0660); + +long mcf_clink_mask; +module_param(mcf_clink_mask, long, 0660); + +long mcf_core_mask; +module_param(mcf_core_mask, long, 0660); + +long mcf_soc_mask; +module_param(mcf_soc_mask, long, 0660); + +long mss_channel_mask; +module_param(mss_channel_mask, long, 0660); + +long mss_hub_mask; +module_param(mss_hub_mask, long, 0660); + +long pcie_mask; +module_param(pcie_mask, long, 0660); + +long smmu_mask; +module_param(smmu_mask, long, 0660); + +/* Socket number */ +int socket_number; +/* + * The socket number must be 0, 1, 2, or 3. + */ +static int set_socket_number(const char *val, const struct kernel_param *kp) +{ + int socket_num = 0, ret; + + ret = kstrtoint(val, 10, &socket_num); + if (ret != 0 || socket_num < 0 || socket_num > 3) + return -EINVAL; + + return param_set_int(val, kp); +} + +static const struct kernel_param_ops param_ops = { + .set = set_socket_number, + .get = param_get_int, +}; +module_param_cb(socket, ¶m_ops, &socket_number, 0664); +#endif /* CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE */ + /* * This function is invoked by register_ip API. * Convert the external resource enum to internal IP index. @@ -106,13 +184,10 @@ int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, case TH500_HWPM_IP_MCF_CLINK: #endif #if defined(CONFIG_TH500_HWPM_IP_MCF_C2C) - case TH500_HWPM_IP_MCF_C2C: + case TH500_HWPM_IP_MCF_C2C: #endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU) - case TH500_HWPM_IP_MCF_OCU: -#endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX) - case TH500_HWPM_IP_MCF_IOBHX: +#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC) + case TH500_HWPM_IP_MCF_SOC: #endif /* * MSS channel, MCF CORE, MCF CLINK, MCF C2C, MCF SOC, @@ -211,32 +286,9 @@ int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, ret = 0; } #endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU) - /* Check base address in TH500_HWPM_IP_MCF_OCU */ - ip_idx = TH500_HWPM_IP_MCF_OCU; - ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops, - base_address, ip_idx, available); - if (ret != 0) { - /* - * Return value of ENODEV will indicate that the base - * address doesn't belong to this IP. - * This case is valid, as not all base addresses are - * shared between MSS IPs. - * In this case, reset return value to 0. - */ - if (ret != -ENODEV) { - tegra_hwpm_err(hwpm, - "IP %d base 0x%llx:Failed to %s fs/ops", - ip_idx, base_address, - available == true ? "set" : "reset"); - goto fail; - } - ret = 0; - } -#endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX) - /* Check base address in TH500_HWPM_IP_MCF_IOBHX */ - ip_idx = TH500_HWPM_IP_MCF_IOBHX; +#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC) + /* Check base address in TH500_HWPM_IP_MCF_SOC */ + ip_idx = TH500_HWPM_IP_MCF_SOC; ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops, base_address, ip_idx, available); if (ret != 0) { @@ -384,13 +436,19 @@ int th500_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm) int err; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct hwpm_ip *chip_ip = NULL; - extern int validate_current_config; tegra_hwpm_fn(hwpm, " "); - if (!tegra_hwpm_is_platform_silicon() || validate_current_config == 0) { +#ifdef CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE + extern int validate_current_config; + + + if (validate_current_config != 0) + return 0; +#endif + + if (!tegra_hwpm_is_platform_silicon()) return 0; - } err = th500_hwpm_validate_emc_config(hwpm); if (err != 0) { @@ -493,26 +551,30 @@ int th500_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm) return 0; } +/* + * This routine force enables IPs in TH500 chip. Many of the IPs in TH500 do + * not have any IP drivers. Therefore, there is no natural way for them to be + * enabled for performance monitoring. The approach taken here is to provide + * module parameters for this driver, such that when the driver is loaded, the + * user can provide bitmasks for the IPs she wants to enable. For example, to + * enable PCI-E controllers 0 and 1, she could provide the module parameter + * pcie_mask=0x3. The valid range of mask values depends on each IP. + * + * Linux has two ways to provide module parameters: (1) On the command line at + * 'insmod' time, or (2) via /etc/modprobe.d/nvhwpm.conf file. + * + * The following routine simply examples each mask and force enables the IP by + * calling tegra_hwpm_set_fs_info_ip_ops(). The complicated looking data + * structures in this routine are just convenience structures that permit + * looping over all IPs vs. writing custom code for each IP separately. + */ int th500_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) { + int err = 0; + + tegra_hwpm_fn(hwpm, " "); + #if defined(CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE) - extern int socket_number; - - extern long int nvlctrl_mask; - extern long int nvlrx_mask; - extern long int nvltx_mask; - extern long int c2c_mask; - extern long int cl2_mask; - extern long int mcf_c2c_mask; - extern long int mcf_clink_mask; - extern long int mcf_core_mask; - extern long int mcf_iobhx_mask; - extern long int mcf_ocu_mask; - extern long int mss_hub_mask; - extern long int mss_channel_mask; - extern long int pcie_mask; - extern long int smmu_mask; - extern struct hwpm_ip_inst th500_nvlctrl_inst_static_array[]; extern struct hwpm_ip_inst th500_nvlrx_inst_static_array[]; extern struct hwpm_ip_inst th500_nvltx_inst_static_array[]; @@ -521,23 +583,16 @@ int th500_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) extern struct hwpm_ip_inst th500_mcf_c2c_inst_static_array[]; extern struct hwpm_ip_inst th500_mcf_clink_inst_static_array[]; extern struct hwpm_ip_inst th500_mcf_core_inst_static_array[]; - extern struct hwpm_ip_inst th500_mcf_iobhx_inst_static_array[]; - extern struct hwpm_ip_inst th500_mcf_ocu_inst_static_array[]; + extern struct hwpm_ip_inst th500_mcf_soc_inst_static_array[]; extern struct hwpm_ip_inst th500_mss_hub_inst_static_array[]; extern struct hwpm_ip_inst th500_mss_channel_inst_static_array[]; extern struct hwpm_ip_inst th500_pcie_xalrc_inst_static_array[]; extern struct hwpm_ip_inst th500_pcie_xtlrc_inst_static_array[]; extern struct hwpm_ip_inst th500_pcie_xtlq_inst_static_array[]; extern struct hwpm_ip_inst th500_smmu_inst_static_array[]; -#endif /* CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE */ - - int err = 0; - -#if defined(CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE) int ret = 0; int ip, inst; - const u32 socket_shift = 44; /* bits */ - u64 socket_offset, base_addr; + u64 base_addr; struct hwpm_ip_inst *ip_inst = NULL; struct hwpm_ip_element_info *elem_info = NULL; @@ -570,11 +625,8 @@ int th500_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) #if defined(CONFIG_TH500_HWPM_IP_MCF_CORE) {"mcf_core", mcf_core_mask, TH500_HWPM_IP_MCF_CORE, TH500_HWPM_IP_MCF_CORE_NUM_INSTANCES, th500_mcf_core_inst_static_array}, #endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX) - {"mcf_iobhx", mcf_iobhx_mask, TH500_HWPM_IP_MCF_IOBHX, TH500_HWPM_IP_MCF_IOBHX_NUM_INSTANCES, th500_mcf_iobhx_inst_static_array}, -#endif -#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU) - {"mcf_ocu", mcf_ocu_mask, TH500_HWPM_IP_MCF_OCU, TH500_HWPM_IP_MCF_OCU_NUM_INSTANCES, th500_mcf_ocu_inst_static_array}, +#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC) + {"mcf_soc", mcf_soc_mask, TH500_HWPM_IP_MCF_SOC, TH500_HWPM_IP_MCF_SOC_NUM_INSTANCES, th500_mcf_soc_inst_static_array}, #endif #if defined(CONFIG_TH500_HWPM_IP_MSS_HUB) {"mss_hub", mss_hub_mask, TH500_HWPM_IP_MSS_HUB, TH500_HWPM_IP_MSS_HUB_NUM_INSTANCES, th500_mss_hub_inst_static_array}, @@ -592,18 +644,11 @@ int th500_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) #endif }; int force_enable_ips_size = sizeof(force_enable_ips)/sizeof(force_enable_ips[0]); -#endif /* CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE */ - - tegra_hwpm_fn(hwpm, " "); - -#if defined(CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE) - socket_offset = (u64)socket_number << socket_shift; for (ip = 1; ip < force_enable_ips_size; ip++) { struct hwpm_force_enable_ip *current_ip = &force_enable_ips[ip]; - tegra_hwpm_err(hwpm, "Force enabling %s on socket %d", current_ip->name, - socket_number); + tegra_hwpm_dbg(hwpm, hwpm_info, "Force enabling %s on socket 0", current_ip->name); for (inst = 0; inst < current_ip->instances; inst++) { if (!(current_ip->mask & (1ULL << inst))) { @@ -614,7 +659,7 @@ int th500_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm) ip_inst = ¤t_ip->inst_static_array[inst]; elem_info = &ip_inst->element_info[TEGRA_HWPM_APERTURE_TYPE_PERFMUX]; - base_addr = socket_offset + elem_info->range_start; + base_addr = elem_info->range_start; ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, base_addr, current_ip->id, true); if (ret != 0) { diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h index 158d9e4..f8d7611 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm.h @@ -85,8 +85,7 @@ enum tegra_hwpm_ip_enum { TEGRA_HWPM_IP_NVLRX, TEGRA_HWPM_IP_NVLTX, TEGRA_HWPM_IP_MSS_HUB, - TEGRA_HWPM_IP_MCF_OCU, - TEGRA_HWPM_IP_MCF_IOBHX, + TEGRA_HWPM_IP_MCF_SOC, TEGRA_HWPM_IP_MCF_C2C, TEGRA_HWPM_IP_MCF_CLINK, TEGRA_HWPM_IP_MCF_CORE, @@ -128,8 +127,7 @@ enum tegra_hwpm_resource_enum { TEGRA_HWPM_RESOURCE_NVLRX, TEGRA_HWPM_RESOURCE_NVLTX, TEGRA_HWPM_RESOURCE_MSS_HUB, - TEGRA_HWPM_RESOURCE_MCF_OCU, - TEGRA_HWPM_RESOURCE_MCF_IOBHX, + TEGRA_HWPM_RESOURCE_MCF_SOC, TEGRA_HWPM_RESOURCE_MCF_C2C, TEGRA_HWPM_RESOURCE_MCF_CLINK, TEGRA_HWPM_RESOURCE_MCF_CORE, diff --git a/drivers/tegra/hwpm/include/tegra_hwpm_log.h b/drivers/tegra/hwpm/include/tegra_hwpm_log.h index 1dfe1c3..1f42332 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm_log.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm_log.h @@ -86,7 +86,7 @@ enum tegra_soc_hwpm_log_type { hwpm_dbg_reserve_resource | hwpm_dbg_release_resource | \ hwpm_dbg_alloc_pma_stream | hwpm_dbg_bind | hwpm_dbg_allowlist | \ hwpm_dbg_regops | hwpm_dbg_update_get_put | hwpm_dbg_driver_release | \ - hwpm_dbg_kmem) + hwpm_dbg_kmem | hwpm_dbg_active) #ifdef __KERNEL__ diff --git a/drivers/tegra/hwpm/os/linux/debugfs.c b/drivers/tegra/hwpm/os/linux/debugfs.c index d9577a4..ea29156 100644 --- a/drivers/tegra/hwpm/os/linux/debugfs.c +++ b/drivers/tegra/hwpm/os/linux/debugfs.c @@ -25,7 +25,6 @@ void tegra_hwpm_debugfs_init(struct tegra_hwpm_os_linux *hwpm_linux) { struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm; - extern int dbg_mask; if (!hwpm_linux) { tegra_hwpm_err(hwpm, "Invalid hwpm_linux struct"); @@ -43,8 +42,6 @@ void tegra_hwpm_debugfs_init(struct tegra_hwpm_os_linux *hwpm_linux) debugfs_create_u32("log_mask", S_IRUGO|S_IWUSR, hwpm_linux->debugfs_root, &hwpm->dbg_mask); - hwpm->dbg_mask = ((u32)dbg_mask & hwpm_dbg_all_bits); - return; fail: diff --git a/drivers/tegra/hwpm/os/linux/driver.c b/drivers/tegra/hwpm/os/linux/driver.c index 494455f..e1ce91c 100644 --- a/drivers/tegra/hwpm/os/linux/driver.c +++ b/drivers/tegra/hwpm/os/linux/driver.c @@ -1,6 +1,5 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +/* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: GPL-2.0-only * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -10,8 +9,6 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ #ifdef CONFIG_TEGRA_HWPM_OOT #include @@ -19,13 +16,11 @@ #include #include -#include #include #include #include #include #include -#include #include #include @@ -38,68 +33,6 @@ #include #include -/* - * Optional module parameters - */ -#define S_IRWUG (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP) - -/* Debug mask at driver load time. Can be overridden via debugfs later */ -int dbg_mask = 0; -module_param(dbg_mask, int, S_IRWUG); - -/* This is a WAR on TH500 */ -int validate_current_config = 1; -module_param(validate_current_config, int, S_IRWUG); - -/* - * IP software masks to be used for force-enablement. - * 0x0 means "do not force-enable" - */ -long int nvlctrl_mask = 0x0; -module_param(nvlctrl_mask, long, S_IRWUG); - -long int nvlrx_mask = 0x0; -module_param(nvlrx_mask, long, S_IRWUG); - -long int nvltx_mask = 0x0; -module_param(nvltx_mask, long, S_IRWUG); - -long int c2c_mask = 0x0; -module_param(c2c_mask, long, S_IRWUG); - -long int cl2_mask = 0x0; -module_param(cl2_mask, long, S_IRWUG); - -long int mcf_c2c_mask = 0x0; -module_param(mcf_c2c_mask, long, S_IRWUG); - -long int mcf_clink_mask = 0x0; -module_param(mcf_clink_mask, long, S_IRWUG); - -long int mcf_core_mask = 0x0; -module_param(mcf_core_mask, long, S_IRWUG); - -long int mcf_iobhx_mask = 0x0; -module_param(mcf_iobhx_mask, long, S_IRWUG); - -long int mcf_ocu_mask = 0x0; -module_param(mcf_ocu_mask, long, S_IRWUG); - -long int mss_channel_mask = 0x0; -module_param(mss_channel_mask, long, S_IRWUG); - -long int mss_hub_mask = 0x0; -module_param(mss_hub_mask, long, S_IRWUG); - -long int pcie_mask = 0x0; -module_param(pcie_mask, long, S_IRWUG); - -long int smmu_mask = 0x0; -module_param(smmu_mask, long, S_IRWUG); - -/* Socket number */ -int socket_number = 0x0; - static const struct of_device_id tegra_soc_hwpm_of_match[] = { { .compatible = "nvidia,t234-soc-hwpm", @@ -117,26 +50,6 @@ static const struct of_device_id tegra_soc_hwpm_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_soc_hwpm_of_match); -/* - * The socket number must be 0, 1, 2, or 3. - */ -static int set_socket_number(const char *val, const struct kernel_param *kp) -{ - int socket_num = 0, ret; - - ret = kstrtoint(val, 10, &socket_num); - if (ret != 0 || socket_num < 0 || socket_num > 3) - return -EINVAL; - - return param_set_int(val, kp); -} - -static const struct kernel_param_ops param_ops = { - .set = set_socket_number, - .get = param_get_int, -}; -module_param_cb(socket, ¶m_ops, &socket_number, S_IRWUG | S_IROTH); - #if defined(NV_CLASS_STRUCT_DEVNODE_HAS_CONST_DEV_ARG) static char *tegra_hwpm_get_devnode(const struct device *dev, umode_t *mode) #else diff --git a/drivers/tegra/hwpm/os/linux/io_utils.c b/drivers/tegra/hwpm/os/linux/io_utils.c index 394160b..ea5d942 100644 --- a/drivers/tegra/hwpm/os/linux/io_utils.c +++ b/drivers/tegra/hwpm/os/linux/io_utils.c @@ -1,6 +1,5 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +/* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: GPL-2.0-only * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -10,8 +9,6 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ #include @@ -147,6 +144,10 @@ static int ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst, } *val = __raw_readl(ptr); iounmap(ptr); + + /* If all F's received, it's a failure */ + if (*val == 0xFFFFFFFFU) + return -ENODEV; } } return 0; diff --git a/drivers/tegra/hwpm/os/linux/ip_utils.c b/drivers/tegra/hwpm/os/linux/ip_utils.c index a216956..67b022b 100644 --- a/drivers/tegra/hwpm/os/linux/ip_utils.c +++ b/drivers/tegra/hwpm/os/linux/ip_utils.c @@ -1,6 +1,5 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +/* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: GPL-2.0-only * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -10,8 +9,6 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ #include @@ -108,11 +105,8 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_IP_MSS_HUB: ip_enum_idx = TEGRA_HWPM_IP_MSS_HUB; break; - case TEGRA_SOC_HWPM_IP_MCF_OCU: - ip_enum_idx = TEGRA_HWPM_IP_MCF_OCU; - break; - case TEGRA_SOC_HWPM_IP_MCF_IOBHX: - ip_enum_idx = TEGRA_HWPM_IP_MCF_IOBHX; + case TEGRA_SOC_HWPM_IP_MCF_SOC: + ip_enum_idx = TEGRA_HWPM_IP_MCF_SOC; break; case TEGRA_SOC_HWPM_IP_MCF_C2C: ip_enum_idx = TEGRA_HWPM_IP_MCF_C2C; @@ -255,11 +249,8 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm, case TEGRA_SOC_HWPM_RESOURCE_MSS_HUB: res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_HUB; break; - case TEGRA_SOC_HWPM_RESOURCE_MCF_OCU: - res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_OCU; - break; - case TEGRA_SOC_HWPM_RESOURCE_MCF_IOBHX: - res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_IOBHX; + case TEGRA_SOC_HWPM_RESOURCE_MCF_SOC: + res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_SOC; break; case TEGRA_SOC_HWPM_RESOURCE_MCF_C2C: res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_C2C; diff --git a/include/uapi/linux/tegra-soc-hwpm-uapi.h b/include/uapi/linux/tegra-soc-hwpm-uapi.h index 15280a2..9493df0 100644 --- a/include/uapi/linux/tegra-soc-hwpm-uapi.h +++ b/include/uapi/linux/tegra-soc-hwpm-uapi.h @@ -1,6 +1,5 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +/* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: GPL-2.0-only * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -10,8 +9,6 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . * * tegra-soc-hwpm-uapi.h: * This is the userspace API header for the Tegra SOC HWPM driver. @@ -51,8 +48,7 @@ enum tegra_soc_hwpm_ip { TEGRA_SOC_HWPM_IP_NVLRX, TEGRA_SOC_HWPM_IP_NVLTX, TEGRA_SOC_HWPM_IP_MSS_HUB, - TEGRA_SOC_HWPM_IP_MCF_OCU, - TEGRA_SOC_HWPM_IP_MCF_IOBHX, + TEGRA_SOC_HWPM_IP_MCF_SOC, TEGRA_SOC_HWPM_IP_MCF_C2C, TEGRA_SOC_HWPM_IP_MCF_CLINK, TEGRA_SOC_HWPM_IP_MCF_CORE, @@ -132,8 +128,7 @@ enum tegra_soc_hwpm_resource { TEGRA_SOC_HWPM_RESOURCE_NVLRX, TEGRA_SOC_HWPM_RESOURCE_NVLTX, TEGRA_SOC_HWPM_RESOURCE_MSS_HUB, - TEGRA_SOC_HWPM_RESOURCE_MCF_OCU, - TEGRA_SOC_HWPM_RESOURCE_MCF_IOBHX, + TEGRA_SOC_HWPM_RESOURCE_MCF_SOC, TEGRA_SOC_HWPM_RESOURCE_MCF_C2C, TEGRA_SOC_HWPM_RESOURCE_MCF_CLINK, TEGRA_SOC_HWPM_RESOURCE_MCF_CORE,