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git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-22 17:30:40 +03:00
tegra: hwpm: Enable PVA, DLA, MSS_Channel in HWPM
- Enable PVA, NVDLA and MSS_Channel IPs for HWPM profiling. - Force enable MSS_Channel in Hypervisor config, NVDLA by default. - Remove hypervisor checks in ip_readl and ip_writel functions. - Replace PCIE config enable flag from CONFIG_PCIE_TEGRA to CONFIG_PCIE_TEGRA194. - Add missing resource status init value for MSS channel IP. Bug 3632111 Change-Id: I6b36a3a3b3179b99542d8ed03027c8849fe9f712 Signed-off-by: vasukis <vasukis@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2725087 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
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44
Makefile
44
Makefile
@@ -41,6 +41,33 @@ obj-y += hal/t234/ip/rtr/t234_hwpm_ip_rtr.o
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# IP config flag and IP specific .o file.
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# IP config flag and IP specific .o file.
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#
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#
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#
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# Define a Minimal IP config flag
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# Enable only MSS_Channel, NVDLA and PVA IPs
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# When CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE is set to y.
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#
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CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE=y
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ifeq ($(CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE),y)
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ccflags-y += -DCONFIG_HWPM_ALLOW_FORCE_ENABLE
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endif
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ifeq ($(CONFIG_TEGRA_GRHOST_NVDLA),y)
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ccflags-y += -DCONFIG_SOC_HWPM_IP_NVDLA
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obj-y += hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.o
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endif
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ifeq ($(CONFIG_TEGRA_GRHOST_PVA),y)
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ccflags-y += -DCONFIG_SOC_HWPM_IP_PVA
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obj-y += hal/t234/ip/pva/t234_hwpm_ip_pva.o
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endif
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ifeq ($(CONFIG_NV_TEGRA_MC),y)
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ccflags-y += -DCONFIG_SOC_HWPM_IP_MSS_CHANNEL
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obj-y += hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.o
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endif
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ifneq ($(CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE),y)
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ccflags-y += -DCONFIG_SOC_HWPM_IP_DISPLAY
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ccflags-y += -DCONFIG_SOC_HWPM_IP_DISPLAY
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obj-y += hal/t234/ip/display/t234_hwpm_ip_display.o
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obj-y += hal/t234/ip/display/t234_hwpm_ip_display.o
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@@ -55,9 +82,6 @@ obj-y += hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.o
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endif
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endif
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ifeq ($(CONFIG_NV_TEGRA_MC),y)
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ifeq ($(CONFIG_NV_TEGRA_MC),y)
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ccflags-y += -DCONFIG_SOC_HWPM_IP_MSS_CHANNEL
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obj-y += hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.o
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ccflags-y += -DCONFIG_SOC_HWPM_IP_MSS_ISO_NISO_HUBS
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ccflags-y += -DCONFIG_SOC_HWPM_IP_MSS_ISO_NISO_HUBS
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obj-y += hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.o
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obj-y += hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.o
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@@ -73,11 +97,6 @@ ccflags-y += -DCONFIG_SOC_HWPM_IP_NVDEC
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obj-y += hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.o
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obj-y += hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.o
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endif
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endif
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ifeq ($(CONFIG_TEGRA_GRHOST_NVDLA),y)
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ccflags-y += -DCONFIG_SOC_HWPM_IP_NVDLA
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obj-y += hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.o
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endif
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ifeq ($(CONFIG_TEGRA_GRHOST_NVENC),y)
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ifeq ($(CONFIG_TEGRA_GRHOST_NVENC),y)
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ccflags-y += -DCONFIG_SOC_HWPM_IP_NVENC
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ccflags-y += -DCONFIG_SOC_HWPM_IP_NVENC
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obj-y += hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.o
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obj-y += hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.o
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@@ -88,16 +107,11 @@ ccflags-y += -DCONFIG_SOC_HWPM_IP_OFA
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obj-y += hal/t234/ip/ofa/t234_hwpm_ip_ofa.o
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obj-y += hal/t234/ip/ofa/t234_hwpm_ip_ofa.o
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endif
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endif
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ifeq ($(CONFIG_PCIE_TEGRA),y)
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ifeq ($(CONFIG_PCIE_TEGRA194),y)
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ccflags-y += -DCONFIG_SOC_HWPM_IP_PCIE
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ccflags-y += -DCONFIG_SOC_HWPM_IP_PCIE
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obj-y += hal/t234/ip/pcie/t234_hwpm_ip_pcie.o
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obj-y += hal/t234/ip/pcie/t234_hwpm_ip_pcie.o
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endif
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endif
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ifeq ($(CONFIG_TEGRA_GRHOST_PVA),y)
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ccflags-y += -DCONFIG_SOC_HWPM_IP_PVA
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obj-y += hal/t234/ip/pva/t234_hwpm_ip_pva.o
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endif
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ccflags-y += -DCONFIG_SOC_HWPM_IP_SCF
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ccflags-y += -DCONFIG_SOC_HWPM_IP_SCF
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obj-y += hal/t234/ip/scf/t234_hwpm_ip_scf.o
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obj-y += hal/t234/ip/scf/t234_hwpm_ip_scf.o
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@@ -112,3 +126,5 @@ obj-y += hal/t234/ip/vic/t234_hwpm_ip_vic.o
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endif
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endif
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endif
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endif
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endif
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@@ -640,5 +640,6 @@ struct hwpm_ip t234_hwpm_ip_mss_channel = {
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.dependent_fuse_mask = TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK,
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.dependent_fuse_mask = TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK,
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.override_enable = false,
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.override_enable = false,
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.inst_fs_mask = 0U,
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.inst_fs_mask = 0U,
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.resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID,
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.reserved = false,
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.reserved = false,
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};
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};
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@@ -42,7 +42,7 @@ int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
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/* Convert tegra_soc_hwpm_resource to internal enum */
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/* Convert tegra_soc_hwpm_resource to internal enum */
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if (!(t234_hwpm_is_resource_active(hwpm,
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if (!(t234_hwpm_is_resource_active(hwpm,
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hwpm_ip_ops->resource_enum, &ip_idx))) {
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hwpm_ip_ops->resource_enum, &ip_idx))) {
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tegra_hwpm_err(hwpm,
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tegra_hwpm_dbg(hwpm, hwpm_dbg_ip_register,
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"SOC hwpm resource %d (base 0x%llx) is unconfigured",
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"SOC hwpm resource %d (base 0x%llx) is unconfigured",
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hwpm_ip_ops->resource_enum,
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hwpm_ip_ops->resource_enum,
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hwpm_ip_ops->ip_base_address);
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hwpm_ip_ops->ip_base_address);
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@@ -178,8 +178,8 @@ int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
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}
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}
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ret = 0;
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ret = 0;
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}
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}
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break;
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#endif
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#endif
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break;
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case T234_HWPM_IP_PMA:
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case T234_HWPM_IP_PMA:
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case T234_HWPM_IP_RTR:
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case T234_HWPM_IP_RTR:
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default:
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default:
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@@ -297,10 +297,10 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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tegra_hwpm_fn(hwpm, " ");
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tegra_hwpm_fn(hwpm, " ");
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#if defined(CONFIG_HWPM_ALLOW_FORCE_ENABLE)
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#if defined(CONFIG_HWPM_ALLOW_FORCE_ENABLE)
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if (tegra_platform_is_vsp()) {
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/* Static IP instances as per VSP netlist */
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/* MSS CHANNEL: vsp has single instance available */
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#if defined(CONFIG_SOC_HWPM_IP_MSS_CHANNEL)
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#if defined(CONFIG_SOC_HWPM_IP_MSS_CHANNEL)
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if (is_tegra_hypervisor_mode()) {
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_mc0_base_r(),
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addr_map_mc0_base_r(),
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T234_HWPM_IP_MSS_CHANNEL, true);
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T234_HWPM_IP_MSS_CHANNEL, true);
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@@ -309,7 +309,9 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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"T234_HWPM_IP_MSS_CHANNEL force enable failed");
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"T234_HWPM_IP_MSS_CHANNEL force enable failed");
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return ret;
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return ret;
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}
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}
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}
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#endif
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#endif
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#if defined(CONFIG_SOC_HWPM_IP_MSS_GPU_HUB)
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#if defined(CONFIG_SOC_HWPM_IP_MSS_GPU_HUB)
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/* MSS GPU HUB */
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/* MSS GPU HUB */
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@@ -322,7 +324,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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return ret;
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return ret;
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}
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}
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#endif
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#endif
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}
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if (tegra_platform_is_silicon()) {
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if (tegra_platform_is_silicon()) {
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/* Static IP instances corresponding to silicon */
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/* Static IP instances corresponding to silicon */
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/* VI */
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/* VI */
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@@ -358,6 +360,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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}
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}
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#endif
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#endif
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#if defined(CONFIG_SOC_HWPM_IP_NVDLA)
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/* NVDLA */
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/* NVDLA */
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_nvdla0_base_r(),
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addr_map_nvdla0_base_r(),
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@@ -371,6 +374,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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if (ret != 0) {
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if (ret != 0) {
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return ret;
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return ret;
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}
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}
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#endif
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/* MGBE */
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/* MGBE */
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/*
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/*
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@@ -443,17 +447,6 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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#endif
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#endif
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*/
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*/
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#if defined(CONFIG_SOC_HWPM_IP_MSS_GPU_HUB)
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/* MSS GPU HUB */
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_mss_nvlink_1_base_r(),
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T234_HWPM_IP_MSS_GPU_HUB, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_MSS_GPU_HUB force enable failed");
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return ret;
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}
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#endif
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}
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}
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#endif
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#endif
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/*
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/*
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@@ -472,7 +465,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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}
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}
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#endif
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#endif
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return 0;
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return ret;
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}
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}
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int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,
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int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,
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@@ -99,12 +99,6 @@ static int ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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u64 reg_addr = tegra_hwpm_safe_add_u64(
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u64 reg_addr = tegra_hwpm_safe_add_u64(
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aperture->start_abs_pa, offset);
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aperture->start_abs_pa, offset);
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if (is_tegra_hypervisor_mode()) {
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tegra_hwpm_err(hwpm,
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"Fallback method not implemented on hypervisor config");
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return -EINVAL;
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}
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ptr = ioremap(reg_addr, 0x4);
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ptr = ioremap(reg_addr, 0x4);
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if (!ptr) {
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if (!ptr) {
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tegra_hwpm_err(hwpm,
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tegra_hwpm_err(hwpm,
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@@ -153,12 +147,6 @@ static int ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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u64 reg_addr = tegra_hwpm_safe_add_u64(
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u64 reg_addr = tegra_hwpm_safe_add_u64(
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aperture->start_abs_pa, offset);
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aperture->start_abs_pa, offset);
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if (is_tegra_hypervisor_mode()) {
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tegra_hwpm_err(hwpm,
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"Fallback method not implemented on hypervisor config");
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return -EINVAL;
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}
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ptr = ioremap(reg_addr, 0x4);
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ptr = ioremap(reg_addr, 0x4);
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if (!ptr) {
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if (!ptr) {
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tegra_hwpm_err(hwpm,
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tegra_hwpm_err(hwpm,
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