tegra: hwpm: Enable PVA, DLA, MSS_Channel in HWPM

- Enable PVA, NVDLA and MSS_Channel IPs for HWPM
profiling.
- Force enable MSS_Channel in Hypervisor config,
NVDLA by default.
- Remove hypervisor checks in ip_readl and ip_writel
functions.
- Replace PCIE config enable flag from CONFIG_PCIE_TEGRA to
CONFIG_PCIE_TEGRA194.
- Add missing resource status init value for MSS channel IP.

Bug 3632111

Change-Id: I6b36a3a3b3179b99542d8ed03027c8849fe9f712
Signed-off-by: vasukis <vasukis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2725087
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
vasukis
2022-06-05 22:41:56 +00:00
committed by mobile promotions
parent 5c94e7dad3
commit d1de75a664
4 changed files with 42 additions and 44 deletions

View File

@@ -41,6 +41,33 @@ obj-y += hal/t234/ip/rtr/t234_hwpm_ip_rtr.o
# IP config flag and IP specific .o file. # IP config flag and IP specific .o file.
# #
#
# Define a Minimal IP config flag
# Enable only MSS_Channel, NVDLA and PVA IPs
# When CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE is set to y.
#
CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE=y
ifeq ($(CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE),y)
ccflags-y += -DCONFIG_HWPM_ALLOW_FORCE_ENABLE
endif
ifeq ($(CONFIG_TEGRA_GRHOST_NVDLA),y)
ccflags-y += -DCONFIG_SOC_HWPM_IP_NVDLA
obj-y += hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.o
endif
ifeq ($(CONFIG_TEGRA_GRHOST_PVA),y)
ccflags-y += -DCONFIG_SOC_HWPM_IP_PVA
obj-y += hal/t234/ip/pva/t234_hwpm_ip_pva.o
endif
ifeq ($(CONFIG_NV_TEGRA_MC),y)
ccflags-y += -DCONFIG_SOC_HWPM_IP_MSS_CHANNEL
obj-y += hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.o
endif
ifneq ($(CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE),y)
ccflags-y += -DCONFIG_SOC_HWPM_IP_DISPLAY ccflags-y += -DCONFIG_SOC_HWPM_IP_DISPLAY
obj-y += hal/t234/ip/display/t234_hwpm_ip_display.o obj-y += hal/t234/ip/display/t234_hwpm_ip_display.o
@@ -55,9 +82,6 @@ obj-y += hal/t234/ip/mgbe/t234_hwpm_ip_mgbe.o
endif endif
ifeq ($(CONFIG_NV_TEGRA_MC),y) ifeq ($(CONFIG_NV_TEGRA_MC),y)
ccflags-y += -DCONFIG_SOC_HWPM_IP_MSS_CHANNEL
obj-y += hal/t234/ip/mss_channel/t234_hwpm_ip_mss_channel.o
ccflags-y += -DCONFIG_SOC_HWPM_IP_MSS_ISO_NISO_HUBS ccflags-y += -DCONFIG_SOC_HWPM_IP_MSS_ISO_NISO_HUBS
obj-y += hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.o obj-y += hal/t234/ip/mss_iso_niso_hubs/t234_hwpm_ip_mss_iso_niso_hubs.o
@@ -73,11 +97,6 @@ ccflags-y += -DCONFIG_SOC_HWPM_IP_NVDEC
obj-y += hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.o obj-y += hal/t234/ip/nvdec/t234_hwpm_ip_nvdec.o
endif endif
ifeq ($(CONFIG_TEGRA_GRHOST_NVDLA),y)
ccflags-y += -DCONFIG_SOC_HWPM_IP_NVDLA
obj-y += hal/t234/ip/nvdla/t234_hwpm_ip_nvdla.o
endif
ifeq ($(CONFIG_TEGRA_GRHOST_NVENC),y) ifeq ($(CONFIG_TEGRA_GRHOST_NVENC),y)
ccflags-y += -DCONFIG_SOC_HWPM_IP_NVENC ccflags-y += -DCONFIG_SOC_HWPM_IP_NVENC
obj-y += hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.o obj-y += hal/t234/ip/nvenc/t234_hwpm_ip_nvenc.o
@@ -88,16 +107,11 @@ ccflags-y += -DCONFIG_SOC_HWPM_IP_OFA
obj-y += hal/t234/ip/ofa/t234_hwpm_ip_ofa.o obj-y += hal/t234/ip/ofa/t234_hwpm_ip_ofa.o
endif endif
ifeq ($(CONFIG_PCIE_TEGRA),y) ifeq ($(CONFIG_PCIE_TEGRA194),y)
ccflags-y += -DCONFIG_SOC_HWPM_IP_PCIE ccflags-y += -DCONFIG_SOC_HWPM_IP_PCIE
obj-y += hal/t234/ip/pcie/t234_hwpm_ip_pcie.o obj-y += hal/t234/ip/pcie/t234_hwpm_ip_pcie.o
endif endif
ifeq ($(CONFIG_TEGRA_GRHOST_PVA),y)
ccflags-y += -DCONFIG_SOC_HWPM_IP_PVA
obj-y += hal/t234/ip/pva/t234_hwpm_ip_pva.o
endif
ccflags-y += -DCONFIG_SOC_HWPM_IP_SCF ccflags-y += -DCONFIG_SOC_HWPM_IP_SCF
obj-y += hal/t234/ip/scf/t234_hwpm_ip_scf.o obj-y += hal/t234/ip/scf/t234_hwpm_ip_scf.o
@@ -112,3 +126,5 @@ obj-y += hal/t234/ip/vic/t234_hwpm_ip_vic.o
endif endif
endif endif
endif

View File

@@ -640,5 +640,6 @@ struct hwpm_ip t234_hwpm_ip_mss_channel = {
.dependent_fuse_mask = TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK, .dependent_fuse_mask = TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK,
.override_enable = false, .override_enable = false,
.inst_fs_mask = 0U, .inst_fs_mask = 0U,
.resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID,
.reserved = false, .reserved = false,
}; };

View File

@@ -42,7 +42,7 @@ int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
/* Convert tegra_soc_hwpm_resource to internal enum */ /* Convert tegra_soc_hwpm_resource to internal enum */
if (!(t234_hwpm_is_resource_active(hwpm, if (!(t234_hwpm_is_resource_active(hwpm,
hwpm_ip_ops->resource_enum, &ip_idx))) { hwpm_ip_ops->resource_enum, &ip_idx))) {
tegra_hwpm_err(hwpm, tegra_hwpm_dbg(hwpm, hwpm_dbg_ip_register,
"SOC hwpm resource %d (base 0x%llx) is unconfigured", "SOC hwpm resource %d (base 0x%llx) is unconfigured",
hwpm_ip_ops->resource_enum, hwpm_ip_ops->resource_enum,
hwpm_ip_ops->ip_base_address); hwpm_ip_ops->ip_base_address);
@@ -178,8 +178,8 @@ int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
} }
ret = 0; ret = 0;
} }
break;
#endif #endif
break;
case T234_HWPM_IP_PMA: case T234_HWPM_IP_PMA:
case T234_HWPM_IP_RTR: case T234_HWPM_IP_RTR:
default: default:
@@ -297,10 +297,10 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
#if defined(CONFIG_HWPM_ALLOW_FORCE_ENABLE) #if defined(CONFIG_HWPM_ALLOW_FORCE_ENABLE)
if (tegra_platform_is_vsp()) {
/* Static IP instances as per VSP netlist */
/* MSS CHANNEL: vsp has single instance available */
#if defined(CONFIG_SOC_HWPM_IP_MSS_CHANNEL) #if defined(CONFIG_SOC_HWPM_IP_MSS_CHANNEL)
if (is_tegra_hypervisor_mode()) {
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_mc0_base_r(), addr_map_mc0_base_r(),
T234_HWPM_IP_MSS_CHANNEL, true); T234_HWPM_IP_MSS_CHANNEL, true);
@@ -309,7 +309,9 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
"T234_HWPM_IP_MSS_CHANNEL force enable failed"); "T234_HWPM_IP_MSS_CHANNEL force enable failed");
return ret; return ret;
} }
}
#endif #endif
#if defined(CONFIG_SOC_HWPM_IP_MSS_GPU_HUB) #if defined(CONFIG_SOC_HWPM_IP_MSS_GPU_HUB)
/* MSS GPU HUB */ /* MSS GPU HUB */
@@ -322,7 +324,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
return ret; return ret;
} }
#endif #endif
}
if (tegra_platform_is_silicon()) { if (tegra_platform_is_silicon()) {
/* Static IP instances corresponding to silicon */ /* Static IP instances corresponding to silicon */
/* VI */ /* VI */
@@ -358,6 +360,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
} }
#endif #endif
#if defined(CONFIG_SOC_HWPM_IP_NVDLA)
/* NVDLA */ /* NVDLA */
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL, ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_nvdla0_base_r(), addr_map_nvdla0_base_r(),
@@ -371,6 +374,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }
#endif
/* MGBE */ /* MGBE */
/* /*
@@ -443,17 +447,6 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
#endif #endif
*/ */
#if defined(CONFIG_SOC_HWPM_IP_MSS_GPU_HUB)
/* MSS GPU HUB */
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
addr_map_mss_nvlink_1_base_r(),
T234_HWPM_IP_MSS_GPU_HUB, true);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"T234_HWPM_IP_MSS_GPU_HUB force enable failed");
return ret;
}
#endif
} }
#endif #endif
/* /*
@@ -472,7 +465,7 @@ int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
} }
#endif #endif
return 0; return ret;
} }
int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm, int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,

View File

@@ -99,12 +99,6 @@ static int ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
u64 reg_addr = tegra_hwpm_safe_add_u64( u64 reg_addr = tegra_hwpm_safe_add_u64(
aperture->start_abs_pa, offset); aperture->start_abs_pa, offset);
if (is_tegra_hypervisor_mode()) {
tegra_hwpm_err(hwpm,
"Fallback method not implemented on hypervisor config");
return -EINVAL;
}
ptr = ioremap(reg_addr, 0x4); ptr = ioremap(reg_addr, 0x4);
if (!ptr) { if (!ptr) {
tegra_hwpm_err(hwpm, tegra_hwpm_err(hwpm,
@@ -153,12 +147,6 @@ static int ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
u64 reg_addr = tegra_hwpm_safe_add_u64( u64 reg_addr = tegra_hwpm_safe_add_u64(
aperture->start_abs_pa, offset); aperture->start_abs_pa, offset);
if (is_tegra_hypervisor_mode()) {
tegra_hwpm_err(hwpm,
"Fallback method not implemented on hypervisor config");
return -EINVAL;
}
ptr = ioremap(reg_addr, 0x4); ptr = ioremap(reg_addr, 0x4);
if (!ptr) { if (!ptr) {
tegra_hwpm_err(hwpm, tegra_hwpm_err(hwpm,