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tegra: hwpm: fix sparse errors
Below listed functions are defined and used in the same source file, hence update the functions to be static. - tegra_hwpm_element_disable - tegra_hwpm_element_reserve - tegra_hwpm_element_release Bug 3528414 Change-Id: Ib9aa44001fb5fac1e339b3264a4d750af09b9a01 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2847009 GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -20,7 +20,7 @@
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <tegra_hwpm.h>
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int tegra_hwpm_element_reserve(struct tegra_soc_hwpm *hwpm,
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static int tegra_hwpm_element_reserve(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *element)
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struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *element)
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{
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{
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int err = 0;
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int err = 0;
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@@ -57,7 +57,7 @@ fail:
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return err;
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return err;
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}
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}
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int tegra_hwpm_element_disable(struct tegra_soc_hwpm *hwpm,
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static int tegra_hwpm_element_disable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *element)
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struct hwpm_ip_aperture *element)
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{
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{
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int err = 0;
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int err = 0;
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@@ -94,7 +94,7 @@ fail:
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return err;
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return err;
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}
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}
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int tegra_hwpm_element_release(struct tegra_soc_hwpm *hwpm,
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static int tegra_hwpm_element_release(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *element)
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struct hwpm_ip_aperture *element)
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{
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{
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int err = 0;
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int err = 0;
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -49,11 +49,6 @@ int tegra_hwpm_reserve_resource(struct tegra_soc_hwpm *hwpm, u32 resource);
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int tegra_hwpm_release_resources(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_release_resources(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_element_reserve(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *perfmon);
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int tegra_hwpm_element_release(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon);
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int tegra_hwpm_set_fs_info_ip_ops(struct tegra_soc_hwpm *hwpm,
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int tegra_hwpm_set_fs_info_ip_ops(struct tegra_soc_hwpm *hwpm,
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struct tegra_hwpm_ip_ops *ip_ops,
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struct tegra_hwpm_ip_ops *ip_ops,
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u64 base_address, u32 ip_idx, bool available);
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u64 base_address, u32 ip_idx, bool available);
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