From da3bda1364a08c0910ea51f7eccf485c0f60c766 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Wed, 20 Sep 2023 14:18:38 -0700 Subject: [PATCH] tegra: hwpm: improve common function readability - HALs get_rtr_int_idx and get_ip_max_idx return the chip specific router index and number of IPs. This information is static for a chip and doesn't require any input. Hence, update the HAL definition to not require hwpm pointer as an argument. Update definition and references for these HALs. - Add new HAL to get PMA and RTR structure pointers. Implement and update other chip specific functions to use new HAL. - Add new timer macro to check a condition and timeout after given retries. Update necessary code to use new timer macro. - Correct validate_emc_config function to compute correct available mss channel mask based on fuse value. - Update tegra_hwpm_readl and tegra_hwpm_writel macros to assert error value. This way error checks are added at one spot and not sprinkled all over the driver code. - Update get_mem_bytes_put_ptr() and membuf_overflow_status() to return error as function return and accept arguments to return mem_head pointer and overflow status respectively. Add overflow status macros to use throughout driver. Update HAL definition and references accordingly. - conftest is only compiled for OOT config atm. Add OOT config check to include conftest header. Jira THWPM-109 Change-Id: I77d150e860fa344a1604d241e27718150fdb8647 Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2982555 Reviewed-by: Adeel Raza Reviewed-by: Vishal Aslot GVS: Gerrit_Virtual_Submit --- drivers/tegra/hwpm/Makefile.th500.sources | 1 - drivers/tegra/hwpm/common/aperture.c | 6 +- drivers/tegra/hwpm/common/init.c | 7 +- drivers/tegra/hwpm/common/ip.c | 4 +- drivers/tegra/hwpm/common/resource.c | 10 +- drivers/tegra/hwpm/hal/t234/ip/rtr/t234_rtr.h | 5 +- drivers/tegra/hwpm/hal/t234/t234_aperture.c | 326 +++++--------- drivers/tegra/hwpm/hal/t234/t234_interface.c | 7 +- drivers/tegra/hwpm/hal/t234/t234_internal.h | 15 +- drivers/tegra/hwpm/hal/t234/t234_ip.c | 15 +- drivers/tegra/hwpm/hal/t234/t234_mem_mgmt.c | 248 ++++------- drivers/tegra/hwpm/hal/t234/t234_resource.c | 28 +- .../hwpm/hal/th500/soc/ip/rtr/th500_rtr.h | 10 +- .../hwpm/hal/th500/soc/th500_soc_aperture.c | 404 +++++------------- .../hwpm/hal/th500/soc/th500_soc_internal.h | 10 +- .../hwpm/hal/th500/soc/th500_soc_mem_mgmt.c | 246 ++++------- .../hwpm/hal/th500/soc/th500_soc_resource.c | 26 +- .../tegra/hwpm/hal/th500/th500_interface.c | 7 +- drivers/tegra/hwpm/hal/th500/th500_internal.h | 6 +- drivers/tegra/hwpm/hal/th500/th500_ip.c | 4 +- drivers/tegra/hwpm/include/tegra_hwpm.h | 15 +- drivers/tegra/hwpm/include/tegra_hwpm_io.h | 19 +- drivers/tegra/hwpm/include/tegra_hwpm_log.h | 10 +- .../tegra/hwpm/include/tegra_hwpm_mem_mgmt.h | 5 +- .../tegra/hwpm/include/tegra_hwpm_timers.h | 20 +- drivers/tegra/hwpm/os/linux/io_utils.c | 5 +- drivers/tegra/hwpm/os/linux/mem_mgmt_utils.c | 24 +- drivers/tegra/hwpm/os/linux/mem_mgmt_utils.h | 4 +- 28 files changed, 534 insertions(+), 953 deletions(-) diff --git a/drivers/tegra/hwpm/Makefile.th500.sources b/drivers/tegra/hwpm/Makefile.th500.sources index f7fea36..cb8e27a 100644 --- a/drivers/tegra/hwpm/Makefile.th500.sources +++ b/drivers/tegra/hwpm/Makefile.th500.sources @@ -12,7 +12,6 @@ nvhwpm-th500-objs += $(nvhwpm-th500-soc-objs) # Include TH500 CCPLEX files ifneq ($(wildcard $(srctree.hwpm)/drivers/tegra/hwpm/Makefile.th500.ccplex.sources),) -$(info "--------------Makefile.th500.ccplex.sources available") include $(srctree.hwpm)/drivers/tegra/hwpm/Makefile.th500.ccplex.sources nvhwpm-th500-objs += $(nvhwpm-th500-ccplex-objs) endif diff --git a/drivers/tegra/hwpm/common/aperture.c b/drivers/tegra/hwpm/common/aperture.c index e1c0a57..634d32e 100644 --- a/drivers/tegra/hwpm/common/aperture.c +++ b/drivers/tegra/hwpm/common/aperture.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -841,7 +841,7 @@ int tegra_hwpm_func_single_ip(struct tegra_soc_hwpm *hwpm, } break; case TEGRA_HWPM_RELEASE_RESOURCES: - if (ip_idx == active_chip->get_rtr_int_idx(hwpm)) { + if (ip_idx == active_chip->get_rtr_int_idx()) { tegra_hwpm_dbg(hwpm, hwpm_dbg_release_resource, "Router will be released later"); return 0; @@ -933,7 +933,7 @@ int tegra_hwpm_func_all_ip(struct tegra_soc_hwpm *hwpm, func_args->full_alist_idx = 0ULL; } - for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(hwpm); + for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(); ip_idx++) { err = tegra_hwpm_func_single_ip( diff --git a/drivers/tegra/hwpm/common/init.c b/drivers/tegra/hwpm/common/init.c index 5871d83..1d16a32 100644 --- a/drivers/tegra/hwpm/common/init.c +++ b/drivers/tegra/hwpm/common/init.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -278,6 +278,11 @@ bool tegra_hwpm_validate_primary_hals(struct tegra_soc_hwpm *hwpm) return false; } + if (hwpm->active_chip->get_rtr_pma_perfmux_ptr == NULL) { + tegra_hwpm_err(hwpm, "get_rtr_pma_perfmux_ptr HAL uninitialized"); + return false; + } + if (hwpm->active_chip->extract_ip_ops == NULL) { tegra_hwpm_err(hwpm, "extract_ip_ops uninitialized"); return false; diff --git a/drivers/tegra/hwpm/common/ip.c b/drivers/tegra/hwpm/common/ip.c index 550bb23..399ad7d 100644 --- a/drivers/tegra/hwpm/common/ip.c +++ b/drivers/tegra/hwpm/common/ip.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -585,7 +585,7 @@ static bool tegra_hwpm_addr_in_all_ip(struct tegra_soc_hwpm *hwpm, tegra_hwpm_fn(hwpm, " "); - for (idx = 0U; idx < active_chip->get_ip_max_idx(hwpm); idx++) { + for (idx = 0U; idx < active_chip->get_ip_max_idx(); idx++) { struct hwpm_ip *chip_ip = active_chip->chip_ips[idx]; if (chip_ip == NULL) { diff --git a/drivers/tegra/hwpm/common/resource.c b/drivers/tegra/hwpm/common/resource.c index 177211f..a092cb0 100644 --- a/drivers/tegra/hwpm/common/resource.c +++ b/drivers/tegra/hwpm/common/resource.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -44,10 +44,10 @@ int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm) err = tegra_hwpm_func_single_ip(hwpm, NULL, TEGRA_HWPM_RESERVE_GIVEN_RESOURCE, - active_chip->get_rtr_int_idx(hwpm)); + active_chip->get_rtr_int_idx()); if (err != 0) { tegra_hwpm_err(hwpm, "failed to reserve IP %d", - active_chip->get_rtr_int_idx(hwpm)); + active_chip->get_rtr_int_idx()); return err; } return err; @@ -62,10 +62,10 @@ int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm) err = tegra_hwpm_func_single_ip(hwpm, NULL, TEGRA_HWPM_RELEASE_ROUTER, - active_chip->get_rtr_int_idx(hwpm)); + active_chip->get_rtr_int_idx()); if (err != 0) { tegra_hwpm_err(hwpm, "failed to release IP %d", - active_chip->get_rtr_int_idx(hwpm)); + active_chip->get_rtr_int_idx()); return err; } return err; diff --git a/drivers/tegra/hwpm/hal/t234/ip/rtr/t234_rtr.h b/drivers/tegra/hwpm/hal/t234/ip/rtr/t234_rtr.h index 16fe27f..c0aa661 100644 --- a/drivers/tegra/hwpm/hal/t234/ip/rtr/t234_rtr.h +++ b/drivers/tegra/hwpm/hal/t234/ip/rtr/t234_rtr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,8 +34,9 @@ #define T234_HWPM_IP_RTR_NUM_BROADCAST_PER_INST 0U #define T234_HWPM_IP_RTR_STATIC_RTR_INST 0U +#define T234_HWPM_IP_RTR_STATIC_RTR_PERFMUX_INDEX 0U #define T234_HWPM_IP_RTR_STATIC_PMA_INST 1U -#define T234_HWPM_IP_RTR_PERMUX_INDEX 0U +#define T234_HWPM_IP_RTR_STATIC_PMA_PERFMUX_INDEX 0U extern struct hwpm_ip t234_hwpm_ip_rtr; diff --git a/drivers/tegra/hwpm/hal/t234/t234_aperture.c b/drivers/tegra/hwpm/hal/t234/t234_aperture.c index 6700fdc..a03e236 100644 --- a/drivers/tegra/hwpm/hal/t234/t234_aperture.c +++ b/drivers/tegra/hwpm/hal/t234/t234_aperture.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -30,41 +30,56 @@ #include #include +int t234_hwpm_get_rtr_pma_perfmux_ptr(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_aperture **rtr_perfmux_ptr, + struct hwpm_ip_aperture **pma_perfmux_ptr) +{ + struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; + struct hwpm_ip *chip_ip = active_chip->chip_ips[ + active_chip->get_rtr_int_idx()]; + struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_RTR_INST]; + struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_INST]; + + if (rtr_perfmux_ptr != NULL) { + *rtr_perfmux_ptr = &ip_inst_rtr->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_STATIC_RTR_PERFMUX_INDEX]; + } + + if (pma_perfmux_ptr != NULL) { + *pma_perfmux_ptr = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + T234_HWPM_IP_RTR_STATIC_PMA_PERFMUX_INDEX]; + } + + return 0; +} + int t234_hwpm_check_status(struct tegra_soc_hwpm *hwpm) { int err = 0; u32 reg_val = 0U; u32 field_mask = 0U; u32 field_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_RTR_INST]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *rtr_perfmux = NULL; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - /* Check ROUTER state */ - err = tegra_hwpm_readl(hwpm, rtr_perfmux, - pmmsys_sys0router_enginestatus_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); - if (pmmsys_sys0router_enginestatus_status_v(reg_val) != - pmmsys_sys0router_enginestatus_status_empty_v()) { - tegra_hwpm_err(hwpm, "Router not ready value 0x%x", reg_val); - return -EINVAL; - } + /* Check ROUTER state */ + tegra_hwpm_readl(hwpm, rtr_perfmux, + pmmsys_sys0router_enginestatus_r(), ®_val); + hwpm_assert_print(hwpm, + (pmmsys_sys0router_enginestatus_status_v(reg_val) == + pmmsys_sys0router_enginestatus_status_empty_v()), + return -EINVAL, "Router not ready value 0x%x", reg_val); /* Check PMA state */ field_mask = pmasys_enginestatus_status_m() | @@ -72,19 +87,12 @@ int t234_hwpm_check_status(struct tegra_soc_hwpm *hwpm) field_val = pmasys_enginestatus_status_empty_f() | pmasys_enginestatus_rbufempty_empty_f(); - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_enginestatus_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + hwpm_assert_print(hwpm, ((reg_val & field_mask) == field_val), + return -EINVAL, "PMA not ready value 0x%x", reg_val); - if ((reg_val & field_mask) != field_val) { - tegra_hwpm_err(hwpm, "PMA not ready value 0x%x", reg_val); - return -EINVAL; - } - - return err; + return 0; } int t234_hwpm_disable_triggers(struct tegra_soc_hwpm *hwpm) @@ -93,116 +101,48 @@ int t234_hwpm_disable_triggers(struct tegra_soc_hwpm *hwpm) u32 reg_val = 0U; u32 field_mask = 0U; u32 field_val = 0U; + u32 retries = 10U; u32 sleep_msecs = 100; - struct tegra_hwpm_timeout timeout; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_RTR_INST]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *rtr_perfmux = NULL; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + /* Disable PMA triggers */ - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_trigger_config_user_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmasys_trigger_config_user_pma_pulse_m(), pmasys_trigger_config_user_pma_pulse_disable_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_trigger_config_user_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } /* Wait for PERFMONs to idle */ - err = tegra_hwpm_timeout_init(hwpm, &timeout, 10U); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm timeout init failed"); - return err; - } - - do { - err = tegra_hwpm_readl(hwpm, rtr_perfmux, - pmmsys_sys0router_perfmonstatus_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } - tegra_hwpm_msleep(sleep_msecs); - } while ((pmmsys_sys0router_perfmonstatus_merged_v(reg_val) != 0U) && - (tegra_hwpm_timeout_expired(hwpm, &timeout) == 0)); - - if (pmmsys_sys0router_perfmonstatus_merged_v(reg_val) != 0U) { - tegra_hwpm_err(hwpm, "Timeout expired for " - "NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_EMPTY"); - return -ETIMEDOUT; - } + tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, rtr_perfmux, + pmmsys_sys0router_perfmonstatus_r(), ®_val, + (pmmsys_sys0router_perfmonstatus_merged_v(reg_val) != 0U), + "PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_EMPTY timed out"); /* Wait for ROUTER to idle */ - err = tegra_hwpm_timeout_init(hwpm, &timeout, 10U); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm timeout init failed"); - return err; - } - - do { - err = tegra_hwpm_readl(hwpm, rtr_perfmux, - pmmsys_sys0router_enginestatus_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } - tegra_hwpm_msleep(sleep_msecs); - } while ((pmmsys_sys0router_enginestatus_status_v(reg_val) != - pmmsys_sys0router_enginestatus_status_empty_v()) && - (tegra_hwpm_timeout_expired(hwpm, &timeout) == 0)); - if (pmmsys_sys0router_enginestatus_status_v(reg_val) != - pmmsys_sys0router_enginestatus_status_empty_v()) { - tegra_hwpm_err(hwpm, "Timeout expired for " - "NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_EMPTY"); - return -ETIMEDOUT; - } + tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, rtr_perfmux, + pmmsys_sys0router_enginestatus_r(), ®_val, + (pmmsys_sys0router_enginestatus_status_v(reg_val) != + pmmsys_sys0router_enginestatus_status_empty_v()), + "PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_EMPTY timed out"); /* Wait for PMA to idle */ - err = tegra_hwpm_timeout_init(hwpm, &timeout, 10U); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm timeout init failed"); - return err; - } - field_mask = pmasys_enginestatus_status_m() | pmasys_enginestatus_rbufempty_m(); field_val = pmasys_enginestatus_status_empty_f() | pmasys_enginestatus_rbufempty_empty_f(); - do { - err = tegra_hwpm_readl(hwpm, pma_perfmux, - pmasys_enginestatus_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } - tegra_hwpm_msleep(sleep_msecs); - } while (((reg_val & field_mask) != field_val) && - (tegra_hwpm_timeout_expired(hwpm, &timeout) == 0)); - - if ((reg_val & field_mask) != field_val) { - tegra_hwpm_err(hwpm, "Timeout expired for " - "NV_PERF_PMASYS_ENGINESTATUS"); - return -ETIMEDOUT; - } + tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, pma_perfmux, + pmasys_enginestatus_r(), ®_val, + ((reg_val & field_mask) != field_val), + "PMASYS_ENGINESTATUS timed out"); return err; } @@ -211,45 +151,27 @@ int t234_hwpm_init_prod_values(struct tegra_soc_hwpm *hwpm) { int err = 0; u32 val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_controlb_r(), &val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_controlb_r(), &val); val = set_field(val, pmasys_controlb_coalesce_timeout_cycles_m(), pmasys_controlb_coalesce_timeout_cycles__prod_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_controlb_r(), val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_controlb_r(), val); - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_channel_config_user_r(0), &val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } val = set_field(val, pmasys_channel_config_user_coalesce_timeout_cycles_m(), pmasys_channel_config_user_coalesce_timeout_cycles__prod_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_config_user_r(0), val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } /* CG enable is expected PROD value */ err = hwpm->active_chip->enable_cg(hwpm); @@ -267,32 +189,20 @@ int t234_hwpm_disable_cg(struct tegra_soc_hwpm *hwpm) u32 field_mask = 0U; u32 field_val = 0U; u32 reg_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_RTR_INST]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *rtr_perfmux = NULL; + struct hwpm_ip_aperture *pma_perfmux = NULL; - err = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + tegra_hwpm_fn(hwpm, " "); + + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); reg_val = set_field(reg_val, pmasys_cg2_slcg_m(), pmasys_cg2_slcg_disabled_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); field_mask = pmmsys_sys0router_cg2_slcg_perfmon_m() | pmmsys_sys0router_cg2_slcg_router_m() | @@ -300,19 +210,11 @@ int t234_hwpm_disable_cg(struct tegra_soc_hwpm *hwpm) field_val = pmmsys_sys0router_cg2_slcg_perfmon_disabled_f() | pmmsys_sys0router_cg2_slcg_router_disabled_f() | pmmsys_sys0router_cg2_slcg_disabled_f(); - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_cg2_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, field_mask, field_val); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_cg2_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -323,32 +225,20 @@ int t234_hwpm_enable_cg(struct tegra_soc_hwpm *hwpm) u32 reg_val = 0U; u32 field_mask = 0U; u32 field_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_RTR_INST]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *rtr_perfmux = NULL; + struct hwpm_ip_aperture *pma_perfmux = NULL; - err = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + tegra_hwpm_fn(hwpm, " "); + + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); reg_val = set_field(reg_val, pmasys_cg2_slcg_m(), pmasys_cg2_slcg_enabled_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); field_mask = pmmsys_sys0router_cg2_slcg_perfmon_m() | pmmsys_sys0router_cg2_slcg_router_m() | @@ -356,19 +246,11 @@ int t234_hwpm_enable_cg(struct tegra_soc_hwpm *hwpm) field_val = pmmsys_sys0router_cg2_slcg_perfmon__prod_f() | pmmsys_sys0router_cg2_slcg_router__prod_f() | pmmsys_sys0router_cg2_slcg__prod_f(); - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_cg2_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, field_mask, field_val); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_cg2_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } diff --git a/drivers/tegra/hwpm/hal/t234/t234_interface.c b/drivers/tegra/hwpm/hal/t234/t234_interface.c index 28cddf5..1406565 100644 --- a/drivers/tegra/hwpm/hal/t234/t234_interface.c +++ b/drivers/tegra/hwpm/hal/t234/t234_interface.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -46,6 +46,7 @@ static struct tegra_soc_hwpm_chip t234_chip_info = { .get_rtr_int_idx = t234_get_rtr_int_idx, .get_ip_max_idx = t234_get_ip_max_idx, + .get_rtr_pma_perfmux_ptr = t234_hwpm_get_rtr_pma_perfmux_ptr, .extract_ip_ops = t234_hwpm_extract_ip_ops, .force_enable_ips = t234_hwpm_force_enable_ips, @@ -307,12 +308,12 @@ bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm, return (config_ip != TEGRA_HWPM_IP_INACTIVE); } -u32 t234_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm) +u32 t234_get_rtr_int_idx(void) { return T234_HWPM_IP_RTR; } -u32 t234_get_ip_max_idx(struct tegra_soc_hwpm *hwpm) +u32 t234_get_ip_max_idx(void) { return T234_HWPM_IP_MAX; } diff --git a/drivers/tegra/hwpm/hal/t234/t234_internal.h b/drivers/tegra/hwpm/hal/t234/t234_internal.h index 906e695..cf416a2 100644 --- a/drivers/tegra/hwpm/hal/t234/t234_internal.h +++ b/drivers/tegra/hwpm/hal/t234/t234_internal.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -84,8 +84,11 @@ bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm, bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm, u32 res_enum, u32 *config_ip_index); -u32 t234_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm); -u32 t234_get_ip_max_idx(struct tegra_soc_hwpm *hwpm); +u32 t234_get_rtr_int_idx(void); +u32 t234_get_ip_max_idx(void); +int t234_hwpm_get_rtr_pma_perfmux_ptr(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_aperture **rtr_perfmux_ptr, + struct hwpm_ip_aperture **pma_perfmux_ptr); int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, u32 resource_enum, u64 base_address, @@ -111,7 +114,9 @@ int t234_hwpm_stream_mem_bytes(struct tegra_soc_hwpm *hwpm); int t234_hwpm_disable_pma_streaming(struct tegra_soc_hwpm *hwpm); int t234_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm, u64 mem_bump); -u64 t234_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm); -bool t234_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm); +int t234_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm, + u64 *mem_head_ptr); +int t234_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm, + u32 *overflow_status); #endif /* T234_HWPM_INTERNAL_H */ diff --git a/drivers/tegra/hwpm/hal/t234/t234_ip.c b/drivers/tegra/hwpm/hal/t234/t234_ip.c index ec319ba..60d41c1 100644 --- a/drivers/tegra/hwpm/hal/t234/t234_ip.c +++ b/drivers/tegra/hwpm/hal/t234/t234_ip.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -211,6 +211,7 @@ static int t234_hwpm_validate_emc_config(struct tegra_soc_hwpm *hwpm) #endif u32 emc_disable_fuse_val = 0U; u32 emc_disable_fuse_val_mask = 0xFU; + u32 emc_disable_fuse_bit_idx = 0U; u32 emc_element_floorsweep_mask = 0U; u32 idx = 0U; int err; @@ -235,16 +236,16 @@ static int t234_hwpm_validate_emc_config(struct tegra_soc_hwpm *hwpm) * Convert floorsweep fuse value to available EMC elements. */ do { - if (emc_disable_fuse_val & 0x1U) { - emc_element_floorsweep_mask = - (emc_element_floorsweep_mask << 4U) | 0xFU; + if (emc_disable_fuse_val & (0x1U << emc_disable_fuse_bit_idx)) { + emc_element_floorsweep_mask |= + (0xFU << (emc_disable_fuse_bit_idx * 4U)); } - emc_disable_fuse_val = (emc_disable_fuse_val >> 1U); + emc_disable_fuse_bit_idx++; emc_disable_fuse_val_mask = (emc_disable_fuse_val_mask >> 1U); } while (emc_disable_fuse_val_mask != 0U); /* Set fuse value in MSS IP instances */ - for (idx = 0U; idx < active_chip->get_ip_max_idx(hwpm); idx++) { + for (idx = 0U; idx < active_chip->get_ip_max_idx(); idx++) { switch (idx) { #if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL) case T234_HWPM_IP_MSS_CHANNEL: @@ -362,7 +363,7 @@ int t234_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm) return 0; } - for (idx = 0U; idx < active_chip->get_ip_max_idx(hwpm); idx++) { + for (idx = 0U; idx < active_chip->get_ip_max_idx(); idx++) { chip_ip = active_chip->chip_ips[idx]; if ((hwpm_global_disable != diff --git a/drivers/tegra/hwpm/hal/t234/t234_mem_mgmt.c b/drivers/tegra/hwpm/hal/t234/t234_mem_mgmt.c index ebe48c2..a5a71b0 100644 --- a/drivers/tegra/hwpm/hal/t234/t234_mem_mgmt.c +++ b/drivers/tegra/hwpm/hal/t234/t234_mem_mgmt.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,41 +33,23 @@ int t234_hwpm_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm) { int err = 0; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outbase_r(0), 0); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outbaseupper_r(0), 0); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outsize_r(0), 0); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_bytes_addr_r(0), 0); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -79,66 +61,46 @@ int t234_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm) u32 outbase_hi = 0; u32 outsize = 0; u64 mem_bytes_addr = 0ULL; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; struct tegra_hwpm_mem_mgmt *mem_mgmt = hwpm->mem_mgmt; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_fn(hwpm, " "); + outbase_lo = mem_mgmt->stream_buf_va & pmasys_channel_outbase_ptr_m(); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outbase_r(0), outbase_lo); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } tegra_hwpm_dbg(hwpm, hwpm_verbose, "OUTBASE = 0x%x", outbase_lo); outbase_hi = (mem_mgmt->stream_buf_va >> 32) & pmasys_channel_outbaseupper_ptr_m(); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outbaseupper_r(0), outbase_hi); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } tegra_hwpm_dbg(hwpm, hwpm_verbose, "OUTBASEUPPER = 0x%x", outbase_hi); outsize = mem_mgmt->stream_buf_size & pmasys_channel_outsize_numbytes_m(); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outsize_r(0), outsize); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } tegra_hwpm_dbg(hwpm, hwpm_verbose, "OUTSIZE = 0x%x", outsize); mem_bytes_addr = mem_mgmt->mem_bytes_buf_va & pmasys_channel_mem_bytes_addr_ptr_m(); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_bytes_addr_r(0), mem_bytes_addr); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } tegra_hwpm_dbg(hwpm, hwpm_verbose, "MEM_BYTES_ADDR = 0x%llx", (unsigned long long)mem_bytes_addr); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_block_r(0), pmasys_channel_mem_block_valid_f( pmasys_channel_mem_block_valid_true_v())); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -146,24 +108,18 @@ int t234_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm) int t234_hwpm_invalidate_mem_config(struct tegra_soc_hwpm *hwpm) { int err = 0; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_block_r(0), + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_block_r(0), pmasys_channel_mem_block_valid_f( pmasys_channel_mem_block_valid_false_v())); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -174,34 +130,24 @@ int t234_hwpm_stream_mem_bytes(struct tegra_soc_hwpm *hwpm) u32 reg_val = 0U; u32 *mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_mgmt->mem_bytes_kernel); - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + *mem_bytes_kernel_u32 = TEGRA_HWPM_MEM_BYTES_INVALID; - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_channel_control_user_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmasys_channel_control_user_update_bytes_m(), pmasys_channel_control_user_update_bytes_doit_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_control_user_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -210,49 +156,31 @@ int t234_hwpm_disable_pma_streaming(struct tegra_soc_hwpm *hwpm) { int err = 0; u32 reg_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + /* Disable PMA streaming */ - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_trigger_config_user_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmasys_trigger_config_user_record_stream_m(), pmasys_trigger_config_user_record_stream_disable_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_trigger_config_user_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_channel_control_user_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmasys_channel_control_user_stream_m(), pmasys_channel_control_user_stream_disable_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_control_user_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -261,81 +189,69 @@ int t234_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm, u64 mem_bump) { int err = 0; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + if (mem_bump > (u64)U32_MAX) { tegra_hwpm_err(hwpm, "mem_bump is out of bounds"); return -EINVAL; } - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_bump_r(0), mem_bump); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } -u64 t234_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm) +int t234_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm, + u64 *mem_head_ptr) { int err = 0; u32 reg_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_readl(hwpm, pma_perfmux, - pmasys_channel_mem_head_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return 0ULL; - } + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); - return (u64)reg_val; + tegra_hwpm_readl(hwpm, pma_perfmux, + pmasys_channel_mem_head_r(0), ®_val); + *mem_head_ptr = (u64)reg_val; + + return err; } -bool t234_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm) +int t234_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm, + u32 *overflow_status) { int err = 0; u32 reg_val, field_val; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - T234_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - T234_HWPM_IP_RTR_PERMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_readl(hwpm, pma_perfmux, + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_channel_status_secure_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } field_val = pmasys_channel_status_secure_membuf_status_v( reg_val); - return (field_val == - pmasys_channel_status_secure_membuf_status_overflowed_v()); + *overflow_status = (field_val == + pmasys_channel_status_secure_membuf_status_overflowed_v()) ? + TEGRA_HWPM_MEMBUF_OVERFLOWED : TEGRA_HWPM_MEMBUF_NOT_OVERFLOWED; + + return err; } diff --git a/drivers/tegra/hwpm/hal/t234/t234_resource.c b/drivers/tegra/hwpm/hal/t234/t234_resource.c index 5b7751c..17af535 100644 --- a/drivers/tegra/hwpm/hal/t234/t234_resource.c +++ b/drivers/tegra/hwpm/hal/t234/t234_resource.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,7 +33,6 @@ int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *perfmon) { - int err = 0; u32 reg_val; tegra_hwpm_fn(hwpm, " "); @@ -44,20 +43,12 @@ int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm, (unsigned long long)perfmon->start_abs_pa, (unsigned long long)perfmon->end_abs_pa); - err = tegra_hwpm_readl(hwpm, perfmon, + tegra_hwpm_readl(hwpm, perfmon, pmmsys_sys0_enginestatus_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0_enginestatus_enable_m(), pmmsys_sys0_enginestatus_enable_out_f()); - err = tegra_hwpm_writel(hwpm, perfmon, + tegra_hwpm_writel(hwpm, perfmon, pmmsys_sys0_enginestatus_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -65,7 +56,6 @@ int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm, int t234_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *perfmon) { - int err = 0; u32 reg_val; tegra_hwpm_fn(hwpm, " "); @@ -84,18 +74,10 @@ int t234_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm, (unsigned long long)perfmon->start_abs_pa, (unsigned long long)perfmon->end_abs_pa); - err = tegra_hwpm_readl(hwpm, perfmon, pmmsys_control_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + tegra_hwpm_readl(hwpm, perfmon, pmmsys_control_r(0), ®_val); reg_val = set_field(reg_val, pmmsys_control_mode_m(), pmmsys_control_mode_disable_f()); - err = tegra_hwpm_writel(hwpm, perfmon, pmmsys_control_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } + tegra_hwpm_writel(hwpm, perfmon, pmmsys_control_r(0), reg_val); return 0; } diff --git a/drivers/tegra/hwpm/hal/th500/soc/ip/rtr/th500_rtr.h b/drivers/tegra/hwpm/hal/th500/soc/ip/rtr/th500_rtr.h index a1029c0..a722dd3 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/ip/rtr/th500_rtr.h +++ b/drivers/tegra/hwpm/hal/th500/soc/ip/rtr/th500_rtr.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: MIT */ -/* SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -32,9 +33,10 @@ #define TH500_HWPM_IP_RTR_NUM_PERFMUX_PER_INST 1U #define TH500_HWPM_IP_RTR_NUM_BROADCAST_PER_INST 0U -#define TH500_HWPM_IP_RTR_STATIC_RTR_INST 0U -#define TH500_HWPM_IP_RTR_STATIC_PMA_INST 1U -#define TH500_HWPM_IP_RTR_PERFMUX_INDEX 0U +#define TH500_HWPM_IP_RTR_STATIC_RTR_INST 0U +#define TH500_HWPM_IP_RTR_STATIC_RTR_PERFMUX_INDEX 0U +#define TH500_HWPM_IP_RTR_STATIC_PMA_INST 1U +#define TH500_HWPM_IP_RTR_STATIC_PMA_PERFMUX_INDEX 0U extern struct hwpm_ip th500_hwpm_ip_rtr; diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_aperture.c b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_aperture.c index f9cc32c..ae2287b 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_aperture.c +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_aperture.c @@ -30,53 +30,62 @@ #include #include -int th500_hwpm_soc_check_status(struct tegra_soc_hwpm *hwpm) +int th500_hwpm_soc_get_rtr_pma_perfmux_ptr(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_aperture **rtr_perfmux_ptr, + struct hwpm_ip_aperture **pma_perfmux_ptr) { - int err = 0; - u32 reg_val = 0U; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; + active_chip->get_rtr_int_idx()]; struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ TH500_HWPM_IP_RTR_STATIC_RTR_INST]; struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + + if (rtr_perfmux_ptr != NULL) { + *rtr_perfmux_ptr = &ip_inst_rtr->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + TH500_HWPM_IP_RTR_STATIC_RTR_PERFMUX_INDEX]; + } + + if (pma_perfmux_ptr != NULL) { + *pma_perfmux_ptr = &ip_inst_pma->element_info[ + TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ + TH500_HWPM_IP_RTR_STATIC_PMA_PERFMUX_INDEX]; + } + + return 0; +} + +int th500_hwpm_soc_check_status(struct tegra_soc_hwpm *hwpm) +{ + int err = 0; + u32 reg_val = 0U; + struct hwpm_ip_aperture *rtr_perfmux = NULL; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - /* Check ROUTER state */ - err = tegra_hwpm_readl(hwpm, rtr_perfmux, - pmmsys_sys0router_enginestatus_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); - if (pmmsys_sys0router_enginestatus_status_v(reg_val) != - pmmsys_sys0router_enginestatus_status_empty_v()) { - tegra_hwpm_err(hwpm, "Router not ready value 0x%x", reg_val); - return -EINVAL; - } + /* Check ROUTER state */ + tegra_hwpm_readl(hwpm, rtr_perfmux, + pmmsys_sys0router_enginestatus_r(), ®_val); + hwpm_assert_print(hwpm, + pmmsys_sys0router_enginestatus_status_v(reg_val) == + pmmsys_sys0router_enginestatus_status_empty_v(), + return -EINVAL, "Router not ready value 0x%x", reg_val); /* Check PMA state */ - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_channel_status_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } - - if ((reg_val & pmasys_channel_status_engine_status_m()) != - pmasys_channel_status_engine_status_empty_f()) { - tegra_hwpm_err(hwpm, "PMA not ready value 0x%x", reg_val); - return -EINVAL; - } + hwpm_assert_print(hwpm, + ((reg_val & pmasys_channel_status_engine_status_m()) == + pmasys_channel_status_engine_status_empty_f()), + return -EINVAL, "PMA not ready value 0x%x", reg_val); return err; } @@ -85,118 +94,47 @@ int th500_hwpm_soc_disable_triggers(struct tegra_soc_hwpm *hwpm) { int err = 0; u32 reg_val = 0U; + u32 retries = 10U; u32 sleep_msecs = 100; - struct tegra_hwpm_timeout timeout; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_RTR_INST]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *rtr_perfmux = NULL; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + /* Disable PMA triggers */ - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_command_slice_trigger_config_user_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmasys_command_slice_trigger_config_user_pma_pulse_m(), pmasys_command_slice_trigger_config_user_pma_pulse_disable_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_command_slice_trigger_config_user_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } /* Wait for PERFMONs to idle */ - err = tegra_hwpm_timeout_init(hwpm, &timeout, 10U); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm timeout init failed"); - return err; - } - - do { - err = tegra_hwpm_readl(hwpm, rtr_perfmux, - pmmsys_sysrouter_enginestatus_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } - tegra_hwpm_msleep(sleep_msecs); - } while ((pmmsys_sysrouter_enginestatus_merged_perfmon_status_v( - reg_val) != 0U) && - (tegra_hwpm_timeout_expired(hwpm, &timeout) == 0)); - - if (pmmsys_sysrouter_enginestatus_merged_perfmon_status_v( - reg_val) != 0U) { - tegra_hwpm_err(hwpm, "Timeout expired for " - "NV_PERF_PMMSYS_SYSROUTER_ENGINESTATUS_PERFMON_STATUS"); - return -ETIMEDOUT; - } + tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, rtr_perfmux, + pmmsys_sysrouter_enginestatus_r(), ®_val, + (pmmsys_sysrouter_enginestatus_merged_perfmon_status_v( + reg_val) != 0U), + "PMMSYS_SYSROUTER_ENGINESTATUS_PERFMON_STATUS timed out"); /* Wait for ROUTER to idle */ - err = tegra_hwpm_timeout_init(hwpm, &timeout, 10U); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm timeout init failed"); - return err; - } - - do { - err = tegra_hwpm_readl(hwpm, rtr_perfmux, - pmmsys_sys0router_enginestatus_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } - tegra_hwpm_msleep(sleep_msecs); - } while ((pmmsys_sys0router_enginestatus_status_v(reg_val) != - pmmsys_sys0router_enginestatus_status_empty_v()) && - (tegra_hwpm_timeout_expired(hwpm, &timeout) == 0)); - - if (pmmsys_sys0router_enginestatus_status_v(reg_val) != - pmmsys_sys0router_enginestatus_status_empty_v()) { - tegra_hwpm_err(hwpm, "Timeout expired for " - "NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS"); - return -ETIMEDOUT; - } + tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, rtr_perfmux, + pmmsys_sys0router_enginestatus_r(), ®_val, + (pmmsys_sys0router_enginestatus_status_v(reg_val) != + pmmsys_sys0router_enginestatus_status_empty_v()), + "PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS timed out"); /* Wait for PMA to idle */ - err = tegra_hwpm_timeout_init(hwpm, &timeout, 10U); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm timeout init failed"); - return err; - } - - do { - err = tegra_hwpm_readl(hwpm, pma_perfmux, - pmasys_channel_status_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } - tegra_hwpm_msleep(sleep_msecs); - } while (((reg_val & pmasys_channel_status_engine_status_m()) != - pmasys_channel_status_engine_status_empty_f()) && - (tegra_hwpm_timeout_expired(hwpm, &timeout) == 0)); - - if ((reg_val & pmasys_channel_status_engine_status_m()) != - pmasys_channel_status_engine_status_empty_f()) { - tegra_hwpm_err(hwpm, "Timeout expired for " - "NV_PERF_PMASYS_CHANNEL_STATUS"); - return -ETIMEDOUT; - } + tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, rtr_perfmux, + pmasys_channel_status_r(0), ®_val, + ((reg_val & pmasys_channel_status_engine_status_m()) != + pmasys_channel_status_engine_status_empty_f()), + "PMASYS_CHANNEL_STATUS timed out"); return err; } @@ -205,82 +143,44 @@ int th500_hwpm_soc_init_prod_values(struct tegra_soc_hwpm *hwpm) { int err = 0; u32 reg_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_RTR_INST]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *rtr_perfmux = NULL; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_readl(hwpm, pma_perfmux, + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_channel_config_user_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmasys_channel_config_user_coalesce_timeout_cycles_m(), pmasys_channel_config_user_coalesce_timeout_cycles__prod_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_config_user_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); reg_val = set_field(reg_val, pmasys_cg2_slcg_m(), pmasys_cg2_slcg__prod_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_cg1_secure_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0router_cg1_secure_flcg_perfmon_m(), pmmsys_sys0router_cg1_secure_flcg_perfmon__prod_f()); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_cg1_secure_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_perfmon_cg2_secure_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0router_perfmon_cg2_secure_slcg_m(), pmmsys_sys0router_perfmon_cg2_secure_slcg__prod_f()); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_perfmon_cg2_secure_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -289,80 +189,44 @@ int th500_hwpm_soc_disable_cg(struct tegra_soc_hwpm *hwpm) { int err = 0; u32 reg_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_RTR_INST]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *rtr_perfmux = NULL; + struct hwpm_ip_aperture *pma_perfmux = NULL; - err = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + tegra_hwpm_fn(hwpm, " "); + + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); reg_val = set_field(reg_val, pmasys_cg2_slcg_m(), pmasys_cg2_slcg_disabled_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_cg1_secure_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0router_cg1_secure_flcg_perfmon_m(), pmmsys_sys0router_cg1_secure_flcg_perfmon_disabled_f()); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_cg1_secure_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_perfmon_cg2_secure_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0router_perfmon_cg2_secure_slcg_m(), pmmsys_sys0router_perfmon_cg2_secure_slcg_disabled_f()); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_perfmon_cg2_secure_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_cg2_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0router_cg2_slcg_m(), pmmsys_sys0router_cg2_slcg_disabled_f()); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_cg2_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -371,80 +235,44 @@ int th500_hwpm_soc_enable_cg(struct tegra_soc_hwpm *hwpm) { int err = 0; u32 reg_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_RTR_INST]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *rtr_perfmux = &ip_inst_rtr->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *rtr_perfmux = NULL; + struct hwpm_ip_aperture *pma_perfmux = NULL; - err = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + tegra_hwpm_fn(hwpm, " "); + + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r(), ®_val); reg_val = set_field(reg_val, pmasys_cg2_slcg_m(), pmasys_cg2_slcg_enabled_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_cg2_r(), reg_val); - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_cg1_secure_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0router_cg1_secure_flcg_perfmon_m(), pmmsys_sys0router_cg1_secure_flcg_perfmon_enabled_f()); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_cg1_secure_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_perfmon_cg2_secure_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0router_perfmon_cg2_secure_slcg_m(), pmmsys_sys0router_perfmon_cg2_secure_slcg_enabled_f()); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_perfmon_cg2_secure_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_readl(hwpm, rtr_perfmux, + tegra_hwpm_readl(hwpm, rtr_perfmux, pmmsys_sys0router_cg2_r(), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0router_cg2_slcg_m(), pmmsys_sys0router_cg2_slcg_enabled_f()); - err = tegra_hwpm_writel(hwpm, rtr_perfmux, + tegra_hwpm_writel(hwpm, rtr_perfmux, pmmsys_sys0router_cg2_r(), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_internal.h b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_internal.h index 4b73140..3cb7e37 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_internal.h +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_internal.h @@ -34,6 +34,10 @@ int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm, int th500_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm); int th500_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm); +int th500_hwpm_soc_get_rtr_pma_perfmux_ptr(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_aperture **rtr_perfmux_ptr, + struct hwpm_ip_aperture **pma_perfmux_ptr); + int th500_hwpm_soc_init_prod_values(struct tegra_soc_hwpm *hwpm); int th500_hwpm_soc_disable_cg(struct tegra_soc_hwpm *hwpm); int th500_hwpm_soc_enable_cg(struct tegra_soc_hwpm *hwpm); @@ -52,7 +56,9 @@ int th500_hwpm_soc_stream_mem_bytes(struct tegra_soc_hwpm *hwpm); int th500_hwpm_soc_disable_pma_streaming(struct tegra_soc_hwpm *hwpm); int th500_hwpm_soc_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm, u64 mem_bump); -u64 th500_hwpm_soc_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm); -bool th500_hwpm_soc_membuf_overflow_status(struct tegra_soc_hwpm *hwpm); +int th500_hwpm_soc_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm, + u64 *mem_head_ptr); +int th500_hwpm_soc_membuf_overflow_status(struct tegra_soc_hwpm *hwpm, + u32 *overflow_status); #endif /* TH500_HWPM_SOC_INTERNAL_H */ diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_mem_mgmt.c b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_mem_mgmt.c index 510cd2d..21b2e34 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_mem_mgmt.c +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_mem_mgmt.c @@ -32,41 +32,23 @@ int th500_hwpm_soc_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm) { int err = 0; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outbase_r(0), 0); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outbaseupper_r(0), 0); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outsize_r(0), 0); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_bytes_addr_r(0), 0); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -78,65 +60,44 @@ int th500_hwpm_soc_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm) u32 outbase_hi = 0; u32 outsize = 0; u32 mem_bytes_addr = 0; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; struct tegra_hwpm_mem_mgmt *mem_mgmt = hwpm->mem_mgmt; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + outbase_lo = mem_mgmt->stream_buf_va & pmasys_channel_outbase_ptr_m(); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outbase_r(0), outbase_lo); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } tegra_hwpm_dbg(hwpm, hwpm_verbose, "OUTBASE = 0x%x", outbase_lo); outbase_hi = (mem_mgmt->stream_buf_va >> 32) & pmasys_channel_outbaseupper_ptr_m(); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outbaseupper_r(0), outbase_hi); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } tegra_hwpm_dbg(hwpm, hwpm_verbose, "OUTBASEUPPER = 0x%x", outbase_hi); outsize = mem_mgmt->stream_buf_size & pmasys_channel_outsize_numbytes_m(); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_outsize_r(0), outsize); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } tegra_hwpm_dbg(hwpm, hwpm_verbose, "OUTSIZE = 0x%x", outsize); mem_bytes_addr = mem_mgmt->mem_bytes_buf_va & pmasys_channel_mem_bytes_addr_ptr_m(); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_bytes_addr_r(0), mem_bytes_addr); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } tegra_hwpm_dbg(hwpm, hwpm_verbose, "MEM_BYTES_ADDR = 0x%x", mem_bytes_addr); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_block_r(0), pmasys_channel_mem_blockupper_valid_f( pmasys_channel_mem_blockupper_valid_true_v())); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -144,23 +105,18 @@ int th500_hwpm_soc_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm) int th500_hwpm_soc_invalidate_mem_config(struct tegra_soc_hwpm *hwpm) { int err = 0; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_block_r(0), + + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_block_r(0), pmasys_channel_mem_blockupper_valid_f( pmasys_channel_mem_blockupper_valid_false_v())); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -171,34 +127,24 @@ int th500_hwpm_soc_stream_mem_bytes(struct tegra_soc_hwpm *hwpm) u32 reg_val = 0U; u32 *mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_mgmt->mem_bytes_kernel); - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + *mem_bytes_kernel_u32 = TEGRA_HWPM_MEM_BYTES_INVALID; - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_channel_control_user_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmasys_channel_control_user_update_bytes_m(), pmasys_channel_control_user_update_bytes_doit_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_control_user_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -207,49 +153,31 @@ int th500_hwpm_soc_disable_pma_streaming(struct tegra_soc_hwpm *hwpm) { int err = 0; u32 reg_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + /* Disable PMA streaming */ - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_command_slice_trigger_config_user_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmasys_command_slice_trigger_config_user_record_stream_m(), pmasys_command_slice_trigger_config_user_record_stream_disable_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_command_slice_trigger_config_user_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } - err = tegra_hwpm_readl(hwpm, pma_perfmux, + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_channel_control_user_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmasys_channel_config_user_stream_m(), pmasys_channel_config_user_stream_disable_f()); - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_control_user_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -258,81 +186,69 @@ int th500_hwpm_soc_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm, u64 mem_bump) { int err = 0; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + if (mem_bump > (u64)U32_MAX) { tegra_hwpm_err(hwpm, "mem_bump is out of bounds"); return -EINVAL; } - err = tegra_hwpm_writel(hwpm, pma_perfmux, + tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_bump_r(0), mem_bump); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } -u64 th500_hwpm_soc_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm) +int th500_hwpm_soc_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm, + u64 *mem_head_ptr) { int err = 0; u32 reg_val = 0U; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_readl(hwpm, pma_perfmux, - pmasys_channel_mem_head_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return 0ULL; - } + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); - return (u64)reg_val; + tegra_hwpm_readl(hwpm, pma_perfmux, + pmasys_channel_mem_head_r(0), ®_val); + *mem_head_ptr = (u64)reg_val; + + return err; } -bool th500_hwpm_soc_membuf_overflow_status(struct tegra_soc_hwpm *hwpm) +int th500_hwpm_soc_membuf_overflow_status(struct tegra_soc_hwpm *hwpm, + u32 *overflow_status) { int err = 0; u32 reg_val, field_val; - struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; - struct hwpm_ip *chip_ip = active_chip->chip_ips[ - active_chip->get_rtr_int_idx(hwpm)]; - struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[ - TH500_HWPM_IP_RTR_STATIC_PMA_INST]; - struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[ - TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[ - TH500_HWPM_IP_RTR_PERFMUX_INDEX]; + struct hwpm_ip_aperture *pma_perfmux = NULL; tegra_hwpm_fn(hwpm, " "); - err = tegra_hwpm_readl(hwpm, pma_perfmux, + err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, + &pma_perfmux); + hwpm_assert_print(hwpm, err == 0, return err, + "get rtr pma perfmux failed"); + + tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_channel_status_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } field_val = pmasys_channel_status_membuf_status_v( reg_val); - return (field_val == - pmasys_channel_status_membuf_status_overflowed_v()); + *overflow_status = (field_val == + pmasys_channel_status_membuf_status_overflowed_v()) ? + TEGRA_HWPM_MEMBUF_OVERFLOWED : TEGRA_HWPM_MEMBUF_NOT_OVERFLOWED; + + return err; } diff --git a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_resource.c b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_resource.c index 14f960f..4751b83 100644 --- a/drivers/tegra/hwpm/hal/th500/soc/th500_soc_resource.c +++ b/drivers/tegra/hwpm/hal/th500/soc/th500_soc_resource.c @@ -32,7 +32,6 @@ int th500_hwpm_soc_perfmon_enable(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *perfmon) { - int err = 0; u32 reg_val; tegra_hwpm_fn(hwpm, " "); @@ -42,20 +41,12 @@ int th500_hwpm_soc_perfmon_enable(struct tegra_soc_hwpm *hwpm, "Enabling PERFMON(0x%llx - 0x%llx)", perfmon->start_abs_pa, perfmon->end_abs_pa); - err = tegra_hwpm_readl(hwpm, perfmon, + tegra_hwpm_readl(hwpm, perfmon, pmmsys_sys0_enginestatus_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } reg_val = set_field(reg_val, pmmsys_sys0_enginestatus_enable_m(), pmmsys_sys0_enginestatus_enable_out_f()); - err = tegra_hwpm_writel(hwpm, perfmon, + tegra_hwpm_writel(hwpm, perfmon, pmmsys_sys0_enginestatus_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } return 0; } @@ -63,7 +54,6 @@ int th500_hwpm_soc_perfmon_enable(struct tegra_soc_hwpm *hwpm, int th500_hwpm_soc_perfmon_disable(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_aperture *perfmon) { - int err = 0; u32 reg_val; tegra_hwpm_fn(hwpm, " "); @@ -81,18 +71,10 @@ int th500_hwpm_soc_perfmon_disable(struct tegra_soc_hwpm *hwpm, "Disabling PERFMON(0x%llx - 0x%llx)", perfmon->start_abs_pa, perfmon->end_abs_pa); - err = tegra_hwpm_readl(hwpm, perfmon, pmmsys_control_r(0), ®_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm read failed"); - return err; - } + tegra_hwpm_readl(hwpm, perfmon, pmmsys_control_r(0), ®_val); reg_val = set_field(reg_val, pmmsys_control_mode_m(), pmmsys_control_mode_disable_f()); - err = tegra_hwpm_writel(hwpm, perfmon, pmmsys_control_r(0), reg_val); - if (err != 0) { - tegra_hwpm_err(hwpm, "hwpm write failed"); - return err; - } + tegra_hwpm_writel(hwpm, perfmon, pmmsys_control_r(0), reg_val); return 0; } diff --git a/drivers/tegra/hwpm/hal/th500/th500_interface.c b/drivers/tegra/hwpm/hal/th500/th500_interface.c index 5a785ef..007fab8 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_interface.c +++ b/drivers/tegra/hwpm/hal/th500/th500_interface.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -46,6 +46,7 @@ static struct tegra_soc_hwpm_chip th500_chip_info = { .get_rtr_int_idx = th500_get_rtr_int_idx, .get_ip_max_idx = th500_get_ip_max_idx, + .get_rtr_pma_perfmux_ptr = th500_hwpm_soc_get_rtr_pma_perfmux_ptr, .extract_ip_ops = th500_hwpm_extract_ip_ops, .force_enable_ips = th500_hwpm_force_enable_ips, @@ -259,12 +260,12 @@ bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm, return (config_ip != TEGRA_HWPM_IP_INACTIVE); } -u32 th500_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm) +u32 th500_get_rtr_int_idx(void) { return TH500_HWPM_IP_RTR; } -u32 th500_get_ip_max_idx(struct tegra_soc_hwpm *hwpm) +u32 th500_get_ip_max_idx(void) { return TH500_HWPM_IP_MAX; } diff --git a/drivers/tegra/hwpm/hal/th500/th500_internal.h b/drivers/tegra/hwpm/hal/th500/th500_internal.h index a343fa2..9c8302e 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_internal.h +++ b/drivers/tegra/hwpm/hal/th500/th500_internal.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: MIT */ -/* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +/* SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -52,7 +52,7 @@ bool th500_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm, bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm, u32 res_index, u32 *config_ip_index); -u32 th500_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm); -u32 th500_get_ip_max_idx(struct tegra_soc_hwpm *hwpm); +u32 th500_get_rtr_int_idx(void); +u32 th500_get_ip_max_idx(void); #endif /* TH500_HWPM_INTERNAL_H */ diff --git a/drivers/tegra/hwpm/hal/th500/th500_ip.c b/drivers/tegra/hwpm/hal/th500/th500_ip.c index 69052a5..2485516 100644 --- a/drivers/tegra/hwpm/hal/th500/th500_ip.c +++ b/drivers/tegra/hwpm/hal/th500/th500_ip.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: MIT -/* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +/* SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -343,7 +343,7 @@ int th500_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm) return 0; } - for (idx = 0U; idx < active_chip->get_ip_max_idx(hwpm); idx++) { + for (idx = 0U; idx < active_chip->get_ip_max_idx(); idx++) { chip_ip = active_chip->chip_ips[idx]; if ((hwpm_global_disable != diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h index bef1759..7874a50 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -451,8 +451,11 @@ struct tegra_soc_hwpm_chip { bool (*is_resource_active)(struct tegra_soc_hwpm *hwpm, u32 res_enum, u32 *config_ip_index); - u32 (*get_rtr_int_idx)(struct tegra_soc_hwpm *hwpm); - u32 (*get_ip_max_idx)(struct tegra_soc_hwpm *hwpm); + int (*get_rtr_pma_perfmux_ptr)(struct tegra_soc_hwpm *hwpm, + struct hwpm_ip_aperture **rtr_perfmux_ptr, + struct hwpm_ip_aperture **pma_perfmux_ptr); + u32 (*get_rtr_int_idx)(void); + u32 (*get_ip_max_idx)(void); int (*extract_ip_ops)(struct tegra_soc_hwpm *hwpm, u32 resource_enum, u64 base_address, @@ -487,8 +490,10 @@ struct tegra_soc_hwpm_chip { int (*disable_pma_streaming)(struct tegra_soc_hwpm *hwpm); int (*update_mem_bytes_get_ptr)(struct tegra_soc_hwpm *hwpm, u64 mem_bump); - u64 (*get_mem_bytes_put_ptr)(struct tegra_soc_hwpm *hwpm); - bool (*membuf_overflow_status)(struct tegra_soc_hwpm *hwpm); + int (*get_mem_bytes_put_ptr)(struct tegra_soc_hwpm *hwpm, + u64 *mem_head_ptr); + int (*membuf_overflow_status)(struct tegra_soc_hwpm *hwpm, + u32 *overflow_status); size_t (*get_alist_buf_size)(struct tegra_soc_hwpm *hwpm); int (*zero_alist_regs)(struct tegra_soc_hwpm *hwpm, diff --git a/drivers/tegra/hwpm/include/tegra_hwpm_io.h b/drivers/tegra/hwpm/include/tegra_hwpm_io.h index caff55a..68d49cb 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm_io.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm_io.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -24,7 +24,8 @@ #ifndef TEGRA_HWPM_IO_H #define TEGRA_HWPM_IO_H -#include "tegra_hwpm_types.h" +#include +#include /** * Sets a particular field value in input data. @@ -76,11 +77,17 @@ static inline u32 get_field(u32 input_data, u32 mask) #define tegra_hwpm_fake_writel(hwpm, aperture, addr, val) \ tegra_hwpm_fake_writel_impl(hwpm, aperture, addr, val) -#define tegra_hwpm_readl(hwpm, aperture, addr, val) \ - tegra_hwpm_readl_impl(hwpm, aperture, addr, val) +#define tegra_hwpm_readl(hwpm, aperture, addr, val) ({ \ + int err = tegra_hwpm_readl_impl(hwpm, aperture, addr, val); \ + hwpm_assert_print(hwpm, err == 0, return err, \ + "hwpm read addr 0x%lx failed", (u64)addr); \ + }) -#define tegra_hwpm_writel(hwpm, aperture, addr, val) \ - tegra_hwpm_writel_impl(hwpm, aperture, addr, val) +#define tegra_hwpm_writel(hwpm, aperture, addr, val)({ \ + int err = tegra_hwpm_writel_impl(hwpm, aperture, addr, val); \ + hwpm_assert_print(hwpm, err == 0, return err, \ + "hwpm write addr 0x%lx failed", (u64)addr); \ + }) #define tegra_hwpm_regops_readl(hwpm, ip_inst, aperture, addr, val) \ tegra_hwpm_regops_readl_impl(hwpm, ip_inst, aperture, addr, val) diff --git a/drivers/tegra/hwpm/include/tegra_hwpm_log.h b/drivers/tegra/hwpm/include/tegra_hwpm_log.h index 4f7006c..d669208 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm_log.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm_log.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -93,4 +93,12 @@ enum tegra_soc_hwpm_log_type { tegra_hwpm_dbg_impl(hwpm, hwpm_fn, fmt, ##arg) #endif +#define hwpm_assert_print(hwpm, cond, bail_out_code, fmt, arg...) \ + do { \ + if (!(cond)) { \ + tegra_hwpm_err(hwpm, fmt, ##arg); \ + bail_out_code; \ + } \ + } while (0) + #endif /* TEGRA_HWPM_LOG_H */ diff --git a/drivers/tegra/hwpm/include/tegra_hwpm_mem_mgmt.h b/drivers/tegra/hwpm/include/tegra_hwpm_mem_mgmt.h index f4b812f..b540b04 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm_mem_mgmt.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm_mem_mgmt.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -30,4 +30,7 @@ #include #endif +#define TEGRA_HWPM_MEMBUF_NOT_OVERFLOWED 0U +#define TEGRA_HWPM_MEMBUF_OVERFLOWED 1U + #endif /* TEGRA_HWPM_MEM_MGMT_H */ diff --git a/drivers/tegra/hwpm/include/tegra_hwpm_timers.h b/drivers/tegra/hwpm/include/tegra_hwpm_timers.h index 93f99ab..06a5494 100644 --- a/drivers/tegra/hwpm/include/tegra_hwpm_timers.h +++ b/drivers/tegra/hwpm/include/tegra_hwpm_timers.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ #define TEGRA_HWPM_TIMERS_H #include +#include #ifdef __KERNEL__ #include @@ -39,4 +40,21 @@ #define tegra_hwpm_msleep(msecs) \ tegra_hwpm_msleep_impl(msecs) +#define tegra_hwpm_timeout_print(hwpm, retries, sleep_ms, \ + aperture, reg, reg_val, check, fmt, arg...) ({ \ + int err = 0; \ + struct tegra_hwpm_timeout timeout; \ + \ + err = tegra_hwpm_timeout_init(hwpm, &timeout, retries); \ + hwpm_assert_print(hwpm, err == 0, return err, \ + "hwpm timeout init failed"); \ + \ + do { \ + tegra_hwpm_readl(hwpm, aperture, reg, reg_val); \ + tegra_hwpm_msleep(sleep_msecs); \ + } while ((check) && (tegra_hwpm_timeout_expired(hwpm, &timeout) == 0)); \ + \ + hwpm_assert_print(hwpm, !(check), return -ETIMEDOUT, fmt, ##arg); \ +}) + #endif /* TEGRA_HWPM_TIMERS_H */ diff --git a/drivers/tegra/hwpm/os/linux/io_utils.c b/drivers/tegra/hwpm/os/linux/io_utils.c index 266de61..fb90f23 100644 --- a/drivers/tegra/hwpm/os/linux/io_utils.c +++ b/drivers/tegra/hwpm/os/linux/io_utils.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -190,7 +190,8 @@ static int hwpm_readl(struct tegra_soc_hwpm *hwpm, } else { if (aperture->dt_mmio == NULL) { tegra_hwpm_err(hwpm, - "aperture is not iomapped as expected"); + "aperture (0x%llx-0x%llx) not iomapped", + aperture->start_abs_pa, aperture->end_abs_pa); return -ENODEV; } diff --git a/drivers/tegra/hwpm/os/linux/mem_mgmt_utils.c b/drivers/tegra/hwpm/os/linux/mem_mgmt_utils.c index d7f3acf..6785015 100644 --- a/drivers/tegra/hwpm/os/linux/mem_mgmt_utils.c +++ b/drivers/tegra/hwpm/os/linux/mem_mgmt_utils.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -360,7 +360,8 @@ fail: int tegra_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm, struct tegra_soc_hwpm_update_get_put *update_get_put) { - int ret; + int ret = 0; + u32 overflowed_status = 0U; tegra_hwpm_fn(hwpm, " "); @@ -382,7 +383,7 @@ int tegra_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm, update_get_put->mem_bump); if (ret != 0) { tegra_hwpm_err(hwpm, "Failed to update mem_bytes get ptr"); - return -EINVAL; + return ret; } /* Stream MEM_BYTES value to MEM_BYTES buffer */ @@ -396,16 +397,25 @@ int tegra_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm, /* Read HW put pointer */ if (update_get_put->b_read_mem_head) { - update_get_put->mem_head = - hwpm->active_chip->get_mem_bytes_put_ptr(hwpm); + ret = hwpm->active_chip->get_mem_bytes_put_ptr(hwpm, + &update_get_put->mem_head); + if (ret != 0) { + tegra_hwpm_err(hwpm, "Failed to get mem_bytes put ptr"); + return ret; + } tegra_hwpm_dbg(hwpm, hwpm_dbg_update_get_put, "MEM_HEAD = 0x%llx", update_get_put->mem_head); } /* Check overflow error status */ if (update_get_put->b_check_overflow) { - update_get_put->b_overflowed = - (u8) hwpm->active_chip->membuf_overflow_status(hwpm); + ret = hwpm->active_chip->membuf_overflow_status(hwpm, + &overflowed_status); + if (ret != 0) { + tegra_hwpm_err(hwpm, "Failed to get overflow status"); + return ret; + } + update_get_put->b_overflowed = (u8) overflowed_status; tegra_hwpm_dbg(hwpm, hwpm_dbg_update_get_put, "OVERFLOWED = %u", update_get_put->b_overflowed); } diff --git a/drivers/tegra/hwpm/os/linux/mem_mgmt_utils.h b/drivers/tegra/hwpm/os/linux/mem_mgmt_utils.h index 158f33d..52751db 100644 --- a/drivers/tegra/hwpm/os/linux/mem_mgmt_utils.h +++ b/drivers/tegra/hwpm/os/linux/mem_mgmt_utils.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,7 +17,9 @@ #ifndef TEGRA_HWPM_OS_LINUX_MEM_MGMT_UTILS_H #define TEGRA_HWPM_OS_LINUX_MEM_MGMT_UTILS_H +#ifdef CONFIG_TEGRA_HWPM_OOT #include +#endif #include #include