nv-tegra-mirror/linux-hwpm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-hwpm.git synced 2025-12-22 09:12:05 +03:00
Code Issues Packages Projects Releases Wiki Activity

tegra: hwpm: add test for NVTHERM, CSN, IPMU

Browse Source 
Add mode B and E test for these IPS:
- NVTHERM
- CSN
- IPMU

JIRA MSST-831

Change-Id: If67ed0ab41f1ee4369311261ce73d5a0643326bb
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3341509
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Yifei Wan <ywan@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
This commit is contained in:
Besar Wicaksono
2025-04-15 21:23:36 +00:00
committed by mobile promotions
parent 4d309240ac
commit dbbd871203
2 changed files with 590 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files

681
libnvsochwpm/test/t410_test.cpp
View File

@@ -1,17 +1,22 @@
/* /* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * SPDX-License-Identifier: GPL-2.0-only
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* *
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto. Any use, reproduction, disclosure or
* distribution of this software and related documentation without an express
* license agreement from NVIDIA CORPORATION is strictly prohibited.
*/ */
#include "t410_test.h" #include "t410_test.h"
#include "soc_mode_e_buffer.h" #include "soc_mode_e_buffer.h"
#include "common/register_util.h" #include "common/register_util.h"
#include "tb500/nv_ref_dev_perf.h" #include "tb500/nv_ref_dev_perf.h"
#include "tb500/address_map_new.h"
#include "ip_names.h" #include "ip_names.h"
#include <unistd.h> #include <unistd.h>
@@ -174,7 +179,7 @@ TEST_F(T410Tests, EnumerateIPsNegative)
for (j = 0; j < ip_count; j++) { for (j = 0; j < ip_count; j++) {
cur_ip = ip[j]; cur_ip = ip[j];
printf("\t%d - ip id = %u, name: %s", j, cur_ip, kIpNames[cur_ip]); printf("\t%d - ip id = %u, name: %s\n", j, cur_ip, kIpNames[cur_ip]);
// Should fail with invalid attribute. // Should fail with invalid attribute.
ip_attr = (nv_soc_hwpm_ip_attribute)0xffffffff; ip_attr = (nv_soc_hwpm_ip_attribute)0xffffffff;
@@ -188,7 +193,7 @@ TEST_F(T410Tests, EnumerateIPsNegative)
// Should fail with invalid buffer size. // Should fail with invalid buffer size.
ASSERT_NE(0, ASSERT_NE(0,
api_table.nv_soc_hwpm_ip_get_info_fn( api_table.nv_soc_hwpm_ip_get_info_fn(
dev, cur_ip, ip_attr, sizeof(uint8_t), &fs_mask)); dev, cur_ip, ip_attr, 0, &fs_mask));
// Should fail with invalid buffer ptr. // Should fail with invalid buffer ptr.
ASSERT_NE(0, ASSERT_NE(0,
@@ -291,7 +296,7 @@ TEST_F(T410Tests, EnumerateResourcesNegative)
for (j = 0; j < res_count; j++) { for (j = 0; j < res_count; j++) {
cur_res = res[j]; cur_res = res[j];
printf("\t%d - res id = %u, name: %s", printf("\t%d - res id = %u, name: %s\n",
j, cur_res, kResourceNames[cur_res]); j, cur_res, kResourceNames[cur_res]);
// Should fail with invalid attribute. // Should fail with invalid attribute.
@@ -565,6 +570,8 @@ TEST_F(T410Tests, SessionAllocPma)
{ {
uint32_t i; uint32_t i;
nv_soc_hwpm_device dev; nv_soc_hwpm_device dev;
nv_soc_hwpm_device_attribute dev_attr;
tegra_soc_hwpm_platform platform;
nv_soc_hwpm_session session; nv_soc_hwpm_session session;
nv_soc_hwpm_session_attribute session_attr; nv_soc_hwpm_session_attribute session_attr;
@@ -574,9 +581,20 @@ TEST_F(T410Tests, SessionAllocPma)
printf("Device %d:\n", i); printf("Device %d:\n", i);
dev = t410_dev[i]; dev = t410_dev[i];
dev_attr = NV_SOC_HWPM_DEVICE_ATTRIBUTE_SOC_PLATFORM;
ASSERT_EQ(0,
api_table.nv_soc_hwpm_device_get_info_fn(
dev, dev_attr, sizeof(platform), &platform));
// Maximum CMA size for NVIDIA config is 1024MB. // Maximum CMA size for NVIDIA config is 1024MB.
static const uint32_t kNumSizes = 3; static const uint32_t kNumSizes = 3;
static const uint32_t kSizes[kNumSizes] = {64 *1024, 256 * 1024, 768 * 1024}; static const uint32_t kSiliconSizes[kNumSizes] = {64 *1024, 256 * 1024, 768 * 1024};
static const uint32_t kPresiSizes[kNumSizes] = {16 *1024, 32 * 1024, 64 * 1024};
const uint32_t* kSizes =
(platform == TEGRA_SOC_HWPM_PLATFORM_SILICON) ?
kSiliconSizes : kPresiSizes;
for (uint32_t j = 0; j < kNumSizes; j++) { for (uint32_t j = 0; j < kNumSizes; j++) {
printf("PMA size: %u\n", kSizes[j]); printf("PMA size: %u\n", kSizes[j]);
@@ -941,17 +959,19 @@ void T410Tests::TestRegopsRead(nv_soc_hwpm_session session,
// Verify the register value. // Verify the register value.
printf("streaming cap: 0x%x\n", reg_ops_params[0].in_out_val32); printf("streaming cap: 0x%x\n", reg_ops_params[0].in_out_val32);
ASSERT_EQ(0x0000224U, reg_ops_params[0].in_out_val32); // TODO: update this value from Rahul.
// My understanding this should be 0x224 (2 BLOCKs), but it is 0x424 (4 BLOCKs) on FPGA.
EXPECT_EQ(0x0000424U, reg_ops_params[0].in_out_val32);
printf("pma_record_buffer_pma_va: 0x%lx\n", pma_record_buffer_pma_va); printf("pma_record_buffer_pma_va: 0x%lx\n", pma_record_buffer_pma_va);
printf("stream buf base lo: 0x%x\n", reg_ops_params[1].in_out_val32); printf("stream buf base lo: 0x%x\n", reg_ops_params[1].in_out_val32);
ASSERT_EQ(pma_record_buffer_pma_va & 0xffffffffULL, reg_ops_params[1].in_out_val32); EXPECT_EQ(pma_record_buffer_pma_va & 0xffffffffULL, reg_ops_params[1].in_out_val32);
printf("stream buf base hi: 0x%x\n", reg_ops_params[2].in_out_val32); printf("stream buf base hi: 0x%x\n", reg_ops_params[2].in_out_val32);
ASSERT_EQ(pma_record_buffer_pma_va >> 32, reg_ops_params[2].in_out_val32); EXPECT_EQ(pma_record_buffer_pma_va >> 32, reg_ops_params[2].in_out_val32);
printf("stream buf size: 0x%x\n", reg_ops_params[3].in_out_val32); printf("stream buf size: 0x%x\n", reg_ops_params[3].in_out_val32);
ASSERT_EQ(record_buffer_size, reg_ops_params[3].in_out_val32); EXPECT_EQ(record_buffer_size, reg_ops_params[3].in_out_val32);
} }
void T410Tests::TestRegopsWrite(nv_soc_hwpm_session session) void T410Tests::TestRegopsWrite(nv_soc_hwpm_session session)
@@ -1209,15 +1229,19 @@ void T410Tests::EnablePmaStreaming(nv_soc_hwpm_session session, const PmaConfigu
#define NV_PERF_PMMSYS_SYS0_SIGVAL_ONE 1 #define NV_PERF_PMMSYS_SYS0_SIGVAL_ONE 1
#define NV_PERF_PMMSYS_SYS0_SIGVAL_PMA_TRIGGER 2 #define NV_PERF_PMMSYS_SYS0_SIGVAL_PMA_TRIGGER 2
// armss.h #define PM_DOMAIN_BASE(domain) (uint64_t)((0)?NV_PERF_##domain)
#define MC_MCC_CTL_PERFMUX_0 0x0000000000008914 #define PM_REG(domain, reg, i) (uint64_t)(NV_PERF_##domain##_##reg(i))
#define MC_MCC_CTL_PERFMUX_0_MCC_CTL_PERFMUX_EN 31:31 #define PM_OFF(domain, reg) \
#define MC_MCC_CTL_PERFMUX_0_MCC_CTL_PERFMUX_SEL 7:0 (uint64_t)(PM_REG(domain, reg, 0) - PM_DOMAIN_BASE(domain))
#define NV_ADDRESS_MAP_MC0_BASE 0x0000000004040000 #define PM_BASE(domain, reg, perfmon_idx) \
(uint64_t)(PM_REG(domain, reg, perfmon_idx) - PM_OFF(domain, reg))
#define PM_ADDR(domain, reg, base) \
(uint64_t)(base + PM_OFF(domain, reg))
void T410Tests::SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationParams &params) void T410Tests::SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationParams &params)
{ {
const uint32_t perfmon_idx = params.perfmon_idx; const uint32_t perfmon_idx = params.perfmon_idx;
const uint64_t perfmon_base = params.perfmon_base;
uint32_t mode; uint32_t mode;
if (params.mode == PmmConfigurationParams::Mode::MODE_C) { if (params.mode == PmmConfigurationParams::Mode::MODE_C) {
@@ -1226,20 +1250,10 @@ void T410Tests::SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationPara
return; return;
} }
// Enable command packet encoding. Seems like this is needed so perfmon
// can process trigger command from PMA.
const uint32_t secure_config =
REG32_WR(
0,
NV_PERF_PMMSYS_SECURE_CONFIG_COMMAND_PKT_DECODER,
NV_PERF_PMMSYS_SECURE_CONFIG_COMMAND_PKT_DECODER_ENABLE);
RegOpWrite32(
session, NV_PERF_PMMSYS_SECURE_CONFIG(perfmon_idx), secure_config, 0xFFFFFFFF);
// Set ENGINE_SEL to pma_trigger // Set ENGINE_SEL to pma_trigger
RegOpWrite32( RegOpWrite32(
session, session,
NV_PERF_PMMSYS_ENGINE_SEL(perfmon_idx), PM_ADDR(PMMSYS, ENGINE_SEL, perfmon_base),
NV_PERF_PMMSYS_SYS0_SIGVAL_PMA_TRIGGER, NV_PERF_PMMSYS_SYS0_SIGVAL_PMA_TRIGGER,
0xFFFFFFFF); 0xFFFFFFFF);
@@ -1260,30 +1274,30 @@ void T410Tests::SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationPara
NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGB_EN, NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGB_EN,
NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGB_EN_ENABLE); NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGB_EN_ENABLE);
} }
RegOpWrite32(session, NV_PERF_PMMSYS_CONTROLB(perfmon_idx), control_b, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CONTROLB, perfmon_base), control_b, 0xFFFFFFFF);
// Set perfmon id // Set perfmon id
const uint32_t soc_perfmon_prefix = 0x700; // TODO: Temporary identifier const uint32_t soc_perfmon_prefix = 0x700; // TODO: Temporary identifier
const uint32_t perfmon_id = perfmon_idx | soc_perfmon_prefix; const uint32_t perfmon_id = perfmon_idx | soc_perfmon_prefix;
RegOpWrite32(session, NV_PERF_PMMSYS_PERFMONID(perfmon_idx), perfmon_id, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, PERFMONID, perfmon_base), perfmon_id, 0xFFFFFFFF);
// Reset CYA control // Reset CYA control
RegOpWrite32(session, NV_PERF_PMMSYS_CLAMP_CYA_CONTROL(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CLAMP_CYA_CONTROL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_WBSKEW0(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, WBSKEW0, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_WBSKEW1(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, WBSKEW1, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_WBSKEW2(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, WBSKEW2, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_WBSKEW_CHAIN0(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, WBSKEW_CHAIN0, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_WBSKEW_CHAIN1(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, WBSKEW_CHAIN1, perfmon_base), 0x0, 0xFFFFFFFF);
// Do not use truth tables // Do not use truth tables
RegOpWrite32(session, NV_PERF_PMMSYS_TRIG0_OP(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG0_OP, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_TRIG1_OP(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG1_OP, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_EVENT_OP(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, EVENT_OP, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_SAMPLE_OP(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, SAMPLE_OP, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_FT0_INPUTSEL(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, FT0_INPUTSEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_FT1_INPUTSEL(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, FT1_INPUTSEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_FT2_INPUTSEL(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, FT2_INPUTSEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_FT3_INPUTSEL(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, FT3_INPUTSEL, perfmon_base), 0x0, 0xFFFFFFFF);
if (params.mode == PmmConfigurationParams::Mode::MODE_B) { if (params.mode == PmmConfigurationParams::Mode::MODE_B) {
mode = NV_PERF_PMMSYS_CONTROL_MODE_B; mode = NV_PERF_PMMSYS_CONTROL_MODE_B;
@@ -1300,38 +1314,38 @@ void T410Tests::SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationPara
| REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_INCBASE, 2) | REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_INCBASE, 2)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_TRUE) | REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_TRUE)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_INCFN, counter_mode); | REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_INCFN, counter_mode);
RegOpWrite32(session, NV_PERF_PMMSYS_CNTR0_INC(perfmon_idx), counter0_inc, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CNTR0_INC, perfmon_base), counter0_inc, 0xFFFFFFFF);
const uint32_t counter1_inc = 0 const uint32_t counter1_inc = 0
| REG32_WR(0, NV_PERF_PMMSYS_CNTR1_INC_INCMASK, 0xF) | REG32_WR(0, NV_PERF_PMMSYS_CNTR1_INC_INCMASK, 0xF)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR1_INC_INCBASE, 6) | REG32_WR(0, NV_PERF_PMMSYS_CNTR1_INC_INCBASE, 6)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL_TRUE) | REG32_WR(0, NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL_TRUE)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR1_INC_INCFN, counter_mode); | REG32_WR(0, NV_PERF_PMMSYS_CNTR1_INC_INCFN, counter_mode);
RegOpWrite32(session, NV_PERF_PMMSYS_CNTR1_INC(perfmon_idx), counter1_inc, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CNTR1_INC, perfmon_base), counter1_inc, 0xFFFFFFFF);
const uint32_t counter2_inc = 0 const uint32_t counter2_inc = 0
| REG32_WR(0, NV_PERF_PMMSYS_CNTR2_INC_INCMASK, 0xF) | REG32_WR(0, NV_PERF_PMMSYS_CNTR2_INC_INCMASK, 0xF)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR2_INC_INCBASE, 10) | REG32_WR(0, NV_PERF_PMMSYS_CNTR2_INC_INCBASE, 10)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL_TRUE) | REG32_WR(0, NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL_TRUE)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR2_INC_INCFN, counter_mode); | REG32_WR(0, NV_PERF_PMMSYS_CNTR2_INC_INCFN, counter_mode);
RegOpWrite32(session, NV_PERF_PMMSYS_CNTR2_INC(perfmon_idx), counter2_inc, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CNTR2_INC, perfmon_base), counter2_inc, 0xFFFFFFFF);
const uint32_t counter3_inc = 0 const uint32_t counter3_inc = 0
| REG32_WR(0, NV_PERF_PMMSYS_CNTR3_INC_INCMASK, 0xF) | REG32_WR(0, NV_PERF_PMMSYS_CNTR3_INC_INCMASK, 0xF)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR3_INC_INCBASE, 14) | REG32_WR(0, NV_PERF_PMMSYS_CNTR3_INC_INCBASE, 14)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL_TRUE) | REG32_WR(0, NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL_TRUE)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR3_INC_INCFN, counter_mode); | REG32_WR(0, NV_PERF_PMMSYS_CNTR3_INC_INCFN, counter_mode);
RegOpWrite32(session, NV_PERF_PMMSYS_CNTR3_INC(perfmon_idx), counter3_inc, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CNTR3_INC, perfmon_base), counter3_inc, 0xFFFFFFFF);
} else if (params.mode == PmmConfigurationParams::Mode::MODE_E) { } else if (params.mode == PmmConfigurationParams::Mode::MODE_E) {
mode = NV_PERF_PMMSYS_CONTROL_MODE_E; mode = NV_PERF_PMMSYS_CONTROL_MODE_E;
// Reset RAWCNT, except if they are to be primed for overflow (useful in Mode E) // Reset RAWCNT, except if they are to be primed for overflow (useful in Mode E)
uint32_t rawCntVal = params.enable_overflow_priming ? 0xEFFFFF00 : 0; uint32_t rawCntVal = params.enable_overflow_priming ? 0xEFFFFF00 : 0;
RegOpWrite32(session, NV_PERF_PMMSYS_RAWCNT0(perfmon_idx), rawCntVal, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, RAWCNT0, perfmon_base), rawCntVal, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_RAWCNT1(perfmon_idx), rawCntVal, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, RAWCNT1, perfmon_base), rawCntVal, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_RAWCNT2(perfmon_idx), rawCntVal, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, RAWCNT2, perfmon_base), rawCntVal, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_RAWCNT3(perfmon_idx), rawCntVal, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, RAWCNT3, perfmon_base), rawCntVal, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_RAWCNT4(perfmon_idx), rawCntVal, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, RAWCNT4, perfmon_base), rawCntVal, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_RAWCNT5(perfmon_idx), rawCntVal, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, RAWCNT5, perfmon_base), rawCntVal, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_RAWCNT6(perfmon_idx), rawCntVal, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, RAWCNT6, perfmon_base), rawCntVal, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_RAWCNT7(perfmon_idx), rawCntVal, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, RAWCNT7, perfmon_base), rawCntVal, 0xFFFFFFFF);
// Configure counters by INC // Configure counters by INC
const uint32_t signal_sel = (params.collect_one) ? 1 : 0; const uint32_t signal_sel = (params.collect_one) ? 1 : 0;
@@ -1340,10 +1354,10 @@ void T410Tests::SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationPara
| REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_INCBASE, signal_sel) | REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_INCBASE, signal_sel)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_TRUE) | REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL, NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_TRUE)
| REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_INCFN, NV_PERF_PMMSYS_CNTR0_INC_INCFN_NOP); | REG32_WR(0, NV_PERF_PMMSYS_CNTR0_INC_INCFN, NV_PERF_PMMSYS_CNTR0_INC_INCFN_NOP);
RegOpWrite32(session, NV_PERF_PMMSYS_CNTR0_INC(perfmon_idx), counter_inc, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CNTR0_INC, perfmon_base), counter_inc, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_CNTR1_INC(perfmon_idx), counter_inc, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CNTR1_INC, perfmon_base), counter_inc, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_CNTR2_INC(perfmon_idx), counter_inc, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CNTR2_INC, perfmon_base), counter_inc, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_CNTR3_INC(perfmon_idx), counter_inc, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CNTR3_INC, perfmon_base), counter_inc, 0xFFFFFFFF);
} }
// Finally, program CONTROL register // Finally, program CONTROL register
@@ -1359,12 +1373,12 @@ void T410Tests::SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationPara
| REG32_WR(0, NV_PERF_PMMSYS_CONTROL_DRIVE_DEBUG_PORT, NV_PERF_PMMSYS_CONTROL_DRIVE_DEBUG_PORT_NORMAL) | REG32_WR(0, NV_PERF_PMMSYS_CONTROL_DRIVE_DEBUG_PORT, NV_PERF_PMMSYS_CONTROL_DRIVE_DEBUG_PORT_NORMAL)
| REG32_WR(0, NV_PERF_PMMSYS_CONTROL_CTXSW_TIMER, NV_PERF_PMMSYS_CONTROL_CTXSW_TIMER_ENABLE) | REG32_WR(0, NV_PERF_PMMSYS_CONTROL_CTXSW_TIMER, NV_PERF_PMMSYS_CONTROL_CTXSW_TIMER_ENABLE)
| REG32_WR(0, NV_PERF_PMMSYS_CONTROL_WBMASK, NV_PERF_PMMSYS_CONTROL_WBMASK_DISABLE); | REG32_WR(0, NV_PERF_PMMSYS_CONTROL_WBMASK, NV_PERF_PMMSYS_CONTROL_WBMASK_DISABLE);
RegOpWrite32(session, NV_PERF_PMMSYS_CONTROL(perfmon_idx), pmm_control, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CONTROL, perfmon_base), pmm_control, 0xFFFFFFFF);
} }
void T410Tests::SetupWatchbus(nv_soc_hwpm_session session, const PmmConfigurationParams &params) void T410Tests::SetupWatchbusPma(nv_soc_hwpm_session session, const PmmConfigurationParams &params)
{ {
const uint32_t perfmon_idx = params.perfmon_idx; const uint64_t perfmon_base = params.perfmon_base;
if (params.mode == PmmConfigurationParams::Mode::MODE_C) { if (params.mode == PmmConfigurationParams::Mode::MODE_C) {
// Not supporting mode C testing for now. // Not supporting mode C testing for now.
@@ -1375,7 +1389,7 @@ void T410Tests::SetupWatchbus(nv_soc_hwpm_session session, const PmmConfiguratio
// SIGNAL(name/width/domain/instancetype):--/sys0.pma2pm_0_static_pattern_11111111_32/32/sys0/sys/ // SIGNAL(name/width/domain/instancetype):--/sys0.pma2pm_0_static_pattern_11111111_32/32/sys0/sys/
// ROUTE(index/registers):--/0/2/ // ROUTE(index/registers):--/0/2/
// DESTINATION(lsb_bitposition/watchbus_readback_index/watchbus_readback_lsb):--/22/0/0/ // DESTINATION(lsb_bitposition/watchbus_readback_index/watchbus_readback_lsb):--/22/0/0/
// Source: //hw/tools/perfalyze/chips/th500/pml_files/soc_perf/pm_programming_guide.txt // Source: //hw/nvmobile_tb50x/ip/perf/hwpm_soc/2.2/dvlib/specs/src_tb500/pm_programming_guide.txt
const uint32_t channel_perfmux_sel = 0 const uint32_t channel_perfmux_sel = 0
| REG32_WR( | REG32_WR(
0, 0,
@@ -1386,15 +1400,309 @@ void T410Tests::SetupWatchbus(nv_soc_hwpm_session session, const PmmConfiguratio
// Map 16-bit signals onto reduced watchbus by SEL // Map 16-bit signals onto reduced watchbus by SEL
// See above comment, the start of the signal is targeted to watchbus bit 22. // See above comment, the start of the signal is targeted to watchbus bit 22.
RegOpWrite32(session, NV_PERF_PMMSYS_EVENT_SEL(perfmon_idx), 0x19181716, 0xFFFFFFFF); // 'E' from EEEE RegOpWrite32(session, PM_ADDR(PMMSYS, EVENT_SEL, perfmon_base), 0x19181716, 0xFFFFFFFF); // 'E' from EEEE
RegOpWrite32(session, NV_PERF_PMMSYS_TRIG0_SEL(perfmon_idx), 0x1D1C1B1A, 0xFFFFFFFF); // 'E' from EEEE RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG0_SEL, perfmon_base), 0x1D1C1B1A, 0xFFFFFFFF); // 'E' from EEEE
RegOpWrite32(session, NV_PERF_PMMSYS_TRIG1_SEL(perfmon_idx), 0x21201F1E, 0xFFFFFFFF); // 'E' from EEEE RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG1_SEL, perfmon_base), 0x21201F1E, 0xFFFFFFFF); // 'E' from EEEE
RegOpWrite32(session, NV_PERF_PMMSYS_SAMPLE_SEL(perfmon_idx), 0x25242322, 0xFFFFFFFF); // 'E' from EEEE RegOpWrite32(session, PM_ADDR(PMMSYS, SAMPLE_SEL, perfmon_base), 0x25242322, 0xFFFFFFFF); // 'E' from EEEE
} else if (params.mode == PmmConfigurationParams::Mode::MODE_E) { } else if (params.mode == PmmConfigurationParams::Mode::MODE_E) {
RegOpWrite32(session, NV_PERF_PMMSYS_TRIG0_SEL(perfmon_idx), 0x0, 0xFFFFFFFF); // PMA perfmon true bit.
RegOpWrite32(session, NV_PERF_PMMSYS_TRIG1_SEL(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG0_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_EVENT_SEL(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG1_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_SAMPLE_SEL(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, EVENT_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, SAMPLE_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
}
}
// TODO: remove hardcoded values
// Based on https://sc.talos.nvidia.com/serve;file-limit=none/home/tegra_manuals/html/manuals/tb500c/dev_therm.html:
#define NV_HWPM_GLOBAL_0_THERM_PM_CTRL_ENABLE 31:31
#define NV_HWPM_GLOBAL_0_THERM_PM_CTRL_ENABLE_ENABLE 0x1
#define NV_HWPM_GLOBAL_0_THERM_PM_SELECT_FLEX_A 5:0
#define NV_THERM_PERFMUX 0xFE0001010768
TEST_F(T410Tests, SessionRegOpsNvtherm)
{
uint32_t i, channel_perfmux_sel;
nv_soc_hwpm_device dev;
nv_soc_hwpm_session session;
nv_soc_hwpm_resource res_ids[1] = { NV_SOC_HWPM_RESOURCE_NVTHERM };
GetDevices();
for (i = 0; i < t410_dev_count; i++) {
printf("Device %d:\n", i);
dev = t410_dev[i];
// Allocate session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_alloc_fn(dev, &session));
// Reserve resource.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_reserve_resources_fn(session, 1, res_ids));
// Start session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_start_fn(session));
// The perfmux value should be initialized to 0.
RegOpRead32(session, NV_THERM_PERFMUX, &channel_perfmux_sel);
EXPECT_EQ(0x0U, channel_perfmux_sel);
// Set the perfmux to static pattern 1.
const uint32_t mux_sel = 0x4;
const uint32_t write_val = 0
| REG32_WR(
0,
NV_HWPM_GLOBAL_0_THERM_PM_SELECT_FLEX_A,
mux_sel)
| REG32_WR(
0,
NV_HWPM_GLOBAL_0_THERM_PM_CTRL_ENABLE,
NV_HWPM_GLOBAL_0_THERM_PM_CTRL_ENABLE_ENABLE);
RegOpWrite32(session, NV_THERM_PERFMUX, write_val, 0xFFFFFFFF);
// Read back the perfmux value.
RegOpRead32(session, NV_THERM_PERFMUX, &channel_perfmux_sel);
EXPECT_EQ(write_val, channel_perfmux_sel);
// Free session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_free_fn(session));
}
}
void T410Tests::SetupWatchbusNvtherm(nv_soc_hwpm_session session, const PmmConfigurationParams &params)
{
const uint64_t perfmon_base = params.perfmon_base;
if (params.mode == PmmConfigurationParams::Mode::MODE_C) {
// Not supporting mode C testing for now.
ASSERT_TRUE(false);
return;
} else if (params.mode == PmmConfigurationParams::Mode::MODE_B) {
// NVTHERM perfmux.
// SIGNAL(name/width/domain/instancetype):--/nvtherm0.therm_flex_a_static_pattern_5555_16/16/nvtherm0/tjv/
// ROUTE(index/registers):--/0/2/
// DESTINATION(lsb_bitposition/watchbus_readback_index/watchbus_readback_lsb):--/22/0/0/
// REGWRITE(field/addr/val/mask/chipletoffset/instanceoffset/instancecount/instancetype):--/NV_HWPM_GLOBAL_0_THERM_PM_CTRL_ENABLE/279275970299752/2147483648/2147483648/0/0/1/none/
// REGWRITE(field/addr/val/mask/chipletoffset/instanceoffset/instancecount/instancetype):--/NV_HWPM_GLOBAL_0_THERM_PM_SELECT_FLEX_A/279275970299752/4/63/0/0/1/none/
// Source: //hw/nvmobile_tb50x/ip/perf/hwpm_soc/2.2/dvlib/specs/src_tb500/pm_programming_guide.txt
const uint32_t mux_sel = 0x4;
const uint32_t channel_perfmux_sel = 0
| REG32_WR(
0,
NV_HWPM_GLOBAL_0_THERM_PM_SELECT_FLEX_A,
mux_sel)
| REG32_WR(
0,
NV_HWPM_GLOBAL_0_THERM_PM_CTRL_ENABLE,
NV_HWPM_GLOBAL_0_THERM_PM_CTRL_ENABLE_ENABLE);
RegOpWrite32(session, NV_THERM_PERFMUX, channel_perfmux_sel, 0xFFFFFFFF);
// Map 16-bit signals onto reduced watchbus by SEL
// See above comment, the start of the signal is targeted to watchbus bit 22.
RegOpWrite32(session, PM_ADDR(PMMSYS, EVENT_SEL, perfmon_base), 0x19181716, 0xFFFFFFFF); // '5' from 5555
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG0_SEL, perfmon_base), 0x1D1C1B1A, 0xFFFFFFFF); // '5' from 5555
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG1_SEL, perfmon_base), 0x21201F1E, 0xFFFFFFFF); // '5' from 5555
RegOpWrite32(session, PM_ADDR(PMMSYS, SAMPLE_SEL, perfmon_base), 0x25242322, 0xFFFFFFFF); // '5' from 5555
} else if (params.mode == PmmConfigurationParams::Mode::MODE_E) {
// PMA perfmon true bit.
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG0_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG1_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, EVENT_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, SAMPLE_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
}
}
// TODO: remove hardcoded values
#define NV_HWPM_CSN_0_MBN_PERFMUX (NV_ADDRESS_MAP_COMPUTE_0_MMCTLP_COMP_TYPE_CSN0_CSN_MBN_HWPM_BASE + 0x8ULL)
#define NV_HWPM_CSN_0_MBN_ENABLE 7:7
#define NV_HWPM_CSN_0_MBN_ENABLE_ENABLE 0x1
#define NV_HWPM_CSN_0_MBN_MUX_SEL 6:0
TEST_F(T410Tests, SessionRegOpsCsnMbn)
{
uint32_t i, channel_perfmux_sel;
nv_soc_hwpm_device dev;
nv_soc_hwpm_session session;
nv_soc_hwpm_resource res_ids[1] = { NV_SOC_HWPM_RESOURCE_CSN };
GetDevices();
for (i = 0; i < t410_dev_count; i++) {
printf("Device %d:\n", i);
dev = t410_dev[i];
// Allocate session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_alloc_fn(dev, &session));
// Reserve resource.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_reserve_resources_fn(session, 1, res_ids));
// Start session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_start_fn(session));
// The perfmux value should be initialized to 0.
RegOpRead32(session, NV_HWPM_CSN_0_MBN_PERFMUX, &channel_perfmux_sel);
EXPECT_EQ(0x0U, channel_perfmux_sel);
// Set the perfmux to static pattern 1.
const uint32_t mux_sel = 0x4;
const uint32_t write_val = 0
| REG32_WR(
0,
NV_HWPM_CSN_0_MBN_MUX_SEL,
mux_sel)
| REG32_WR(
0,
NV_HWPM_CSN_0_MBN_ENABLE,
NV_HWPM_CSN_0_MBN_ENABLE_ENABLE);
RegOpWrite32(session, NV_HWPM_CSN_0_MBN_PERFMUX, write_val, 0xFFFFFFFF);
// Read back the perfmux value.
RegOpRead32(session, NV_HWPM_CSN_0_MBN_PERFMUX, &channel_perfmux_sel);
EXPECT_EQ(write_val, channel_perfmux_sel);
// Free session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_free_fn(session));
}
}
void T410Tests::SetupWatchbusCsnMbn(nv_soc_hwpm_session session, const PmmConfigurationParams &params)
{
const uint64_t perfmon_base = params.perfmon_base;
if (params.mode == PmmConfigurationParams::Mode::MODE_C) {
// Not supporting mode C testing for now.
ASSERT_TRUE(false);
return;
} else if (params.mode == PmmConfigurationParams::Mode::MODE_B) {
// CSN-MBN perfmux.
// SIGNAL(name/width/domain/instancetype):--/ucfcsn7p0.csn_mbn02pm_static_pattern_4a4a_16/16/ucfcsn7p0/tjv/
// ROUTE(index/registers):--/0/2/
// DESTINATION(lsb_bitposition/watchbus_readback_index/watchbus_readback_lsb):--/99/2/13/
// REGWRITE(field/addr/val/mask/chipletoffset/instanceoffset/instancecount/instancetype):--/NV_HWPM_GLOBAL_CSN0_CSN_MBN_HWPM_PMC_HWPM_PERF_MUX_0_ENABLE_0/69206024/128/128/0/0/1/none/
// REGWRITE(field/addr/val/mask/chipletoffset/instanceoffset/instancecount/instancetype):--/NV_HWPM_GLOBAL_CSN0_CSN_MBN_HWPM_PMC_HWPM_PERF_MUX_0_MUX_SEL_0/69206024/0/127/0/0/1/none/
// SIGNAL(name/width/domain/instancetype):--/ucfcsn7p0.csn_mbn02pm_static_pattern_a4a4_16/16/ucfcsn7p0/tjv/
// Source: //hw/nvmobile_tb50x/ip/perf/hwpm_soc/2.2/dvlib/specs/src_tb500/pm_programming_guide.txt
const uint32_t mux_sel = 0x0;
const uint32_t channel_perfmux_sel = 0
| REG32_WR(
0,
NV_HWPM_CSN_0_MBN_MUX_SEL,
mux_sel)
| REG32_WR(
0,
NV_HWPM_CSN_0_MBN_ENABLE,
NV_HWPM_CSN_0_MBN_ENABLE_ENABLE);
RegOpWrite32(session, NV_HWPM_CSN_0_MBN_PERFMUX, channel_perfmux_sel, 0xFFFFFFFF);
// Map 16-bit signals onto reduced watchbus by SEL
// See above comment, the start of the signal is targeted to watchbus bit 99.
RegOpWrite32(session, PM_ADDR(PMMSYS, EVENT_SEL, perfmon_base), 0x66656463, 0xFFFFFFFF); // 'a' from 4a4a
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG0_SEL, perfmon_base), 0x6A696867, 0xFFFFFFFF); // '4' from 4a4a
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG1_SEL, perfmon_base), 0x6E6D6C6B, 0xFFFFFFFF); // 'a' from 4a4a
RegOpWrite32(session, PM_ADDR(PMMSYS, SAMPLE_SEL, perfmon_base), 0x7271706F, 0xFFFFFFFF); // '4' from 4a4a
} else if (params.mode == PmmConfigurationParams::Mode::MODE_E) {
// PMA perfmon true bit.
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG0_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG1_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, EVENT_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, SAMPLE_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
}
}
// TODO: remove hardcoded values
#define NV_HWPM_CORE_0_IPMU_PERFMUX (NV_ADDRESS_MAP_COMPUTE_0_MMCTLP_COMP_TYPE_CORE0_CORE_HWPM_BASE + 0x30ULL)
#define NV_HWPM_CORE_0_IPMU_ENABLE 8:8
#define NV_HWPM_CORE_0_IPMU_ENABLE_ENABLE 0x1
#define NV_HWPM_CORE_0_IPMU_MUX_SEL 7:0
TEST_F(T410Tests, SessionRegOpsIpmu)
{
uint32_t i, channel_perfmux_sel;
nv_soc_hwpm_device dev;
nv_soc_hwpm_session session;
nv_soc_hwpm_resource res_ids[1] = { NV_SOC_HWPM_RESOURCE_CPU };
GetDevices();
for (i = 0; i < t410_dev_count; i++) {
printf("Device %d:\n", i);
dev = t410_dev[i];
// Allocate session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_alloc_fn(dev, &session));
// Reserve resource.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_reserve_resources_fn(session, 1, res_ids));
// Start session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_start_fn(session));
// The perfmux value should be initialized to 0.
RegOpRead32(session, NV_HWPM_CORE_0_IPMU_PERFMUX, &channel_perfmux_sel);
EXPECT_EQ(0x0U, channel_perfmux_sel);
// Set the perfmux to static pattern 1.
const uint32_t mux_sel = 0x1;
const uint32_t write_val = 0
| REG32_WR(
0,
NV_HWPM_CORE_0_IPMU_MUX_SEL,
mux_sel)
| REG32_WR(
0,
NV_HWPM_CORE_0_IPMU_ENABLE,
NV_HWPM_CORE_0_IPMU_ENABLE_ENABLE);
RegOpWrite32(session, NV_HWPM_CORE_0_IPMU_PERFMUX, write_val, 0xFFFFFFFF);
// Read back the perfmux value.
RegOpRead32(session, NV_HWPM_CORE_0_IPMU_PERFMUX, &channel_perfmux_sel);
EXPECT_EQ(write_val, channel_perfmux_sel);
// Free session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_free_fn(session));
}
}
void T410Tests::SetupWatchbusIpmu(nv_soc_hwpm_session session, const PmmConfigurationParams &params)
{
const uint64_t perfmon_base = params.perfmon_base;
if (params.mode == PmmConfigurationParams::Mode::MODE_C) {
// Not supporting mode C testing for now.
ASSERT_TRUE(false);
return;
} else if (params.mode == PmmConfigurationParams::Mode::MODE_B) {
// Core-0 IPMU perfmux.
// SIGNAL(name/width/domain/instancetype):--/ucfcsnh0p0.ipmu02pm_static_pattern_a4a4_16/16/ucfcsnh0p0/tjv/
// ROUTE(index/registers):--/0/2/
// DESTINATION(lsb_bitposition/watchbus_readback_index/watchbus_readback_lsb):--/22/0/0/
// REGWRITE(field/addr/val/mask/chipletoffset/instanceoffset/instancecount/instancetype):--/NV_HWPM_GLOBAL_CORE0_IPMU_PERFMUX_CONTROL_PM_EN/4718640/256/256/0/0/1/none/
// REGWRITE(field/addr/val/mask/chipletoffset/instanceoffset/instancecount/instancetype):--/NV_HWPM_GLOBAL_CORE0_IPMU_PERFMUX_CONTROL_PM_SEL/4718640/1/255/0/0/1/none/
// Source: //hw/nvmobile_tb50x/ip/perf/hwpm_soc/2.2/dvlib/specs/src_tb500/pm_programming_guide.txt
const uint32_t mux_sel = 0x1;
const uint32_t channel_perfmux_sel = 0
| REG32_WR(
0,
NV_HWPM_CORE_0_IPMU_MUX_SEL,
mux_sel)
| REG32_WR(
0,
NV_HWPM_CORE_0_IPMU_ENABLE,
NV_HWPM_CORE_0_IPMU_ENABLE_ENABLE);
RegOpWrite32(session, NV_HWPM_CORE_0_IPMU_PERFMUX, channel_perfmux_sel, 0xFFFFFFFF);
// Map 16-bit signals onto reduced watchbus by SEL
// See above comment, the start of the signal is targeted to watchbus bit 22.
RegOpWrite32(session, PM_ADDR(PMMSYS, EVENT_SEL, perfmon_base), 0x19181716, 0xFFFFFFFF); // '4' from a4a4
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG0_SEL, perfmon_base), 0x1D1C1B1A, 0xFFFFFFFF); // 'a' from a4a4
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG1_SEL, perfmon_base), 0x21201F1E, 0xFFFFFFFF); // '4' from a4a4
RegOpWrite32(session, PM_ADDR(PMMSYS, SAMPLE_SEL, perfmon_base), 0x25242322, 0xFFFFFFFF); // 'a' from a4a4
} else if (params.mode == PmmConfigurationParams::Mode::MODE_E) {
// PMA perfmon true bit.
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG0_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, TRIG1_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, EVENT_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
RegOpWrite32(session, PM_ADDR(PMMSYS, SAMPLE_SEL, perfmon_base), 0x0, 0xFFFFFFFF);
} }
} }
@@ -1415,22 +1723,13 @@ void T410Tests::TeardownPma(nv_soc_hwpm_session session)
void T410Tests::TeardownPmm( void T410Tests::TeardownPmm(
nv_soc_hwpm_session session, const PmmConfigurationParams &params) nv_soc_hwpm_session session, const PmmConfigurationParams &params)
{ {
const uint32_t perfmon_idx = params.perfmon_idx; const uint64_t perfmon_base = params.perfmon_base;
// Disable PMMs and reset ENGINE_SELs // Disable PMMs and reset ENGINE_SELs
const uint32_t pmm_engine_sel = 0 const uint32_t pmm_engine_sel = 0
| REG32_WR(0, NV_PERF_PMMSYS_ENGINE_SEL_START, 0xFF); // ZERO | REG32_WR(0, NV_PERF_PMMSYS_ENGINE_SEL_START, 0xFF); // ZERO
RegOpWrite32(session, NV_PERF_PMMSYS_ENGINE_SEL(perfmon_idx), pmm_engine_sel, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, ENGINE_SEL, perfmon_base), pmm_engine_sel, 0xFFFFFFFF);
RegOpWrite32(session, NV_PERF_PMMSYS_CONTROL(perfmon_idx), 0x0, 0xFFFFFFFF); RegOpWrite32(session, PM_ADDR(PMMSYS, CONTROL, perfmon_base), 0x0, 0xFFFFFFFF);
// Disable command packet encoding. Seems like this is needed so perfmon
// can process trigger command from PMA.
const uint32_t secure_config =
REG32_WR(
0,
NV_PERF_PMMSYS_SECURE_CONFIG_COMMAND_PKT_DECODER,
NV_PERF_PMMSYS_SECURE_CONFIG_COMMAND_PKT_DECODER_DISABLE);
RegOpWrite32(session, NV_PERF_PMMSYS_SECURE_CONFIG(perfmon_idx), secure_config, 0xFFFFFFFF);
} }
void T410Tests::TeardownPerfmux(nv_soc_hwpm_session session) void T410Tests::TeardownPerfmux(nv_soc_hwpm_session session)
@@ -1453,48 +1752,91 @@ void T410Tests::IssuePmaTrigger(nv_soc_hwpm_session session)
void T410Tests::HarvestCounters( void T410Tests::HarvestCounters(
nv_soc_hwpm_session session, const PmmConfigurationParams &params, const uint32_t sig_val[4]) nv_soc_hwpm_session session, const PmmConfigurationParams &params, const uint32_t sig_val[4])
{ {
const uint32_t perfmon_idx = params.perfmon_idx; const uint64_t perfmon_base = params.perfmon_base;
uint32_t read_value = 0; uint32_t read_value = 0;
RegOpRead32(session, NV_PERF_PMMSYS_EVENTCNT(perfmon_idx), &read_value); RegOpRead32(session, PM_ADDR(PMMSYS, EVENTCNT, perfmon_base), &read_value);
uint32_t event = read_value; uint32_t event = read_value;
RegOpRead32(session, NV_PERF_PMMSYS_TRIGGERCNT(perfmon_idx), &read_value); RegOpRead32(session, PM_ADDR(PMMSYS, TRIGGERCNT, perfmon_base), &read_value);
uint32_t trig0 = read_value; uint32_t trig0 = read_value;
RegOpRead32(session, NV_PERF_PMMSYS_THRESHCNT(perfmon_idx), &read_value); RegOpRead32(session, PM_ADDR(PMMSYS, THRESHCNT, perfmon_base), &read_value);
uint32_t trig1 = read_value; uint32_t trig1 = read_value;
RegOpRead32(session, NV_PERF_PMMSYS_SAMPLECNT(perfmon_idx), &read_value); RegOpRead32(session, PM_ADDR(PMMSYS, SAMPLECNT, perfmon_base), &read_value);
uint32_t sample = read_value; uint32_t sample = read_value;
RegOpRead32(session, NV_PERF_PMMSYS_ELAPSED(perfmon_idx), &read_value); RegOpRead32(session, PM_ADDR(PMMSYS, ELAPSED, perfmon_base), &read_value);
uint32_t elapsed = read_value; uint32_t elapsed = read_value;
printf("Event: %u, Trig0: %u, Trig1: %u, Sample: %u, Elapsed: %u\n", printf("Event: %u, Trig0: %u, Trig1: %u, Sample: %u, Elapsed: %u\n",
event, trig0, trig1, sample, elapsed); event, trig0, trig1, sample, elapsed);
ASSERT_GT(sig_val[0], 0U); EXPECT_GT(sig_val[0], 0U);
ASSERT_EQ((uint64_t)sig_val[0] * elapsed, event); EXPECT_EQ((uint64_t)sig_val[0] * elapsed, event);
ASSERT_GT(sig_val[1], 0U); EXPECT_GT(sig_val[1], 0U);
ASSERT_EQ((uint64_t)sig_val[1] * elapsed, trig0); EXPECT_EQ((uint64_t)sig_val[1] * elapsed, trig0);
ASSERT_GT(sig_val[2], 0U); EXPECT_GT(sig_val[2], 0U);
ASSERT_EQ((uint64_t)sig_val[2] * elapsed, trig1); EXPECT_EQ((uint64_t)sig_val[2] * elapsed, trig1);
ASSERT_GT(sig_val[3], 0U); EXPECT_GT(sig_val[3], 0U);
ASSERT_EQ((uint64_t)sig_val[3] * elapsed, sample); EXPECT_EQ((uint64_t)sig_val[3] * elapsed, sample);
} }
void T410Tests::InitPmmParams(nv_soc_hwpm_resource resource, PmmConfigurationParams &params)
{
switch (resource) {
case NV_SOC_HWPM_RESOURCE_PMA:
// From //hw/nvmobile_tb50x/ip/perf/hwpm_soc/2.2/dvlib/specs/src_tb500/pm_programming_guide.txt
// PERFMON(domainame/chiplet/index/chipletoffset/regprefix/offsetfromPMMSYS):--/pmasys0/perfmon_sys/1/262144/NV_PERF_PMMSYS_/0/
// Perfmon domain offset pmasys0
params.perfmon_idx = 1;
params.perfmon_base = PM_BASE(PMMSYS, ENGINE_SEL, params.perfmon_idx);
params.expected_sig_val = { 0xE, 0xE, 0xE, 0xE };
break;
case NV_SOC_HWPM_RESOURCE_NVTHERM:
// From //hw/nvmobile_tb50x/ip/perf/hwpm_soc/2.2/dvlib/specs/src_tb500/pm_programming_guide.txt
// PERFMON(domainame/chiplet/index/chipletoffset/regprefix/offsetfromPMMSYS):--/nvtherm0/perfmon_tjv/27264/1048576/NV_PERF_PMMTJV_/-85899345920/
// Perfmon domain offset nvtherm0
params.perfmon_idx = 27264;
params.perfmon_base = PM_BASE(PMMTJV, ENGINE_SEL, params.perfmon_idx);
params.expected_sig_val = { 0x5, 0x5, 0x5, 0x5 };
break;
case NV_SOC_HWPM_RESOURCE_CSN:
// From //hw/nvmobile_tb50x/ip/perf/hwpm_soc/2.2/dvlib/specs/src_tb500/pm_programming_guide.txt
// PERFMON(domainame/chiplet/index/chipletoffset/regprefix/offsetfromPMMSYS):--/ucfcsn7p0/perfmon_tjv/146432/2097152/NV_PERF_PMMTJV_/-85899345920/
// Perfmon domain offset csn0
params.perfmon_idx = 146432;
params.perfmon_base = NV_ADDRESS_MAP_COMPUTE_0_MMCTLP_COMP_TYPE_CSN0_CSN_HWPM_PRI0_BASE;
params.expected_sig_val = { 0xa, 0x4, 0xa, 0x4 };
break;
case NV_SOC_HWPM_RESOURCE_CPU:
// From //hw/nvmobile_tb50x/ip/perf/hwpm_soc/2.2/dvlib/specs/src_tb500/pm_programming_guide.txt
// PERFMON(domainame/chiplet/index/chipletoffset/regprefix/offsetfromPMMSYS):--/ucfcsnh0p0/perfmon_tjv/158720/2097152/NV_PERF_PMMTJV_/-85899345920/
// Perfmon domain offset csnh0
params.perfmon_idx = 158720;
params.perfmon_base = NV_ADDRESS_MAP_COMPUTE_0_MMCTLP_COMP_TYPE_CSNH0_CSN_HWPM_PRI0_BASE;
params.expected_sig_val = { 0x4, 0xa, 0x4, 0xa };
break;
default:
ASSERT_TRUE(false);
break;
}
TEST_F(T410Tests, SessionSignalTestPmaPerfmux) printf("Perfmon idx: %x, base: %lx\n", params.perfmon_idx, params.perfmon_base);
}
void T410Tests::ModeBTest(nv_soc_hwpm_resource resource)
{ {
uint32_t i; uint32_t i;
nv_soc_hwpm_device dev; nv_soc_hwpm_device dev;
nv_soc_hwpm_session session; nv_soc_hwpm_session session;
nv_soc_hwpm_session_attribute session_attr; nv_soc_hwpm_session_attribute session_attr;
GetDevices(); GetDevices();
for (i = 0; i < t410_dev_count; i++) { for (i = 0; i < t410_dev_count; i++) {
@@ -1527,47 +1869,95 @@ TEST_F(T410Tests, SessionSignalTestPmaPerfmux)
// Start session. // Start session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_start_fn(session)); ASSERT_EQ(0, api_table.nv_soc_hwpm_session_start_fn(session));
// From //hw/tools/perfalyze/chips/th500/pml_files/soc_perf/pm_programming_guide.txt printf("Session started\n");
// Perfmon domain offset sys0
const uint32_t perfmon_idx = 30;
PmaConfigurationParams pma_params; PmaConfigurationParams pma_params;
SetupPma(session, pma_params); SetupPma(session, pma_params);
printf("PMA setup done\n");
PmmConfigurationParams pmm_params; PmmConfigurationParams pmm_params;
pmm_params.perfmon_idx = perfmon_idx; InitPmmParams(resource, pmm_params);
pmm_params.mode = PmmConfigurationParams::Mode::MODE_B;
SetupPmm(session, pmm_params); SetupPmm(session, pmm_params);
SetupWatchbus(session, pmm_params);
printf("PMM setup done\n");
switch (resource) {
case NV_SOC_HWPM_RESOURCE_PMA:
SetupWatchbusPma(session, pmm_params);
break;
case NV_SOC_HWPM_RESOURCE_NVTHERM:
SetupWatchbusNvtherm(session, pmm_params);
break;
case NV_SOC_HWPM_RESOURCE_CSN:
SetupWatchbusCsnMbn(session, pmm_params);
break;
case NV_SOC_HWPM_RESOURCE_CPU:
SetupWatchbusIpmu(session, pmm_params);
break;
default:
ASSERT_TRUE(false);
break;
}
printf("Watchbus setup done\n");
// http://nvbugs/3091420: Ignore the first snapshot as it could // http://nvbugs/3091420: Ignore the first snapshot as it could
// contain some undesired noises between perfmux and perfmon. // contain some undesired noises between perfmux and perfmon.
IssuePmaTrigger(session); IssuePmaTrigger(session);
const uint32_t sig_val[4] = { 0xE, 0xE, 0xE, 0xE }; printf("PMA trigger issued\n");
for (int i = 0; i < 5; i++) { for (int i = 0; i < 5; i++) {
IssuePmaTrigger(session); IssuePmaTrigger(session);
HarvestCounters(session, pmm_params, sig_val); printf("PMA trigger issued\n");
HarvestCounters(session, pmm_params, pmm_params.expected_sig_val.data());
printf("Harvested counters\n");
} }
TeardownPerfmux(session); TeardownPerfmux(session);
printf("Perfmux teardown done\n");
TeardownPmm(session, pmm_params); TeardownPmm(session, pmm_params);
printf("PMM teardown done\n");
TeardownPma(session); TeardownPma(session);
printf("PMA teardown done\n");
// Free session. // Free session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_free_fn(session)); ASSERT_EQ(0, api_table.nv_soc_hwpm_session_free_fn(session));
} }
} }
TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreaming) TEST_F(T410Tests, SessionSignalTestPmaPerfmux)
{
ModeBTest(NV_SOC_HWPM_RESOURCE_PMA);
}
TEST_F(T410Tests, SessionSignalTestNvthermPerfmux)
{
ModeBTest(NV_SOC_HWPM_RESOURCE_NVTHERM);
}
TEST_F(T410Tests, SessionSignalTestCsnMbnPerfmux)
{
ModeBTest(NV_SOC_HWPM_RESOURCE_CSN);
}
TEST_F(T410Tests, SessionSignalTestIpmuPerfmux)
{
ModeBTest(NV_SOC_HWPM_RESOURCE_CPU);
}
void T410Tests::ModeETest(nv_soc_hwpm_resource resource)
{ {
nv_soc_hwpm_device dev; nv_soc_hwpm_device dev;
nv_soc_hwpm_device_attribute dev_attr;
tegra_soc_hwpm_platform platform;
nv_soc_hwpm_session session; nv_soc_hwpm_session session;
nv_soc_hwpm_session_attribute session_attr; nv_soc_hwpm_session_attribute session_attr;
uint32_t i, num_mem_bytes, num_triggers, num_perfmons; uint32_t i, num_mem_bytes, num_triggers, num_perfmons;
// From //hw/tools/perfalyze/chips/th500/pml_files/soc_perf/pm_programming_guide.txt
// Perfmon domain offset sys0
const uint32_t perfmon_idx = 30;
num_perfmons = 1; num_perfmons = 1;
GetDevices(); GetDevices();
@@ -1576,6 +1966,11 @@ TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreaming)
printf("Device %d:\n", i); printf("Device %d:\n", i);
dev = t410_dev[i]; dev = t410_dev[i];
dev_attr = NV_SOC_HWPM_DEVICE_ATTRIBUTE_SOC_PLATFORM;
ASSERT_EQ(0,
api_table.nv_soc_hwpm_device_get_info_fn(
dev, dev_attr, sizeof(platform), &platform));
// Allocate session. // Allocate session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_alloc_fn(dev, &session)); ASSERT_EQ(0, api_table.nv_soc_hwpm_session_alloc_fn(dev, &session));
@@ -1584,7 +1979,8 @@ TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreaming)
// Allocate PMA buffers. // Allocate PMA buffers.
nv_soc_hwpm_pma_buffer_params record_buffer_params = {}; nv_soc_hwpm_pma_buffer_params record_buffer_params = {};
record_buffer_params.size = 100 * 1024 * 1024; record_buffer_params.size =
((platform == TEGRA_SOC_HWPM_PLATFORM_SILICON) ? 100 : 32) * 1024 * 1024;
ASSERT_EQ(0, ASSERT_EQ(0,
api_table.nv_soc_hwpm_session_alloc_pma_fn( api_table.nv_soc_hwpm_session_alloc_pma_fn(
session, &record_buffer_params)); session, &record_buffer_params));
@@ -1602,6 +1998,8 @@ TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreaming)
// Start session. // Start session.
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_start_fn(session)); ASSERT_EQ(0, api_table.nv_soc_hwpm_session_start_fn(session));
printf("Session started\n");
// Flush leftover records at the beginning of each subtest // Flush leftover records at the beginning of each subtest
nv_soc_hwpm_pma_channel_state_params set_get_state_param = {}; nv_soc_hwpm_pma_channel_state_params set_get_state_param = {};
set_get_state_param.in_mem_bump = 0; set_get_state_param.in_mem_bump = 0;
@@ -1621,12 +2019,34 @@ TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreaming)
pma_params.enable_streaming = true; pma_params.enable_streaming = true;
SetupPma(session, pma_params); SetupPma(session, pma_params);
printf("PMA setup done\n");
PmmConfigurationParams pmm_params; PmmConfigurationParams pmm_params;
pmm_params.perfmon_idx = perfmon_idx; InitPmmParams(resource, pmm_params);
pmm_params.mode = PmmConfigurationParams::Mode::MODE_E; pmm_params.mode = PmmConfigurationParams::Mode::MODE_E;
pmm_params.collect_one = true; pmm_params.collect_one = true;
SetupPmm(session, pmm_params); SetupPmm(session, pmm_params);
SetupWatchbus(session, pmm_params);
printf("PMM setup done\n");
switch (resource) {
case NV_SOC_HWPM_RESOURCE_PMA:
SetupWatchbusPma(session, pmm_params);
break;
case NV_SOC_HWPM_RESOURCE_NVTHERM:
SetupWatchbusNvtherm(session, pmm_params);
break;
case NV_SOC_HWPM_RESOURCE_CSN:
SetupWatchbusCsnMbn(session, pmm_params);
break;
case NV_SOC_HWPM_RESOURCE_CPU:
SetupWatchbusIpmu(session, pmm_params);
break;
default:
ASSERT_TRUE(false);
break;
}
printf("Watchbus setup done\n");
num_triggers = 5; num_triggers = 5;
usleep(1000000); // 1 second usleep(1000000); // 1 second
@@ -1635,9 +2055,16 @@ TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreaming)
} }
usleep(100000); // 100 milisecond usleep(100000); // 100 milisecond
printf("PMA trigger issued\n");
TeardownPerfmux(session); TeardownPerfmux(session);
printf("Perfmux teardown done\n");
TeardownPmm(session, pmm_params); TeardownPmm(session, pmm_params);
printf("PMM teardown done\n");
TeardownPma(session); TeardownPma(session);
printf("PMA teardown done\n");
ASSERT_EQ(num_triggers * num_perfmons, soc_mode_e_buffer.GetNumValidRecords()); ASSERT_EQ(num_triggers * num_perfmons, soc_mode_e_buffer.GetNumValidRecords());
ASSERT_EQ(num_triggers * num_perfmons, soc_mode_e_buffer.GetNumSamples()); ASSERT_EQ(num_triggers * num_perfmons, soc_mode_e_buffer.GetNumSamples());
@@ -1670,3 +2097,23 @@ TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreaming)
ASSERT_EQ(0, api_table.nv_soc_hwpm_session_free_fn(session)); ASSERT_EQ(0, api_table.nv_soc_hwpm_session_free_fn(session));
} }
} }
TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreamingPma)
{
ModeETest(NV_SOC_HWPM_RESOURCE_PMA);
}
TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreamingNvtherm)
{
ModeETest(NV_SOC_HWPM_RESOURCE_NVTHERM);
}
TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreamingCsnMbn)
{
ModeETest(NV_SOC_HWPM_RESOURCE_CSN);
}
TEST_F(T410Tests, SessionStreamoutTestModeEBasicStreamingIpmu)
{
ModeETest(NV_SOC_HWPM_RESOURCE_CPU);
}

33
libnvsochwpm/test/t410_test.h
View File

@@ -1,11 +1,15 @@
/* /* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. * SPDX-License-Identifier: GPL-2.0-only
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* *
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto. Any use, reproduction, disclosure or
* distribution of this software and related documentation without an express
* license agreement from NVIDIA CORPORATION is strictly prohibited.
*/ */
#ifndef T410_TEST_H #ifndef T410_TEST_H
@@ -13,6 +17,9 @@
#include "nv_soc_hwpm_test.h" #include "nv_soc_hwpm_test.h"
#include <vector>
#include <cstdint>
#define T410_MAX_SOCKETS 2 #define T410_MAX_SOCKETS 2
class T410Tests : public NvSocHwpmTests class T410Tests : public NvSocHwpmTests
@@ -48,14 +55,17 @@ protected:
{ {
mode = MODE_B; mode = MODE_B;
perfmon_idx = 0; perfmon_idx = 0;
perfmon_base = 0;
enable_local_triggering = false; enable_local_triggering = false;
enable_overflow_priming = false; enable_overflow_priming = false;
collect_one = false; collect_one = false;
} }
std::vector<uint32_t> expected_sig_val;
Mode mode; Mode mode;
uint32_t perfmon_idx; uint32_t perfmon_idx;
uint64_t perfmon_base;
bool enable_local_triggering; bool enable_local_triggering;
bool enable_overflow_priming; bool enable_overflow_priming;
@@ -80,7 +90,10 @@ protected:
void SetupPma(nv_soc_hwpm_session session, const PmaConfigurationParams &params); void SetupPma(nv_soc_hwpm_session session, const PmaConfigurationParams &params);
void EnablePmaStreaming(nv_soc_hwpm_session session, const PmaConfigurationParams &params); void EnablePmaStreaming(nv_soc_hwpm_session session, const PmaConfigurationParams &params);
void SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationParams &params); void SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationParams &params);
void SetupWatchbus(nv_soc_hwpm_session session, const PmmConfigurationParams &params); void SetupWatchbusPma(nv_soc_hwpm_session session, const PmmConfigurationParams &params);
void SetupWatchbusNvtherm(nv_soc_hwpm_session session, const PmmConfigurationParams &params);
void SetupWatchbusCsnMbn(nv_soc_hwpm_session session, const PmmConfigurationParams &params);
void SetupWatchbusIpmu(nv_soc_hwpm_session session, const PmmConfigurationParams &params);
void TeardownPma(nv_soc_hwpm_session session); void TeardownPma(nv_soc_hwpm_session session);
void TeardownPmm(nv_soc_hwpm_session session, const PmmConfigurationParams &params); void TeardownPmm(nv_soc_hwpm_session session, const PmmConfigurationParams &params);
void TeardownPerfmux(nv_soc_hwpm_session session); void TeardownPerfmux(nv_soc_hwpm_session session);
@@ -90,6 +103,10 @@ protected:
const PmmConfigurationParams &params, const PmmConfigurationParams &params,
const uint32_t sig_val[4]); const uint32_t sig_val[4]);
void InitPmmParams(nv_soc_hwpm_resource resource, PmmConfigurationParams &params);
void ModeBTest(nv_soc_hwpm_resource resource);
void ModeETest(nv_soc_hwpm_resource resource);
nv_soc_hwpm_device t410_dev[T410_MAX_SOCKETS]; nv_soc_hwpm_device t410_dev[T410_MAX_SOCKETS];
uint32_t t410_dev_count; uint32_t t410_dev_count;
}; };