diff --git a/drivers/tegra/hwpm/hal/t234/ip/display/t234_display.c b/drivers/tegra/hwpm/hal/t234/ip/display/t234_display.c
index c9da61c..ca5cdd6 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/display/t234_display.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/display/t234_display.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_display_inst0_perfmon_element_static_array[
 		.device_index = T234_NVDISPLAY0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_disp_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_disp_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_disp_base_r(),
+		.end_pa = addr_map_rpg_pm_disp_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -48,8 +48,8 @@ static struct hwpm_ip_aperture t234_display_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_disp_base_r(),
 		.end_abs_pa = addr_map_disp_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_disp_base_r(),
+		.end_pa = addr_map_disp_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_disp_alist,
 		.alist_size = ARRAY_SIZE(t234_disp_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/isp/t234_isp.c b/drivers/tegra/hwpm/hal/t234/ip/isp/t234_isp.c
index 39d0e31..270ffc1 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/isp/t234_isp.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/isp/t234_isp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_isp_inst0_perfmon_element_static_array[
 		.device_index = T234_ISP0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_isp0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_isp0_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_isp0_base_r(),
+		.end_pa = addr_map_rpg_pm_isp0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -48,8 +48,8 @@ static struct hwpm_ip_aperture t234_isp_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_isp_thi_base_r(),
 		.end_abs_pa = addr_map_isp_thi_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_isp_thi_base_r(),
+		.end_pa = addr_map_isp_thi_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_isp_thi_alist,
 		.alist_size = ARRAY_SIZE(t234_isp_thi_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/mgbe/t234_mgbe.c b/drivers/tegra/hwpm/hal/t234/ip/mgbe/t234_mgbe.c
index 467a3b7..a1160ef 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/mgbe/t234_mgbe.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/mgbe/t234_mgbe.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_mgbe_inst0_perfmon_element_static_array[
 		.device_index = T234_MGBE0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mgbe0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mgbe0_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mgbe0_base_r(),
+		.end_pa = addr_map_rpg_pm_mgbe0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -49,8 +49,8 @@ static struct hwpm_ip_aperture t234_mgbe_inst1_perfmon_element_static_array[
 		.device_index = T234_MGBE1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mgbe1_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mgbe1_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mgbe1_base_r(),
+		.end_pa = addr_map_rpg_pm_mgbe1_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -69,8 +69,8 @@ static struct hwpm_ip_aperture t234_mgbe_inst2_perfmon_element_static_array[
 		.device_index = T234_MGBE2_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mgbe2_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mgbe2_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mgbe2_base_r(),
+		.end_pa = addr_map_rpg_pm_mgbe2_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -89,8 +89,8 @@ static struct hwpm_ip_aperture t234_mgbe_inst3_perfmon_element_static_array[
 		.device_index = T234_MGBE3_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mgbe3_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mgbe3_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mgbe3_base_r(),
+		.end_pa = addr_map_rpg_pm_mgbe3_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -108,8 +108,8 @@ static struct hwpm_ip_aperture t234_mgbe_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mgbe0_mac_rm_base_r(),
 		.end_abs_pa = addr_map_mgbe0_mac_rm_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mgbe0_mac_rm_base_r(),
+		.end_pa = addr_map_mgbe0_mac_rm_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mgbe_alist,
 		.alist_size = ARRAY_SIZE(t234_mgbe_alist),
@@ -127,8 +127,8 @@ static struct hwpm_ip_aperture t234_mgbe_inst1_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mgbe1_mac_rm_base_r(),
 		.end_abs_pa = addr_map_mgbe1_mac_rm_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mgbe1_mac_rm_base_r(),
+		.end_pa = addr_map_mgbe1_mac_rm_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mgbe_alist,
 		.alist_size = ARRAY_SIZE(t234_mgbe_alist),
@@ -146,8 +146,8 @@ static struct hwpm_ip_aperture t234_mgbe_inst2_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mgbe2_mac_rm_base_r(),
 		.end_abs_pa = addr_map_mgbe2_mac_rm_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mgbe2_mac_rm_base_r(),
+		.end_pa = addr_map_mgbe2_mac_rm_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mgbe_alist,
 		.alist_size = ARRAY_SIZE(t234_mgbe_alist),
@@ -165,8 +165,8 @@ static struct hwpm_ip_aperture t234_mgbe_inst3_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mgbe3_mac_rm_base_r(),
 		.end_abs_pa = addr_map_mgbe3_mac_rm_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mgbe3_mac_rm_base_r(),
+		.end_pa = addr_map_mgbe3_mac_rm_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mgbe_alist,
 		.alist_size = ARRAY_SIZE(t234_mgbe_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/mss_channel/t234_mss_channel.c b/drivers/tegra/hwpm/hal/t234/ip/mss_channel/t234_mss_channel.c
index 6f0f73f..298ee22 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/mss_channel/t234_mss_channel.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/mss_channel/t234_mss_channel.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTA0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss0_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss0_base_r(),
+		.end_pa = addr_map_rpg_pm_mss0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -45,8 +45,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTA1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss1_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss1_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss1_base_r(),
+		.end_pa = addr_map_rpg_pm_mss1_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -61,8 +61,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTA2_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss2_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss2_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss2_base_r(),
+		.end_pa = addr_map_rpg_pm_mss2_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -77,8 +77,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTA3_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss3_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss3_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss3_base_r(),
+		.end_pa = addr_map_rpg_pm_mss3_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -93,8 +93,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTB0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss4_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss4_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss4_base_r(),
+		.end_pa = addr_map_rpg_pm_mss4_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -109,8 +109,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTB1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss5_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss5_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss5_base_r(),
+		.end_pa = addr_map_rpg_pm_mss5_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -125,8 +125,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTB2_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss6_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss6_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss6_base_r(),
+		.end_pa = addr_map_rpg_pm_mss6_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -141,8 +141,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTB3_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss7_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss7_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss7_base_r(),
+		.end_pa = addr_map_rpg_pm_mss7_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -157,8 +157,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTC0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss8_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss8_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss8_base_r(),
+		.end_pa = addr_map_rpg_pm_mss8_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -173,8 +173,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTC1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss9_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss9_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss9_base_r(),
+		.end_pa = addr_map_rpg_pm_mss9_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -189,8 +189,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTC2_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss10_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss10_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss10_base_r(),
+		.end_pa = addr_map_rpg_pm_mss10_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -205,8 +205,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTC3_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss11_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss11_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss11_base_r(),
+		.end_pa = addr_map_rpg_pm_mss11_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -221,8 +221,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTD0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss12_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss12_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss12_base_r(),
+		.end_pa = addr_map_rpg_pm_mss12_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -237,8 +237,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTD1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss13_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss13_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss13_base_r(),
+		.end_pa = addr_map_rpg_pm_mss13_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -253,8 +253,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTD2_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss14_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss14_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss14_base_r(),
+		.end_pa = addr_map_rpg_pm_mss14_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -269,8 +269,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
 		.device_index = T234_MSS_CHANNEL_PARTD3_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mss15_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mss15_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mss15_base_r(),
+		.end_pa = addr_map_rpg_pm_mss15_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -288,8 +288,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc0_base_r(),
 		.end_abs_pa = addr_map_mc0_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc0_base_r(),
+		.end_pa = addr_map_mc0_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -303,8 +303,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc1_base_r(),
 		.end_abs_pa = addr_map_mc1_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc1_base_r(),
+		.end_pa = addr_map_mc1_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -318,8 +318,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc2_base_r(),
 		.end_abs_pa = addr_map_mc2_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc2_base_r(),
+		.end_pa = addr_map_mc2_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -333,8 +333,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc3_base_r(),
 		.end_abs_pa = addr_map_mc3_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc3_base_r(),
+		.end_pa = addr_map_mc3_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -348,8 +348,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc4_base_r(),
 		.end_abs_pa = addr_map_mc4_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc4_base_r(),
+		.end_pa = addr_map_mc4_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -363,8 +363,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc5_base_r(),
 		.end_abs_pa = addr_map_mc5_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc5_base_r(),
+		.end_pa = addr_map_mc5_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -378,8 +378,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc6_base_r(),
 		.end_abs_pa = addr_map_mc6_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc6_base_r(),
+		.end_pa = addr_map_mc6_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -393,8 +393,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc7_base_r(),
 		.end_abs_pa = addr_map_mc7_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc7_base_r(),
+		.end_pa = addr_map_mc7_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -408,8 +408,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc8_base_r(),
 		.end_abs_pa = addr_map_mc8_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc8_base_r(),
+		.end_pa = addr_map_mc8_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -423,8 +423,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc9_base_r(),
 		.end_abs_pa = addr_map_mc9_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc9_base_r(),
+		.end_pa = addr_map_mc9_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -438,8 +438,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc10_base_r(),
 		.end_abs_pa = addr_map_mc10_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc10_base_r(),
+		.end_pa = addr_map_mc10_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -453,8 +453,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc11_base_r(),
 		.end_abs_pa = addr_map_mc11_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc11_base_r(),
+		.end_pa = addr_map_mc11_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -468,8 +468,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc12_base_r(),
 		.end_abs_pa = addr_map_mc12_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc12_base_r(),
+		.end_pa = addr_map_mc12_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -483,8 +483,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc13_base_r(),
 		.end_abs_pa = addr_map_mc13_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc13_base_r(),
+		.end_pa = addr_map_mc13_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -498,8 +498,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc14_base_r(),
 		.end_abs_pa = addr_map_mc14_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc14_base_r(),
+		.end_pa = addr_map_mc14_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -513,8 +513,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc15_base_r(),
 		.end_abs_pa = addr_map_mc15_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc15_base_r(),
+		.end_pa = addr_map_mc15_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
@@ -532,8 +532,8 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_broadcast_element_static_a
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mcb_base_r(),
 		.end_abs_pa = addr_map_mcb_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mcb_base_r(),
+		.end_pa = addr_map_mcb_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_channel_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_channel_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/mss_gpu_hub/t234_mss_gpu_hub.c b/drivers/tegra/hwpm/hal/t234/ip/mss_gpu_hub/t234_mss_gpu_hub.c
index 137a789..3c2d04e 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/mss_gpu_hub/t234_mss_gpu_hub.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/mss_gpu_hub/t234_mss_gpu_hub.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmon_element_static_arr
 		.device_index = T234_MSSNVLHSH0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mssnvl_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mssnvl_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mssnvl_base_r(),
+		.end_pa = addr_map_rpg_pm_mssnvl_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -48,8 +48,8 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mss_nvlink_1_base_r(),
 		.end_abs_pa = addr_map_mss_nvlink_1_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mss_nvlink_1_base_r(),
+		.end_pa = addr_map_mss_nvlink_1_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_nvlink_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_nvlink_alist),
@@ -63,8 +63,8 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mss_nvlink_2_base_r(),
 		.end_abs_pa = addr_map_mss_nvlink_2_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mss_nvlink_2_base_r(),
+		.end_pa = addr_map_mss_nvlink_2_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_nvlink_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_nvlink_alist),
@@ -78,8 +78,8 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mss_nvlink_3_base_r(),
 		.end_abs_pa = addr_map_mss_nvlink_3_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mss_nvlink_3_base_r(),
+		.end_pa = addr_map_mss_nvlink_3_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_nvlink_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_nvlink_alist),
@@ -93,8 +93,8 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mss_nvlink_4_base_r(),
 		.end_abs_pa = addr_map_mss_nvlink_4_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mss_nvlink_4_base_r(),
+		.end_pa = addr_map_mss_nvlink_4_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_nvlink_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_nvlink_alist),
@@ -108,8 +108,8 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mss_nvlink_5_base_r(),
 		.end_abs_pa = addr_map_mss_nvlink_5_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mss_nvlink_5_base_r(),
+		.end_pa = addr_map_mss_nvlink_5_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_nvlink_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_nvlink_alist),
@@ -123,8 +123,8 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mss_nvlink_6_base_r(),
 		.end_abs_pa = addr_map_mss_nvlink_6_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mss_nvlink_6_base_r(),
+		.end_pa = addr_map_mss_nvlink_6_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_nvlink_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_nvlink_alist),
@@ -138,8 +138,8 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mss_nvlink_7_base_r(),
 		.end_abs_pa = addr_map_mss_nvlink_7_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mss_nvlink_7_base_r(),
+		.end_pa = addr_map_mss_nvlink_7_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_nvlink_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_nvlink_alist),
@@ -153,8 +153,8 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mss_nvlink_8_base_r(),
 		.end_abs_pa = addr_map_mss_nvlink_8_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_mss_nvlink_8_base_r(),
+		.end_pa = addr_map_mss_nvlink_8_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mss_nvlink_alist,
 		.alist_size = ARRAY_SIZE(t234_mss_nvlink_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/mss_iso_niso_hubs/t234_mss_iso_niso_hubs.c b/drivers/tegra/hwpm/hal/t234/ip/mss_iso_niso_hubs/t234_mss_iso_niso_hubs.c
index 50f9702..28c9184 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/mss_iso_niso_hubs/t234_mss_iso_niso_hubs.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/mss_iso_niso_hubs/t234_mss_iso_niso_hubs.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmon_element_stati
 		.device_index = T234_MSSHUB0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_msshub0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_msshub0_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_msshub0_base_r(),
+		.end_pa = addr_map_rpg_pm_msshub0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -45,8 +45,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmon_element_stati
 		.device_index = T234_MSSHUB1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_msshub1_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_msshub1_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_msshub1_base_r(),
+		.end_pa = addr_map_rpg_pm_msshub1_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -64,8 +64,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc0_base_r(),
 		.end_abs_pa = addr_map_mc0_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc0_base_r(),
+		.end_pa = addr_map_mc0_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
 		.alist_size =
@@ -80,8 +80,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc1_base_r(),
 		.end_abs_pa = addr_map_mc1_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc1_base_r(),
+		.end_pa = addr_map_mc1_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
 		.alist_size =
@@ -96,8 +96,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc2_base_r(),
 		.end_abs_pa = addr_map_mc2_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc2_base_r(),
+		.end_pa = addr_map_mc2_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
 		.alist_size =
@@ -112,8 +112,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc3_base_r(),
 		.end_abs_pa = addr_map_mc3_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc3_base_r(),
+		.end_pa = addr_map_mc3_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
 		.alist_size =
@@ -128,8 +128,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc4_base_r(),
 		.end_abs_pa = addr_map_mc4_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc4_base_r(),
+		.end_pa = addr_map_mc4_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
 		.alist_size =
@@ -144,8 +144,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc5_base_r(),
 		.end_abs_pa = addr_map_mc5_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc5_base_r(),
+		.end_pa = addr_map_mc5_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
 		.alist_size =
@@ -160,8 +160,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc6_base_r(),
 		.end_abs_pa = addr_map_mc6_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc6_base_r(),
+		.end_pa = addr_map_mc6_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
 		.alist_size =
@@ -176,8 +176,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc7_base_r(),
 		.end_abs_pa = addr_map_mc7_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc7_base_r(),
+		.end_pa = addr_map_mc7_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
 		.alist_size =
@@ -192,8 +192,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc8_base_r(),
 		.end_abs_pa = addr_map_mc8_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc8_base_r(),
+		.end_pa = addr_map_mc8_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc8_res_mss_iso_niso_hub_alist,
 		.alist_size = ARRAY_SIZE(t234_mc8_res_mss_iso_niso_hub_alist),
@@ -211,8 +211,8 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_broadcast_element_sta
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mcb_base_r(),
 		.end_abs_pa = addr_map_mcb_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mcb_base_r(),
+		.end_pa = addr_map_mcb_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mcb_res_mss_iso_niso_hub_alist,
 		.alist_size = ARRAY_SIZE(t234_mcb_res_mss_iso_niso_hub_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/mss_mcf/t234_mss_mcf.c b/drivers/tegra/hwpm/hal/t234/ip/mss_mcf/t234_mss_mcf.c
index 55392cc..cbf3902 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/mss_mcf/t234_mss_mcf.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/mss_mcf/t234_mss_mcf.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
 		.device_index = T234_MSSMCFCLIENT0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mcf0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mcf0_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mcf0_base_r(),
+		.end_pa = addr_map_rpg_pm_mcf0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -45,8 +45,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
 		.device_index = T234_MSSMCFMEM0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mcf1_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mcf1_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mcf1_base_r(),
+		.end_pa = addr_map_rpg_pm_mcf1_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -61,8 +61,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
 		.device_index = T234_MSSMCFMEM1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_mcf2_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_mcf2_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_mcf2_base_r(),
+		.end_pa = addr_map_rpg_pm_mcf2_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -80,8 +80,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc0_base_r(),
 		.end_abs_pa = addr_map_mc0_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc0_base_r(),
+		.end_pa = addr_map_mc0_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to1_mss_mcf_alist,
 		.alist_size = ARRAY_SIZE(t234_mc0to1_mss_mcf_alist),
@@ -95,8 +95,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc1_base_r(),
 		.end_abs_pa = addr_map_mc1_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc1_base_r(),
+		.end_pa = addr_map_mc1_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc0to1_mss_mcf_alist,
 		.alist_size = ARRAY_SIZE(t234_mc0to1_mss_mcf_alist),
@@ -110,8 +110,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc2_base_r(),
 		.end_abs_pa = addr_map_mc2_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc2_base_r(),
+		.end_pa = addr_map_mc2_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc2to7_mss_mcf_alist,
 		.alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist),
@@ -125,8 +125,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc3_base_r(),
 		.end_abs_pa = addr_map_mc3_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc3_base_r(),
+		.end_pa = addr_map_mc3_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc2to7_mss_mcf_alist,
 		.alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist),
@@ -140,8 +140,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc4_base_r(),
 		.end_abs_pa = addr_map_mc4_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc4_base_r(),
+		.end_pa = addr_map_mc4_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc2to7_mss_mcf_alist,
 		.alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist),
@@ -155,8 +155,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc5_base_r(),
 		.end_abs_pa = addr_map_mc5_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc5_base_r(),
+		.end_pa = addr_map_mc5_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc2to7_mss_mcf_alist,
 		.alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist),
@@ -170,8 +170,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc6_base_r(),
 		.end_abs_pa = addr_map_mc6_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc6_base_r(),
+		.end_pa = addr_map_mc6_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc2to7_mss_mcf_alist,
 		.alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist),
@@ -185,8 +185,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mc7_base_r(),
 		.end_abs_pa = addr_map_mc7_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mc7_base_r(),
+		.end_pa = addr_map_mc7_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mc2to7_mss_mcf_alist,
 		.alist_size = ARRAY_SIZE(t234_mc2to7_mss_mcf_alist),
@@ -204,8 +204,8 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_broadcast_element_static_array
 		.name = {'\0'},
 		.start_abs_pa = addr_map_mcb_base_r(),
 		.end_abs_pa = addr_map_mcb_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_mcb_base_r(),
+		.end_pa = addr_map_mcb_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_mcb_mss_mcf_alist,
 		.alist_size = ARRAY_SIZE(t234_mcb_mss_mcf_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/nvdec/t234_nvdec.c b/drivers/tegra/hwpm/hal/t234/ip/nvdec/t234_nvdec.c
index 57ea365..d6e329e 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/nvdec/t234_nvdec.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/nvdec/t234_nvdec.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_nvdec_inst0_perfmon_element_static_array[
 		.device_index = T234_NVDECA0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_nvdec0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_nvdec0_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_nvdec0_base_r(),
+		.end_pa = addr_map_rpg_pm_nvdec0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -48,8 +48,8 @@ static struct hwpm_ip_aperture t234_nvdec_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_nvdec_base_r(),
 		.end_abs_pa = addr_map_nvdec_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_nvdec_base_r(),
+		.end_pa = addr_map_nvdec_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_nvdec_alist,
 		.alist_size = ARRAY_SIZE(t234_nvdec_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/nvdla/t234_nvdla.c b/drivers/tegra/hwpm/hal/t234/ip/nvdla/t234_nvdla.c
index 6ead9d0..029f7a9 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/nvdla/t234_nvdla.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/nvdla/t234_nvdla.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_nvdla_inst0_perfmon_element_static_array[
 		.device_index = T234_NVDLAB0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_nvdla0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_nvdla0_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_nvdla0_base_r(),
+		.end_pa = addr_map_rpg_pm_nvdla0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -49,8 +49,8 @@ static struct hwpm_ip_aperture t234_nvdla_inst1_perfmon_element_static_array[
 		.device_index = T234_NVDLAB1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_nvdla1_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_nvdla1_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_rpg_pm_nvdla1_base_r(),
+		.end_pa = addr_map_rpg_pm_nvdla1_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -68,8 +68,8 @@ static struct hwpm_ip_aperture t234_nvdla_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_nvdla0_base_r(),
 		.end_abs_pa = addr_map_nvdla0_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_nvdla0_base_r(),
+		.end_pa = addr_map_nvdla0_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_nvdla_alist,
 		.alist_size = ARRAY_SIZE(t234_nvdla_alist),
@@ -87,8 +87,8 @@ static struct hwpm_ip_aperture t234_nvdla_inst1_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_nvdla1_base_r(),
 		.end_abs_pa = addr_map_nvdla1_limit_r(),
-		.start_pa = 0,
-		.end_pa = 0,
+		.start_pa = addr_map_nvdla1_base_r(),
+		.end_pa = addr_map_nvdla1_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_nvdla_alist,
 		.alist_size = ARRAY_SIZE(t234_nvdla_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/nvenc/t234_nvenc.c b/drivers/tegra/hwpm/hal/t234/ip/nvenc/t234_nvenc.c
index 9d3046b..2614a26 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/nvenc/t234_nvenc.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/nvenc/t234_nvenc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_nvenc_inst0_perfmon_element_static_array[
 		.device_index = T234_NVENCA0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_nvenc0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_nvenc0_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_nvenc0_base_r(),
+		.end_pa = addr_map_rpg_pm_nvenc0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -48,8 +48,8 @@ static struct hwpm_ip_aperture t234_nvenc_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_nvenc_base_r(),
 		.end_abs_pa = addr_map_nvenc_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_nvenc_base_r(),
+		.end_pa = addr_map_nvenc_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_nvenc_alist,
 		.alist_size = ARRAY_SIZE(t234_nvenc_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/ofa/t234_ofa.c b/drivers/tegra/hwpm/hal/t234/ip/ofa/t234_ofa.c
index 4579b17..d356340 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/ofa/t234_ofa.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/ofa/t234_ofa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_ofa_inst0_perfmon_element_static_array[
 		.device_index = T234_OFAA0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_ofa_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_ofa_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_ofa_base_r(),
+		.end_pa = addr_map_rpg_pm_ofa_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -48,8 +48,8 @@ static struct hwpm_ip_aperture t234_ofa_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_ofa_base_r(),
 		.end_abs_pa = addr_map_ofa_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_ofa_base_r(),
+		.end_pa = addr_map_ofa_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_ofa_alist,
 		.alist_size = ARRAY_SIZE(t234_ofa_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/pcie/t234_pcie.c b/drivers/tegra/hwpm/hal/t234/ip/pcie/t234_pcie.c
index 45c7e38..370e734 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/pcie/t234_pcie.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/pcie/t234_pcie.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_pcie_inst0_perfmon_element_static_array[
 		.device_index = T234_PCIE0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c0_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c0_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -49,8 +49,8 @@ static struct hwpm_ip_aperture t234_pcie_inst1_perfmon_element_static_array[
 		.device_index = T234_PCIE1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c1_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c1_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c1_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c1_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -69,8 +69,8 @@ static struct hwpm_ip_aperture t234_pcie_inst2_perfmon_element_static_array[
 		.device_index = T234_PCIE2_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c2_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c2_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c2_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c2_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -89,8 +89,8 @@ static struct hwpm_ip_aperture t234_pcie_inst3_perfmon_element_static_array[
 		.device_index = T234_PCIE3_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c3_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c3_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c3_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c3_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -109,8 +109,8 @@ static struct hwpm_ip_aperture t234_pcie_inst4_perfmon_element_static_array[
 		.device_index = T234_PCIE4_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c4_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c4_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c4_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c4_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -129,8 +129,8 @@ static struct hwpm_ip_aperture t234_pcie_inst5_perfmon_element_static_array[
 		.device_index = T234_PCIE5_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c5_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c5_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c5_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c5_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -149,8 +149,8 @@ static struct hwpm_ip_aperture t234_pcie_inst6_perfmon_element_static_array[
 		.device_index = T234_PCIE6_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c6_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c6_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c6_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c6_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -169,8 +169,8 @@ static struct hwpm_ip_aperture t234_pcie_inst7_perfmon_element_static_array[
 		.device_index = T234_PCIE7_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c7_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c7_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c7_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c7_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -189,8 +189,8 @@ static struct hwpm_ip_aperture t234_pcie_inst8_perfmon_element_static_array[
 		.device_index = T234_PCIE8_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c8_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c8_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c8_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c8_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -209,8 +209,8 @@ static struct hwpm_ip_aperture t234_pcie_inst9_perfmon_element_static_array[
 		.device_index = T234_PCIE9_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c9_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c9_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c9_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c9_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -229,8 +229,8 @@ static struct hwpm_ip_aperture t234_pcie_inst10_perfmon_element_static_array[
 		.device_index = T234_PCIE10_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pcie_c10_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pcie_c10_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pcie_c10_base_r(),
+		.end_pa = addr_map_rpg_pm_pcie_c10_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -248,8 +248,8 @@ static struct hwpm_ip_aperture t234_pcie_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c0_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c0_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c0_ctl_base_r(),
+		.end_pa = addr_map_pcie_c0_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -267,8 +267,8 @@ static struct hwpm_ip_aperture t234_pcie_inst1_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c1_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c1_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c1_ctl_base_r(),
+		.end_pa = addr_map_pcie_c1_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -286,8 +286,8 @@ static struct hwpm_ip_aperture t234_pcie_inst2_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c2_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c2_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c2_ctl_base_r(),
+		.end_pa = addr_map_pcie_c2_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -305,8 +305,8 @@ static struct hwpm_ip_aperture t234_pcie_inst3_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c3_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c3_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c3_ctl_base_r(),
+		.end_pa = addr_map_pcie_c3_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -324,8 +324,8 @@ static struct hwpm_ip_aperture t234_pcie_inst4_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c4_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c4_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c4_ctl_base_r(),
+		.end_pa = addr_map_pcie_c4_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -343,8 +343,8 @@ static struct hwpm_ip_aperture t234_pcie_inst5_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c5_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c5_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c5_ctl_base_r(),
+		.end_pa = addr_map_pcie_c5_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -362,8 +362,8 @@ static struct hwpm_ip_aperture t234_pcie_inst6_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c6_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c6_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c6_ctl_base_r(),
+		.end_pa = addr_map_pcie_c6_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -381,8 +381,8 @@ static struct hwpm_ip_aperture t234_pcie_inst7_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c7_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c7_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c7_ctl_base_r(),
+		.end_pa = addr_map_pcie_c7_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -400,8 +400,8 @@ static struct hwpm_ip_aperture t234_pcie_inst8_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c8_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c8_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c8_ctl_base_r(),
+		.end_pa = addr_map_pcie_c8_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -419,8 +419,8 @@ static struct hwpm_ip_aperture t234_pcie_inst9_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c9_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c9_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c9_ctl_base_r(),
+		.end_pa = addr_map_pcie_c9_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
@@ -438,8 +438,8 @@ static struct hwpm_ip_aperture t234_pcie_inst10_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pcie_c10_ctl_base_r(),
 		.end_abs_pa = addr_map_pcie_c10_ctl_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pcie_c10_ctl_base_r(),
+		.end_pa = addr_map_pcie_c10_ctl_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pcie_ctl_alist,
 		.alist_size = ARRAY_SIZE(t234_pcie_ctl_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/pma/t234_pma.c b/drivers/tegra/hwpm/hal/t234/ip/pma/t234_pma.c
index c613d30..430dbf6 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/pma/t234_pma.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/pma/t234_pma.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_pma_inst0_perfmon_element_static_array[
 		.device_index = T234_SYS0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pma_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pma_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pma_base_r(),
+		.end_pa = addr_map_rpg_pm_pma_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -49,8 +49,8 @@ static struct hwpm_ip_aperture t234_pma_inst0_perfmux_element_static_array[
 		.device_index = T234_PMA_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_pma_base_r(),
 		.end_abs_pa = addr_map_pma_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pma_base_r(),
+		.end_pa = addr_map_pma_limit_r(),
 		.base_pa = addr_map_pma_base_r(),
 		.alist = t234_pma_res_pma_alist,
 		.alist_size = ARRAY_SIZE(t234_pma_res_pma_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/pva/t234_pva.c b/drivers/tegra/hwpm/hal/t234/ip/pva/t234_pva.c
index 8344c03..84f9c90 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/pva/t234_pva.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/pva/t234_pva.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
 		.device_index = T234_PVAV0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pva0_0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pva0_0_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pva0_0_base_r(),
+		.end_pa = addr_map_rpg_pm_pva0_0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -45,8 +45,8 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
 		.device_index = T234_PVAV1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pva0_1_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pva0_1_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pva0_1_base_r(),
+		.end_pa = addr_map_rpg_pm_pva0_1_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -61,8 +61,8 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
 		.device_index = T234_PVAC0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_pva0_2_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_pva0_2_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_pva0_2_base_r(),
+		.end_pa = addr_map_rpg_pm_pva0_2_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -80,8 +80,8 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_pva0_pm_base_r(),
 		.end_abs_pa = addr_map_pva0_pm_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pva0_pm_base_r(),
+		.end_pa = addr_map_pva0_pm_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_pva0_pm_alist,
 		.alist_size = ARRAY_SIZE(t234_pva0_pm_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/rtr/t234_rtr.c b/drivers/tegra/hwpm/hal/t234/ip/rtr/t234_rtr.c
index 8cb590a..03aab41 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/rtr/t234_rtr.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/rtr/t234_rtr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -30,8 +30,8 @@ static struct hwpm_ip_aperture t234_rtr_inst0_perfmux_element_static_array[
 		.device_index = T234_RTR_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rtr_base_r(),
 		.end_abs_pa = addr_map_rtr_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rtr_base_r(),
+		.end_pa = addr_map_rtr_limit_r(),
 		.base_pa = addr_map_rtr_base_r(),
 		.alist = t234_rtr_alist,
 		.alist_size = ARRAY_SIZE(t234_rtr_alist),
@@ -52,8 +52,8 @@ static struct hwpm_ip_aperture t234_rtr_inst1_perfmux_element_static_array[
 		.device_index = T234_PMA_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_pma_base_r(),
 		.end_abs_pa = addr_map_pma_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_pma_base_r(),
+		.end_pa = addr_map_pma_limit_r(),
 		.base_pa = addr_map_pma_base_r(),
 		.alist = t234_pma_res_cmd_slice_rtr_alist,
 		.alist_size = ARRAY_SIZE(t234_pma_res_cmd_slice_rtr_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/scf/t234_scf.c b/drivers/tegra/hwpm/hal/t234/ip/scf/t234_scf.c
index ada6720..214bc28 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/scf/t234_scf.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/scf/t234_scf.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_scf_inst0_perfmon_element_static_array[
 		.device_index = T234_SCF_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_scf_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_scf_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_scf_base_r(),
+		.end_pa = addr_map_rpg_pm_scf_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/vi/t234_vi.c b/drivers/tegra/hwpm/hal/t234/ip/vi/t234_vi.c
index 97ab1f9..eafb9a3 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/vi/t234_vi.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/vi/t234_vi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_vi_inst0_perfmon_element_static_array[
 		.device_index = T234_VI0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_vi0_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_vi0_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_vi0_base_r(),
+		.end_pa = addr_map_rpg_pm_vi0_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -49,8 +49,8 @@ static struct hwpm_ip_aperture t234_vi_inst1_perfmon_element_static_array[
 		.device_index = T234_VI1_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_vi1_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_vi1_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_vi1_base_r(),
+		.end_pa = addr_map_rpg_pm_vi1_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -68,8 +68,8 @@ static struct hwpm_ip_aperture t234_vi_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_vi_thi_base_r(),
 		.end_abs_pa = addr_map_vi_thi_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_vi_thi_base_r(),
+		.end_pa = addr_map_vi_thi_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_vi_thi_alist,
 		.alist_size = ARRAY_SIZE(t234_vi_thi_alist),
@@ -87,8 +87,8 @@ static struct hwpm_ip_aperture t234_vi_inst1_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_vi2_thi_base_r(),
 		.end_abs_pa = addr_map_vi2_thi_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_vi2_thi_base_r(),
+		.end_pa = addr_map_vi2_thi_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_vi_thi_alist,
 		.alist_size = ARRAY_SIZE(t234_vi_thi_alist),
diff --git a/drivers/tegra/hwpm/hal/t234/ip/vic/t234_vic.c b/drivers/tegra/hwpm/hal/t234/ip/vic/t234_vic.c
index 049a68d..6af4056 100644
--- a/drivers/tegra/hwpm/hal/t234/ip/vic/t234_vic.c
+++ b/drivers/tegra/hwpm/hal/t234/ip/vic/t234_vic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,8 +29,8 @@ static struct hwpm_ip_aperture t234_vic_inst0_perfmon_element_static_array[
 		.device_index = T234_VICA0_PERFMON_DEVICE_NODE_INDEX,
 		.start_abs_pa = addr_map_rpg_pm_vic_base_r(),
 		.end_abs_pa = addr_map_rpg_pm_vic_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_rpg_pm_vic_base_r(),
+		.end_pa = addr_map_rpg_pm_vic_limit_r(),
 		.base_pa = addr_map_rpg_pm_base_r(),
 		.alist = t234_perfmon_alist,
 		.alist_size = ARRAY_SIZE(t234_perfmon_alist),
@@ -48,8 +48,8 @@ static struct hwpm_ip_aperture t234_vic_inst0_perfmux_element_static_array[
 		.name = {'\0'},
 		.start_abs_pa = addr_map_vic_base_r(),
 		.end_abs_pa = addr_map_vic_limit_r(),
-		.start_pa = 0ULL,
-		.end_pa = 0ULL,
+		.start_pa = addr_map_vic_base_r(),
+		.end_pa = addr_map_vic_limit_r(),
 		.base_pa = 0ULL,
 		.alist = t234_vic_alist,
 		.alist_size = ARRAY_SIZE(t234_vic_alist),
diff --git a/drivers/tegra/hwpm/include/tegra_hwpm.h b/drivers/tegra/hwpm/include/tegra_hwpm.h
index 6d7ce89..c95472e 100644
--- a/drivers/tegra/hwpm/include/tegra_hwpm.h
+++ b/drivers/tegra/hwpm/include/tegra_hwpm.h
@@ -206,12 +206,6 @@ struct hwpm_ip_aperture {
 	 */
 	u32 element_index;
 
-	/* MMIO device tree aperture - only populated for perfmon */
-	void __iomem *dt_mmio;
-
-	/* DT tree name */
-	char name[64];
-
 	/*
 	 * Device index corresponding to device node aperture address index
 	 * in Device tree or ACPI table.
@@ -219,22 +213,44 @@ struct hwpm_ip_aperture {
 	 */
 	u32 device_index;
 
-	/* Allowlist */
-	struct allowlist *alist;
-	u64 alist_size;
+	/* MMIO device tree aperture - only populated for perfmon */
+	void __iomem *dt_mmio;
 
-	/* Physical aperture */
-	u64 start_abs_pa;
-	u64 end_abs_pa;
+	/* DT tree name */
+	char name[64];
 
-	/* MMIO aperture */
+	/*
+	 * MMIO address for the aperture. This address range is present
+	 * in the device node.
+	 * MMIO addresses can be same as virtual aperture addresses.
+	 */
 	u64 start_pa;
 	u64 end_pa;
 
-	/* Base address: used to calculate register offset */
+	/*
+	 * Virtual aperture address
+	 * Regops addresses should be in this range.
+	 */
+	u64 start_abs_pa;
+	u64 end_abs_pa;
+
+	/*
+	 * Base address of Perfmon Block
+	 * All perfmon apertures have identical placement of registers
+	 * HWPM read/write logic for perfmons refers to registers in the first
+	 * perfmon block. Use this base address value to compute register
+	 * offset in HWPM read/write functions.
+	 */
 	u64 base_pa;
 
-	/* Fake registers for VDK which doesn't have a SOC HWPM fmodel */
+	/* Allowlist */
+	u64 alist_size;
+	struct allowlist *alist;
+
+	/*
+	 * Fake registers for simulation where SOC HWPM is not implemented
+	 * Use virtual aperture address values for allocation.
+	 */
 	u32 *fake_registers;
 };
 
diff --git a/drivers/tegra/hwpm/os/linux/aperture_utils.c b/drivers/tegra/hwpm/os/linux/aperture_utils.c
index 7902b0b..564cd78 100644
--- a/drivers/tegra/hwpm/os/linux/aperture_utils.c
+++ b/drivers/tegra/hwpm/os/linux/aperture_utils.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -37,6 +37,7 @@ int tegra_hwpm_perfmon_reserve_impl(struct tegra_soc_hwpm *hwpm,
 	}
 
 	/* Reserve */
+	/* Make sure that resource exists in device node */
 	res = platform_get_resource(hwpm_linux->pdev,
 		IORESOURCE_MEM, perfmon->device_index);
 	if ((!res) || (res->start == 0) || (res->end == 0)) {
@@ -44,26 +45,17 @@ int tegra_hwpm_perfmon_reserve_impl(struct tegra_soc_hwpm *hwpm,
 		return -ENOMEM;
 	}
 
-	if (res->start != perfmon->start_abs_pa) {
+	/* Confirm that correct resource is retrived */
+	if (res->start != perfmon->start_pa) {
 		tegra_hwpm_err(hwpm, "Failed to get correct"
 			"perfmon address for %s,"
 			"Expected - 0x%llx, Returned - 0x%llx",
-			perfmon->name, perfmon->start_abs_pa,
-			res->start);
+			perfmon->name, perfmon->start_pa, res->start);
 		return -ENOMEM;
 	}
 
-	perfmon->dt_mmio = devm_ioremap(
-		hwpm_linux->dev, res->start, resource_size(res));
-	if (IS_ERR(perfmon->dt_mmio)) {
-		tegra_hwpm_err(hwpm, "Couldn't map perfmon %s", perfmon->name);
-		return PTR_ERR(perfmon->dt_mmio);
-	}
-
-	perfmon->start_pa = res->start;
-	perfmon->end_pa = res->end;
-
 	if (hwpm->fake_registers_enabled) {
+		/* Allocate resource memory as MMIO */
 		u64 address_range = tegra_hwpm_safe_add_u64(
 			tegra_hwpm_safe_sub_u64(res->end, res->start), 1ULL);
 		u64 num_regs = address_range / sizeof(u32);
@@ -76,7 +68,17 @@ int tegra_hwpm_perfmon_reserve_impl(struct tegra_soc_hwpm *hwpm,
 				perfmon->start_abs_pa, perfmon->end_abs_pa);
 			return -ENOMEM;
 		}
+	} else {
+		/* Map resource memory in kernel space */
+		perfmon->dt_mmio = devm_ioremap(
+			hwpm_linux->dev, res->start, resource_size(res));
+		if (IS_ERR(perfmon->dt_mmio)) {
+			tegra_hwpm_err(hwpm,
+				"Couldn't map perfmon %s", perfmon->name);
+			return PTR_ERR(perfmon->dt_mmio);
+		}
 	}
+
 	return 0;
 }
 
@@ -88,14 +90,11 @@ int tegra_hwpm_perfmux_reserve_impl(struct tegra_soc_hwpm *hwpm,
 
 	tegra_hwpm_fn(hwpm, " ");
 
-	perfmux->start_pa = perfmux->start_abs_pa;
-	perfmux->end_pa = perfmux->end_abs_pa;
-
 	/* Allocate fake registers */
 	if (hwpm->fake_registers_enabled) {
 		u64 address_range = tegra_hwpm_safe_add_u64(
-			tegra_hwpm_safe_sub_u64(
-				perfmux->end_pa, perfmux->start_pa), 1ULL);
+			tegra_hwpm_safe_sub_u64(perfmux->end_abs_pa,
+				perfmux->start_abs_pa), 1ULL);
 		u64 num_regs = address_range / sizeof(u32);
 
 		perfmux->fake_registers =
@@ -103,7 +102,7 @@ int tegra_hwpm_perfmux_reserve_impl(struct tegra_soc_hwpm *hwpm,
 		if (perfmux->fake_registers == NULL) {
 			tegra_hwpm_err(hwpm, "Aperture(0x%llx - 0x%llx):"
 				" Couldn't allocate memory for fake registers",
-				perfmux->start_pa, perfmux->end_pa);
+				perfmux->start_abs_pa, perfmux->end_abs_pa);
 			return -ENOMEM;
 		}
 	}
@@ -149,8 +148,6 @@ int tegra_hwpm_perfmon_release_impl(struct tegra_soc_hwpm *hwpm,
 	}
 	devm_iounmap(hwpm_linux->dev, perfmon->dt_mmio);
 	perfmon->dt_mmio = NULL;
-	perfmon->start_pa = 0ULL;
-	perfmon->end_pa = 0ULL;
 
 	if (perfmon->fake_registers) {
 		tegra_hwpm_kfree(hwpm, perfmon->fake_registers);
diff --git a/drivers/tegra/hwpm/os/linux/io_utils.c b/drivers/tegra/hwpm/os/linux/io_utils.c
index eff3ca3..469b19f 100644
--- a/drivers/tegra/hwpm/os/linux/io_utils.c
+++ b/drivers/tegra/hwpm/os/linux/io_utils.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -97,7 +97,7 @@ static int ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
 			/* Fall back to un-registered IP method */
 			void __iomem *ptr = NULL;
 			u64 reg_addr = tegra_hwpm_safe_add_u64(
-				aperture->start_abs_pa, offset);
+				aperture->start_pa, offset);
 
 			ptr = ioremap(reg_addr, 0x4);
 			if (!ptr) {
@@ -145,7 +145,7 @@ static int ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
 			/* Fall back to un-registered IP method */
 			void __iomem *ptr = NULL;
 			u64 reg_addr = tegra_hwpm_safe_add_u64(
-				aperture->start_abs_pa, offset);
+				aperture->start_pa, offset);
 
 			ptr = ioremap(reg_addr, 0x4);
 			if (!ptr) {
@@ -172,14 +172,15 @@ static int hwpm_readl(struct tegra_soc_hwpm *hwpm,
 		"Aperture (0x%llx-0x%llx) offset(0x%llx)",
 		aperture->start_abs_pa, aperture->end_abs_pa, offset);
 
-	if (aperture->dt_mmio == NULL) {
-		tegra_hwpm_err(hwpm, "aperture is not iomapped as expected");
-		return -ENODEV;
-	}
-
 	if (hwpm->fake_registers_enabled) {
 		return fake_readl(hwpm, aperture, offset, val);
 	} else {
+		if (aperture->dt_mmio == NULL) {
+			tegra_hwpm_err(hwpm,
+				"aperture is not iomapped as expected");
+			return -ENODEV;
+		}
+
 		*val = readl(aperture->dt_mmio + offset);
 	}
 
@@ -199,14 +200,15 @@ static int hwpm_writel(struct tegra_soc_hwpm *hwpm,
 		"Aperture (0x%llx-0x%llx) offset(0x%llx) val(0x%x)",
 		aperture->start_abs_pa, aperture->end_abs_pa, offset, val);
 
-	if (aperture->dt_mmio == NULL) {
-		tegra_hwpm_err(hwpm, "aperture is not iomapped as expected");
-		return -ENODEV;
-	}
-
 	if (hwpm->fake_registers_enabled) {
 		err = fake_writel(hwpm, aperture, offset, val);
 	} else {
+		if (aperture->dt_mmio == NULL) {
+			tegra_hwpm_err(hwpm,
+				"aperture is not iomapped as expected");
+			return -ENODEV;
+		}
+
 		writel(val, aperture->dt_mmio + offset);
 	}
 
@@ -229,6 +231,11 @@ int tegra_hwpm_readl_impl(struct tegra_soc_hwpm *hwpm,
 
 	if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
 		(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
+		/*
+		 * Register address passed for perfmon access is with
+		 * respect to first perfmon block.
+		 * Hence, subtract base_addr from given addr for offset.
+		 */
 		u64 reg_offset = tegra_hwpm_safe_sub_u64(
 					addr, aperture->base_pa);
 		/* HWPM domain registers */
@@ -256,6 +263,11 @@ int tegra_hwpm_writel_impl(struct tegra_soc_hwpm *hwpm,
 
 	if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
 		(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
+		/*
+		 * Register address passed for perfmon access is with
+		 * respect to first perfmon block.
+		 * Hence, subtract base_addr from given addr for offset.
+		 */
 		u64 reg_offset = tegra_hwpm_safe_sub_u64(
 					addr, aperture->base_pa);
 		/* HWPM domain internal registers */
@@ -285,6 +297,11 @@ int tegra_hwpm_regops_readl_impl(struct tegra_soc_hwpm *hwpm,
 		return -ENODEV;
 	}
 
+	/*
+	 * Register address passed to this function always belong to
+	 * virtual address range of the aperture.
+	 * Hence, subtract start_abs_pa from given addr for offset.
+	 */
 	reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa);
 
 	if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
@@ -314,6 +331,11 @@ int tegra_hwpm_regops_writel_impl(struct tegra_soc_hwpm *hwpm,
 		return -ENODEV;
 	}
 
+	/*
+	 * Register address passed to this function always belong to
+	 * virtual address range of the aperture.
+	 * Hence, subtract start_abs_pa from given addr for offset.
+	 */
 	reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa);
 
 	if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||