nv-tegra-mirror/linux-hwpm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-hwpm.git synced 2025-12-22 17:30:40 +03:00
Code Issues Packages Projects Releases Wiki Activity

tegra: hwpm: Modify OS common code for HWPM RM

Browse Source 
Modify the OS common code to be used by HWPM resource
manager on QNX.

Jira THWPM-54

Change-Id: I5e0e8258eececea1526e50e2efe18c79765b86b0
Signed-off-by: vasukis <vasukis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2870342
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Yogesh Solanke <ysolanke@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
This commit is contained in:
vasukis
2023-03-13 17:45:25 +00:00
committed by mobile promotions
parent b27a32e7f0
commit ea6b4bcc07
5 changed files with 25 additions and 104 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/tegra/hwpm/include/tegra_hwpm.h
View File

@@ -146,6 +146,12 @@ struct tegra_hwpm_ip_ops {
enum tegra_soc_hwpm_ip_reg_op reg_op,
u32 inst_element_index, u64 reg_offset,
u32 *reg_data);
/*
* fd - is used to store the
* file descriptor of the IP devctl node
* in QNX
*/
int fd;
};
/* There are 3 types of HWPM components/apertures */

21
drivers/tegra/hwpm/include/tegra_hwpm_aperture.h
View File

@@ -27,26 +27,7 @@
#ifdef __KERNEL__
#include <os/linux/aperture_utils.h>
#else
int tegra_hwpm_perfmon_reserve_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *perfmon)
{
return -EINVAL;
}
int tegra_hwpm_perfmux_reserve_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *perfmux)
{
return -EINVAL;
}
int tegra_hwpm_perfmon_release_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_aperture *perfmon)
{
return -EINVAL;
}
int tegra_hwpm_perfmux_release_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_aperture *perfmux)
{
return -EINVAL;
}
#include <os/qnx/aperture_utils.h>
#endif
#define tegra_hwpm_perfmon_reserve(hwpm, ip_inst, perfmon) \

32
drivers/tegra/hwpm/include/tegra_hwpm_io.h
View File

@@ -62,37 +62,7 @@ static inline u32 get_field(u32 input_data, u32 mask)
#ifdef __KERNEL__
#include <os/linux/io_utils.h>
#else
int tegra_hwpm_read_sticky_bits_impl(struct tegra_soc_hwpm *hwpm,
u64 reg_base, u64 reg_offset, u32 *val)
{
return -EINVAL;
}
int tegra_hwpm_readl_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_aperture *aperture, u64 addr, u32 *val)
{
return -EINVAL;
}
int tegra_hwpm_writel_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_aperture *aperture, u64 addr, u32 val)
{
return -EINVAL;
}
int tegra_hwpm_regops_readl_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture,
u64 addr, u32 *val)
{
return -EINVAL;
}
int tegra_hwpm_regops_writel_impl(struct tegra_soc_hwpm *hwpm,
struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture,
u64 addr, u32 val)
{
return -EINVAL;
}
#include <os/qnx/io_utils.h>
#endif
#define tegra_hwpm_read_sticky_bits(hwpm, reg_base, reg_offset, val) \

9
drivers/tegra/hwpm/include/tegra_hwpm_ip.h
View File

@@ -26,14 +26,11 @@
#ifdef __KERNEL__
#include <os/linux/ip_utils.h>
#else
int tegra_hwpm_complete_ip_register_impl(struct tegra_soc_hwpm *hwpm)
{
return -EINVAL;
}
#endif
#define tegra_hwpm_complete_ip_register(hwpm) \
tegra_hwpm_complete_ip_register_impl(hwpm)
#else
#include <os/qnx/ip_utils.h>
#endif
#endif /* TEGRA_HWPM_IP_H */

61
drivers/tegra/hwpm/include/tegra_hwpm_soc.h
View File

@@ -46,56 +46,23 @@ struct hwpm_soc_chip_info {
#ifdef __KERNEL__
#include <os/linux/soc_utils.h>
#else
u32 tegra_hwpm_get_chip_id_impl(void)
{
return 0U;
}
#include <os/qnx/soc_utils.h>
#define CHIP_ID_UNKNOWN 0x0U
#define CHIP_ID_REV_UNKNOWN 0x0U
u32 tegra_hwpm_get_major_rev_impl(void)
{
return 0U;
}
#define PLAT_SI 0x0
#define PLAT_PRE_SI_QT 0x1
#define PLAT_PRE_SI_VDK 0x8
#define PLAT_PRE_SI_VSP 0x9
#define PLAT_INVALID 0xF
u32 tegra_hwpm_chip_get_revision_impl(void)
{
return 0U;
}
#define TEGRA_FUSE_PRODUCTION_MODE 0x0
u32 tegra_hwpm_get_platform_impl(void)
{
return 0U;
}
bool tegra_hwpm_is_platform_simulation_impl(void)
{
return false;
}
bool tegra_hwpm_is_platform_vsp_impl(void)
{
return false;
}
bool tegra_hwpm_is_platform_silicon_impl(void)
{
return true;
}
bool tegra_hwpm_is_hypervisor_mode_impl(void)
{
return false;
}
int tegra_hwpm_fuse_readl_impl(struct tegra_soc_hwpm *hwpm,
u64 reg_offset, u32 *val)
{
return -EINVAL;
}
int tegra_hwpm_fuse_readl_prod_mode_impl(struct tegra_soc_hwpm *hwpm, u32 *val)
{
return -EINVAL;
}
struct hwpm_soc_chip_info {
u32 chip_id;
u32 chip_id_rev;
u32 platform;
};
#endif