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tegra: hwpm: th500: Add support for MCF C2C

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This patch adds support for MCF C2C performance
monitoring in the driver.

Bug 4287384

Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: I7240fd8765d5c99d590549a6e4f02ba1236d2f99
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2986118
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
This commit is contained in:
Vishal Aslot
2023-09-26 20:27:06 +00:00
committed by mobile promotions
parent 2f26b5849e
commit eb50361122
8 changed files with 433 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/tegra/hwpm/Makefile.th500.soc.sources
View File

@@ -63,4 +63,7 @@ nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.o
ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_IOBHX
nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.o
ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_C2C
nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.o
endif

8
drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h
View File

@@ -272,10 +272,10 @@
#define addr_map_rpg_pm_mcfsys0_limit_r() (0x13e5ffffU)
#define addr_map_rpg_pm_mcfsys1_base_r() (0x13e60000U)
#define addr_map_rpg_pm_mcfsys1_limit_r() (0x13e60fffU)
#define addr_map_rpg_pm_mcfctc0_base_r() (0x13e61000U)
#define addr_map_rpg_pm_mcfctc0_limit_r() (0x13e61fffU)
#define addr_map_rpg_pm_mcfctc1_base_r() (0x13e62000U)
#define addr_map_rpg_pm_mcfctc1_limit_r() (0x13e62fffU)
#define addr_map_rpg_pm_mcfc2c0_base_r() (0x13e61000U)
#define addr_map_rpg_pm_mcfc2c0_limit_r() (0x13e61fffU)
#define addr_map_rpg_pm_mcfc2c1_base_r() (0x13e62000U)
#define addr_map_rpg_pm_mcfc2c1_limit_r() (0x13e62fffU)
#define addr_map_rpg_pm_mcfsoc0_base_r() (0x13e63000U)
#define addr_map_rpg_pm_mcfsoc0_limit_r() (0x13e63fffU)
#define addr_map_rpg_pm_smmu0_base_r() (0x13e64000U)

366
drivers/tegra/hwpm/hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.c Normal file
View File

@@ -0,0 +1,366 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "th500_mcf_c2c.h"
#include <tegra_hwpm.h>
#include <hal/th500/soc/th500_soc_perfmon_device_index.h>
#include <hal/th500/soc/th500_soc_regops_allowlist.h>
#include <hal/th500/soc/hw/th500_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmon_element_static_array[
TH500_HWPM_IP_MCF_C2C_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
.name = "perfmon_mcfc2c0",
.device_index = TH500_MCFCTC0_PERFMON_DEVICE_NODE_INDEX,
.start_abs_pa = addr_map_rpg_pm_mcfc2c0_base_r(),
.end_abs_pa = addr_map_rpg_pm_mcfc2c0_limit_r(),
.start_pa = addr_map_rpg_pm_mcfc2c0_base_r(),
.end_pa = addr_map_rpg_pm_mcfc2c0_limit_r(),
.base_pa = addr_map_rpg_pm_base_r(),
.alist = th500_perfmon_alist,
.alist_size = ARRAY_SIZE(th500_perfmon_alist),
.fake_registers = NULL,
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.element_index_mask = BIT(1),
.element_index = 1U,
.dt_mmio = NULL,
.name = "perfmon_mcfc2c1",
.device_index = TH500_MCFCTC1_PERFMON_DEVICE_NODE_INDEX,
.start_abs_pa = addr_map_rpg_pm_mcfc2c1_base_r(),
.end_abs_pa = addr_map_rpg_pm_mcfc2c1_limit_r(),
.start_pa = addr_map_rpg_pm_mcfc2c1_base_r(),
.end_pa = addr_map_rpg_pm_mcfc2c1_limit_r(),
.base_pa = addr_map_rpg_pm_base_r(),
.alist = th500_perfmon_alist,
.alist_size = ARRAY_SIZE(th500_perfmon_alist),
.fake_registers = NULL,
},
};
static struct hwpm_ip_aperture th500_mcf_c2c_inst0_perfmux_element_static_array[
TH500_HWPM_IP_MCF_C2C_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(0),
.element_index = 1U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc0_base_r(),
.end_abs_pa = addr_map_mc0_limit_r(),
.start_pa = addr_map_mc0_base_r(),
.end_pa = addr_map_mc0_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(1),
.element_index = 2U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc1_base_r(),
.end_abs_pa = addr_map_mc1_limit_r(),
.start_pa = addr_map_mc1_base_r(),
.end_pa = addr_map_mc1_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(2),
.element_index = 3U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc2_base_r(),
.end_abs_pa = addr_map_mc2_limit_r(),
.start_pa = addr_map_mc2_base_r(),
.end_pa = addr_map_mc2_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(3),
.element_index = 4U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc3_base_r(),
.end_abs_pa = addr_map_mc3_limit_r(),
.start_pa = addr_map_mc3_base_r(),
.end_pa = addr_map_mc3_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(4),
.element_index = 5U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc4_base_r(),
.end_abs_pa = addr_map_mc4_limit_r(),
.start_pa = addr_map_mc4_base_r(),
.end_pa = addr_map_mc4_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(5),
.element_index = 6U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc5_base_r(),
.end_abs_pa = addr_map_mc5_limit_r(),
.start_pa = addr_map_mc5_base_r(),
.end_pa = addr_map_mc5_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(6),
.element_index = 7U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc6_base_r(),
.end_abs_pa = addr_map_mc6_limit_r(),
.start_pa = addr_map_mc6_base_r(),
.end_pa = addr_map_mc6_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(7),
.element_index = 8U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc7_base_r(),
.end_abs_pa = addr_map_mc7_limit_r(),
.start_pa = addr_map_mc7_base_r(),
.end_pa = addr_map_mc7_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(8),
.element_index = 9U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc8_base_r(),
.end_abs_pa = addr_map_mc8_limit_r(),
.start_pa = addr_map_mc8_base_r(),
.end_pa = addr_map_mc8_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.element_index_mask = BIT(9),
.element_index = 10U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mc9_base_r(),
.end_abs_pa = addr_map_mc9_limit_r(),
.start_pa = addr_map_mc9_base_r(),
.end_pa = addr_map_mc9_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
};
static struct hwpm_ip_aperture th500_mcf_c2c_inst0_broadcast_element_static_array[
TH500_HWPM_IP_MCF_C2C_NUM_BROADCAST_PER_INST] = {
{
.element_type = IP_ELEMENT_BROADCAST,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mcb_base_r(),
.end_abs_pa = addr_map_mcb_limit_r(),
.start_pa = addr_map_mcb_base_r(),
.end_pa = addr_map_mcb_limit_r(),
.base_pa = 0ULL,
.alist = th500_mcf_c2c_alist,
.alist_size = ARRAY_SIZE(th500_mcf_c2c_alist),
.fake_registers = NULL,
},
};
/* IP instance array */
static struct hwpm_ip_inst th500_mcf_c2c_inst_static_array[
TH500_HWPM_IP_MCF_C2C_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
TH500_HWPM_IP_MCF_C2C_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
.num_element_per_inst =
TH500_HWPM_IP_MCF_C2C_NUM_PERFMUX_PER_INST,
.element_static_array =
th500_mcf_c2c_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_mc0_base_r(),
.range_end = addr_map_mc9_limit_r(),
.element_stride = addr_map_mc0_limit_r() -
addr_map_mc0_base_r() + 1ULL,
.element_slots = 0U,
.element_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_BROADCAST
*/
{
.num_element_per_inst =
TH500_HWPM_IP_MCF_C2C_NUM_BROADCAST_PER_INST,
.element_static_array =
th500_mcf_c2c_inst0_broadcast_element_static_array,
.range_start = addr_map_mcb_base_r(),
.range_end = addr_map_mcb_limit_r(),
.element_stride = addr_map_mcb_limit_r() -
addr_map_mcb_base_r() + 1ULL,
.element_slots = 0U,
.element_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMON
*/
{
.num_element_per_inst =
TH500_HWPM_IP_MCF_C2C_NUM_PERFMON_PER_INST,
.element_static_array =
th500_mcf_c2c_inst0_perfmon_element_static_array,
.range_start = addr_map_rpg_pm_mcfc2c0_base_r(),
.range_end = addr_map_rpg_pm_mcfc2c1_limit_r(),
.element_stride = addr_map_rpg_pm_mcfc2c0_limit_r() -
addr_map_rpg_pm_mcfc2c0_base_r() + 1ULL,
.element_slots = 0U,
.element_arr = NULL,
},
},
.ip_ops = {
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "",
},
};
/* IP structure */
struct hwpm_ip th500_hwpm_ip_mcf_c2c = {
.num_instances = TH500_HWPM_IP_MCF_C2C_NUM_INSTANCES,
.ip_inst_static_array = th500_mcf_c2c_inst_static_array,
.inst_aperture_info = {
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_mc0_base_r(),
.range_end = addr_map_mc9_limit_r(),
.inst_stride = addr_map_mc9_limit_r() -
addr_map_mc0_base_r() + 1ULL,
.inst_slots = 0U,
.inst_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_BROADCAST
*/
{
.range_start = addr_map_mcb_base_r(),
.range_end = addr_map_mcb_limit_r(),
.inst_stride = addr_map_mcb_limit_r() -
addr_map_mcb_base_r() + 1ULL,
.inst_slots = 0U,
.inst_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMON
*/
{
.range_start = addr_map_rpg_pm_mcfc2c0_base_r(),
.range_end = addr_map_rpg_pm_mcfc2c1_limit_r(),
.inst_stride = addr_map_rpg_pm_mcfc2c1_limit_r() -
addr_map_rpg_pm_mcfc2c0_base_r() + 1ULL,
.inst_slots = 0U,
.inst_arr = NULL,
},
},
.dependent_fuse_mask = TEGRA_HWPM_FUSE_SECURITY_MODE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK,
.override_enable = false,
.inst_fs_mask = 0U,
.resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID,
.reserved = false,
};

48
drivers/tegra/hwpm/hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.h Normal file
View File

@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef TH500_HWPM_IP_MCF_C2C_H
#define TH500_HWPM_IP_MCF_C2C_H
#if defined(CONFIG_TH500_HWPM_IP_MCF_C2C)
#define TH500_HWPM_ACTIVE_IP_MCF_C2C TH500_HWPM_IP_MCF_C2C,
/* This data should ideally be available in HW headers */
#define TH500_HWPM_IP_MCF_C2C_NUM_INSTANCES 1U
#define TH500_HWPM_IP_MCF_C2C_NUM_CORE_ELEMENT_PER_INST 10U
#define TH500_HWPM_IP_MCF_C2C_NUM_PERFMON_PER_INST 2U
#define TH500_HWPM_IP_MCF_C2C_NUM_PERFMUX_PER_INST 10U
#define TH500_HWPM_IP_MCF_C2C_NUM_BROADCAST_PER_INST 1U
extern struct hwpm_ip th500_hwpm_ip_mcf_c2c;
#else
#define TH500_HWPM_ACTIVE_IP_MCF_C2C
#endif
#endif /* TH500_HWPM_IP_MCF_C2C_H */

2
drivers/tegra/hwpm/hal/th500/th500_internal.h
View File

@@ -35,6 +35,7 @@
#include <hal/th500/soc/ip/mss_hub/th500_mss_hub.h>
#include <hal/th500/soc/ip/mcf_ocu/th500_mcf_ocu.h>
#include <hal/th500/soc/ip/mcf_iobhx/th500_mcf_iobhx.h>
#include <hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.h>
#define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX
@@ -42,6 +43,7 @@
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_RTR) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PMA) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_CHANNEL) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_C2C) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_C2C) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_SMMU) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_CL2) \

2
drivers/tegra/hwpm/include/tegra_hwpm.h
View File

@@ -86,6 +86,7 @@ enum tegra_hwpm_ip_enum {
TEGRA_HWPM_IP_MSS_HUB,
TEGRA_HWPM_IP_MCF_OCU,
TEGRA_HWPM_IP_MCF_IOBHX,
TEGRA_HWPM_IP_MCF_C2C,
TERGA_HWPM_NUM_IPS
};
@@ -123,6 +124,7 @@ enum tegra_hwpm_resource_enum {
TEGRA_HWPM_RESOURCE_MSS_HUB,
TEGRA_HWPM_RESOURCE_MCF_OCU,
TEGRA_HWPM_RESOURCE_MCF_IOBHX,
TEGRA_HWPM_RESOURCE_MCF_C2C,
TERGA_HWPM_NUM_RESOURCES
};

6
drivers/tegra/hwpm/os/linux/ip_utils.c
View File

@@ -114,6 +114,9 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm,
case TEGRA_SOC_HWPM_IP_MCF_IOBHX:
ip_enum_idx = TEGRA_HWPM_IP_MCF_IOBHX;
break;
case TEGRA_SOC_HWPM_IP_MCF_C2C:
ip_enum_idx = TEGRA_HWPM_IP_MCF_C2C;
break;
default:
tegra_hwpm_err(hwpm,
"Queried enum tegra_soc_hwpm_ip %d is invalid",
@@ -243,6 +246,9 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
case TEGRA_SOC_HWPM_RESOURCE_MCF_IOBHX:
res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_IOBHX;
break;
case TEGRA_SOC_HWPM_RESOURCE_MCF_C2C:
res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_C2C;
break;
default:
tegra_hwpm_err(hwpm,
"Queried enum tegra_soc_hwpm_resource %d is invalid",

2
include/uapi/linux/tegra-soc-hwpm-uapi.h
View File

@@ -53,6 +53,7 @@ enum tegra_soc_hwpm_ip {
TEGRA_SOC_HWPM_IP_MSS_HUB,
TEGRA_SOC_HWPM_IP_MCF_OCU,
TEGRA_SOC_HWPM_IP_MCF_IOBHX,
TEGRA_SOC_HWPM_IP_MCF_C2C,
TERGA_SOC_HWPM_NUM_IPS
};
@@ -128,6 +129,7 @@ enum tegra_soc_hwpm_resource {
TEGRA_SOC_HWPM_RESOURCE_MSS_HUB,
TEGRA_SOC_HWPM_RESOURCE_MCF_OCU,
TEGRA_SOC_HWPM_RESOURCE_MCF_IOBHX,
TEGRA_SOC_HWPM_RESOURCE_MCF_C2C,
TERGA_SOC_HWPM_NUM_RESOURCES
};