nv-tegra-mirror/linux-hwpm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-hwpm.git synced 2025-12-22 17:30:40 +03:00
Code Issues Packages Projects Releases Wiki Activity

tegra: hwpm: t234: update ip structure files

Browse Source 
Update all IP files to include aperture_index variable in
hwpm_ip_aperture structures. This index will be used to
translate dynamic element index to static index.

Bug 4707244

Change-Id: Ic4adb1aadffb4e2039ef5b898ce8ed046881ecde
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3197912
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2024-08-21 10:31:50 -07:00
committed by mobile promotions
parent 48e85a9c07
commit eccff56167
24 changed files with 379 additions and 148 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/tegra/hwpm/hal/t234/ip/display/t234_display.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_display.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_display_inst0_perfmon_element_static_array[
T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -52,6 +58,7 @@ static struct hwpm_ip_aperture t234_display_inst0_perfmux_element_static_array[
T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -84,10 +91,10 @@ static struct hwpm_ip_inst t234_display_inst_static_array[
T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_display_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_disp_base_r(),
.range_end = addr_map_disp_limit_r(),
.element_stride =
addr_map_disp_limit_r() -
.element_stride = addr_map_disp_limit_r() -
addr_map_disp_base_r() + 1ULL,
.element_slots = 0U,
.element_arr = NULL,
@@ -117,8 +124,7 @@ static struct hwpm_ip_inst t234_display_inst_static_array[
t234_display_inst0_perfmon_element_static_array,
.range_start = addr_map_rpg_pm_disp_base_r(),
.range_end = addr_map_rpg_pm_disp_limit_r(),
.element_stride =
addr_map_rpg_pm_disp_limit_r() -
.element_stride = addr_map_rpg_pm_disp_limit_r() -
addr_map_rpg_pm_disp_base_r() + 1ULL,
.element_slots = 0U,
.element_arr = NULL,
@@ -148,6 +154,7 @@ struct hwpm_ip t234_hwpm_ip_display = {
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_disp_base_r(),
.range_end = addr_map_disp_limit_r(),
.inst_stride = addr_map_disp_limit_r() -

19
drivers/tegra/hwpm/hal/t234/ip/display/t234_display.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_DISPLAY_H
#define T234_HWPM_IP_DISPLAY_H
#if defined(CONFIG_T234_HWPM_IP_DISPLAY)
#define T234_HWPM_ACTIVE_IP_DISPLAY T234_HWPM_IP_DISPLAY,
#define T234_HWPM_ACTIVE_IP_DISPLAY T234_HWPM_IP_DISPLAY,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_DISPLAY_NUM_INSTANCES 1U
#define T234_HWPM_IP_DISPLAY_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_DISPLAY_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_DISPLAY_NUM_INSTANCES 1U
#define T234_HWPM_IP_DISPLAY_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_DISPLAY_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_DISPLAY_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_DISPLAY_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_display;

14
drivers/tegra/hwpm/hal/t234/ip/isp/t234_isp.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_isp.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_isp_inst0_perfmon_element_static_array[
T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -52,6 +58,7 @@ static struct hwpm_ip_aperture t234_isp_inst0_perfmux_element_static_array[
T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -84,6 +91,7 @@ static struct hwpm_ip_inst t234_isp_inst_static_array[
T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_isp_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_isp_thi_base_r(),
.range_end = addr_map_isp_thi_limit_r(),
.element_stride = addr_map_isp_thi_limit_r() -
@@ -135,6 +143,7 @@ static struct hwpm_ip_inst t234_isp_inst_static_array[
},
};
/* IP structure */
struct hwpm_ip t234_hwpm_ip_isp = {
.num_instances = T234_HWPM_IP_ISP_NUM_INSTANCES,
.ip_inst_static_array = t234_isp_inst_static_array,
@@ -145,6 +154,7 @@ struct hwpm_ip t234_hwpm_ip_isp = {
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_isp_thi_base_r(),
.range_end = addr_map_isp_thi_limit_r(),
.inst_stride = addr_map_isp_thi_limit_r() -

19
drivers/tegra/hwpm/hal/t234/ip/isp/t234_isp.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_ISP_H
#define T234_HWPM_IP_ISP_H
#if defined(CONFIG_T234_HWPM_IP_ISP)
#define T234_HWPM_ACTIVE_IP_ISP T234_HWPM_IP_ISP,
#define T234_HWPM_ACTIVE_IP_ISP T234_HWPM_IP_ISP,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_ISP_NUM_INSTANCES 1U
#define T234_HWPM_IP_ISP_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_ISP_NUM_INSTANCES 1U
#define T234_HWPM_IP_ISP_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_ISP_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_isp;

28
drivers/tegra/hwpm/hal/t234/ip/mgbe/t234_mgbe.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_mgbe.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_mgbe_inst0_perfmon_element_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -52,6 +58,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst1_perfmon_element_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -72,6 +79,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst2_perfmon_element_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -92,6 +100,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst3_perfmon_element_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -112,6 +121,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst0_perfmux_element_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -131,6 +141,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst1_perfmux_element_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -150,6 +161,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst2_perfmux_element_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -169,6 +181,7 @@ static struct hwpm_ip_aperture t234_mgbe_inst3_perfmux_element_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -201,6 +214,7 @@ static struct hwpm_ip_inst t234_mgbe_inst_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_mgbe_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_mgbe0_mac_rm_base_r(),
.range_end = addr_map_mgbe0_mac_rm_limit_r(),
.element_stride = addr_map_mgbe0_mac_rm_limit_r() -
@@ -264,6 +278,7 @@ static struct hwpm_ip_inst t234_mgbe_inst_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_mgbe_inst1_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_mgbe1_mac_rm_base_r(),
.range_end = addr_map_mgbe1_mac_rm_limit_r(),
.element_stride = addr_map_mgbe1_mac_rm_limit_r() -
@@ -307,9 +322,11 @@ static struct hwpm_ip_inst t234_mgbe_inst_static_array[
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "",
},
{
.hw_inst_mask = BIT(2),
@@ -325,6 +342,7 @@ static struct hwpm_ip_inst t234_mgbe_inst_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_mgbe_inst2_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_mgbe2_mac_rm_base_r(),
.range_end = addr_map_mgbe2_mac_rm_limit_r(),
.element_stride = addr_map_mgbe2_mac_rm_limit_r() -
@@ -368,9 +386,11 @@ static struct hwpm_ip_inst t234_mgbe_inst_static_array[
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "",
},
{
.hw_inst_mask = BIT(3),
@@ -386,6 +406,7 @@ static struct hwpm_ip_inst t234_mgbe_inst_static_array[
T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_mgbe_inst3_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_mgbe3_mac_rm_base_r(),
.range_end = addr_map_mgbe3_mac_rm_limit_r(),
.element_stride = addr_map_mgbe3_mac_rm_limit_r() -
@@ -429,9 +450,11 @@ static struct hwpm_ip_inst t234_mgbe_inst_static_array[
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "",
},
};
@@ -446,6 +469,7 @@ struct hwpm_ip t234_hwpm_ip_mgbe = {
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_mgbe0_mac_rm_base_r(),
.range_end = addr_map_mgbe3_mac_rm_limit_r(),
.inst_stride = addr_map_mgbe0_mac_rm_limit_r() -

19
drivers/tegra/hwpm/hal/t234/ip/mgbe/t234_mgbe.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_MGBE_H
#define T234_HWPM_IP_MGBE_H
#if defined(CONFIG_T234_HWPM_IP_MGBE)
#define T234_HWPM_ACTIVE_IP_MGBE T234_HWPM_IP_MGBE,
#define T234_HWPM_ACTIVE_IP_MGBE T234_HWPM_IP_MGBE,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MGBE_NUM_INSTANCES 4U
#define T234_HWPM_IP_MGBE_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_MGBE_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_MGBE_NUM_INSTANCES 4U
#define T234_HWPM_IP_MGBE_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_MGBE_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_MGBE_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_MGBE_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_mgbe;

42
drivers/tegra/hwpm/hal/t234/ip/mss_channel/t234_mss_channel.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_mss_channel.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_array[
T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 1U,
.dt_mmio = NULL,
@@ -48,6 +54,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 1U,
.element_index_mask = BIT(1),
.element_index = 2U,
.dt_mmio = NULL,
@@ -64,6 +71,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 2U,
.element_index_mask = BIT(2),
.element_index = 3U,
.dt_mmio = NULL,
@@ -80,6 +88,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 3U,
.element_index_mask = BIT(3),
.element_index = 4U,
.dt_mmio = NULL,
@@ -96,6 +105,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 4U,
.element_index_mask = BIT(4),
.element_index = 5U,
.dt_mmio = NULL,
@@ -112,6 +122,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 5U,
.element_index_mask = BIT(5),
.element_index = 6U,
.dt_mmio = NULL,
@@ -128,6 +139,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 6U,
.element_index_mask = BIT(6),
.element_index = 7U,
.dt_mmio = NULL,
@@ -144,6 +156,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 7U,
.element_index_mask = BIT(7),
.element_index = 8U,
.dt_mmio = NULL,
@@ -160,6 +173,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 8U,
.element_index_mask = BIT(8),
.element_index = 9U,
.dt_mmio = NULL,
@@ -176,6 +190,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 9U,
.element_index_mask = BIT(9),
.element_index = 10U,
.dt_mmio = NULL,
@@ -192,6 +207,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 10U,
.element_index_mask = BIT(10),
.element_index = 11U,
.dt_mmio = NULL,
@@ -208,6 +224,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 11U,
.element_index_mask = BIT(11),
.element_index = 12U,
.dt_mmio = NULL,
@@ -224,6 +241,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 12U,
.element_index_mask = BIT(12),
.element_index = 13U,
.dt_mmio = NULL,
@@ -240,6 +258,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 13U,
.element_index_mask = BIT(13),
.element_index = 14U,
.dt_mmio = NULL,
@@ -256,6 +275,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 14U,
.element_index_mask = BIT(14),
.element_index = 15U,
.dt_mmio = NULL,
@@ -272,6 +292,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmon_element_static_arr
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 15U,
.element_index_mask = BIT(15),
.element_index = 16U,
.dt_mmio = NULL,
@@ -292,6 +313,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 1U,
.dt_mmio = NULL,
@@ -307,6 +329,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 1U,
.element_index_mask = BIT(1),
.element_index = 2U,
.dt_mmio = NULL,
@@ -322,6 +345,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 2U,
.element_index_mask = BIT(2),
.element_index = 3U,
.dt_mmio = NULL,
@@ -337,6 +361,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 3U,
.element_index_mask = BIT(3),
.element_index = 4U,
.dt_mmio = NULL,
@@ -352,6 +377,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 4U,
.element_index_mask = BIT(4),
.element_index = 5U,
.dt_mmio = NULL,
@@ -367,6 +393,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 5U,
.element_index_mask = BIT(5),
.element_index = 6U,
.dt_mmio = NULL,
@@ -382,6 +409,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 6U,
.element_index_mask = BIT(6),
.element_index = 7U,
.dt_mmio = NULL,
@@ -397,6 +425,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 7U,
.element_index_mask = BIT(7),
.element_index = 8U,
.dt_mmio = NULL,
@@ -412,6 +441,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 8U,
.element_index_mask = BIT(8),
.element_index = 9U,
.dt_mmio = NULL,
@@ -427,6 +457,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 9U,
.element_index_mask = BIT(9),
.element_index = 10U,
.dt_mmio = NULL,
@@ -442,6 +473,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 10U,
.element_index_mask = BIT(10),
.element_index = 11U,
.dt_mmio = NULL,
@@ -457,6 +489,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 11U,
.element_index_mask = BIT(11),
.element_index = 12U,
.dt_mmio = NULL,
@@ -472,6 +505,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 12U,
.element_index_mask = BIT(12),
.element_index = 13U,
.dt_mmio = NULL,
@@ -487,6 +521,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 13U,
.element_index_mask = BIT(13),
.element_index = 14U,
.dt_mmio = NULL,
@@ -502,6 +537,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 14U,
.element_index_mask = BIT(14),
.element_index = 15U,
.dt_mmio = NULL,
@@ -517,6 +553,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 15U,
.element_index_mask = BIT(15),
.element_index = 16U,
.dt_mmio = NULL,
@@ -536,6 +573,7 @@ static struct hwpm_ip_aperture t234_mss_channel_inst0_broadcast_element_static_a
T234_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST] = {
{
.element_type = IP_ELEMENT_BROADCAST,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,

19
drivers/tegra/hwpm/hal/t234/ip/mss_channel/t234_mss_channel.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_MSS_CHANNEL_H
#define T234_HWPM_IP_MSS_CHANNEL_H
#if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL)
#define T234_HWPM_ACTIVE_IP_MSS_CHANNEL T234_HWPM_IP_MSS_CHANNEL,
#define T234_HWPM_ACTIVE_IP_MSS_CHANNEL T234_HWPM_IP_MSS_CHANNEL,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST 1U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_CORE_ELEMENT_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMON_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_PERFMUX_PER_INST 16U
#define T234_HWPM_IP_MSS_CHANNEL_NUM_BROADCAST_PER_INST 1U
extern struct hwpm_ip t234_hwpm_ip_mss_channel;

36
drivers/tegra/hwpm/hal/t234/ip/mss_gpu_hub/t234_mss_gpu_hub.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_mss_gpu_hub.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmon_element_static_array[
T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -52,8 +58,9 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 1U,
.element_index = 0U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mss_nvlink_1_base_r(),
@@ -67,8 +74,9 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 1U,
.element_index_mask = BIT(1),
.element_index = 2U,
.element_index = 1U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mss_nvlink_2_base_r(),
@@ -82,8 +90,9 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 2U,
.element_index_mask = BIT(2),
.element_index = 3U,
.element_index = 2U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mss_nvlink_3_base_r(),
@@ -97,8 +106,9 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 3U,
.element_index_mask = BIT(3),
.element_index = 4U,
.element_index = 3U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mss_nvlink_4_base_r(),
@@ -112,8 +122,9 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 4U,
.element_index_mask = BIT(4),
.element_index = 5U,
.element_index = 4U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mss_nvlink_5_base_r(),
@@ -127,8 +138,9 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 5U,
.element_index_mask = BIT(5),
.element_index = 6U,
.element_index = 5U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mss_nvlink_6_base_r(),
@@ -142,8 +154,9 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 6U,
.element_index_mask = BIT(6),
.element_index = 7U,
.element_index = 6U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mss_nvlink_7_base_r(),
@@ -157,8 +170,9 @@ static struct hwpm_ip_aperture t234_mss_gpu_hub_inst0_perfmux_element_static_arr
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 7U,
.element_index_mask = BIT(7),
.element_index = 8U,
.element_index = 7U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_mss_nvlink_8_base_r(),
@@ -189,6 +203,7 @@ static struct hwpm_ip_inst t234_mss_gpu_hub_inst_static_array[
T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_mss_gpu_hub_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_mss_nvlink_8_base_r(),
.range_end = addr_map_mss_nvlink_7_limit_r(),
.element_stride = addr_map_mss_nvlink_8_limit_r() -
@@ -251,6 +266,7 @@ struct hwpm_ip t234_hwpm_ip_mss_gpu_hub = {
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_mss_nvlink_8_base_r(),
.range_end = addr_map_mss_nvlink_7_limit_r(),
.inst_stride = addr_map_mss_nvlink_7_limit_r() -

19
drivers/tegra/hwpm/hal/t234/ip/mss_gpu_hub/t234_mss_gpu_hub.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_MSS_GPU_HUB_H
#define T234_HWPM_IP_MSS_GPU_HUB_H
#if defined(CONFIG_T234_HWPM_IP_MSS_GPU_HUB)
#define T234_HWPM_ACTIVE_IP_MSS_GPU_HUB T234_HWPM_IP_MSS_GPU_HUB,
#define T234_HWPM_ACTIVE_IP_MSS_GPU_HUB T234_HWPM_IP_MSS_GPU_HUB,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_CORE_ELEMENT_PER_INST 8U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST 8U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_CORE_ELEMENT_PER_INST 8U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_PERFMUX_PER_INST 8U
#define T234_HWPM_IP_MSS_GPU_HUB_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_mss_gpu_hub;

52
drivers/tegra/hwpm/hal/t234/ip/mss_iso_niso_hubs/t234_mss_iso_niso_hubs.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,21 +19,27 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_mss_iso_niso_hubs.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmon_element_static_array[
T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.element_index = 1U,
.dt_mmio = NULL,
.name = "perfmon_msshub0",
.device_index = T234_MSSHUB0_PERFMON_DEVICE_NODE_INDEX,
@@ -48,8 +54,9 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmon_element_stati
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.element_index_mask = BIT(0),
.element_index = 1U,
.aperture_index = 1U,
.element_index_mask = BIT(1),
.element_index = 2U,
.dt_mmio = NULL,
.name = "perfmon_msshub1",
.device_index = T234_MSSHUB1_PERFMON_DEVICE_NODE_INDEX,
@@ -68,6 +75,7 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 1U,
.dt_mmio = NULL,
@@ -78,12 +86,12 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
.end_pa = addr_map_mc0_limit_r(),
.base_pa = 0ULL,
.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
.alist_size =
ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 1U,
.element_index_mask = BIT(1),
.element_index = 2U,
.dt_mmio = NULL,
@@ -94,12 +102,12 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
.end_pa = addr_map_mc1_limit_r(),
.base_pa = 0ULL,
.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
.alist_size =
ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 2U,
.element_index_mask = BIT(2),
.element_index = 3U,
.dt_mmio = NULL,
@@ -110,12 +118,12 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
.end_pa = addr_map_mc2_limit_r(),
.base_pa = 0ULL,
.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
.alist_size =
ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 3U,
.element_index_mask = BIT(3),
.element_index = 4U,
.dt_mmio = NULL,
@@ -126,12 +134,12 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
.end_pa = addr_map_mc3_limit_r(),
.base_pa = 0ULL,
.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
.alist_size =
ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 4U,
.element_index_mask = BIT(4),
.element_index = 5U,
.dt_mmio = NULL,
@@ -142,12 +150,12 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
.end_pa = addr_map_mc4_limit_r(),
.base_pa = 0ULL,
.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
.alist_size =
ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 5U,
.element_index_mask = BIT(5),
.element_index = 6U,
.dt_mmio = NULL,
@@ -158,12 +166,12 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
.end_pa = addr_map_mc5_limit_r(),
.base_pa = 0ULL,
.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
.alist_size =
ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 6U,
.element_index_mask = BIT(6),
.element_index = 7U,
.dt_mmio = NULL,
@@ -174,12 +182,12 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
.end_pa = addr_map_mc6_limit_r(),
.base_pa = 0ULL,
.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
.alist_size =
ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 7U,
.element_index_mask = BIT(7),
.element_index = 8U,
.dt_mmio = NULL,
@@ -190,12 +198,12 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_perfmux_element_stati
.end_pa = addr_map_mc7_limit_r(),
.base_pa = 0ULL,
.alist = t234_mc0to7_res_mss_iso_niso_hub_alist,
.alist_size =
ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.alist_size = ARRAY_SIZE(t234_mc0to7_res_mss_iso_niso_hub_alist),
.fake_registers = NULL,
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 8U,
.element_index_mask = BIT(8),
.element_index = 9U,
.dt_mmio = NULL,
@@ -215,6 +223,7 @@ static struct hwpm_ip_aperture t234_mss_iso_niso_hub_inst0_broadcast_element_sta
T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_BROADCAST_PER_INST] = {
{
.element_type = IP_ELEMENT_BROADCAST,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -352,4 +361,3 @@ struct hwpm_ip t234_hwpm_ip_mss_iso_niso_hubs = {
.resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID,
.reserved = false,
};

17
drivers/tegra/hwpm/hal/t234/ip/mss_iso_niso_hubs/t234_mss_iso_niso_hubs.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,6 +19,11 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_MSS_ISO_NISO_HUBS_H
@@ -28,11 +33,11 @@
#define T234_HWPM_ACTIVE_IP_MSS_ISO_NISO_HUBS T234_HWPM_IP_MSS_ISO_NISO_HUBS,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_CORE_ELEMENT_PER_INST 9U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST 2U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST 9U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_BROADCAST_PER_INST 1U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_CORE_ELEMENT_PER_INST 9U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMON_PER_INST 2U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_PERFMUX_PER_INST 9U
#define T234_HWPM_IP_MSS_ISO_NISO_HUBS_NUM_BROADCAST_PER_INST 1U
extern struct hwpm_ip t234_hwpm_ip_mss_iso_niso_hubs;

19
drivers/tegra/hwpm/hal/t234/ip/mss_mcf/t234_mss_mcf.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,6 +19,11 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_mss_mcf.h"
@@ -32,6 +37,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -48,6 +54,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 1U,
.element_index_mask = BIT(0),
.element_index = 1U,
.dt_mmio = NULL,
@@ -64,6 +71,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmon_element_static_array[
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 2U,
.element_index_mask = BIT(0),
.element_index = 2U,
.dt_mmio = NULL,
@@ -84,6 +92,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 1U,
.dt_mmio = NULL,
@@ -99,6 +108,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 1U,
.element_index_mask = BIT(1),
.element_index = 2U,
.dt_mmio = NULL,
@@ -114,6 +124,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 2U,
.element_index_mask = BIT(2),
.element_index = 3U,
.dt_mmio = NULL,
@@ -129,6 +140,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 3U,
.element_index_mask = BIT(3),
.element_index = 4U,
.dt_mmio = NULL,
@@ -144,6 +156,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 4U,
.element_index_mask = BIT(4),
.element_index = 5U,
.dt_mmio = NULL,
@@ -159,6 +172,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 5U,
.element_index_mask = BIT(5),
.element_index = 6U,
.dt_mmio = NULL,
@@ -174,6 +188,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 6U,
.element_index_mask = BIT(6),
.element_index = 7U,
.dt_mmio = NULL,
@@ -189,6 +204,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_perfmux_element_static_array[
},
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 7U,
.element_index_mask = BIT(7),
.element_index = 8U,
.dt_mmio = NULL,
@@ -208,6 +224,7 @@ static struct hwpm_ip_aperture t234_mss_mcf_inst0_broadcast_element_static_array
T234_HWPM_IP_MSS_MCF_NUM_BROADCAST_PER_INST] = {
{
.element_type = IP_ELEMENT_BROADCAST,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,

19
drivers/tegra/hwpm/hal/t234/ip/mss_mcf/t234_mss_mcf.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_MSS_MCF_H
#define T234_HWPM_IP_MSS_MCF_H
#if defined(CONFIG_T234_HWPM_IP_MSS_MCF)
#define T234_HWPM_ACTIVE_IP_MSS_MCF T234_HWPM_IP_MSS_MCF,
#define T234_HWPM_ACTIVE_IP_MSS_MCF T234_HWPM_IP_MSS_MCF,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_MSS_MCF_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_MCF_NUM_CORE_ELEMENT_PER_INST 8U
#define T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST 3U
#define T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST 8U
#define T234_HWPM_IP_MSS_MCF_NUM_BROADCAST_PER_INST 1U
#define T234_HWPM_IP_MSS_MCF_NUM_INSTANCES 1U
#define T234_HWPM_IP_MSS_MCF_NUM_CORE_ELEMENT_PER_INST 8U
#define T234_HWPM_IP_MSS_MCF_NUM_PERFMON_PER_INST 3U
#define T234_HWPM_IP_MSS_MCF_NUM_PERFMUX_PER_INST 8U
#define T234_HWPM_IP_MSS_MCF_NUM_BROADCAST_PER_INST 1U
extern struct hwpm_ip t234_hwpm_ip_mss_mcf;

17
drivers/tegra/hwpm/hal/t234/ip/nvdec/t234_nvdec.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_nvdec.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_nvdec_inst0_perfmon_element_static_array[
T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -52,6 +58,7 @@ static struct hwpm_ip_aperture t234_nvdec_inst0_perfmux_element_static_array[
T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -84,6 +91,7 @@ static struct hwpm_ip_inst t234_nvdec_inst_static_array[
T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_nvdec_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_nvdec_base_r(),
.range_end = addr_map_nvdec_limit_r(),
.element_stride = addr_map_nvdec_limit_r() -
@@ -127,11 +135,11 @@ static struct hwpm_ip_inst t234_nvdec_inst_static_array[
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_VALID,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "/dev/nvhost-debug/nvdec_hwpm",
.dev_name = "",
},
};
@@ -146,6 +154,7 @@ struct hwpm_ip t234_hwpm_ip_nvdec = {
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_nvdec_base_r(),
.range_end = addr_map_nvdec_limit_r(),
.inst_stride = addr_map_nvdec_limit_r() -

19
drivers/tegra/hwpm/hal/t234/ip/nvdec/t234_nvdec.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_NVDEC_H
#define T234_HWPM_IP_NVDEC_H
#if defined(CONFIG_T234_HWPM_IP_NVDEC)
#define T234_HWPM_ACTIVE_IP_NVDEC T234_HWPM_IP_NVDEC,
#define T234_HWPM_ACTIVE_IP_NVDEC T234_HWPM_IP_NVDEC,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_NVDEC_NUM_INSTANCES 1U
#define T234_HWPM_IP_NVDEC_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_NVDEC_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_NVDEC_NUM_INSTANCES 1U
#define T234_HWPM_IP_NVDEC_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_NVDEC_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_NVDEC_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_NVDEC_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_nvdec;

24
drivers/tegra/hwpm/hal/t234/ip/nvdla/t234_nvdla.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_nvdla.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_nvdla_inst0_perfmon_element_static_array[
T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -52,6 +58,7 @@ static struct hwpm_ip_aperture t234_nvdla_inst1_perfmon_element_static_array[
T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -72,6 +79,7 @@ static struct hwpm_ip_aperture t234_nvdla_inst0_perfmux_element_static_array[
T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -91,6 +99,7 @@ static struct hwpm_ip_aperture t234_nvdla_inst1_perfmux_element_static_array[
T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -123,6 +132,7 @@ static struct hwpm_ip_inst t234_nvdla_inst_static_array[
T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_nvdla_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_nvdla0_base_r(),
.range_end = addr_map_nvdla0_limit_r(),
.element_stride = addr_map_nvdla0_limit_r() -
@@ -166,11 +176,11 @@ static struct hwpm_ip_inst t234_nvdla_inst_static_array[
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_VALID,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "/dev/nvdladebugfs/nvdla0/hwpm/ctrl",
.dev_name = "",
},
{
.hw_inst_mask = BIT(1),
@@ -186,6 +196,7 @@ static struct hwpm_ip_inst t234_nvdla_inst_static_array[
T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_nvdla_inst1_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_nvdla1_base_r(),
.range_end = addr_map_nvdla1_limit_r(),
.element_stride = addr_map_nvdla1_limit_r() -
@@ -229,11 +240,11 @@ static struct hwpm_ip_inst t234_nvdla_inst_static_array[
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_VALID,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "/dev/nvdladebugfs/nvdla1/hwpm/ctrl",
.dev_name = "",
},
};
@@ -248,6 +259,7 @@ struct hwpm_ip t234_hwpm_ip_nvdla = {
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_nvdla0_base_r(),
.range_end = addr_map_nvdla1_limit_r(),
.inst_stride = addr_map_nvdla0_limit_r() -

19
drivers/tegra/hwpm/hal/t234/ip/nvdla/t234_nvdla.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_NVDLA_H
#define T234_HWPM_IP_NVDLA_H
#if defined(CONFIG_T234_HWPM_IP_NVDLA)
#define T234_HWPM_ACTIVE_IP_NVDLA T234_HWPM_IP_NVDLA,
#define T234_HWPM_ACTIVE_IP_NVDLA T234_HWPM_IP_NVDLA,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_NVDLA_NUM_INSTANCES 2U
#define T234_HWPM_IP_NVDLA_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_NVDLA_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_NVDLA_NUM_INSTANCES 2U
#define T234_HWPM_IP_NVDLA_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_NVDLA_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_NVDLA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_NVDLA_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_nvdla;

19
drivers/tegra/hwpm/hal/t234/ip/pva/t234_pva.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_pva.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -48,6 +54,7 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 1U,
.element_index_mask = BIT(0),
.element_index = 1U,
.dt_mmio = NULL,
@@ -64,6 +71,7 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmon_element_static_array[
},
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 2U,
.element_index_mask = BIT(0),
.element_index = 2U,
.dt_mmio = NULL,
@@ -84,6 +92,7 @@ static struct hwpm_ip_aperture t234_pva_inst0_perfmux_element_static_array[
T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -116,6 +125,7 @@ static struct hwpm_ip_inst t234_pva_inst_static_array[
T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_pva_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_pva0_pm_base_r(),
.range_end = addr_map_pva0_pm_limit_r(),
.element_stride = addr_map_pva0_pm_limit_r() -
@@ -159,11 +169,11 @@ static struct hwpm_ip_inst t234_pva_inst_static_array[
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_VALID,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "/dev/nvpvadebugfs/pva0/hwpm",
.dev_name = "",
},
};
@@ -178,6 +188,7 @@ struct hwpm_ip t234_hwpm_ip_pva = {
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_pva0_pm_base_r(),
.range_end = addr_map_pva0_pm_limit_r(),
.inst_stride = addr_map_pva0_pm_limit_r() -

19
drivers/tegra/hwpm/hal/t234/ip/pva/t234_pva.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_PVA_H
#define T234_HWPM_IP_PVA_H
#if defined(CONFIG_T234_HWPM_IP_PVA)
#define T234_HWPM_ACTIVE_IP_PVA T234_HWPM_IP_PVA,
#define T234_HWPM_ACTIVE_IP_PVA T234_HWPM_IP_PVA,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_PVA_NUM_INSTANCES 1U
#define T234_HWPM_IP_PVA_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST 3U
#define T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_PVA_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_PVA_NUM_INSTANCES 1U
#define T234_HWPM_IP_PVA_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_PVA_NUM_PERFMON_PER_INST 3U
#define T234_HWPM_IP_PVA_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_PVA_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_pva;

14
drivers/tegra/hwpm/hal/t234/ip/vi/t234_vi.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_vi.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_vi_inst0_perfmon_element_static_array[
T234_HWPM_IP_VI_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -52,6 +58,7 @@ static struct hwpm_ip_aperture t234_vi_inst1_perfmon_element_static_array[
T234_HWPM_IP_VI_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -72,6 +79,7 @@ static struct hwpm_ip_aperture t234_vi_inst0_perfmux_element_static_array[
T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -91,6 +99,7 @@ static struct hwpm_ip_aperture t234_vi_inst1_perfmux_element_static_array[
T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -187,6 +196,7 @@ static struct hwpm_ip_inst t234_vi_inst_static_array[
T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_vi_inst1_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_vi2_thi_base_r(),
.range_end = addr_map_vi2_thi_limit_r(),
.element_stride = addr_map_vi2_thi_limit_r() -

19
drivers/tegra/hwpm/hal/t234/ip/vi/t234_vi.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_VI_H
#define T234_HWPM_IP_VI_H
#if defined(CONFIG_T234_HWPM_IP_VI)
#define T234_HWPM_ACTIVE_IP_VI T234_HWPM_IP_VI,
#define T234_HWPM_ACTIVE_IP_VI T234_HWPM_IP_VI,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_VI_NUM_INSTANCES 2U
#define T234_HWPM_IP_VI_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_VI_NUM_INSTANCES 2U
#define T234_HWPM_IP_VI_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_VI_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_vi;

17
drivers/tegra/hwpm/hal/t234/ip/vic/t234_vic.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,19 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t234_vic.h"
#include <tegra_hwpm.h>
#include <hal/t234/t234_regops_allowlist.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
#include <hal/t234/t234_perfmon_device_index.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t234_vic_inst0_perfmon_element_static_array[
T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -52,6 +58,7 @@ static struct hwpm_ip_aperture t234_vic_inst0_perfmux_element_static_array[
T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
@@ -84,6 +91,7 @@ static struct hwpm_ip_inst t234_vic_inst_static_array[
T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST,
.element_static_array =
t234_vic_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_vic_base_r(),
.range_end = addr_map_vic_limit_r(),
.element_stride = addr_map_vic_limit_r() -
@@ -127,11 +135,11 @@ static struct hwpm_ip_inst t234_vic_inst_static_array[
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_VALID,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "/dev/nvhost-debug/vic_hwpm",
.dev_name = "",
},
};
@@ -146,6 +154,7 @@ struct hwpm_ip t234_hwpm_ip_vic = {
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_vic_base_r(),
.range_end = addr_map_vic_limit_r(),
.inst_stride = addr_map_vic_limit_r() -

19
drivers/tegra/hwpm/hal/t234/ip/vic/t234_vic.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,25 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T234_HWPM_IP_VIC_H
#define T234_HWPM_IP_VIC_H
#if defined(CONFIG_T234_HWPM_IP_VIC)
#define T234_HWPM_ACTIVE_IP_VIC T234_HWPM_IP_VIC,
#define T234_HWPM_ACTIVE_IP_VIC T234_HWPM_IP_VIC,
/* This data should ideally be available in HW headers */
#define T234_HWPM_IP_VIC_NUM_INSTANCES 1U
#define T234_HWPM_IP_VIC_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_BROADCAST_PER_INST 0U
#define T234_HWPM_IP_VIC_NUM_INSTANCES 1U
#define T234_HWPM_IP_VIC_NUM_CORE_ELEMENT_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_PERFMON_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_VIC_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t234_hwpm_ip_vic;