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tegra: hwpm: fix cert-c errors

Browse Source 
Fix coding standard cert-c violations because of unsafe calculations.
Introduce safe subtract, add, multiply and cast APIs and use throughout
the hwpm driver.

Bug 3512545

Change-Id: If374629ac75b48a8bc08b1b7a9a41ea5ef0526b1
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2677160
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Prateek Patel <prpatel@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vedashree Vidwans
2022-03-04 16:51:42 -08:00
committed by mobile promotions
parent aaf8e7f5e1
commit edb9e2c245
12 changed files with 349 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
hal/t234/t234_hwpm_alist_utils.c
View File

@@ -17,6 +17,7 @@
#include <tegra_hwpm_log.h>
#include <tegra_hwpm_io.h>
#include <tegra_hwpm.h>
#include <tegra_hwpm_static_analysis.h>
#include <hal/t234/t234_hwpm_internal.h>
#include <hal/t234/t234_hwpm_regops_allowlist.h>
@@ -35,8 +36,9 @@ int t234_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm,
for (alist_idx = 0; alist_idx < aperture->alist_size; alist_idx++) {
if (aperture->alist[alist_idx].zero_at_init) {
regops_writel(hwpm, aperture,
aperture->start_abs_pa +
aperture->alist[alist_idx].reg_offset, 0U);
tegra_hwpm_safe_add_u64(aperture->start_abs_pa,
aperture->alist[alist_idx].reg_offset),
0U);
}
}
return 0;
@@ -86,8 +88,10 @@ int t234_hwpm_get_alist_size(struct tegra_soc_hwpm *hwpm)
}
if (perfmux->alist) {
hwpm->full_alist_size +=
perfmux->alist_size;
hwpm->full_alist_size =
tegra_hwpm_safe_add_u64(
hwpm->full_alist_size,
perfmux->alist_size);
} else {
tegra_hwpm_err(hwpm, "IP %d"
" perfmux %d NULL alist",
@@ -110,8 +114,10 @@ int t234_hwpm_get_alist_size(struct tegra_soc_hwpm *hwpm)
}
if (perfmon->alist) {
hwpm->full_alist_size +=
perfmon->alist_size;
hwpm->full_alist_size =
tegra_hwpm_safe_add_u64(
hwpm->full_alist_size,
perfmon->alist_size);
} else {
tegra_hwpm_err(hwpm, "IP %d"
" perfmon %d NULL alist",
@@ -144,7 +150,8 @@ static int t234_hwpm_copy_alist(struct tegra_soc_hwpm *hwpm,
return -ENOMEM;
}
full_alist[f_alist_idx++] = (aperture->start_abs_pa +
full_alist[f_alist_idx++] = tegra_hwpm_safe_add_u64(
aperture->start_abs_pa,
aperture->alist[alist_idx].reg_offset);
}
@@ -264,7 +271,7 @@ bool t234_hwpm_check_alist(struct tegra_soc_hwpm *hwpm,
return false;
}
reg_offset = phys_addr - aperture->start_abs_pa;
reg_offset = tegra_hwpm_safe_sub_u64(phys_addr, aperture->start_abs_pa);
for (alist_idx = 0; alist_idx < aperture->alist_size; alist_idx++) {
if (reg_offset == aperture->alist[alist_idx].reg_offset) {

37
hal/t234/t234_hwpm_interface_utils.c
View File

@@ -16,6 +16,7 @@
#include <tegra_hwpm_log.h>
#include <tegra_hwpm.h>
#include <tegra_hwpm_static_analysis.h>
#include <hal/t234/t234_hwpm_init.h>
#include <hal/t234/t234_hwpm_internal.h>
@@ -65,7 +66,7 @@ struct tegra_soc_hwpm_chip t234_chip_info = {
};
bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
enum tegra_soc_hwpm_ip ip_index, u32 *config_ip_index)
u32 ip_index, u32 *config_ip_index)
{
u32 config_ip = TEGRA_SOC_HWPM_IP_INACTIVE;
@@ -161,7 +162,7 @@ bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
}
bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
enum tegra_soc_hwpm_resource res_index, u32 *config_ip_index)
u32 res_index, u32 *config_ip_index)
{
u32 config_ip = TEGRA_SOC_HWPM_IP_INACTIVE;
@@ -275,10 +276,11 @@ static int t234_hwpm_init_ip_perfmux_apertures(struct tegra_soc_hwpm *hwpm,
return 0;
}
perfmux_address_range = chip_ip->perfmux_range_end -
chip_ip->perfmux_range_start + 1ULL;
chip_ip->num_perfmux_slots =
(u32) (perfmux_address_range / chip_ip->inst_perfmux_stride);
perfmux_address_range = tegra_hwpm_safe_add_u64(
tegra_hwpm_safe_sub_u64(chip_ip->perfmux_range_end,
chip_ip->perfmux_range_start), 1ULL);
chip_ip->num_perfmux_slots = tegra_hwpm_safe_cast_u64_to_u32(
perfmux_address_range / chip_ip->inst_perfmux_stride);
chip_ip->ip_perfmux = kzalloc(
sizeof(hwpm_ip_perfmux *) * chip_ip->num_perfmux_slots,
@@ -299,11 +301,12 @@ static int t234_hwpm_init_ip_perfmux_apertures(struct tegra_soc_hwpm *hwpm,
perfmux = &chip_ip->perfmux_static_array[perfmux_idx];
/* Compute perfmux offset from perfmux range start */
perfmux_offset =
perfmux->start_abs_pa - chip_ip->perfmux_range_start;
perfmux_offset = tegra_hwpm_safe_sub_u64(
perfmux->start_abs_pa, chip_ip->perfmux_range_start);
/* Compute perfmux slot index */
idx = (u32)(perfmux_offset / chip_ip->inst_perfmux_stride);
idx = tegra_hwpm_safe_cast_u64_to_u32(
perfmux_offset / chip_ip->inst_perfmux_stride);
/* Set perfmux slot pointer */
chip_ip->ip_perfmux[idx] = perfmux;
@@ -325,10 +328,11 @@ static int t234_hwpm_init_ip_perfmon_apertures(struct tegra_soc_hwpm *hwpm,
return 0;
}
perfmon_address_range = chip_ip->perfmon_range_end -
chip_ip->perfmon_range_start + 1ULL;
chip_ip->num_perfmon_slots =
(u32) (perfmon_address_range / chip_ip->inst_perfmon_stride);
perfmon_address_range = tegra_hwpm_safe_add_u64(
tegra_hwpm_safe_sub_u64(chip_ip->perfmon_range_end,
chip_ip->perfmon_range_start), 1ULL);
chip_ip->num_perfmon_slots = tegra_hwpm_safe_cast_u64_to_u32(
perfmon_address_range / chip_ip->inst_perfmon_stride);
chip_ip->ip_perfmon = kzalloc(
sizeof(hwpm_ip_perfmon *) * chip_ip->num_perfmon_slots,
@@ -349,11 +353,12 @@ static int t234_hwpm_init_ip_perfmon_apertures(struct tegra_soc_hwpm *hwpm,
perfmon = &chip_ip->perfmon_static_array[perfmon_idx];
/* Compute perfmon offset from perfmon range start */
perfmon_offset =
perfmon->start_abs_pa - chip_ip->perfmon_range_start;
perfmon_offset = tegra_hwpm_safe_sub_u64(
perfmon->start_abs_pa, chip_ip->perfmon_range_start);
/* Compute perfmon slot index */
idx = (u32)(perfmon_offset / chip_ip->inst_perfmon_stride);
idx = tegra_hwpm_safe_cast_u64_to_u32(
perfmon_offset / chip_ip->inst_perfmon_stride);
/* Set perfmon slot pointer */
chip_ip->ip_perfmon[idx] = perfmon;

4
hal/t234/t234_hwpm_internal.h
View File

@@ -66,9 +66,9 @@ struct tegra_soc_hwpm;
struct hwpm_ip_aperture;
bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
enum tegra_soc_hwpm_ip ip_index, u32 *config_ip_index);
u32 ip_index, u32 *config_ip_index);
bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
enum tegra_soc_hwpm_resource res_index, u32 *config_ip_index);
u32 res_index, u32 *config_ip_index);
int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops, bool available);

11
hal/t234/t234_hwpm_ip_utils.c
View File

@@ -16,6 +16,7 @@
#include <tegra_hwpm_log.h>
#include <tegra_hwpm.h>
#include <tegra_hwpm_static_analysis.h>
#include <hal/t234/t234_hwpm_internal.h>
#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
@@ -115,8 +116,8 @@ static int t234_hwpm_update_ip_ops_info(struct tegra_soc_hwpm *hwpm,
}
/* Update IP ops info for all perfmux in the instance */
max_num_perfmux =
chip_ip->num_instances * chip_ip->num_perfmux_per_inst;
max_num_perfmux = tegra_hwpm_safe_mult_u32(
chip_ip->num_instances, chip_ip->num_perfmux_per_inst);
for (perfmux_idx = 0U; perfmux_idx < max_num_perfmux; perfmux_idx++) {
perfmux = &chip_ip->perfmux_static_array[perfmux_idx];
@@ -235,8 +236,10 @@ static int t234_hwpm_find_ip_perfmux_index(struct tegra_soc_hwpm *hwpm,
* Since all IP instances are configured to be in consecutive memory,
* instance index can be found using instance physical address stride.
*/
addr_offset = base_addr - chip_ip->perfmux_range_start;
perfmux_idx = (u32)(addr_offset / chip_ip->inst_perfmux_stride);
addr_offset = tegra_hwpm_safe_sub_u64(
base_addr, chip_ip->perfmux_range_start);
perfmux_idx = tegra_hwpm_safe_cast_u64_to_u32(
addr_offset / chip_ip->inst_perfmux_stride);
/* Make sure instance index is valid */
if (perfmux_idx >= chip_ip->num_perfmux_slots) {

22
hal/t234/t234_hwpm_regops_utils.c
View File

@@ -13,6 +13,7 @@
#include <uapi/linux/tegra-soc-hwpm-uapi.h>
#include <tegra_hwpm_static_analysis.h>
#include <tegra_hwpm_log.h>
#include <tegra_hwpm_io.h>
#include <tegra_hwpm.h>
@@ -36,8 +37,10 @@ static bool t234_hwpm_is_addr_in_ip_perfmon(struct tegra_soc_hwpm *hwpm,
}
/* Find perfmon idx corresponding phys addr */
address_offset = phys_addr - chip_ip->perfmon_range_start;
perfmon_idx = (u32)(address_offset / chip_ip->inst_perfmon_stride);
address_offset = tegra_hwpm_safe_sub_u64(
phys_addr, chip_ip->perfmon_range_start);
perfmon_idx = tegra_hwpm_safe_cast_u64_to_u32(
address_offset / chip_ip->inst_perfmon_stride);
perfmon = chip_ip->ip_perfmon[perfmon_idx];
@@ -108,8 +111,10 @@ static bool t234_hwpm_is_addr_in_ip_perfmux(struct tegra_soc_hwpm *hwpm,
}
/* Find perfmux idx corresponding phys addr */
address_offset = phys_addr - chip_ip->perfmux_range_start;
perfmux_idx = (u32)(address_offset / chip_ip->inst_perfmux_stride);
address_offset = tegra_hwpm_safe_sub_u64(
phys_addr, chip_ip->perfmux_range_start);
perfmux_idx = tegra_hwpm_safe_cast_u64_to_u32(
address_offset / chip_ip->inst_perfmux_stride);
perfmux = chip_ip->ip_perfmux[perfmux_idx];
@@ -214,6 +219,7 @@ int t234_hwpm_exec_reg_ops(struct tegra_soc_hwpm *hwpm,
int ret = 0;
u32 reg_val = 0U;
u32 ip_idx = TEGRA_SOC_HWPM_IP_INACTIVE; /* ip_idx is unknown */
u64 addr_hi = 0ULL;
struct hwpm_ip_aperture *aperture = NULL;
tegra_hwpm_fn(hwpm, " ");
@@ -250,12 +256,13 @@ int t234_hwpm_exec_reg_ops(struct tegra_soc_hwpm *hwpm,
break;
case TEGRA_SOC_HWPM_REG_OP_CMD_RD64:
addr_hi = tegra_hwpm_safe_add_u64(reg_op->phys_addr, 4ULL);
reg_op->reg_val_lo = regops_readl(hwpm,
aperture,
reg_op->phys_addr);
reg_op->reg_val_hi = regops_readl(hwpm,
aperture,
reg_op->phys_addr + 4ULL);
addr_hi);
reg_op->status = TEGRA_SOC_HWPM_REG_OP_STATUS_SUCCESS;
break;
@@ -270,6 +277,8 @@ int t234_hwpm_exec_reg_ops(struct tegra_soc_hwpm *hwpm,
/* Read Modify Write operation */
case TEGRA_SOC_HWPM_REG_OP_CMD_WR64:
addr_hi = tegra_hwpm_safe_add_u64(reg_op->phys_addr, 4ULL);
/* Lower 32 bits */
reg_val = regops_readl(hwpm, aperture, reg_op->phys_addr);
reg_val = set_field(reg_val, reg_op->mask_lo,
@@ -277,8 +286,7 @@ int t234_hwpm_exec_reg_ops(struct tegra_soc_hwpm *hwpm,
regops_writel(hwpm, aperture, reg_op->phys_addr, reg_val);
/* Upper 32 bits */
reg_val = regops_readl(hwpm, aperture,
reg_op->phys_addr + 4ULL);
reg_val = regops_readl(hwpm, aperture, addr_hi);
reg_val = set_field(reg_val, reg_op->mask_hi,
reg_op->reg_val_hi);
regops_writel(hwpm, aperture, reg_op->phys_addr, reg_val);

12
hal/t234/t234_hwpm_resource_utils.c
View File

@@ -16,6 +16,7 @@
#include <linux/of_address.h>
#include <uapi/linux/tegra-soc-hwpm-uapi.h>
#include <tegra_hwpm_static_analysis.h>
#include <tegra_hwpm_log.h>
#include <tegra_hwpm_io.h>
#include <tegra_hwpm.h>
@@ -76,11 +77,12 @@ static int t234_hwpm_perfmux_reserve(struct tegra_soc_hwpm *hwpm,
/* Allocate fake registers */
if (hwpm->fake_registers_enabled) {
u64 num_regs = 0;
u64 address_range = tegra_hwpm_safe_add_u64(
tegra_hwpm_safe_sub_u64(
perfmux->end_pa, perfmux->start_pa), 1ULL);
u64 num_regs = address_range / sizeof(u32);
u32 **fake_regs = &perfmux->fake_registers;
num_regs = (perfmux->end_pa + 1 - perfmux->start_pa) /
sizeof(u32);
*fake_regs = (u32 *)kzalloc(sizeof(u32) * num_regs, GFP_KERNEL);
if (!(*fake_regs)) {
tegra_hwpm_err(hwpm, "Aperture(0x%llx - 0x%llx):"
@@ -165,7 +167,9 @@ int t234_hwpm_perfmon_reserve(struct tegra_soc_hwpm *hwpm,
perfmon->end_pa = res->end;
if (hwpm->fake_registers_enabled) {
u64 num_regs = (res->end + 1 - res->start) / sizeof(u32);
u64 address_range = tegra_hwpm_safe_add_u64(
tegra_hwpm_safe_sub_u64(res->end, res->start), 1ULL);
u64 num_regs = address_range / sizeof(u32);
perfmon->fake_registers = (u32 *)kzalloc(sizeof(u32) * num_regs,
GFP_KERNEL);
if (perfmon->fake_registers == NULL) {