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tegra: hwpm: Support for Credit Programming

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- Add HWPM Driver support for Credit Programming. Credit
programming can be accomplished by read-write into
secure HWPM registers, which cannot come in as a reg_ops
request from User Space application.

- Implement an empty credit programming handler for T234 and
th500.

- Implement OS agnostic HALs for Credit programming.

Bug 4571175

Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: I18dcff47dfe461bce3dcb6d78f39ff0156b4b0a5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3127013
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
vasukis
2024-04-26 19:13:45 +00:00
committed by mobile promotions
parent 5d80b2edb5
commit f672287ded
3 changed files with 18 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/tegra/hwpm/hal/t234/t234_interface.c
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT // SPDX-License-Identifier: MIT
/* /*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -58,6 +58,7 @@ static struct tegra_soc_hwpm_chip t234_chip_info = {
.init_prod_values = t234_hwpm_init_prod_values, .init_prod_values = t234_hwpm_init_prod_values,
.disable_cg = t234_hwpm_disable_cg, .disable_cg = t234_hwpm_disable_cg,
.enable_cg = t234_hwpm_enable_cg, .enable_cg = t234_hwpm_enable_cg,
.credit_program = NULL,
.reserve_rtr = tegra_hwpm_reserve_rtr, .reserve_rtr = tegra_hwpm_reserve_rtr,
.release_rtr = tegra_hwpm_release_rtr, .release_rtr = tegra_hwpm_release_rtr,

4
drivers/tegra/hwpm/hal/th500/th500_interface.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT // SPDX-License-Identifier: MIT
/* /*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -59,6 +59,8 @@ static struct tegra_soc_hwpm_chip th500_chip_info = {
.disable_cg = th500_hwpm_soc_disable_cg, .disable_cg = th500_hwpm_soc_disable_cg,
.enable_cg = th500_hwpm_soc_enable_cg, .enable_cg = th500_hwpm_soc_enable_cg,
.credit_program = NULL,
.reserve_rtr = tegra_hwpm_reserve_rtr, .reserve_rtr = tegra_hwpm_reserve_rtr,
.release_rtr = tegra_hwpm_release_rtr, .release_rtr = tegra_hwpm_release_rtr,

14
drivers/tegra/hwpm/include/tegra_hwpm.h
View File

@@ -56,6 +56,7 @@ struct tegra_hwpm_os_qnx;
#endif #endif
struct tegra_hwpm_mem_mgmt; struct tegra_hwpm_mem_mgmt;
struct tegra_hwpm_allowlist_map; struct tegra_hwpm_allowlist_map;
struct tegra_soc_hwpm_exec_credit_program;
enum tegra_soc_hwpm_ip_reg_op; enum tegra_soc_hwpm_ip_reg_op;
/* /*
@@ -140,6 +141,15 @@ enum tegra_hwpm_resource_enum {
TERGA_HWPM_NUM_RESOURCES TERGA_HWPM_NUM_RESOURCES
}; };
/* Used in Credit Programming */
enum tegra_hwpm_credit_cmd {
TEGRA_HWPM_CMD_SET_HS_CREDITS,
TEGRA_HWPM_CMD_GET_HS_CREDITS,
TEGRA_HWPM_CMD_GET_TOTAL_HS_CREDITS,
TEGRA_HWPM_CMD_GET_CHIPLET_HS_CREDITS_POOL,
TEGRA_HWPM_CMD_GET_HS_CREDITS_MAPPING
};
/* /*
* This structure is copy of struct tegra_soc_hwpm_ip_ops uapi structure. * This structure is copy of struct tegra_soc_hwpm_ip_ops uapi structure.
* This is not a hard requirement as each value from tegra_soc_hwpm_ip_ops * This is not a hard requirement as each value from tegra_soc_hwpm_ip_ops
@@ -536,7 +546,9 @@ struct tegra_soc_hwpm_chip {
int (*init_prod_values)(struct tegra_soc_hwpm *hwpm); int (*init_prod_values)(struct tegra_soc_hwpm *hwpm);
int (*disable_cg)(struct tegra_soc_hwpm *hwpm); int (*disable_cg)(struct tegra_soc_hwpm *hwpm);
int (*enable_cg)(struct tegra_soc_hwpm *hwpm); int (*enable_cg)(struct tegra_soc_hwpm *hwpm);
int (*credit_program)(struct tegra_soc_hwpm *hwpm,
u32 *num_credits, u8 cblock_idx,
u8 pma_channel_idx, uint16_t credit_cmd);
int (*reserve_rtr)(struct tegra_soc_hwpm *hwpm); int (*reserve_rtr)(struct tegra_soc_hwpm *hwpm);
int (*release_rtr)(struct tegra_soc_hwpm *hwpm); int (*release_rtr)(struct tegra_soc_hwpm *hwpm);