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tegra: hwpm: add IP floorsweep info for silicon

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Add floorsweep masks for IPs on silicon. Only verified IPs at the moment
are enabled in the driver.

Bug 3335822

Change-Id: I449d44e4430d273b0680ef9b7f89106df9376d5e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2585983
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2021-08-30 10:00:37 -07:00
committed by mobile promotions
parent 818008bdaf
commit f7fa0cd28f
1 changed files with 16 additions and 0 deletions
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16
tegra-soc-hwpm-ioctl.c
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@@ -1246,6 +1246,22 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp)
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_MCF] = 0x1; hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_MCF] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_NVLINK] = 0x1; hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_NVLINK] = 0x1;
} }
if (tegra_platform_is_silicon()) {
/* Update fs_info once IP is validated */
/* Static IP instances corresponding to silicon */
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_ISP] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_VIC] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_PVA] = 0x1;
/*
* Bug 3362415: MSS Channel cannot be force enabled on TOT
* Mark MSS channels as floorswept.
*/
/* hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_CHANNEL] = 0xFFFF; */
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_GPU_HUB] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_MCF] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_NVLINK] = 0x1;
}
/* Map PMA and RTR apertures */ /* Map PMA and RTR apertures */
hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT] = hwpm->dt_apertures[TEGRA_SOC_HWPM_PMA_DT] =