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tegra: hwpm: update IP registration interface

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Enum tegra_soc_hwpm_ip is defined to query IP information. To untangle
its use from HWPM related functionality, enum tegra_soc_hwpm_resource
should be used by IP drivers to register with HWPM.

An IP can have multiple instances with multiple IP core elements in
each instance. Currently, the IP <-> HWPM register access API passes
register offset only. However, it is not possible to figure out
requested specific register access only with register offset. For
example, MC device has one instance with 16 duplicate channels. To
access channel x perfmux register, HWPM driver should pass perfmux
register offset alongwith channel number (index).
Add instance element index as an argument to the register access API,
tegra_soc_hwpm_ip_ops.hwpm_ip_reg_op().
-Update internal copy of tegra_soc_hwpm_ip_ops.
-Update hwpm_ip_reg_op() implemented in flcn driver.
-Update hwpm_ip_reg_op() implemented in pva driver.

Update hwpm_ip_pm() in flcn driver to use nvhost power management APIs.

Bug 3573882
Jira THWPM-8

Change-Id: I0138927f383e9a67085816132ce33538bd609560
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2713274
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vedashree Vidwans
2022-05-16 11:29:42 -07:00
committed by mobile promotions
parent 787831388d
commit fe7a4734a2
6 changed files with 22 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
common/tegra_hwpm_ip_utils.c
View File

@@ -201,7 +201,7 @@ static int tegra_hwpm_complete_ip_register(struct tegra_soc_hwpm *hwpm)
while (node != NULL) {
tegra_hwpm_dbg(hwpm, hwpm_info, "IP ext idx %d info",
node->ip_ops.ip_index);
node->ip_ops.resource_enum);
ret = hwpm->active_chip->extract_ip_ops(
hwpm, &node->ip_ops, true);
if (ret != 0) {

2
hal/t234/t234_hwpm_internal.h
View File

@@ -80,7 +80,7 @@ int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops, bool available);
int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm);
int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,
u32 ip_index, u64 *fs_mask, u8 *ip_status);
u32 ip_enum, u64 *fs_mask, u8 *ip_status);
int t234_hwpm_init_prod_values(struct tegra_soc_hwpm *hwpm);
int t234_hwpm_disable_slcg(struct tegra_soc_hwpm *hwpm);

21
hal/t234/t234_hwpm_ip_utils.c
View File

@@ -29,12 +29,13 @@ int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
tegra_hwpm_fn(hwpm, " ");
/* Convert tegra_soc_hwpm_ip to internal enum */
if (!(t234_hwpm_is_ip_active(hwpm,
hwpm_ip_ops->ip_index, &ip_idx))) {
/* Convert tegra_soc_hwpm_resource to internal enum */
if (!(t234_hwpm_is_resource_active(hwpm,
hwpm_ip_ops->resource_enum, &ip_idx))) {
tegra_hwpm_err(hwpm,
"SOC hwpm IP %d (base 0x%llx) is unconfigured",
hwpm_ip_ops->ip_index, hwpm_ip_ops->ip_base_address);
"SOC hwpm resource %d (base 0x%llx) is unconfigured",
hwpm_ip_ops->resource_enum,
hwpm_ip_ops->ip_base_address);
goto fail;
}
@@ -306,7 +307,7 @@ fail:
}
int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,
u32 ip_index, u64 *fs_mask, u8 *ip_status)
u32 ip_enum, u64 *fs_mask, u8 *ip_status)
{
u32 ip_idx = 0U;
struct tegra_soc_hwpm_chip *active_chip = NULL;
@@ -316,17 +317,17 @@ int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,
tegra_hwpm_fn(hwpm, " ");
/* Convert tegra_soc_hwpm_ip to internal enum */
if (!(t234_hwpm_is_ip_active(hwpm, ip_index, &ip_idx))) {
if (!(t234_hwpm_is_ip_active(hwpm, ip_enum, &ip_idx))) {
tegra_hwpm_dbg(hwpm, hwpm_info,
"SOC hwpm IP %d is not configured", ip_index);
"SOC hwpm IP %d is not configured", ip_enum);
*ip_status = TEGRA_SOC_HWPM_IP_STATUS_INVALID;
*fs_mask = 0ULL;
/* Remove after uapi update */
if (ip_index == TEGRA_SOC_HWPM_IP_MSS_NVLINK) {
if (ip_enum == TEGRA_SOC_HWPM_IP_MSS_NVLINK) {
tegra_hwpm_dbg(hwpm, hwpm_verbose,
"For hwpm IP %d setting status as valid",
ip_index);
ip_enum);
*ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID;
}
return 0;

7
include/tegra_hwpm.h
View File

@@ -65,11 +65,13 @@ struct tegra_hwpm_ip_ops {
* For read:
* input : dev - IP device handle
* input : reg_op - TEGRA_SOC_HWPM_IP_REG_OP_READ
* input : inst_element_index - element index within IP instance
* input : reg_offset - register offset
* output: reg_data - u32 read value
* For write:
* input : dev - IP device handle
* input : reg_op - TEGRA_SOC_HWPM_IP_REG_OP_WRITE
* input : inst_element_index - element index within IP instance
* input : reg_offset - register offset
* output: reg_data - u32 write value
* Return:
@@ -77,7 +79,8 @@ struct tegra_hwpm_ip_ops {
*/
int (*hwpm_ip_reg_op)(void *dev,
enum tegra_soc_hwpm_ip_reg_op reg_op,
__u64 reg_offset, __u32 *reg_data);
u32 inst_element_index, u64 reg_offset,
u32 *reg_data);
};
/* There are 3 types of HWPM components/apertures */
@@ -303,7 +306,7 @@ struct tegra_soc_hwpm_chip {
struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops, bool available);
int (*force_enable_ips)(struct tegra_soc_hwpm *hwpm);
int (*get_fs_info)(struct tegra_soc_hwpm *hwpm,
u32 ip_index, u64 *fs_mask, u8 *ip_status);
u32 ip_enum, u64 *fs_mask, u8 *ip_status);
int (*init_prod_values)(struct tegra_soc_hwpm *hwpm);
int (*disable_slcg)(struct tegra_soc_hwpm *hwpm);

4
os/linux/tegra_hwpm_io.c
View File

@@ -67,7 +67,7 @@ static int ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
err = (*ip_ops_ptr->hwpm_ip_reg_op)(ip_ops_ptr->ip_dev,
TEGRA_SOC_HWPM_IP_REG_OP_READ,
offset, val);
aperture->dt_index, offset, val);
if (err < 0) {
tegra_hwpm_err(hwpm, "Aperture (0x%llx-0x%llx) "
"read offset(0x%llx) failed",
@@ -121,7 +121,7 @@ static int ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
err = (*ip_ops_ptr->hwpm_ip_reg_op)(ip_ops_ptr->ip_dev,
TEGRA_SOC_HWPM_IP_REG_OP_WRITE,
offset, &val);
aperture->dt_index, offset, &val);
if (err < 0) {
tegra_hwpm_err(hwpm, "Aperture (0x%llx-0x%llx) "
"write offset(0x%llx) val 0x%x failed",

4
os/linux/tegra_hwpm_ip.c
View File

@@ -110,7 +110,7 @@ void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
hwpm_ip_ops, REGISTER_IP);
if (ret < 0) {
tegra_hwpm_err(hwpm, "Failed to set IP ops for IP %d",
hwpm_ip_ops->ip_index);
hwpm_ip_ops->resource_enum);
}
}
}
@@ -141,7 +141,7 @@ void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
hwpm_ip_ops, UNREGISTER_IP);
if (ret < 0) {
tegra_hwpm_err(hwpm, "Failed to reset IP ops for IP %d",
hwpm_ip_ops->ip_index);
hwpm_ip_ops->resource_enum);
}
}
}