- HALs get_rtr_int_idx and get_ip_max_idx return the chip specific
router index and number of IPs. This information is static for a chip
and doesn't require any input. Hence, update the HAL definition to not
require hwpm pointer as an argument. Update definition and references
for these HALs.
- Add new HAL to get PMA and RTR structure pointers. Implement and
update other chip specific functions to use new HAL.
- Add new timer macro to check a condition and timeout after given
retries. Update necessary code to use new timer macro.
- Correct validate_emc_config function to compute correct available mss
channel mask based on fuse value.
- Update tegra_hwpm_readl and tegra_hwpm_writel macros to assert error
value. This way error checks are added at one spot and not sprinkled all
over the driver code.
- Update get_mem_bytes_put_ptr() and membuf_overflow_status() to return
error as function return and accept arguments to return mem_head pointer
and overflow status respectively. Add overflow status macros to use
throughout driver. Update HAL definition and references accordingly.
- conftest is only compiled for OOT config atm. Add OOT config check to
include conftest header.
Jira THWPM-109
Change-Id: I77d150e860fa344a1604d241e27718150fdb8647
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2982555
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Vishal Aslot <vaslot@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
On production board, MC config details are available through fuses. Add
function to read MC config fuse. Use the floorsweep fuse info to find
available elements.
Bug 3936487
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I9e1549e3dfb9c06d8013ca2e1d43eb21bf0289f4
(cherry picked from commit f38e98a94ab8d478af3ebe1c922da606df9b67dc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2888554
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- Create tegra_hwpm_element_enable() instead of directly using
perfmon_enable() HAL. This will allow us to expand
tegra_hwpm_element_enable in future.
- Update log messages in ip structure init code and floorsweep info
function.
- It is possible that IP instances and elements to have 0 start range
address. So, modify check for available elements to use range end
instead.
- Use tegra_hwpm_fake_readl() and tegra_hwpm_fake_writel() macros
instead of fake_readl() and fake_write() functions. That way we have
similar implementation of IO functions and macros can be used across
OSes.
- Check that reserve perfmon function is invoked only for HWPM
components. This check will be useful for expansion in types of
components in the future.
- Clean up and rearrange tegra_hwpm_regops_readl_impl() and
tegra_hwpm_regops_writel_impl() to have designated code corresponding to
the element type.
- Currently, device open and release functions are incorrectly using
clock enable/disable functions instead of using HALs. Correct open and
close functions to use lock HALs.
- Currently, tegra_hwpm_update_mem_bytes() doesn't validate mem_mgmt
structure allocation before accessing mem_bytes_kernel pointer. This can
lead to kernel crash. Update tegra_hwpm_update_mem_bytes() to return
error if mem_mgmt structure s not allocated.
Jira THWPM-74
Change-Id: Ia40bd51187e5ea08572dbee81e577dacf5fb66b6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
(cherry picked from commit 411f07484d68dfde0d350a5c67f2748e876b11b8)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2888553
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Modify OS agnostic files in common, hal and include folder to use MIT
license. This will allow the files to be shared between different OSes.
Modify OS specific files in os/linux and uapi folders to add SPDX
identifier for GPLv2.
Jira THWPM-69
Change-Id: I4fef142354a46fc23b67616204ccf0712a99caec
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797453
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Below listed functions are defined and used in the same source file,
hence update the functions to be static.
- tegra_hwpm_element_disable
- tegra_hwpm_element_reserve
- tegra_hwpm_element_release
Bug 3528414
Change-Id: Ib9aa44001fb5fac1e339b3264a4d750af09b9a01
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2847009
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
- Zeroing of PMA trigger registers is unnecessary. Remove corresponding
logic from HWPM teardown function.
- During device open, add a check for PMA/RTR status. This will ensure
that PMA/RTR are ready to start new profiling session. Device open will
fail if RTR and PMA enginestatus is not ready(idle).
- SOC HWPM driver disables and releases all reserved IPs before teardown
steps. Update teardown logic to zero out IP allowlist registers during
teardown.
Jira THWPM-41
Bug 3714516
Change-Id: Iede5a5ed9860e2a73c8e4a04aeedfc061458c793
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2776229
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797444
HWPM files are copied from the previous source in linux-nvidia repo
withgit history. Create folders and move files to obtain expected folder
structure.
Bug 3787076
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
