Currently, read/write functions validate aperture and mmio address
pointers. However, the error cannot be returned to the parent resulting
into undetected errors.
Modify all read write functions to return error on failure. This will
also allow HWPM driver to know about unavailable IP perfmuxes.
Jira THWPM-41
Change-Id: I6cc4ba7a831d5058657d4f2536b1ce3ab20b30c6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2707446
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Introduced macros to define HWPM aperture types perfmon, perfmux and
broadcast.
Added new enum to define element type.
IP perfmux and IP broadcast are handled in similar way. Whereas, HWPM
perfmux should use HWPM perfmon functions.
Updated hwpm structures are as below
Parent HWPM structure
-> Active chip structure
-> Array of IPs
-> HALs
IP structure
-> Array of instances
-> Array of instance info with respect to perfmon, perfmux, broadcast
-> Instance mask : indicates available instances
-> reserved status
Instance structure
-> Array of element info with respect to perfmon, perfmux, broadcast
-> Array of corresponding element structures
-> Element mask : indicates available elements in the instance
Element structure
-> Aperture address details
-> DT node / MMIO details
Update all functions to use new HWPM structures.
Update hwpm_probe to include force IP enable step.
Jira THWPM-41
Change-Id: I9461063d2136b34e841322c4ddd77a20486424c6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2706489
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
- Update HWPM driver to add HAL layer. This will allow support for multiple chips.
- Add below data structure hierarchy for HWPM driver
HWPM driver structure -> chip info struct -> ip info array -> perfmux/perfmon info array
NOTE: To make commit message more legible, using "aperture" instead of "perfmux and/or perfmon"
- Chip info structure contains
- Array of IP info
- HAL function pointers
- IP info structure contains IP specific info
- Number of instances
- Number of apertures per instance
- Aperture ranges, strides, static info array
- Aperture dynamic arrays
- Aperture info structure contains
- Hw index
- Physical address info
- MMIO address info
- Add separate IP info files
- Create separate files that include logic for allowlist, memory buffer, resources, ip, regops to make functions more legible.
- Move probe, ioctl and io functions to os/linux path.
- Add fn, info, register and verbose debug log levels to controls debug messages
- add debugfs node to update dbg_mask
- Correct MGBE perfmux base address
Jira THWPM-41
Change-Id: I8ffdaa657789e2a187cbb98502d0359bb57f9c54
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2651377
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
