- Update HWPM driver to add HAL layer. This will allow support for multiple chips.
- Add below data structure hierarchy for HWPM driver
HWPM driver structure -> chip info struct -> ip info array -> perfmux/perfmon info array
NOTE: To make commit message more legible, using "aperture" instead of "perfmux and/or perfmon"
- Chip info structure contains
- Array of IP info
- HAL function pointers
- IP info structure contains IP specific info
- Number of instances
- Number of apertures per instance
- Aperture ranges, strides, static info array
- Aperture dynamic arrays
- Aperture info structure contains
- Hw index
- Physical address info
- MMIO address info
- Add separate IP info files
- Create separate files that include logic for allowlist, memory buffer, resources, ip, regops to make functions more legible.
- Move probe, ioctl and io functions to os/linux path.
- Add fn, info, register and verbose debug log levels to controls debug messages
- add debugfs node to update dbg_mask
- Correct MGBE perfmux base address
Jira THWPM-41
Change-Id: I8ffdaa657789e2a187cbb98502d0359bb57f9c54
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2651377
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Move chip specific code to chip specific folder. This will allow
multiple chip support in the future.
Create new specific functions
- Initialize hwpm structures
- Reserve and release PMA and RTR apertures
- Zero, update and check allowlists
- Set and get fake registers for MC aperture on simulation
- perfmon dt aperture enums
Jira THWPM-41
Change-Id: Ib80f324283c8d29b5c6f7bb6345a6df2410954e6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2620234
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add support for IP registering mechanism for runtime
callback and perfmux read/writes.
void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops);
IP's callback are called to disable and enable IP runtime pm.
At this moment, only VIC/NVENC/OFA driver registration is supported.
Also will take-up perfmux register read/write in follow-up patch.
Bug 3333031
Bug 3333042
Change-Id: If559cae73be1edbdb7139b4183ce3e1dc0943053
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2607267
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add a driver for programming the Tegra SOC HWPM path. SOC HWPM allows
performance monitoring of various Tegra IPs.
The profiling tests cases are configured through IOCTLs sent by a
userspace profiling app. The IOCTLs provide the following features:
- IP discovery and reservation
- Buffer management
- Whitelist query
- Register read/write ops
Bug 200702306
Bug 3305495
Change-Id: I65003b126e01bd03d856767c55aa2424bcfd11fb
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2515148
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
