On production board, MC config details are available through fuses. Add
function to read MC config fuse. Use the floorsweep fuse info to find
available elements.
Bug 3936487
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I9e1549e3dfb9c06d8013ca2e1d43eb21bf0289f4
(cherry picked from commit f38e98a94ab8d478af3ebe1c922da606df9b67dc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2888554
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- Create tegra_hwpm_element_enable() instead of directly using
perfmon_enable() HAL. This will allow us to expand
tegra_hwpm_element_enable in future.
- Update log messages in ip structure init code and floorsweep info
function.
- It is possible that IP instances and elements to have 0 start range
address. So, modify check for available elements to use range end
instead.
- Use tegra_hwpm_fake_readl() and tegra_hwpm_fake_writel() macros
instead of fake_readl() and fake_write() functions. That way we have
similar implementation of IO functions and macros can be used across
OSes.
- Check that reserve perfmon function is invoked only for HWPM
components. This check will be useful for expansion in types of
components in the future.
- Clean up and rearrange tegra_hwpm_regops_readl_impl() and
tegra_hwpm_regops_writel_impl() to have designated code corresponding to
the element type.
- Currently, device open and release functions are incorrectly using
clock enable/disable functions instead of using HALs. Correct open and
close functions to use lock HALs.
- Currently, tegra_hwpm_update_mem_bytes() doesn't validate mem_mgmt
structure allocation before accessing mem_bytes_kernel pointer. This can
lead to kernel crash. Update tegra_hwpm_update_mem_bytes() to return
error if mem_mgmt structure s not allocated.
Jira THWPM-74
Change-Id: Ia40bd51187e5ea08572dbee81e577dacf5fb66b6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
(cherry picked from commit 411f07484d68dfde0d350a5c67f2748e876b11b8)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2888553
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Modify OS agnostic files in common, hal and include folder to use MIT
license. This will allow the files to be shared between different OSes.
Modify OS specific files in os/linux and uapi folders to add SPDX
identifier for GPLv2.
Jira THWPM-69
Change-Id: I4fef142354a46fc23b67616204ccf0712a99caec
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797453
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
HWPM components (PMA, RTR, perfmon) have MMIO address space and a
corresponding virtual address region. It is possible that both MMIO and
virtual addresses are same for an aperture.
MMIO address of an aperture is used in device node to enable the
aperture and further to map HWPM component in the driver.
Virtual addresses are used by the applications to execute regops on HWPM
apertures. Virtual addresses are also used to fake aperture address
space in simulation.
This patch updates
- HWPM aperture structures to include MMIO address.
- aperture ioremap function to use MMIO address values.
- fake register allocation to use virtual address values.
Jira THWPM-41
Change-Id: I05acb68dcb278722cd333e1187b2355d1d739e93
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
(cherry picked from commit 1c0e8107b4cddad7532c10dddc22bb30cef2540b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2853213
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Below listed functions are defined and used in the same source file,
hence update the functions to be static.
- tegra_hwpm_element_disable
- tegra_hwpm_element_reserve
- tegra_hwpm_element_release
Bug 3528414
Change-Id: Ib9aa44001fb5fac1e339b3264a4d750af09b9a01
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2847009
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Add Device_index tag to read IP perfmon register address
index from ACPI or DTSI tables. Device_index will be
used to retrieve resource information from acpi tables
or device trees. This will replace current logic to
procure resource details using device names.
JIRA THWPM-71
Change-Id: I964546f2262dd77ec0acfb58f49d044c870deae6
Signed-off-by: vasukis <vasukis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797448
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Tested-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Currently, dt_index aperture spec actually holds the element index of
the aperture within the IP instance. Hence, replace dt_index with
element_index to better indicate its purpose.
JIRA THWPM-71
Change-Id: Ic805da3281c60991e7966a80f442d84a2cfcf7cc
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797447
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
- Make clock reset functions into HALs. This way we can control
clock-reset logic for any chip. Set clock-reset HAL pointers to
appropriate functions.
- Remove clock-reset function wrappers as these will not be required and
corresponding HAL pointers will be used.
- As clock reset init is defined as a HAL, modify probe logic to
initialize chip info before invoking any HALs.
- Move common/primary HAL validation logic to common code and implement
new HAL to validate chip specific HALs. This way we can ensure that HAL
pointers are set as expected.
- Keep only one definition for t234_hwpm_init_chip_info as t234 should
always be initialized and hence only single definition should be
available.
- Expected return value of 0 indicates success and any other value
(mostly negative in current logic) indicates error, compare function
returns with 0 to print error in tegra_hwpm_release().
- Since a build can support both ACPI and device tree, update
init_chip_info() to retrieve chip information from ACPI and device tree
in case of failure.
Jira THWPM-41
Bug 3583624
Change-Id: I03fefae0b3b0c8ce46d175d39e4fdbb45e2bb22f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2789668
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797445
- Zeroing of PMA trigger registers is unnecessary. Remove corresponding
logic from HWPM teardown function.
- During device open, add a check for PMA/RTR status. This will ensure
that PMA/RTR are ready to start new profiling session. Device open will
fail if RTR and PMA enginestatus is not ready(idle).
- SOC HWPM driver disables and releases all reserved IPs before teardown
steps. Update teardown logic to zero out IP allowlist registers during
teardown.
Jira THWPM-41
Bug 3714516
Change-Id: Iede5a5ed9860e2a73c8e4a04aeedfc061458c793
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2776229
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797444
HWPM files are copied from the previous source in linux-nvidia repo
withgit history. Create folders and move files to obtain expected folder
structure.
Bug 3787076
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
