// SPDX-License-Identifier: MIT
/*
 * SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <tegra_hwpm_mem_mgmt.h>
#include <tegra_hwpm_timers.h>
#include <tegra_hwpm_log.h>
#include <tegra_hwpm_io.h>
#include <tegra_hwpm.h>

#include <hal/t264/t264_internal.h>
#include <hal/t264/ip/rtr/t264_rtr.h>
#include <hal/t264/hw/t264_pmasys_soc_hwpm.h>
#include <hal/t264/hw/t264_pmmsys_soc_hwpm.h>

int t264_hwpm_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm)
{
	int err = 0;
	u32 reset_val = 0U;
	struct hwpm_ip_aperture *pma_perfmux = NULL;

	tegra_hwpm_fn(hwpm, " ");

	err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, &pma_perfmux);
	hwpm_assert_print(hwpm, err == 0, return err,
		"get rtr pma perfmux failed");

	/* Reset OUTBASE register */
	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_outbase_r(0, 0), &reset_val);
	reset_val = set_field(reset_val,
		pmasys_channel_outbase_ptr_m(),
		pmasys_channel_outbase_ptr_init_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_outbase_r(0, 0), reset_val);

	/* Reset OUTBASEUPPER register */
	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_outbaseupper_r(0, 0), &reset_val);
	reset_val = set_field(reset_val,
		pmasys_channel_outbaseupper_ptr_m(),
		pmasys_channel_outbaseupper_ptr_init_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_outbaseupper_r(0, 0), reset_val);

	/* Reset OUTSIZE register */
	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_outsize_r(0, 0), &reset_val);
	reset_val = set_field(reset_val,
		pmasys_channel_outsize_numbytes_m(),
		pmasys_channel_outsize_numbytes_init_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_outsize_r(0, 0), reset_val);

	/* Reset MEM_BYTES_ADDR register */
	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_mem_bytes_addr_r(0, 0), &reset_val);
	reset_val = set_field(reset_val,
		pmasys_channel_mem_bytes_addr_ptr_m(),
		pmasys_channel_mem_bytes_addr_ptr_init_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_mem_bytes_addr_r(0, 0), reset_val);

	/* Reset MEM_HEAD register */
	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_mem_head_r(0, 0), &reset_val);
	reset_val = set_field(reset_val,
		pmasys_channel_mem_head_ptr_m(),
		pmasys_channel_mem_head_ptr_init_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_mem_head_r(0, 0), reset_val);

	/* Reset MEM_BYTES register */
	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_mem_bytes_r(0, 0), &reset_val);
	reset_val = set_field(reset_val,
		pmasys_channel_mem_bytes_numbytes_m(),
		pmasys_channel_mem_bytes_numbytes_init_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_mem_bytes_r(0, 0), reset_val);

	/* Reset MEMBUF_STATUS */
	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_control_user_r(0, 0), &reset_val);
	reset_val = set_field(reset_val,
		pmasys_channel_control_user_membuf_clear_status_m(),
		pmasys_channel_control_user_membuf_clear_status_doit_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_control_user_r(0, 0), reset_val);

	return 0;
}

int t264_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm)
{
	int err = 0;
	u32 outbase_lo = 0U;
	u32 outbase_hi = 0U;
	u32 outsize = 0U;
	u32 mem_bytes_addr = 0U;
	u32 membuf_status = 0U;
	u32 mem_head = 0U;
	u32 bpc_mem_block = 0U;
	struct hwpm_ip_aperture *pma_perfmux = NULL;
	struct tegra_hwpm_mem_mgmt *mem_mgmt = hwpm->mem_mgmt;

	tegra_hwpm_fn(hwpm, " ");

	err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL, &pma_perfmux);
	hwpm_assert_print(hwpm, err == 0, return err,
		"get rtr pma perfmux failed");

	outbase_lo = mem_mgmt->stream_buf_va & pmasys_channel_outbase_ptr_m();
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_outbase_r(0, 0), outbase_lo);
	tegra_hwpm_dbg(hwpm, hwpm_dbg_alloc_pma_stream, "OUTBASE = 0x%x", outbase_lo);

	outbase_hi = (mem_mgmt->stream_buf_va >> 32) &
			pmasys_channel_outbaseupper_ptr_m();
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_outbaseupper_r(0, 0), outbase_hi);
	tegra_hwpm_dbg(hwpm, hwpm_dbg_alloc_pma_stream, "OUTBASEUPPER = 0x%x", outbase_hi);

	outsize = mem_mgmt->stream_buf_size &
			pmasys_channel_outsize_numbytes_m();
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_outsize_r(0, 0), outsize);
	tegra_hwpm_dbg(hwpm, hwpm_dbg_alloc_pma_stream, "OUTSIZE = 0x%x", outsize);

	mem_bytes_addr = mem_mgmt->mem_bytes_buf_va &
			pmasys_channel_mem_bytes_addr_ptr_m();
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_mem_bytes_addr_r(0, 0), mem_bytes_addr);
	tegra_hwpm_dbg(hwpm, hwpm_dbg_alloc_pma_stream,
		"MEM_BYTES_ADDR = 0x%x", mem_bytes_addr);

	/* Update MEM_HEAD to OUTBASE */
	mem_head = mem_mgmt->stream_buf_va & pmasys_channel_mem_head_ptr_m();
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_mem_head_r(0, 0), mem_head);
	tegra_hwpm_dbg(hwpm, hwpm_dbg_alloc_pma_stream, "MEM_HEAD = 0x%x", mem_head);

	/* Reset MEMBUF_STATUS */
	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_control_user_r(0, 0), &membuf_status);
	membuf_status = set_field(membuf_status,
		pmasys_channel_control_user_membuf_clear_status_m(),
		pmasys_channel_control_user_membuf_clear_status_doit_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_control_user_r(0, 0), membuf_status);

	/* Update CBLOCK_BPC_MEM_BLOCK to OUTBASE to ensure BPC is bound */
	bpc_mem_block = mem_mgmt->stream_buf_va &
		pmasys_cblock_bpc_mem_block_base_m();
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_cblock_bpc_mem_block_r(0), outbase_lo);
	tegra_hwpm_dbg(hwpm, hwpm_dbg_alloc_pma_stream, "bpc_mem_block = 0x%x",
		bpc_mem_block);

	/* Mark mem block valid */
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_cblock_bpc_mem_blockupper_r(0),
		pmasys_cblock_bpc_mem_blockupper_valid_f(
			pmasys_cblock_bpc_mem_blockupper_valid_true_v()));

	return 0;
}

int t264_hwpm_invalidate_mem_config(struct tegra_soc_hwpm *hwpm)
{
	int err = 0;
	struct hwpm_ip_aperture *pma_perfmux = NULL;

	tegra_hwpm_fn(hwpm, " ");

	err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL,
		&pma_perfmux);
	hwpm_assert_print(hwpm, err == 0, return err,
		"get rtr pma perfmux failed");

	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_cblock_bpc_mem_blockupper_r(0),
		pmasys_cblock_bpc_mem_blockupper_valid_f(
			pmasys_cblock_bpc_mem_blockupper_valid_false_v()));

	return 0;
}

int t264_hwpm_stream_mem_bytes(struct tegra_soc_hwpm *hwpm)
{
	int err = 0;
	u32 reg_val = 0U;
	u32 *mem_bytes_kernel_u32 =
		(u32 *)(hwpm->mem_mgmt->mem_bytes_kernel);
	struct hwpm_ip_aperture *pma_perfmux = NULL;

	tegra_hwpm_fn(hwpm, " ");

	err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL,
		&pma_perfmux);
	hwpm_assert_print(hwpm, err == 0, return err,
		"get rtr pma perfmux failed");

	*mem_bytes_kernel_u32 = TEGRA_HWPM_MEM_BYTES_INVALID;

	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_control_user_r(0, 0), &reg_val);
	reg_val = set_field(reg_val,
		pmasys_channel_control_user_update_bytes_m(),
		pmasys_channel_control_user_update_bytes_doit_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_control_user_r(0, 0), reg_val);

	return 0;
}

int t264_hwpm_disable_pma_streaming(struct tegra_soc_hwpm *hwpm)
{
	int err = 0;
	u32 reg_val = 0U;
	struct hwpm_ip_aperture *pma_perfmux = NULL;

	tegra_hwpm_fn(hwpm, " ");

	err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL,
		&pma_perfmux);
	hwpm_assert_print(hwpm, err == 0, return err,
		"get rtr pma perfmux failed");

	/* Disable PMA streaming */
	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_command_slice_trigger_config_user_r(0), &reg_val);
	reg_val = set_field(reg_val,
		pmasys_command_slice_trigger_config_user_record_stream_m(),
		pmasys_command_slice_trigger_config_user_record_stream_disable_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_command_slice_trigger_config_user_r(0), reg_val);

	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_control_user_r(0, 0), &reg_val);
	reg_val = set_field(reg_val,
		pmasys_channel_config_user_stream_m(),
		pmasys_channel_config_user_stream_disable_f());
	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_control_user_r(0, 0), reg_val);

	return 0;
}

int t264_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm,
	u64 mem_bump)
{
	int err = 0;
	struct hwpm_ip_aperture *pma_perfmux = NULL;

	tegra_hwpm_fn(hwpm, " ");

	err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL,
		&pma_perfmux);
	hwpm_assert_print(hwpm, err == 0, return err,
		"get rtr pma perfmux failed");

	if (mem_bump > (u64)U32_MAX) {
		tegra_hwpm_err(hwpm, "mem_bump is out of bounds");
		return -EINVAL;
	}

	tegra_hwpm_writel(hwpm, pma_perfmux,
		pmasys_channel_mem_bump_r(0, 0), mem_bump);

	return 0;
}

int t264_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm,
	u64 *mem_head_ptr)
{
	int err = 0;
	u32 reg_val = 0U;
	struct hwpm_ip_aperture *pma_perfmux = NULL;

	tegra_hwpm_fn(hwpm, " ");

	err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL,
		&pma_perfmux);
	hwpm_assert_print(hwpm, err == 0, return err,
		"get rtr pma perfmux failed");

	tegra_hwpm_readl(hwpm, pma_perfmux,
			pmasys_channel_mem_head_r(0, 0), &reg_val);
	*mem_head_ptr = (u64)reg_val;

	return err;
}

int t264_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm,
	u32 *overflow_status)
{
	int err = 0;
	u32 reg_val, field_val;
	struct hwpm_ip_aperture *pma_perfmux = NULL;

	tegra_hwpm_fn(hwpm, " ");

	err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL,
		&pma_perfmux);
	hwpm_assert_print(hwpm, err == 0, return err,
		"get rtr pma perfmux failed");

	tegra_hwpm_readl(hwpm, pma_perfmux,
		pmasys_channel_status_r(0, 0), &reg_val);
	field_val = pmasys_channel_status_membuf_status_v(
		reg_val);

	*overflow_status = (field_val ==
		pmasys_channel_status_membuf_status_overflowed_v()) ?
		TEGRA_HWPM_MEMBUF_OVERFLOWED : TEGRA_HWPM_MEMBUF_NOT_OVERFLOWED;

	return err;
}